Ion beam etching with sidewall cleaning

Abstract

To provide patterned magnetoresistive random access memory (MRAM) stacks by etching MRAM stacks using ion beam etching techniques.SOLUTION: In a method, patterned MRAM stacks 620a, 620b are formed by performing a main etch through a plurality of MRAM layers 650-670 disposed on a substrate 610, where the main etch includes using ion beam etching (IBE). After the main etch, a gapfill dielectric material 680 is deposited in spaces between the patterned MRAM stacks. The gapfill dielectric material is selectively etched or formed to an etch depth that is above a depth of an underlayer 630. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.SELECTED DRAWING: Figure 6E

Description

Technical Field

[0001] [Incorporation by Reference] As part of this application, a PCT application form is filed simultaneously with this specification. Each application specified in the simultaneously filed PCT application form and for which this application claims benefit or priority is hereby incorporated by reference in its entirety for all purposes into this specification.

Background Art

[0002] Magnetic random access memory (MRAM) is a non-volatile memory that utilizes a magnetoresistive effect such as tunneling magnetoresistance (TMR). MRAM has an integration density as high as that of static random access memory (SRAM) and high-speed performance comparable to that of dynamic random access memory (DRAM). Since the materials of the MRAM stack are highly non-volatile and sensitive to reactive chemicals, typically, the MRAM stack is etched using an ion beam etching technique.

[0003] The background description provided herein is for the purpose of generally presenting the content of the present disclosure. The research by the inventors named at the present time within the scope described in this background art section, as well as aspects of the description that cannot be separately regarded as prior art at the time of filing, are not recognized as prior art against the present disclosure, whether expressly or impliedly.

Summary of the Invention

[0004] A method of ion beam etching is provided herein. The method comprises etching through a plurality of magnetic random access memory (MRAM) layers disposed on a substrate to form a patterned MRAM stack, wherein the plurality of MRAM layers includes one or more magnetic layers and a tunnel barrier layer, and the etching through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer. The method further comprises forming a gap fill dielectric material in the space between the patterned MRAM stacks and performing IBE trim etching to remove at least a portion of the gap fill dielectric material and the conductive material deposited on the sidewalls of the patterned MRAM stacks.

[0005] In some embodiments, the gap-fill dielectric material is formed to a sufficient depth over a lower layer disposed between the substrate and the plurality of MRAM layers, such that no recess occurs in the lower layer even when IBE trim etching is performed. In some embodiments, the sufficient depth over the lower layer is between about 1 nm and about 20 nm from the upper surface of the lower layer. In some embodiments, forming the gap-fill dielectric material in the space between the patterned MRAM stacks includes depositing the gap-fill dielectric material in the space between the patterned MRAM stacks and over the patterned MRAM stacks. In some embodiments, forming the gap-fill dielectric material in the space between the patterned MRAM stacks includes selectively etching the gap-fill dielectric material to an etching depth above the depth of the tunnel barrier layer. In some embodiments, the gap-fill dielectric material includes silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or a combination thereof. In some embodiments, the operations of etching through the plurality of MRAM layers, forming the gap-fill dielectric material, and performing IBE trim etching are performed without introducing a vacuum break during the operations. In some embodiments, the ion beam etching through at least the tunnel barrier layer includes applying a first ion beam having an energy of about 200 eV to about 10,000 eV to the substrate, and performing the IBE trim etching includes applying a second ion beam having an energy of about 20 eV to about 400 eV to the substrate. In some embodiments, performing the IBE trim etching is performed without etching through a lower layer disposed under the plurality of MRAM layers.

[0006] Another aspect involves an apparatus for performing ion beam etching. The apparatus includes an ion beam source chamber, a processing chamber coupled to the ion beam source chamber, and a control unit. The control unit is configured to perform the following operations: placing a substrate in the processing chamber; placing a plurality of MRAM layers on the substrate, where the plurality of MRAM layers includes one or more magnetic layers and a tunnel barrier layer; etching through the plurality of MRAM layers disposed on the substrate to form a patterned MRAM stack, where the etching through the plurality of MRAM layers includes ion beam etching (IBE) that penetrates at least the tunnel barrier layer; forming a gap-fill dielectric material in the space between the patterned MRAM stacks; and performing IBE trim etching to remove at least a portion of the gap-fill dielectric material and the conductive material deposited on the sidewalls of the patterned MRAM stack.

[0007] In some embodiments, the control unit configured to provide instructions for forming the gap-fill dielectric material is further configured to provide instructions for performing the following operation: depositing the gap-fill dielectric material in the space between the patterned MRAM stacks and on the patterned MRAM stacks. In some embodiments, the control unit configured to provide instructions for forming the gap-fill dielectric material is further configured to provide instructions for performing the following operation: selectively etching the gap-fill dielectric material to an etching depth above the depth of the tunnel barrier layer. In some embodiments, the gap-fill dielectric material is formed to a sufficient depth over the underlying layer disposed between the substrate and the plurality of MRAM layers such that no recess occurs in the underlying layer even when IBE trim etching is performed.

Brief Description of the Drawings

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[0017] In the present disclosure, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art will understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer that is at any of many stages of fabricating an integrated circuit. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is implemented on a wafer. However, the present disclosure is not so limited. The workpiece can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces on which the present disclosure can be utilized include various products such as printed circuit boards.

[0018] Introduction An electronic device stores data using an integrated circuit that includes a memory. One type of memory commonly used in electronic circuits is DRAM. DRAM stores each bit of data in a separate capacitor on the integrated circuit. The capacitor can be either charged or discharged, representing the two states of the bit. Since the charge on the capacitor leaks out slowly, the data will be gradually lost unless the charge on the capacitor is refreshed periodically. DRAM is a type of volatile memory, in contrast to non-volatile memory, because the data is lost when the power is turned off.

[0019] Unlike conventional RAM chip technology, the data in MRAM is stored not as a flow of charge or current, but by magnetic storage elements. A magnetic storage element can be formed from two ferromagnetic plates, each of which can hold magnetization, separated by a thin non-magnetic insulating layer. One of the two ferromagnetic plates can be a permanent magnet set to a specific polarity, and the other of the two ferromagnetic plates can be changed to match that of an external magnetic field in order to store memory. Such a configuration with two ferromagnetic plates and a thin non-magnetic insulating layer is known as a magnetic tunnel junction. MRAM is a type of non-volatile memory because it is able to retain stored data even when the power is turned off.

[0020] FIG. 1 is a schematic cross-sectional view of an exemplary MRAM stack on a substrate, according to some embodiments. The MRAM stack 100 has a dielectric layer 110, such as SiO 2is disposed thereon, which is deposited on a silicon or glass substrate (not shown). In the case of an embedded MRAM, since the embedded MRAM can be an MRAM embedded in a non-memory circuit such as a metallization layer, there are various structures (not shown) including the transistor level of the logic circuit and three to five metallization layers between the substrate and the MRAM stack 100. All of these structures are either covered by the dielectric layer 110 or inserted into the dielectric layer 110. The MRAM stack 100 can include an upper electrode layer 120 and a lower electrode layer 130. The lower electrode layer 130 is disposed on the dielectric layer 110 and can include a single-layer metal or a multi-layer stack including a plurality of metal layers and other material layers (e.g., dielectric materials). The upper electrode layer 120 is disposed on the lower electrode layer 130 and can include a single-layer metal or a multi-layer stack including a plurality of metal layers and other material layers (e.g., dielectric materials). The MRAM stack 100 can be disposed in an array of MRAM cells connected by metal word lines and bit lines. In some embodiments, the lower electrode layer 130 is connected to the word line and the upper electrode layer 120 is connected to the bit line.

[0021] The MRAM stack 100 can include memory elements or magnetoresistive effect elements, and the memory elements or magnetoresistive effect elements can be disposed between an upper electrode layer 120 and a lower electrode layer 130. The memory elements or magnetoresistive effect elements can be a multilayer film or a magnetic tunnel junction (MTJ) stack 140. The MTJ stack 140 can include magnetic layers 150, 160 with a barrier layer 170 between the magnetic layers 150, 160. Further, the MTJ stack 140 can include a plurality of MTJ stacks and a plurality of barrier layers, and each barrier layer is disposed between a pair of magnetic layers. It will be understood that the MTJ stack 140 is illustrative and not limiting and can include many other layers not shown in FIG. 1. The first magnetic layer 150 is designed to function as a free magnetic layer, and the second magnetic layer 160 has a fixed magnetization direction. In some embodiments, each of the first magnetic layer 150 and the second magnetic layer 160 includes a magnetic material such as cobalt (Co), nickel (Ni), iron (Fe), or a combination thereof (e.g., CoNi, CoFe, NiFe, CoNiFe). Each of the first magnetic layer 150 and the second magnetic layer 160 can further include a non-magnetic material such as boron (B), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), aluminum (Al), silicon (Si), germanium (Ge), gallium (Ga), oxygen (O), nitrogen (N), carbon (C), platinum (Pt), palladium (Pd), ruthenium (Ru), or phosphorus (P) to form a magnetic compound (e.g., CoFeB). It should be understood that each of the first magnetic layer 150 and the second magnetic layer 160 can include one or more sub-layers. In some embodiments, the second magnetic layer 160 can be coupled to and disposed on an antiferromagnetic layer (not shown). The MTJ stack 140 further includes a tunnel barrier layer or a barrier layer 170 between the first magnetic layer 150 and the second magnetic layer 160, and the barrier layer 170 can include a non-magnetic insulating material such as magnesium oxide (MgO).Accordingly, the MTJ stack 140 can include a pair of ferromagnetic layers (i.e., the first magnetic layer 150 and the second magnetic layer 160) sandwiching a non-magnetic intermediate layer (i.e., the barrier layer 170) that collectively generates the magnetoresistive effect. The resistivity of the MTJ stack 140 changes when the magnetization of the first magnetic layer 150 changes direction with respect to the magnetization of the second magnetic layer 160, shows a low-resistance state when the magnetization orientations of the pair of ferromagnetic layers are substantially parallel, and shows a high-resistance state when the magnetization orientations of the pair of ferromagnetic layers are substantially anti-parallel. Accordingly, the MRAM stack 100 has two stable states and can be enabled to function as a non-volatile memory.

[0022] In some embodiments, the upper electrode layer 120 can function as a hard mask layer. During processing, the upper electrode layer 120 can be deposited on the first magnetic layer 150 to pattern the underlying MTJ stack 140. However, it should be understood that the positions of the first magnetic layer 150 and the second magnetic layer 160 can be reversed and the upper electrode layer 120 can be deposited on the second magnetic layer 160. In some embodiments, the upper electrode layer 120 includes tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or other high melting point metals. The MTJ stack 140 can be formed on the lower electrode layer 130, and the lower electrode layer 130 includes a conductive material such as Ta, Ti, W, TiN, TaN, Pt, Ru, etc.

[0023] It should be understood that the MRAM stack 100 can include several other layers not necessarily shown in FIG. 1. The layers within the MRAM stack 100 are not necessarily limited to metals or conductive materials, but can also include one or more layers of dielectric materials.

[0024] The etching materials within the MRAM stack, including the MRAM stack 100 of FIG. 1, can present many challenges. Hard materials are typically etched in chemical etching processes such as reactive ion etching (RIE). However, reactive ion etching of materials such as cobalt, iron, nickel, and other magnetic elements is difficult because these materials do not readily become volatile when exposed to typical etchant chemistries. Thus, many materials within the MRAM stack require more aggressive etchant chemistries. On the other hand, certain materials within the MRAM stack cannot tolerate such aggressive etchant chemistries. For example, a tunnel barrier layer such as MgO cannot tolerate reactive chemicals, which may include radicals, ions, and neutral species containing fluorine, chlorine, iodine, oxygen, or hydrogen. These chemicals can cause reactions with the tunnel barrier layer, thereby damaging the tunnel barrier layer and potentially adversely affecting the electrical and magnetic properties of the MRAM stack. In some cases, the tunneling magnetoresistance (TMR) effect in the MRAM stack is impaired.

[0025] Ion beam etching (IBE) is widely used in various industries for patterning thin films. Ion beam etching, which can also be referred to as ion milling, provides a highly directed beam of charged particles for etching features on a substrate. Ion beam etching can be applied using only physically inert gases in a purely physical etching process, but in some cases, reactive species can be used to apply ion beam etching and increase the etching of materials by chemical / reactive components. Generally speaking, ion beam etching can physically etch through hard materials by using individual particles to ablate the exposed target and remove atoms and molecules. Using ion beam etching makes it possible to etch materials within the MRAM stack while avoiding reactive chemicals that can degrade sensitive layers such as the tunnel barrier layer.

[0026] Features within the MRAM stack can be patterned by ion beam etching. Ion beam etching can generally be one without chemical reactions and physically etches the layers and materials exposed by the hard mask. Thereby, atoms and molecules are sputtered from the target. The sputtered atoms and molecules can be directed towards the exposed sidewalls of the MRAM stack and redeposited on the exposed sidewalls. Therefore, etching and redeposition can occur simultaneously. The redeposited material can be cleaned from the sidewalls of the MRAM stack by performing ion beam etching at an energy lower than that of ion beam etching for patterning the MRAM stack and at a different collision angle.

[0027] FIG. 2 is a schematic cross-sectional view of an MRAM layer that has undergone ion beam etching and sidewall redeposition. MRAM stacks 220a, 220b are formed on a substrate 210. Each of the MRAM stacks 220a, 220b can include a pair of magnetic layers, and a tunnel barrier layer (e.g., MgO) can be sandwiched between the magnetic layers. In some embodiments, it should be understood that each of the MRAM stacks 220a, 220b can include a plurality of tunnel barrier layers, each of which is sandwiched between a pair of magnetic layers. Examples of the layers and materials within the MRAM stacks 220a, 220b are described above with respect to the MRAM stack 100 of FIG. 1. Conventional MRAM patterning processes include hard mask patterning, top electrode patterning, MTJ patterning, and bottom electrode patterning. Ion beam etching can be used in part or all of the aforementioned patterning processes, and it should be understood that ion beam etching can be used in MTJ patterning. Reactive ion etching or ion beam etching can be used for top electrode patterning and bottom electrode patterning. To pattern the MRAM stacks 220a, 220b, an ion beam 225 can be applied to the substrate 210 to physically etch the layers and materials exposed by the hard mask. The ion beam 225 sputters atoms and molecules from the surface exposed to the ion beam 225. As shown in FIG. 2, the sputtered atoms and molecules 275 can be directed toward the sidewalls of the MRAM stacks 220a, 220b and redeposited on the sidewalls. Some of the layers on the substrate 210, such as the layers of the MTJ stack, can include metal atoms such as Fe, Co, and Ni atoms. As the ion beam etching progresses through the MTJ stack, such metal atoms can be removed and redeposited on the sidewalls of the MRAM stacks 220a, 220b. When a conductive material is redeposited on the sidewalls of the tunnel barrier layer, which can be on the order of only a few nanometers thick, the magnetic layers are short-circuited in the MRAM stacks 220a, 220b.

[0028] The ion beam 225 applied to the substrate 210 can be directed at an angle. The incident angle of the ion beam 225 can be adjusted to control parameters such as etching rate, uniformity, shape, topography, and the composition of the target surface. In some cases, the incident angle of the ion beam 225 is adjusted to clean the sidewalls of the re-deposited material. A lower incident angle of the ion beam 225 (i.e., higher perpendicularity) can result in more re-deposition of the material, while an optimized higher incident angle of the ion beam 225 (i.e., lower perpendicularity) can result in a cleaner sidewall surface by removing the re-deposited material. Furthermore, as the device density increases and the aspect ratio increases, the feasibility of using a higher incident angle for cleaning the sidewall surface is further limited.

[0029] Ion Beam Etching Apparatus FIG. 3 is a schematic diagram of an exemplary ion beam etching apparatus according to some embodiments. The ion beam etching apparatus 310 includes a processing chamber 312 having a substrate holder 314 for supporting a substrate 316. The substrate 316 can be a semiconductor wafer. A plurality of MRAM layers as described above can be formed on the substrate 316. The plurality of MRAM layers can include one or more magnetic layers and a single tunnel barrier layer or a plurality of tunnel barrier layers. The plurality of MRAM layers can further include an upper electrode layer and a lower electrode layer. The substrate 316 can be attached to the substrate holder 314 using any suitable technique. For example, the substrate 316 is mechanically or electrostatically connected to the substrate holder 314. In some embodiments, the substrate holder 314 can include an electrostatic chuck (ESC) for providing an accurate tilt and rotation and engaging the substrate 316.

[0030] The ion beam etching apparatus 310 further includes an ion beam source chamber 322. The processing chamber 312 is outside the ion beam source chamber 322 and can be coupled to the ion beam source chamber 322. The ion beam source chamber 322 can be separated from the processing chamber 312 by an ion extractor 340 and / or a mechanical shutter 348. An induction coil 332 can be disposed around the outer wall of the ion beam source chamber 322. A plasma generator 334 supplies RF power to the induction coil 332. The plasma generator 334 can include an RF source 336 and a matching network 338. During use, a gas mixture is introduced into the ion beam source chamber 322, and RF power is supplied to the induction coil 332 to generate a plasma within the ion beam source chamber 322, and the plasma generates ions.

[0031] The ion beam etching apparatus 310 further includes a gas delivery system 350 fluidly coupled to the ion beam source chamber 322. The gas delivery system 350 delivers one or more gas mixtures to the ion beam source chamber 322. The gas delivery system 350 can include one or more gas sources 352, valves 354, mass flow controllers (MFCs) 356, and a mixing manifold 358 that are in fluid communication with the ion beam source chamber 322. In some embodiments, the gas delivery system 350 is configured to deliver an inert gas such as helium (He), neon (Ne), argon (Ar), xenon (Xe), or krypton (Kr). In some embodiments, the gas delivery system 350 delivers a gas mixture that further includes a reactive chemical with the inert gas.

[0032] The ion extractor 340 extracts positive ions from the plasma and accelerates the positive ions in the beam towards the substrate 316. The ion extractor 340 may include a plurality of electrodes forming a grid or a grid system. As shown in FIG. 3, the ion extractor 340 includes three electrodes, and the first electrode 342, the second electrode 344, and the third electrode 346 are present in this order from the gas supply system 350. A positive voltage is applied to the first electrode 342, and a negative voltage is applied to the second electrode 344, so that the ions are accelerated by the difference in their potentials. The third electrode 346 is grounded. By controlling the potential difference between the second electrode 344 and the third electrode 346, the energy and divergence of the ion beam are controlled. A mechanical shutter 348 may be adjacent to the ion extractor 340. The neutralizer 360 can supply electrons to the processing chamber 312 and neutralize the charge of the ion beam passing through the ion extractor 340 and the mechanical shutter 348. The neutralizer 360 may have its own gas supply system that uses an inert gas such as argon or xenon. In some embodiments, the ion extractor 340 and / or the mechanical shutter 348 can be controlled such that the ion beam is fed to the substrate 316 continuously or in pulses.

[0033] The position of the substrate holder 314 can be controlled using the position control unit 366. In particular, the position control unit 366 can control the tilt angle around the tilt axis and the rotation of the substrate holder 314 to position the substrate 316. In some embodiments, an endpoint detector 368 can be used to detect the location of the ion beam relative to the substrate 316 and / or the substrate holder 314. A pump 370, such as a turbo molecular pump, can be used to control the pressure in the processing chamber 312 and evacuate reactants from the processing chamber 312.

[0034] The ion beam etching apparatus 310 may further include a control unit 390. The control unit 390 (which may include one or more physical or logical control units) controls some or all of the operations of the ion beam etching apparatus 310. In some embodiments, the control unit 390 may be used to control the plasma generator 334, the gas delivery system 350, the neutralizer 360, the position control unit 366, and the pump 370. The control unit 390 can include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepping motor control unit board, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions can be stored in a memory device associated with the control unit 390 and can be provided via a network. In a particular embodiment, the control unit 390 executes system control software. The system control software may include instructions for controlling the timing and / or magnitude of the application of any one or more of the following chamber operating conditions: gas mixture and / or composition, gas flow rate, chamber pressure, chamber temperature, substrate / substrate holder temperature, substrate position, substrate holder tilt, substrate holder rotation, voltage applied to the grid, frequency and power applied to a coil or other plasma generating component, and other parameters of a particular process performed by the tool. The system control software can further control purge and cleaning operations through the pump 370. The system control software can be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components required to perform various process tool processes. The system control software can be coded in any suitable computer-readable programming language.

[0035] In some embodiments, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of the semiconductor manufacturing process may include one or more instructions for execution by the control unit 390. Instructions for setting process conditions for a stage may be included, for example, in the corresponding recipe stage. In some embodiments, the recipe stages may be arranged in order such that the steps of the ion beam etching process are executed in a specific order for that process stage. For example, the recipe may be configured to perform separation etching using high-energy ion beam etching and trim etching using low-energy ion beam etching.

[0036] Other computer software and / or programs may be used in some embodiments. Examples of programs or sections of programs for this purpose include a substrate placement program, a process gas composition control program, a pressure control program, a heater control program, and an RF power control program.

[0037] The control unit 390 can control these and other aspects based on sensor outputs (e.g., when power, potential, pressure, gas level, etc. reach specific thresholds), the timing of operations (e.g., when opening a valve at a specific time in the process), or instructions received from the user.

[0038] In a broad sense, the control unit 390 may be defined as an electronic device having various integrated circuits, logic, memories, and / or software that receive instructions, issue instructions, control operations, enable a cleaning operation, enable endpoint measurement, etc. The integrated circuit may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, i.e., a microcontroller that executes program instructions (e.g., software). The program instructions are instructions communicated to the control unit 390 in the form of various individual settings (or program files) that may define operation parameters for executing a specific process on or for a semiconductor substrate or for a system. The operation parameters may, in some embodiments, be part of a recipe defined by a process engineer to implement one or more processing steps in the patterning of an MRAM stack on a substrate.

[0039] In some embodiments, the control unit 390 may be part of a computer that is integrated or coupled with the system, or otherwise network-connected to the system, or coupled to such a computer, or a combination thereof. For example, the control unit 390 may be within the "cloud", or may be all or part of the fab host computer system. This enables remote access to substrate processing. The computer can enable remote access to the system, monitor the current progress of the fabrication operation, consider the history of past fabrication operations, consider trends or performance criteria from multiple fabrication operations, change the parameters of the current process, set the processing steps following the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system through a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, and such parameters and / or settings are then communicated from the remote computer to the system. In some examples, the control unit 390 receives instructions in the form of data. Such data specifies the parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that the control unit 390 is configured to interact with or control. Thus, as described above, the control unit 390 may be distributed, for example, by comprising one or more individual control units that are network-connected to each other and cooperate towards a common purpose (such as the processes and controls described herein). Examples of such a distributed control unit 390 for such a purpose include one or more integrated circuits on a chamber that are remotely located (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that are combined to control the process in the chamber.

[0040] As described above, depending on one or more processing steps performed by a tool, the control unit 390 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, proximate tools, tools located throughout the factory, a main computer, another control unit, or a tool used for material transport to load and unload a substrate container to and from a tool location and / or load port within a semiconductor manufacturing factory. The foregoing examples are described in FIGS. 7-9 with which the control unit 390 may communicate.

[0041] Ion Beam Etching by Sidewall Cleaning In the present disclosure, a dielectric gap fill material is deposited between an IBE isolation etching process for patterning an MRAM stack and an IBE trim etching process for cleaning sidewalls of the patterned MRAM stack. Typically, the IBE trim etching process for cleaning sidewalls of a patterned MRAM stack causes sputtering of a metal or conductive material that can redeposit on the sidewalls. If the etching front of the IBE trim etching process includes a metal or conductive material, sputtering of the metal or conductive material can occur. One approach to avoid such sputtering is to use silicon oxide (SiO 2) is to provide a thick layer of a dielectric material such as this. The thick layer of the dielectric material can be provided under the MRAM layer or under the magnetic layer in the MTJ stack. The thick layer of the dielectric material can have a thickness of at least about 40 nm, at least about 50 nm, at least about 75 nm, or at least about 100 nm. Thus, the material that redeposits on the sidewalls during ion beam etching is a dielectric material rather than a conductive material. However, providing a thick layer of a dielectric material under the magnetic layer of the MTJ stack is unrealistic, as it can increase operational overhead, complicate the manufacturing process, increase costs, and even reduce performance. For example, many MRAM devices are embedded memories that exist between the metallization layers of an integrated circuit (IC), and the thickness of the dielectric layer where the MRAM device is located cannot be easily changed.

[0042] Figures 4A and 4B show schematic cross-sectional views of ion beam etching through a plurality of MRAM layers and underlying layers. The MRAM stack 400 can include a first magnetic layer 450, a tunnel barrier layer 470, and a second magnetic layer 460, with the tunnel barrier layer 470 between the first magnetic layer 450 and the second magnetic layer 460. The first magnetic layer 450 can also be called a free layer and is designed to function as a free magnetic layer, and the second magnetic layer 460 can be called a reference layer and is designed to have a fixed magnetization direction. In some embodiments, the first magnetic layer 450 and the second magnetic layer 460 can include a magnetic material such as Co, Ni, Fe, Pt, or a combination thereof. The tunnel barrier layer 470 can include a non-magnetic insulating material such as MgO. The combination of the first magnetic layer 450, the tunnel barrier layer 470, and the second magnetic layer 460 generates a magnetoresistive effect. The MRAM stack 400 is disposed on the substrate 410 with an underlying layer 430 between the substrate 410 and the MRAM stack 400. The underlying layer 430 is silicon oxide (SiO 2) can include one or more layers of a dielectric material such as. In some embodiments, a hard mask layer or an electrode layer (not shown) can be disposed on top of the MRAM stack 400. In some embodiments, the electrode layer (not shown) can be disposed between the lower layer 430 and the substrate 410. In some embodiments, the MRAM stack 400 can include a plurality of tunnel barrier layers each sandwiched between a first magnetic layer and a second magnetic layer.

[0043] Ion beam etching through the layers of the MRAM stack 400 can be performed to form a patterned MRAM stack, which can include lines, pillars, or other patterned features. The ion beam etching for forming the patterned MRAM stack can be performed at high power and a relatively low angle of incidence. Additionally, after performing the ion beam etching to form the patterned MRAM stack, the sidewalls of the patterned MRAM stack can be cleaned to remove unwanted material redeposited on the sidewalls. The ion beam etching for cleaning the sidewalls of the patterned MRAM stack can be performed at a lower power and a relatively high angle of incidence from the normal to the substrate surface.

[0044] In FIG. 4A, the ion beam 425 can be directed at an angle to clean the sidewalls of the patterned MRAM stack. For example, the substrate 410 can be tilted or rotated to adjust the ion collision angle of the ion beam 425. The ion beam 425 collides with the sidewalls of the patterned MRAM stack to remove unwanted material. The ion beam 425 also collides with the bottom surface of the MRAM stack 400 to sputter the atoms and molecules on the bottom surface. The sputtered atoms and molecules 475 can be directed towards the sidewalls of the patterned MRAM stack and as a result, redeposit on the sidewalls of the patterned MRAM stack. When the etching front of the ion beam 425 has a conductive material (e.g., metal), at least a portion of the conductive material can be redeposited on the sidewalls of the patterned MRAM stack. In FIG. 4A, when the etching front of the ion beam 425 includes the second magnetic layer 460, magnetic elements having Co, Ni, Pt, or Fe may redeposit on the sidewalls of the patterned MRAM stack, which can reduce the electrical and magnetic performance of the MRAM stack 400.

[0045] Rather than having an etching front of a conductive material, the etching front can include a dielectric material. In FIG. 4B, the ion beam 425 collides with the bottom surface of the MRAM stack 400 and directs the sputtered atoms and molecules 475 towards the exposed surfaces of the patterned MRAM stack. The etching front of the ion beam 425 includes the underlying layer 430 and SiO 2Dielectric materials such as can be redeposited on the sidewalls of the patterned MRAM stack. Sputtered atoms and molecules 475 from the dielectric material in the lower layer 430 are unlikely to degrade the electrical and magnetic performance of the MRAM stack 400. Thus, overetching can be performed through the lower layer 430 while providing harmless backsputtering to the patterned MRAM stack. The thickness of the lower layer 430 can be sufficient to function as an etching front for ion beam etching to properly clean the sidewalls of the patterned MRAM stack. However, as described above, it may not be desirable to incorporate a sufficiently thick lower layer 430 between the substrate 410 and the MRAM stack 400, and having a particularly thick lower layer 430 can be unrealistic in various devices.

[0046] In the present disclosure, the lower layer having a dielectric material with a thickness sufficient to enable removal of the sidewall material redeposited before the dielectric material is etched away does not include an MRAM stack that functions as an etching front during cleaning. In the present disclosure, an IBE main etching process is performed to form a patterned MRAM stack, and subsequently, a gap-fill dielectric material is deposited in the space between the patterned MRAM stacks. The gap-fill dielectric material can be etched back or formed to a sufficient depth such that the deposited gap-fill dielectric material remains throughout all or most of the subsequent IBE trim etching cleaning step. In some embodiments, the thickness of the deposited gap-fill dielectric material extends above the depth of the tunnel barrier layer. Following the deposition of the gap-fill dielectric material, an IBE overetching or trim etching process is performed to clean the sidewalls of the patterned MRAM stack, and the etching front during the IBE trim etching process includes the gap-fill dielectric material.

[0047] FIG. 5 shows a flow diagram of an exemplary method of ion beam etching according to some embodiments. The operations of process 500 of FIG. 5 may include additional, fewer, or different operations. In connection with the description of process 500 of FIG. 5, FIGS. 6A-6F show a series of cross-sectional schematic views showing main etching, gap filling, planarization, etch back, IBE trim etching, and encapsulation operations. The operations of process 500 may be implemented using an ion beam etching apparatus such as the ion beam etching apparatus 310 of FIG. 3.

[0048] In block 510 of process 500, a plurality of MRAM layers disposed on a substrate are etched through to form a patterned MRAM stack, the plurality of MRAM layers including one or more magnetic layers and tunnel barrier layers. The etching through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer. In some embodiments, the etching through the plurality of MRAM layers includes ion beam etching through the plurality of MRAM layers. In some embodiments, the etching through the plurality of MRAM layers includes reactive ion etching (RIE) through some of the plurality of MRAM layers and ion beam etching through at least the tunnel barrier layer. In some embodiments, the plurality of MRAM layers includes two or more tunnel barrier layers, and the ion beam etching is performed through the two or more tunnel barrier layers. To pattern the MRAM stack, a hard mask can be formed on the plurality of MRAM layers. The hard mask can be made of, for example, W, Ti, Ta, TiN, or other high melting point metals. The etching through the plurality of MRAM layers in block 510 may also be referred to as "main etching", "cut etching", "separation etching", "first etching", or "IBE separation etching".

[0049] Etching through multiple MRAM layers can include etching through an MTJ stack including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer between the first magnetic layer and the second magnetic layer. The first magnetic layer can be disposed on top of the tunnel barrier layer, and the second magnetic layer can be disposed under the tunnel barrier layer. The tunnel barrier layer can include a non-magnetic insulating material such as MgO. Each of the first magnetic layer and the second magnetic layer may include a magnetic element such as Co, Ni, Pt, Fe, or a combination thereof. In some embodiments, the etching through the MTJ stack can include ion beam etching through the MTJ stack. The etching can stop at a lower layer or a dielectric layer after etching through at least the second magnetic layer. The etching through multiple MRAM layers can include ion beam etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer without etching through the lower layer. Thus, the main etching or the isolation etching can be carried out up to the interface between the lower layer to be etched and the multiple MRAM layers, and the lower layer can include a dielectric material such as SiO 2 2. The main etching can be carried out with respect to the upper surface of the lower layer, and the main etching can stop on the lower layer using emission spectroscopy or an endpoint detector.

[0050] When performing ion beam etching through at least some of the MRAM layers, an ion beam of an inert gas can be generated from an ion beam source chamber. The ion beam source chamber can be coupled to a processing chamber in which the substrate is located. The ion beam can be generated in the ion beam source chamber using a gas mixture containing an inert gas. The inert gas can include helium (He), neon (Ne), argon (Ar), xenon (Xe), krypton (Kr), or a combination thereof. In some embodiments, the gas mixture can include one or more reactive gases to increase the etching of the material by chemical / reactive components. In some embodiments, the gas mixture does not contain or substantially does not contain reactive gases. RF power can be applied to a coil surrounding the ion beam source chamber to generate a plasma, and ions are extracted from the plasma to form an ion beam. A voltage is applied to an ion extractor (e.g., a grid) to extract the ions and form an ion beam, and the ion beam can be accelerated toward the processing chamber. Control of the voltage applied to the ion extractor can be used to control the etching rate when performing ion beam etching. A high voltage ion beam can be about 400 V to about 2000 V to perform "fast" etching at a high etching rate, and a low voltage ion beam can be about 30 V to about 400 V to perform "soft" etching at a low etching rate. Ion beam etching (main etching or isolation etching) through at least some of the plurality of MRAM layers including the tunnel barrier layer to form a patterned MRAM stack can be performed at a relatively high voltage. Thus, the main etching used to etch through the plurality of MRAM layers to form a patterned MRAM stack can be performed at a high voltage of about 400 V to about 2000 V. On the other hand, trim etching or over-etching used to clean the sidewalls of the patterned MRAM stack can be performed at a low voltage of about 30 V to about 400 V.

[0051] In some embodiments, etching through at least some of the plurality of MRAM layers may include applying an ion beam having an ion energy of from about 200 eV to about 10,000 eV to the substrate. The main etching can be performed at a high ion energy to efficiently etch the materials within the MRAM layer as compared to trim etching. In some embodiments, the main etching or the isolation etching can be performed in 10 minutes or less, 3 minutes or less, or 1 minute or less. In some embodiments, the main etching can be performed in an ion beam etching apparatus having an ion beam source chamber coupled to the processing chamber. An exemplary ion beam etching apparatus is described in FIG. 3 above.

[0052] In some embodiments, some of the MRAM layers can be etched using reactive ion etching. Specifically, since the reactive species from the reactive ion etching may damage the tunnel barrier layer, the reactive ion etching can be applied to layers other than the tunnel barrier layer. Reactive ion etching can be followed by ion beam etching to etch through the tunnel barrier layer. In some embodiments, the reactive ion etching can be applied to a hard mask layer or an electrode layer disposed on the tunnel barrier layer. In some embodiments, the reactive ion etching may be applied to a first magnetic layer disposed on the tunnel barrier layer. In some embodiments, the reactive ion etching may be applied to a second magnetic layer disposed under the tunnel barrier layer. In some embodiments, the reactive ion etching may be applied to an electrode layer disposed under the second magnetic layer. Nevertheless, any of the aforementioned MRAM layers can be etched using ion beam etching instead of reactive ion etching. Thus, the sequence of main etching in etching through a plurality of MRAM layers can include RIE followed by IBE, RIE followed by IBE and IBE followed by RIE, IBE followed by RIE, or IBE throughout.

[0053] During main etching, conductive material can redeposit on the sidewalls of the patterned MRAM stack. The redeposited conductive material can be derived from one or more magnetic layers within the plurality of MRAM layers. Typically, when etching one or more magnetic layers of the plurality of MRAM layers, etching by-products that can redeposit on the exposed surface are generated. The etching by-products can include atoms or molecules of a metal or conductive material. These etching by-products are sputtered when an ion beam is applied to the plurality of MRAM layers. One or more magnetic layers can include a non-volatile material, and the non-volatile material can include a magnetic material such as Co, Ni, Pt, Fe, etc. When such etching by-products redeposit on the sidewall surface of the tunnel barrier layer, the MTJ stack can be damaged and lead to a short circuit.

[0054] Etching through the plurality of MRAM layers forms a patterned MRAM stack, and the patterned MRAM stack is a line, pillar, or other patterned feature. The main etching forms a space between the patterned MRAM stacks. In some embodiments, the patterned MRAM stack is a pillar having a high aspect ratio, and the height-to-width aspect ratio of the patterned MRAM stack is at least 5:1, at least 7:1, at least 10:1, or at least 20:1. In some embodiments, the pitch between adjacent MRAM stacks can be about 300 nm or less, about 10 nm to about 300 nm, or about 30 nm to about 250 nm.

[0055] In some embodiments, prior to block 510 of process 500, the substrate can be placed within the processing chamber of an ion beam etching apparatus. The plurality of MRAM layers can be disposed on the substrate, and the plurality of MRAM layers can include one or more magnetic layers and a tunnel barrier layer.

[0056] FIG. 6A shows a schematic cross-sectional view of exemplary main etching according to some embodiments. A plurality of MRAM layers 650, 660, and 670 are disposed on a substrate 610, and an underlying layer 630 is disposed between the plurality of MRAM layers 650, 660, and 670 and the substrate 610. The aspects of the plurality of MRAM layers 650, 660, and 670 and the underlying layer 630 are described in FIGS. 1 and 2. The plurality of MRAM layers 650, 660, and 670 include at least a first magnetic layer 650, a second magnetic layer 660, and a tunnel barrier layer 670 between the first magnetic layer 650 and the second magnetic layer 660. As described above, the plurality of MRAM layers 650, 660, and 670 may each include a plurality of tunnel barrier layers sandwiched between a first magnetic layer and a second magnetic layer. Main etching is performed to form the patterned MRAM stacks 620a, 620b. The main etching can stop on the top surface of the underlying layer 630. In some embodiments, the main etching or the isolation etching is performed through at least the tunnel barrier layer 670 when forming the patterned MRAM stacks 620a, 620b. The ion beam of the main etching or the isolation etching can be provided at a relatively high ion energy and a relatively low angle of incidence to the normal of the substrate surface. A residue 605 containing a metal or a conductive material is formed on the sidewalls of the patterned MRAM stacks 620a, 620b as a result of the main etching. Sputtered atoms and / or molecules from the ion beam etching of the plurality of MRAM layers 650, 660, and 670 can cause the accumulation of the residue 605. The residue 605 is formed on the tunnel barrier layer 670 and may degrade the performance of the tunnel barrier layer 670.

[0057] Returning to FIG. 5, at block 520 of process 500, a gap-fill dielectric material is formed in the space between the patterned MRAM stacks. In some embodiments, the gap-fill dielectric material can be formed along the sidewalls and on the bottom surface of the patterned MRAM stacks. In some embodiments, the gap-fill dielectric material can be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), or plasma-enhanced chemical vapor deposition (PECVD). However, it should be understood that the gap-fill dielectric material can be deposited using any other suitable deposition technique such as atomic layer deposition (ALD). For example, the gap-fill dielectric material can be deposited in the space between the patterned MRAM stacks using a deposition technique to achieve bottom-up filling.

[0058] In some embodiments, the gap-fill dielectric material includes any suitable dielectric material such as silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, germanium nitride, magnesium oxide, or combinations thereof. For example, the gap-fill dielectric material includes one or both of silicon nitride and silicon oxide. The gap-fill dielectric material can include a layer of silicon nitride and a layer of silicon oxide, or can include only a layer of silicon nitride. In some embodiments, it is desirable to avoid direct contact of silicon oxide with the patterned MRAM stacks. The aforementioned dielectric materials can fill the space between the patterned MRAM stacks or at least fill the space above the underlying layer. Forming a gap-fill dielectric material in the space between the patterned MRAM stacks is sometimes referred to as a "gap-fill" or "dielectric gap-fill" process.

[0059] In some embodiments, gap fill can be performed in a deposition chamber such as a CVD, PVD, or PECVD chamber. The gap fill can be performed after the main etching and before the IBE trim etching. In some embodiments, the main etching and the gap fill can be performed by an integrated tool or a multi-station processing tool. The operations of the main etching at block 510 and the gap fill at block 520 can be performed without introducing a vacuum break during the operations.

[0060] In some embodiments, forming a gap fill dielectric material in the space between the patterned MRAM stacks includes depositing the gap fill dielectric material in the space between the patterned MRAM stacks and on the patterned MRAM stacks, and selectively etching the gap fill dielectric material to a sufficient depth over the underlying layer. In some embodiments, the sufficient depth over the underlying layer can correspond to a sufficient thickness such that at least a portion of the gap fill dielectric material remains after subsequent trim etching at block 530. The gap fill dielectric material can be first deposited on the patterned MRAM stacks to form an overburden. The gap fill deposition process is typically somewhat conformal, with material depositing along the sidewalls, bottom, and top surfaces of the patterned MRAM stacks. Since there can be a variation in the deposition rate between the top surface and the bottom surface of the patterned MRAM stacks, the gap fill deposition process can result in some "bread-loafing". This typically leads to non-uniform topography from the gap fill. Thus, an overburden of the gap fill dielectric material can deposit when filling the space between the patterned MRAM stacks, and the overburden of the gap fill dielectric material can have a non-uniform thickness across the entire top surface of the gap fill dielectric material. In other words, some portions of the gap fill dielectric material are thicker than other portions.

[0061] After depositing an overburden of gap-fill dielectric material over the patterned MRAM stack, the overburden can be removed. In some embodiments, process 500 further includes planarizing the gap-fill dielectric material deposited over the patterned MRAM stack. For example, the overburden can be removed using chemical mechanical polishing (CMP) or etching.

[0062] In addition to, or instead of, overburden planarization, the deposited gap-fill dielectric material may be selectively etched using dry etching or wet etching techniques, and the gap-fill dielectric material is selectively etched to a depth over the underlying layer. In some embodiments, the depth may be between the top surface of the tunnel barrier layer and the top surface of the first magnetic layer, between the bottom surface of the tunnel barrier layer and the bottom surface of the second magnetic layer, or between the bottom surface of the second magnetic layer and the top surface of the underlying layer. When multiple MRAM layers include multiple tunnel barrier layers having multiple first / second magnetic layers, the depth may be measured with respect to the lowest tunnel barrier layer and the lowest first / second magnetic layer. In some embodiments, the selective etching is plasma etching that selectively removes the gap-fill dielectric material without, or substantially without, removing the hard mask layer or the MRAM layer. The etching may have an etching selectivity greater than about 10:1 between the gap-fill dielectric material and the hard mask layer or the MRAM layer, which means that the gap-fill dielectric material is etched at an etching rate more than 10 times that of the hard mask layer or the MRAM layer. For example, the gap-fill dielectric material can be etched using a fluorine plasma in a reactive ion etching (RIE) or chemical down-stream etching (CDE) chamber. When the dielectric material is silicon oxide, it can also be removed with hydrogen fluoride (HF) vapor. The sufficient depth over the underlying layer may be between about 1 nm and about 20 nm from the depth of the underlying layer, between about 2 nm and about 15 nm from the depth of the underlying layer, or between about 3 nm and about 10 nm from the depth of the underlying layer. In some embodiments, the selective etching may proceed to remove the gap-fill dielectric material without exposing the underlying layer. In some embodiments, the selective etching may proceed to remove the gap-fill dielectric material without significantly etching through the underlying layer. As used herein, "significantly etching through" the underlying layer may constitute etching through at least 3 nm or at least 5 nm of the underlying layer. In some embodiments, the sufficient depth over the underlying layer may be over the tunnel barrier layer.As described above, exposing the tunnel barrier layer to reactive chemicals can damage the tunnel barrier layer. Selective etching leaves the remaining gap fill dielectric material and functions as an etch front during IBE trim etching to clean the sidewalls of the patterned MRAM stack. In some embodiments, the selective etching can be stopped at an etch depth just above the depth of the tunnel barrier layer or at a sufficient depth above the underlying layer using suitable endpoint detection techniques such as optical emission spectroscopy (OES) or interferometric endpoint detection (IEP). Selective etching is sometimes referred to as an "etch back" process or an "isotropic etch back" process.

[0063] Figure 6B shows a cross-sectional schematic view of an exemplary gap fill process following the main etching of Figure 6A according to some embodiments. After the main etching, the gap fill dielectric material 680 is deposited into the space between the patterned MRAM stacks 620a, 620b using a suitable deposition technique such as CVD, PVD, or PECVD. In some embodiments, the gap fill dielectric material 680 is conformally deposited along the exposed surfaces (e.g., sidewalls) of the patterned MRAM stacks 620a, 620b to perform the gap fill. Thus, the recesses, gaps, trenches, openings, or spaces are filled with the gap fill dielectric material 680. An overburden of the gap fill dielectric material 680 is deposited over the patterned MRAM stacks 620a, 620b. In some embodiments, the gap fill dielectric material 680 includes silicon nitride or a combination of silicon nitride and silicon oxide.

[0064] FIG. 6C shows a schematic cross-sectional view of an exemplary planarization process following the gap fill process of FIG. 6B according to some embodiments. After the overburden of the gap fill dielectric material 680 is deposited, the upper surface of the overburden can become non-uniform. For example, non-uniform topography may result in more dielectric gap fill material 680 in the magnetic field region compared to the gap fill region, which can lead to bread-loafing. A planarization process such as CMP or etching can be performed to smooth the topography and remove the overburden.

[0065] FIG. 6D shows a schematic cross-sectional view of an exemplary etch-back process following the planarization process of FIG. 6C according to some embodiments. After the planarization process or the gap fill process, an etch-back process is performed to selectively remove the gap fill dielectric material 680 with respect to the plurality of MRAM layers 650, 660, and 670, or at least with respect to the first magnetic layer 650. In some embodiments, the etch-back process selectively removes the gap fill dielectric material 680 with respect to the hard mask layer. The etch-back process can be a dry etch or a wet etch. The dry etch can be a plasma etch. The etch-back process can be performed to remove the gap fill dielectric material 680 to an etch depth above the lower layer 630. In some embodiments, the etch-back process can be performed to remove the gap fill dielectric material 680 to an etch depth slightly above the depth of the tunnel barrier layer 670. Specifically, the etch-back process can be performed to an etch depth slightly above the interface between the tunnel barrier layer 670 and the first magnetic layer 650. For example, the remaining gap fill dielectric material 680 can be at an etch depth several nanometers above the upper surface of the tunnel barrier layer 670. Thus, the tunnel barrier layer 670 is not exposed to the etch-back process. However, it will be understood that some embodiments involving a conformal deposition process may not require this etch-back or planarization process.

[0066] Returning to FIG. 5, at block 530 of process 500, ion beam etching is performed to remove at least a portion of the gap fill dielectric material and conductive material deposited on the sidewalls of the patterned MRAM stack. The ion beam etching after forming the gap fill dielectric material over the lower layer functions to clean the sidewalls of the patterned MRAM stack. The ion beam etching for cleaning the sidewalls of the patterned MRAM stack can remove the gap fill dielectric material down to an etching depth below the depth of the tunnel barrier layer. In some embodiments, the etching depth below the depth of the tunnel barrier layer does not reach the depth of the lower layer. The ion beam etching for cleaning the sidewalls of the patterned MRAM stack may also be referred to as "over-etching", "trim etching", "IBE trim etching", "sidewall cleaning etching", or "low power trim etching".

[0067] The material deposited on the sidewalls of the patterned MRAM stack can include a metal or a conductive material. The metal or conductive material can be sputtered when the main etching is performed at block 510 and can be redeposited on the sidewalls of the patterned MRAM stack. In other words, after the main etching, materials that may be damaged by backsputtering can be located on the sidewalls of the patterned MRAM stack. In some embodiments, some metals can include W, Ta, Ti, or TiN from the hard mask layer or the electrode layer, and some metals can include Co, Ni, Pt, or Fe from the first or second magnetic layer. The metal or conductive material can form unwanted residues on the sidewalls of the patterned MRAM stack and may degrade the electrical and magnetic properties of the MTJ stack. Ion beam etching is performed at block 530, and the ion beam etching is performed at an optimized incident angle with low power to remove the unwanted residues.

[0068] In the case of ion beam etching to remove the material redeposited on the sidewalls of the patterned MRAM stack, a gas mixture containing an inert gas can be used to generate an ion beam from an ion beam source chamber. In some embodiments, the gas mixture can include one or more reactive gases to increase the etching of the material by chemical / reactive components. In some embodiments, the gas mixture does not contain or substantially does not contain reactive gases. Ion beam etching to remove the material redeposited on the sidewalls of the patterned MRAM stack can be performed at a relatively low voltage. In some embodiments, the etching to remove the material redeposited on the sidewalls of the patterned MRAM stack can include applying an ion beam having an energy of about 20 eV to about 400 eV to the substrate. IBE trim etching can be performed at a low ion energy to remove unwanted residues as compared to the main etching. In some embodiments, the IBE trim etching can be performed for about 1 minute or more, 3 minutes or more, 5 minutes or more, or 10 minutes or more. In some embodiments, the IBE trim etching can be performed alternately in the first and second directions, with or without rotation of the substrate. Low ion energy is desirable for trimming to reduce the effect of ion-induced mixing of the MTJ layer.

[0069] In some embodiments, IBE trim etching can be performed with an ion beam etching apparatus such as the ion beam etching apparatus described in FIG. 3. IBE trim etching may be performed following gap fill, following planarization, or following etch back. In some embodiments, IBE trim etching and gap fill can be performed by an integrated tool or a multi-station processing tool. The operations of gap fill at block 520 and IBE trim etching at block 530 can be performed without introducing a vacuum break during the operations. In some embodiments, the operations of main etching at block 510, gap fill at block 520, and IBE trim etching at block 530 can be performed without introducing a vacuum break during the operations.

[0070] It is preferred that metals and other conductive materials are not exposed during IBE trim etching. Since the remaining gap fill dielectric material functions as an etching front during IBE trim etching, the backsputtering of the metal or conductive material is significantly reduced. Instead, using the etching front of the gap fill dielectric material does not adversely affect the electrical and magnetic properties of the MTJ stack. IBE trim etching can remove the gap fill dielectric material to an etching depth below the interface between the tunnel barrier layer and the second magnetic layer without etching the underlying layer. This maintains the initial etching front from the main etching at block 510 and prevents dents or significant dents in the underlying layer.

[0071] In some embodiments, IBE trimming removes material deposited on the exposed sidewalls of the patterned MRAM stack. The exposed sidewalls of the patterned MRAM stack do not include, or substantially do not include, metal or conductive material deposited on the sidewalls of the patterned MRAM stack. The threshold when the sidewalls are considered clean enough can be set by the short - circuit performance of the MRAM device. This is measured as the ratio of devices that short - circuit among all devices. Typically, only one device or less per million will short - circuit. Thus, the remaining residue is thin enough to minimize its impact on the off - state resistance of the MRAM device. For example, "substantially free" with respect to the redeposited conductive material can refer to a deposition thickness of less than about 1.5 nm, less than about 1.0 nm, or less than about 0.5 nm. Thus, the conductive material redeposited on the tunnel barrier layer after IBE trimming can be negligible or zero. Since IBE trimming can be performed for a time sufficient to remove unwanted material, the exposed sidewalls of the patterned MRAM stack do not include, or substantially do not include, redeposited conductive material.

[0072] FIG. 6E shows a cross-sectional schematic view of an exemplary IBE trim etching process following the etch-back process of FIG. 6D, according to some embodiments. The remaining gap-fill dielectric material 680 functions as an etch front during the IBE trim etching process. During the IBE trim etching process, an ion beam 625 is provided at a relatively low ion energy and an optimized angle of incidence to clean the sidewalls of the patterned MRAM stacks 620a, 620b. As the IBE trim etching process proceeds, the ion beam 625 removes residue 605 from the sidewalls of the patterned MRAM stacks 620a, 620b. Sputtered atoms and / or molecules 675 from the ion beam 625 can be directed towards the sidewalls of the patterned MRAM stacks 620a, 620b. However, the sputtered atoms and / or molecules 675 include dielectric material from the remaining gap-fill dielectric material 680 that does not adversely affect the properties of the patterned MRAM stacks 620a, 620b. The IBE trim etching process proceeds to an etch depth that is below the depth of the tunnel barrier layer 670 and above the lower layer 630. In some embodiments, the IBE trim etching process does not significantly proceed into the lower layer 630. The exposed sidewalls of the patterned MRAM stacks 620a, 620b are free of residue 605 that includes a conductive or magnetic material.

[0073] In some embodiments, process 500 further includes conformally depositing a encapsulation material on at least the exposed sidewalls of the patterned MRAM stack after performing IBE trim etching at block 530. The encapsulation material can include a suitable dielectric material such as silicon nitride. The encapsulation material can be deposited to prevent or minimize damage to the tunnel barrier layer that may be exposed to air.

[0074] FIG. 6F shows a cross-sectional schematic view of an exemplary encapsulation process following the IBE trimming process of FIG. 6E, according to some embodiments. The encapsulation layer 690 includes a dielectric material such as silicon nitride and is conformally deposited on the exposed surfaces of the patterned MRAM stacks 620a, 620b. The encapsulation layer 690 is conformally deposited along the sidewalls of the patterned MRAM stacks 620a, 620b and functions to at least protect the tunnel barrier layer 670 from exposure to the ambient environment.

[0075] FIG. 7 shows a block diagram of an exemplary processing system for performing a deposition and ion beam etching process, according to some embodiments. The processing system 700 can be a multi-station processing tool with one or more process stations. The processing system 700 can include an inbound load lock 702 and an outbound load lock 704, either or both of which can include a plasma generation source. A robot 706 is configured to move a substrate from a cassette loaded through a pod 708 at atmospheric pressure to the inbound load lock 702 through an atmospheric port 710. The substrate is placed on a pedestal 712 within the inbound load lock 702 by the robot 706, the atmospheric port 710 is closed, and the load lock 702 is pumped down. A chamber transfer port 716 to a processing chamber 714 is opened, and another substrate handling system 718, functioning as another robot, places the substrate on one of the processing stations 780, 782 for processing or on a loading station to the processing station 790. It should be understood that although the embodiment illustrated in FIG. 7 includes load locks, in some embodiments, the substrate may be directly introduced into the processing station.

[0076] The illustrated processing chamber 714 includes three processing stations 780, 782, and 790. The processing station 790 can be a removable module and can be suitable for processing multiple substrates at a time. In this example, the processing station 790 includes four sub-stations numbered from 1 to 4 in the embodiment shown in FIG. 7.

[0077] Each processing station (780, 782, and each of 1, 2, 3, and 4) can have a heating pedestal and a gas line inlet. It should be understood that in some embodiments, each processing station can have different purposes or multiple purposes. For example, in some embodiments, processing station 780 can be used to deposit a gap-fill dielectric material on a substrate, and the deposition technique can be CVD, PECVD, or other suitable deposition techniques. In some embodiments, processing station 782 can be used to perform main etching by IBE, and processing station 790 can be used to perform IBE trim etching. In some other embodiments, processing station 790 may be used to perform both main etching and ion beam etching for IBE trim etching. Processing station 782 can be used to perform CMP, selective etch back, or other processes such as CVD / PECVD / PVD. In some embodiments, processing station 790 can have multiple sub-stations 1 to 4 for performing multiple IBE trim etching processes or other processes. IBE trim etching may take longer than main etching and deposition processes. The illustrated processing station 790 includes four sub-stations, but it should be understood that the processing stations according to the present disclosure can include any suitable number of sub-stations. In addition, although the processing system 700 includes three processing stations (780, 782, and 790), it should be understood that in some embodiments, since each station can be a removable or modifiable module, the apparatus can include more or fewer than three stations. For example, in some embodiments, processing system 700 can have four or more stations, but in some other embodiments, processing system 700 can have two or fewer stations. In some embodiments, an additional processing station can be used to perform a planarization process such as CMP.In some embodiments, an additional processing station can be used to perform selective etch-back to remove the gap-fill dielectric material.

[0078] In some embodiments, the processing system 700 can be an integrated multi-station processing tool for performing IBE (main etching and trim etching) and CVD / PECVD / PVD. For example, the processing stations 780, 782, and 790 can be used to perform main etching, gap-fill, trim etching, and encapsulation operations. The main etching, gap-fill, trim etching, and encapsulation operations can be performed without introducing a vacuum break during the operations. Additional operations such as planarization (e.g., CMP) and / or selective etch-back (e.g., plasma etching) can be performed in a separate tool or an integrated multi-station processing tool. It should be understood that such operations can be performed in a separate tool because the tunnel barrier layer of the MTJ stack is not exposed to air or the ambient environment during planarization or selective etch-back. The tunnel barrier layer is protected by the gap-fill dielectric material during planarization or selective etch-back.

[0079] FIG. 7 shows a substrate handling system 718 for transferring a substrate within the processing system 700. In some embodiments, the substrate handling system 718 can transfer a substrate between various processing stations and / or between a processing station and a load lock. Additionally, the processing station 790 can include a separate substrate handling system 760 that is used to move a substrate from another loading station 762 to the processing station 790. It should be understood that any suitable substrate handling system can be used. Non-limiting examples include a substrate carousel and a substrate handling robot.

[0080] In various embodiments, the integration of various stations can address concerns about footprint reduction, and the integration of various stations can efficiently transfer substrates during operation without introducing a vacuum break. FIG. 7 also illustrates an embodiment of a system control unit 750 used to control the process conditions and hardware state of the processing system 700. The system control unit 750 can include one or more memory devices 756, one or more mass storage devices 754, and one or more processors 752. Aspects of the system control unit 750 are described above with respect to FIG. 3. Depending on one or more processing steps performed by the tool, the system control unit 950 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, proximate tools, tools located throughout the factory, the main computer, another control unit, or a tool used for material transfer to carry substrates into and out of the container of the tool at the tool location.

[0081] FIG. 8 shows an alternative block diagram of an exemplary processing system for performing deposition and ion beam etching processes, according to some embodiments. Processing system 800 includes a transfer module 803. Transfer module 803 provides a clean pressurized environment to minimize the risk of contamination of the substrate being processed as the substrate moves between various reactor modules. Mounted to transfer module 803 are multi-station reactors 807, 808, and 809, which in this context are referred to as reactors or tool modules or simply modules, each capable of performing ion beam etching and / or deposition. Reactors 807, 808, and 809 can include a plurality of stations 811, 813, 815, and 817 that can perform operations sequentially or non-sequentially according to the disclosed embodiments. Stations 811, 813, 815, and 817 can each include a heating pedestal or substrate support, one or more gas inlets or showerheads, or a distribution plate. One or more of modules 807, 808, and 809 can be capable of performing ion beam etching, which can be used to perform main etching and / or trim etching. Thus, one or more of modules 807, 808, and 809 can include an ion beam etching apparatus having an ion beam source chamber and a processing chamber, as described above with respect to FIG. 3. Another one or more of modules 807, 808, and 809 can be capable of performing deposition operations such as CVD / PECVD / PVD. Thus, the operations of main etching, gap fill, trim etching, and encapsulation can be performed without introducing a vacuum break during operation.

[0082] The processing system 800 may also include one or more substrate source modules 801, and the substrates are stored before and after processing. The atmospheric pressure robot 804 and the atmospheric transfer chamber 819 can first remove the substrate from the source module 801 and transfer it to the load lock 821. The second substrate transfer device (generally a robot arm unit) 805 within the transfer module 803 moves the substrate from the load lock 821 to a module attached to the transfer module 803 or between modules in a pressurized (e.g., vacuum) environment.

[0083] In various embodiments, the system control unit 829 is used to control the process conditions and activities during processing. The system control unit 829 typically includes one or more memory devices and one or more processors. The aspects of the system control unit 829 have been described above with respect to FIG. 3. Depending on one or more processing steps performed by the tool, the system control unit 829 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, proximate tools, tools located throughout the factory, the main computer, another control unit, or a tool used for material transfer to carry substrates into and out of the substrate container at the tool location.

[0084] FIG. 9 shows a block diagram of an exemplary processing system for performing a planarization and / or etching process according to some embodiments. The processing systems 700 and 800 can be integrated multi-station processing tools for performing ion beam etching and deposition, and can transfer substrates to the processing system 900 to perform a planarization and / or selective etching process.

[0085] The processing system 900 may include a vacuum transfer module 938 (VTM). The arrangement of transfer modules for transferring substrates between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. The airlock 930, also known as a load lock or transfer module, is shown in the vacuum transfer module 938 with four processing modules 920a, 920b, 920c, and 920d that can be individually optimized to perform various operations. By way of example, one or more of the processing modules 920a, 920b, 920c, and 920d may be implemented to perform selective etching. One or more of the processing modules 920a, 920b, 920c, and 920d may be implemented to perform a planarization process such as CMP. In some embodiments, one or more of the processing modules 920a, 920b, 920c, and 920d may be implemented to perform ion beam etching or deposition. The airlock 930 and the processing modules 920a, 920b, 920c, and 920d are sometimes referred to as "stations". Each station has a facet 936 that interfaces the station to the vacuum transfer module 938. Inside each facet 936, sensors 1 - 18 are used to detect the passage of the substrate 926 when moving between respective stations.

[0086] The robot 922 can be used to transfer the substrate 926 between stations. In one embodiment, the robot 922 has one arm, and in another embodiment, the robot 922 has two arms, and each arm has an end effector 924 for selecting a substrate such as the substrate 926 for conveyance. The front-end robot 932 within the atmospheric transfer module (ATM) 940 is used to transfer the substrate 926 from the cassette or from the front opening unified pod (FOUP) 934 within the load port module (LPM) 942 to the air lock 930. The module center 928 within the processing modules 920a, 920b, 920c, and 920d is one place for placing the substrate 926. The aligner 944 within the ATM 940 is used to align the substrate.

[0087] In an exemplary processing method, the substrate is placed in one of the FOUPs 934 within the LPM942. The front-end robot 932 transfers the substrate from the FOUP 934 to the aligner 944, whereby the substrate 926 can be properly centered before being etched or processed. After being aligned, the substrate 926 is moved into the airlock 930 by the front-end robot 932. Since the airlock module can match the environment between the ATM and the VTM, the substrate 926 can move between the two pressure environments without being damaged. From the airlock 930, the substrate 926 is moved by the robot 922 through the vacuum transfer module 938 to one of the processing modules 920a, 920b, 920c, and 920d. To achieve this movement of the substrate, the robot 922 uses the end effector 924 on each of its arms. When the substrate 926 is processed, the substrate 926 is moved from the processing modules 920a, 920b, 920c, and 920d to the airlock 930 by the robot 922. From here, the substrate 926 can be moved by the front-end robot 932 to one of the FOUPs or the aligner 944. The control unit described above with respect to FIG. 3 can be implemented using the tool of FIG. 9. Depending on one or more processing steps performed by the tool, the control unit may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, proximate tools, tools located throughout the factory, the main computer, another control unit, or the tool used for material transfer for loading and unloading the substrate container to and from the tool location.

[0088] Conclusion In the foregoing description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order not to obscure the disclosed embodiments unnecessarily. The disclosed embodiments are described in conjunction with specific embodiments, but it will be understood that the disclosed embodiments are not intended to be limiting.

[0089] The foregoing embodiments have been described in some detail for purposes of clarity of understanding, but it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Note that there are many other ways to implement the processes, systems, and apparatuses of this embodiment. Accordingly, this embodiment should be regarded as illustrative and not restrictive, and those embodiments should not be limited to the details described herein.

Claims

1. 1. A method of ion beam etching comprising the steps of: etching through a plurality of magnetoresistive random access memory (MRAM) layers disposed on a substrate to form a patterned MRAM stack, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer, and etching through the plurality of MRAM layers including ion beam etching (IBE) through at least the tunnel barrier layer; forming a gap fill dielectric material in spaces between the patterned MRAM stacks; performing an IBE trim etch to remove at least a portion of the gap-fill dielectric material and conductive material deposited on sidewalls of the patterned MRAM stack; A method comprising:

2. 2. The method of claim 1 , the gap-fill dielectric material is formed to a sufficient depth above an underlying layer disposed between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not recess the underlying layer.

3. 3. The method of claim 2, The method, wherein the sufficient depth above the underlayer is between about 1 nm and about 20 nm from a top surface of the underlayer.

4. 2. The method of claim 1 , forming the gap-fill dielectric material in spaces between the patterned MRAM stacks; depositing the gap-fill dielectric material in the spaces between and over the patterned MRAM stacks. A method comprising:

5. 5. The method of claim 4, forming the gap-fill dielectric material in spaces between the patterned MRAM stacks; Selectively etching the gap-fill dielectric material to an etch depth above a depth of the tunnel barrier layer. The method further comprising:

6. 6. The method of claim 5, planarizing the gap-fill dielectric material deposited over the patterned MRAM stack; The method further comprising:

7. The method according to any one of claims 1 to 6, The method, wherein the gap-fill dielectric material comprises silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or a combination thereof.

8. 8. The method of claim 7, The method, wherein the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide.

9. The method according to any one of claims 1 to 6, The method, wherein the operations of etching through the plurality of MRAM layers, forming the gap-fill dielectric material, and performing the IBE trim etch are performed without introducing a vacuum break between operations.

10. The method according to any one of claims 1 to 6, the plurality of MRAM layers including a first magnetic layer, a second magnetic layer, the tunnel barrier layer between the first magnetic layer and the second magnetic layer, and an underlayer disposed below the second magnetic layer, the underlayer including a dielectric material and the tunnel barrier layer including a non-magnetic insulating material.

11. 11. The method of claim 10, The method, wherein etching through the plurality of MRAM layers comprises ion beam etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer without etching through the underlayers.

12. 11. The method of claim 10, The method, wherein etching through the plurality of MRAM layers includes reactive ion etching (RIE) through the first magnetic layer and ion beam etching through the tunnel barrier layer.

13. 11. The method of claim 10, The method of claim 1, wherein etching through the plurality of MRAM layers includes etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, and wherein etching through the plurality of MRAM layers is stopped on the underlayer.

14. The method according to any one of claims 1 to 6, 11. The method of claim 10, wherein ion beam etching through at least the tunnel barrier layer comprises applying a first ion beam to the substrate having an energy of about 200 eV to about 10,000 eV, and performing an IBE trim etch comprises applying a second ion beam to the substrate having an energy of about 20 eV to about 400 eV.

15. The method according to any one of claims 1 to 6, The method, wherein performing an IBE trim etch is done without etching through an underlying layer disposed below the plurality of MRAM layers.

16. The method according to any one of claims 1 to 6, the conductive material comprises tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), nickel (Ni), iron (Fe), platinum (Pt), ruthenium (Ru), or a combination thereof, and the sidewalls of the patterned MRAM stack are substantially free of the conductive material deposited on the sidewalls of the patterned MRAM stack after performing the IBE trim etch. method.

17. The method according to any one of claims 1 to 6, conformally depositing an encapsulant material on at least the sidewalls of the patterned MRAM stack after performing the IBE trim etch. The method further comprising:

18. 1. An apparatus for performing ion beam etching, comprising: an ion beam source chamber; a process chamber coupled to the ion beam source chamber; A control unit, The control unit: disposing a plurality of MRAM layers on a substrate in the processing chamber, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer; etching through the plurality of MRAM layers disposed on the substrate to form a patterned MRAM stack, the etching through the plurality of MRAM layers including ion beam etching (IBE) through at least the tunnel barrier layer; forming a gap-fill dielectric material in spaces between the patterned MRAM stacks; and performing an IBE trim etch to remove at least a portion of the gap-fill dielectric material and conductive material deposited on sidewalls of the patterned MRAM stack; An apparatus configured to provide instructions for performing the steps of:

19. 20. The apparatus of claim 18, The controller configured to provide instructions to form the gap-fill dielectric material includes: depositing the gap-fill dielectric material in the spaces between and over the patterned MRAM stacks. The apparatus is further configured to provide instructions for performing the steps of:

20. 20. The apparatus of claim 19, The controller configured to provide instructions to form the gap-fill dielectric material includes: Selectively etching the gap-fill dielectric material to an etch depth above a depth of the tunnel barrier layer. The apparatus is further configured to provide instructions for performing the steps of:

21. 21. The apparatus of claim 20, The control unit is planarizing the gap-fill dielectric material deposited over the patterned MRAM stack prior to selectively etching the gap-fill dielectric material. The apparatus is further configured to provide instructions for performing the steps of:

22. An apparatus according to any one of claims 18 to 21, comprising: The device, wherein the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide.

23. An apparatus according to any one of claims 18 to 21, comprising: the controller configured to provide instructions to perform an IBE trim etch is further configured to apply a first ion beam having an energy between about 200 eV and about 10,000 eV to the substrate, and the controller configured to provide instructions to perform an IBE trim etch is further configured to apply a second ion beam having an energy between about 20 eV and about 400 eV to the substrate.

24. An apparatus according to any one of claims 18 to 21, comprising: the gap-fill dielectric material is formed to a sufficient depth above an underlying layer disposed between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not recess the underlying layer.

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