High-sensitivity depth sensor with non-avalanche photodetector

Abstract

To provide a high-sensitivity depth sensor with a non-avalanche photodetector.SOLUTION: A sensing device (100) includes a light source (101) to emit light, a light sensor (105) to detect reflection of the emitted light, and a distance determination circuit responsive to reflected-light detection within the light sensor. The light sensor includes a photodetector (115) having a photocharge storage capacity in excess of one electron and an output circuit (117) which generates an output signal responsive to light detection within the photodetector with latency of less than 100 nanoseconds. The distance determination circuit (119) measures an elapsed time on the basis of transition of the output signal in response to photonic detection within the photodetector and determines a distance between the sensing device and a surface which yielded the reflection of the emitted light on the basis of the elapsed time.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of U.S. Provisional Application No. 62 / 698,805, filed Jul. 16, 2018, which is incorporated herein by reference. This application also incorporates by reference U.S. Application No. 15 / 301,267 (35 USC 371(c) as of Sep. 30, 2016, now U.S. Patent No. 10,319,776), No. 15 / 555,911 (35 USC 371(c) as of Sep. 5, 2017, now U.S. Patent No. 10,283,539), and No. 62 / 676,266 (filed May 24, 2018), and International Applications No. PCT / US17 / 22607 (International filing date Sep. 15, 2018) and No. PCT / US19 / 34036 (International filing date May 24, 2019).

Background Art

[0002] (Introduction) A three - dimensional imaging device or depth sensor generally measures the time it takes for a light pulse (emitted from a light source near the sensor) to reflect back from the surface of an object for detection by the sensor, or measures the envelope attenuation in the reflection of a carrier wave used to modulate a continuous light source (the attenuation indicates a phase shift of the modulated carrier wave) to determine the depth of the object, or the distance between the sensor and the object. In both pulse - based and phase - based detection systems, the optical sensor needs to detect the reflected light and record its magnitude and / or arrival time with sufficient resolution to meet the accuracy requirements of the application. For example, an optical sensor in a pulse - based system aimed at measuring distance / depth with an accuracy of 5 mm needs to have a low light sensitivity sufficient to detect weak pulses of reflection and resolve the round - trip flight time of the light pulse to within about 33 picoseconds (ps).

Summary of the Invention

[0003] Conventional 3D imaging devices and depth sensors typically employ solid-state optical sensors (photodetectors) with electron avalanche gain, such as single-photon avalanche diodes (SPADs) and silicon photomultipliers (SiPMs). Although they are fast and highly sensitive to single photons, avalanche gain photodetectors have several drawbacks, including high dark current (i.e., noisy), single electron well capacity, low quantum efficiency (QE), low spatial resolution, and low manufacturing yield. Other more robust (i.e., having deeper photowells and / or higher QE, spatial resolution, and manufacturing yield) photodetectors have generally been avoided due to impractically long readout latencies. For example, in sensors with pin photodiodes (PPDs) read out by photocharge transfer to a floating diffusion node (such as in conventional 4-transistor imaging pixels), the charge transfer time alone is typically on the order of hundreds of nanoseconds (corresponding to distance measurement resolution in the hundreds of meters), and thus is an impractical latency for many depth sensing applications.

[0004] The disclosure herein relates to solid-state optical sensors that may be deployed in 3D imaging devices or depth sensors.

[0005] The various embodiments described herein are shown by way of example, and not as a limitation, in the figures of the accompanying drawings, in which like reference numerals refer to like elements.

Brief Description of the Drawings

[0006]

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DETAILED DESCRIPTION OF THE INVENTION

[0007] Optical sensors with multi-carrier photowell depth and sub-nanosecond readout latency (or latency below a few nanoseconds) are disclosed in various embodiments herein with corresponding embodiments of an analog front end (AFE) and a time-to-digital converter (TDC) that provide fast and / or robust signal digitization. When deployed within a depth sensor or 3D sensor, the low latency readout and multi-photon sensitivity (i.e., depth of multi-electron or multi-hole wells) combined with an improved AFE / TDC enable dramatically improved depth detection (higher sensitivity, finer resolution) compared to conventional avalanche gain sensors.

[0008] FIG. 1 shows an embodiment of a depth sensor (or 3D sensor) 100 having a light source 101 and a low latency multi-photowell optical sensor 105, i.e., an optical sensor having a photowell capable of storing multiple optical carriers (as opposed to a single optical carrier avalanche gain sensor), and generating a sensor output indicative of the accumulation of optical carriers (and thus incident photon collisions) either immediately upon the occurrence of an incident photon collision or within a few nanoseconds (or less than 1 nanosecond) from a readout pulse. Referring to the detailed view 110, for example, the optical sensor 105 includes an optional light receiving optical element for focusing inbound (reflected) light onto a low latency readout (LLR) multi-well photodetector 115, which then outputs a detection signal to a time-to-digital converter (TDC) 119 via an analog front end (AFE) 117. The TDC output is supplied to back-end processing logic (not particularly shown) within the depth sensor 100 that determines and outputs measurement data.

[0009] FIG. 2 shows, in this case, an embodiment of the low latency multi-photowell photodetector of FIG. 1 having a pin photodiode (PPD) 121 and a pin floating diffusion node (PFD) 123 interconnected by a gated channel (i.e., opened and closed by transfer gate 125). Read controller 140 asserts a transfer gate (TG) pulse at transfer gate 125 to form a charge transfer channel between the PPD and the PFD, and thus transfer the photocharge accumulated in the photodiode to the pin floating diffusion node for reading via source follower transistor 127. The pin region within the floating diffusion cancels the TG pulse feedthrough to the floating diffusion node, avoiding the relatively long floating diffusion stabilization time (delay before readout) that plagues non-pinned floating diffusion structures, and thus dramatically shortening the time between TG pulse assertion and stabilization of the output signal. In some embodiments, for example, the delay between TG pulse assertion (at the source terminal of transistor 127) and output signal stabilization is reduced from hundreds of nanoseconds to less than 100 nanoseconds, more typically less than 10 nanoseconds, or 5 nanoseconds or less (e.g., 3, 2, or 1 nanosecond, or even sub-nanosecond intervals), thereby shortening the readout latency of the photodetector by two or more orders of magnitude. The pin photodiode can be designed to have a photowell (multi-photo carrier storage well, SW) of any practical size, and the floating diffusion node can likewise be sized to provide a sufficiently high conversion gain (depending on the ratio of the capacitances of the PPD and PFD) and low input-referred readout noise to enable photon counting sensitivity. Source follower transistor 127 is named after its configuration within the source follower circuit, which is implemented by a voltage follower operation between the gate terminal (to which the pin floating diffusion node 123 is coupled) and the source terminal of the transistor.More specifically, current source 131 establishes a constant bias current through transistor 127 to cause the photodetector output at the source terminal of transistor 127 to follow the potential of the pin floating diffusion node (at the gate of transistor 127), resulting in a steady-state gate-source voltage, i.e., any change in the PFD potential appears at the source of the SF transistor and thus at the signal output AFE. Reset transistor 129 is provided to enable resetting of the PFD and PPD. When the read controller asserts a reset pulse (RST), the PFD node is returned to VDD (in this example), and when the read controller simultaneously generates RST and TG signals, both the PFD and PPD storage nodes are returned to VDD.

[0010] Continuing to refer to FIG. 2, the p+ pin region within the n+ floating diffusion can be sized as needed to reduce the TG pulse feedthrough caused by TG-FD capacitive coupling. Referring to physical cross-section 150 (showing the pin layer of the pin photodiode and the storage well (SW) components together with the pin region and capacitive storage (FD) region of the pin floating diffusion node), transfer gate 125 (implemented, for example, by doped polysilicon) is disposed on the surface oxide to enable formation of an enhancement channel within substrate 153 between the PPD and the PFD.

[0011] Figure 3 shows an exemplary detection cycle within the low-latency multi-well photodetector of FIG. 2. At the start (150) of the detection cycle, the readout controller asserts a reset pulse to reset the floating diffusion node (to VDD in this example), and then outputs a series of TG pulses to repeatedly sample the charge accumulation level within the pin photodiode. Each TG pulse enables the transfer of the collected (generated) photo-charge from the storage well of the photodiode to the pin floating diffusion node (i.e., the charge collected by the PPD since the previous TG pulse assertion is transferred to the PFD, thereby changing the PFD potential), and such charge transfer results in an output voltage step having a magnitude (dV1, dV2, dV3) corresponding to the number of transferred optical carriers. Note that, in contrast to conventional CMOS image sensors that reset the floating diffusion prior to all charge transfer events (i.e., prior to all TG pulses) (assert the RST pulse), the floating diffusion reset operation is performed only at the start of the photo-detection cycle to restore the output voltage to a relatively high value (reset value).

[0012] Within a depth sensor or 3D sensor, the AFE and TDC record the magnitude and timing of the output signal of the photodetector following each TG pulse, enabling the back-end logic / computing circuitry to generate depth measurements that depend on the time-of-flight (e.g., determining the time at which the output signal falls below a detection threshold and applying that time to the depth measurement calculation). Generally, the detection resolution is constrained by the TG pulse cycle time (tcyc), but the measurement value generation logic can interpolate between voltage decrement events of consecutive pulse cycles to perform measurements with a resolution less than tcyc (e.g., modeling a linear photon collision profile over the duration of the detection cycle and using the coefficients of that linear profile to estimate the threshold crossing within a given tcyc interval).

[0013] Figure 4 shows a photodiode reset sequence, i.e., the simultaneous assertion of the RST and TG signals during the "blind phase" which is being adjusted, that can be executed for each detection cycle or for every few detection cycles. The latter approach enables the averaging of measurements captured along different photowell filling points (i.e., potentially correcting for the non-linearity of the charge transfer operation) and amortizes the overhead of the blind phase over multiple detection cycles. In the example shown, immediately after the end of the photodiode reset operation (which can actually be an electrical shutter used to clear thermally generated carriers and / or charges generated by ambient light), an optical pulse is emitted and the output of the TG pulse train is then started shortly thereafter or immediately (i.e., depending on the minimum depth measurement).

[0014] In an alternative embodiment, the transfer gate 125 and the pin floating diffusion node 123 can be omitted from the low latency photodetector shown in FIG. 2, in which case the pin photodiode 121 continuously drives the gate of the source follower transistor 127. Such a configuration results in a relatively instantaneous output in response to photon detection since the charge transfer operation is not required and can thus be applied to time-critical systems where the sensitivity requirements are relaxed.

[0015] FIG. 5 shows an alternative embodiment of the low latency multi-photowell photodetector shown in FIG. 1 having a JFET-based device 201 that in this case doubles as a multi-well photodiode (PD) 203 and a source follower transistor 205 for driving downstream signal processing logic. As shown in cross-sectional view 220, the source and channel of the depletion mode JFET are implemented over a dual-region n-doped storage well (i.e., having an n-doped region 221 and a less highly n-doped region 223), while the transistor drain is implemented over a p-type substrate in which the dual-region storage well is formed. The pn junction between the p-type substrate and the n-type storage well effectively constitutes the placement of the photodiode below the JFET (i.e., a stacked JFET / PD structure). From a functional perspective, the drain of the JFET is internally connected to the substrate and biased to VSS (the connection is not shown), while the source of the JFET is coupled to a constant current source 215 (which itself is coupled between VDD and the JFET source terminal). When a photon collision results in electron-hole pairs in the silicon, the electrons (photocharges) are collected by the storage well and accumulated in the more highly n-doped region (221) surrounding the JFET channel, modulating the electrostatic potential of the storage well and thus modulating the width of the depletion region in the channel, as indicated by the dashed depletion profile at 230, effectively varying the channel resistance. Since the current flowing through the channel is kept constant by the current source 215, the voltage at the source of the JFET follows the potential of the storage well (i.e., when the detector is biased within the saturation range) and thus varies in proportion to the number of photons absorbed.

[0016] The JFET-based detector of FIG. 5 offers several advantages compared to the pin photodiode detection scheme. One is that since the absorbed photons result in an instantaneous voltage change in the detector output, charge transfer operations are not required, enabling higher time resolution and thus more accurate depth measurements. Also, the JFET-based detector exhibits a higher conversion gain and lower input-referred readout noise than MOSFET-based detectors (e.g., pin photodiode-based detectors) because the parasitic capacitance and voltage noise from the source follower are further reduced, which can enable single-photon sensitivity.

[0017] FIG. 6 shows an exemplary operation sequence within the JFET-based photodetector of FIG. 5. First, during the blind phase, an electrical shutter is applied by applying a positive bias to the reset gate, i.e., element 211 in FIG. 5 (i.e., assert RST to switch on), to clear (reset to VDD) the storage well of the photodiode. At the end of the blind phase, an optical pulse is emitted to initiate the depth sensing (and / or 3D imaging) operation. Subsequently, each photon collision results in the capture of photoelectrons in the storage well and thus, as shown at 251, a decrement in the output voltage. The timing and magnitude of the output voltage change are recorded by subsequent readout electronics (AFE / TDC circuitry), enabling the generation of depth / distance / proximity measurements within the backend processing logic.

[0018] FIG. 7 shows an exemplary top view and cross-sectional view of a p-type JFET transistor vertically stacked on a photodiode, as in the detector of FIG. 5. In the illustrated embodiment, the JFET-based detector includes a pair of (p+) type highly doped source and drain regions, an n-type doped storage well (SW) for collecting and storing photoelectrons, a p-type doped channel interconnecting the source and drain regions, and an oxide-filled isolation trench (implemented using, for example, shallow trench isolation (STI) technology, implantation-based isolation, etc.) for separating the source region from the p-type substrate. The reset transistor is physically coupled to the n-type region of the storage well to cause a reset operation in the storage well, the reset drain is always biased at a positive voltage higher than the threshold voltage of the transistor (e.g., VDD), and the reset operation can be asserted by applying a positive bias to the reset gate. In an alternative embodiment, the JFET-based detector is implemented with an n-type channel, while reversing the doping polarity of each region while maintaining the relative doping concentration.

[0019] Figures 8 and 9 show alternative JFET-based photodetector circuits. In the embodiment of FIG. 8, gate-less reset is achieved using punch-through diodes 281, 283. The punch-through diodes form an npn junction with the n-type doped well of the photodiode. It performs the reset operation of the photodiode by applying a positive pulse to the reset drain n-well. Compared with the conventional reset transistor approach, the parasitic capacitance between the reset gate and the voltage output node (e.g., the photodiode or the floating diffusion) is reduced, so that the conversion gain is increased and the input-referred readout noise is reduced. (Gate-less reset can be implemented using or the gated reset configuration shown in FIG. 5) In the embodiment of FIG. 9, the JFET is biased to function as a common-source amplifier (instead of the common-drain source follower configuration shown in FIG. 5) to increase the gain of the detector. More specifically, a constant current source is coupled between the drain and VSS (which can be grounded) to bias the JFET drain potential, while a resistance control transistor 291 (RES) is coupled between the JFET source and VDD to bias the JFET source terminal.

[0020] As described above, avalanche gain photodetectors such as SPADs and SiPMs have only a single electron (photon) well capacitance and thus saturate after each detected photon and need to be reset before the next detection. The limited capacitance limits the functionality of the detector. For example, when the full well capacitance (FWC) is greater than one electron, as in the case of the pin photodiodes and JFET-based photodetectors described above, optical intensity information can be acquired during the detection cycle and used for more informative / descriptive measurements, such as detecting the reflectance coefficient and texture of the detected object. More specifically, the pin photodiodes and JFET-based photodetectors described herein are implemented with a well capacitance far exceeding a single photoelectron, e.g., 2, 3, 5, 10, 100, 1000, or more photoelectron well depths or more (or any well depth between these limits) and thus can result in an output signal that varies gradually over the course of a given detection cycle (e.g., as shown in FIGS. 3 and 6). In some embodiments, an AFE and TDC capable of capturing arrival time and intensity information within the detection cycle corresponding to consecutive photon reception events (including events or sub-intervals in which two or more photoelectrons are captured) occurring prior to detector saturation are coupled with such multi-well low latency photodetectors to enable high-speed readout of such in-cycle information.

[0021] In some embodiments of the sensor system, a high-bandwidth and low-noise gain stage is implemented within an analog front end (AFE) that amplifies the low-latency photodetector output signal and prepares the signal for high-speed digitization, enabling high-sensitivity / high-resolution depth measurement that exploits additional detection data made available by the multi-carrier photowell. In general, the required AFE gain is application-specific and depends on the detector's conversion gain and the depth of the photowell. For applications that require relatively low time resolution and high sensitivity (i.e., long-range / high-spatial-resolution depth measurement), for example, a low-latency CMOS photodetector with very low readout noise (e.g., a CMOS photodetector having a pin region within a floating diffusion as described above) and a pump gate jot (i.e., as described in U.S. Application No. 15 / 301,267) can be used. A charge transfer amplifier (CTA) can be used to read out these photodetectors (pixels). A stack structure can also be used to increase the bandwidth of the in-pixel amplifier. For example, a cluster parallel architecture can be implemented as described in International Application PCT / US17 / 22607. In any case, after amplification by the analog front end, the output signal of the photodetector can be buffered (if necessary) by one or more inverters and applied to a TDC (e.g., a counter and circuitry for latching the counter output when an AFE output exceeding a predetermined or programmed threshold is detected).

[0022] Figure 10 shows an embodiment of an AFE / TDC having a parallel amplification path with a decreasing gain for triggering the latch operation in each register with each photon detection count, i.e., latching the output of the global counter 310 and thus the measured value of the time generated. For example, when coupled between a photodetector having a 1 mV / e conversion gain and registers 311, 313, 315 having a trigger threshold of 300 mV (i.e., a latch signal of 300 mV or more triggers the latch operation in the register, thereby recording the global count at the time of triggering), the gains of amplifiers 321, 323, 325 are set to 300 times (300 volts per volt or 300 V / V), 150 times, and 100 times, respectively. By this operation, single photon detection (collection of a single photoelectron in the photodiode storage well) generates a latch trigger signal (300 mV) at the latch input 311 via the amplifier stage 321 to capture the time of the detection event (i.e., latch the output of the global counter in response to the first photon detection). The lower gain levels in amplifier stages 323 and 325 result in output signals (150 mV and 100 mV) below the threshold at the latch inputs of registers 313 and 315, so those registers remain ready and are available to latch subsequent global count values. Thus, when a second photon is detected, the output signal of the photodetector doubles from 1 mV to 2 mV, thus resulting in an output of 300 mV from amplifier stage 323, triggering a count-latch operation in register 313 to capture the time (global count) of the second photon detection event. When a third photon is detected, the photodetector increments by another 1 mV (to 3 mV), resulting in an output of 300 mV from amplifier stage 325, thus latching the global count (and the time of detection of the third photon) in register 315. In an alternative embodiment, additional AFE gain stages and TDC registers may be provided to generate a TDC output for subsequent photon detection events up to the well depth (saturation level) of the photodetector (capture of global count values).Also, an optical sensor having an array of photodetectors (pixels within the array) may include a corresponding array of the AFE / TDC units shown in FIG. 10 (a single global counter may be provided to provide an elapsed time count for the entire array).

[0023] FIG. 11 shows an alternative AFE / TDC embodiment where a single amplifier stage outputs an amplified photodetector output signal to the latch inputs of registers having respective progressively increasing latch thresholds. Continuing with the exemplary 1 mV / e conversion gain photodetector, an amplifier stage 325 having a 100 V / V gain drives the latch inputs of registers 341, 343, and 345 having latch trigger thresholds of 50 mV, 150 mV, and 250 mV, respectively. With this configuration, single photon detection generates a 100 mV amplifier output and thus triggers the count-latch operation in register 341 (i.e., the 100 mV output from amplifier 325 exceeds the 50 mV latch threshold of register 341 but does not exceed the 150 mV and 250 mV thresholds of registers 343 and 345). Detection of a second photon latches the output of global counter 311 in register 343 (i.e., amplifier 325 generates a 200 mV output that exceeds the 150 mV latch threshold of register 343), and detection of a third photon latches the global count in register 345 (i.e., 300 mV output from the amplifier > 250 mV latch threshold of register 345). Similar to the embodiment of FIG. 10, in the alternative embodiment, additional TDC registers having progressively increasing latch thresholds may be provided to generate a TDC output for subsequent photon detection events up to the well depth (saturation level) of the photodetector (capture of global count values). Also, an optical sensor having an array of photodetectors may include a corresponding array of the AFE / TDC units shown in FIG. 11 (however, a single global counter may be provided to provide an elapsed time count for the entire AFE / TDC array).

[0024] The AFE / TDC circuits shown in FIGS. 10 and 11, particularly the amplifier stage(s), may be implemented in a stacked process to increase the responsivity of the photodetector IC and / or decrease the length (and thus the parasitic capacitance) of the photodetector output line (e.g., column output line), thereby increasing the bandwidth of the AFE / TDC circuit. In such a stacked multi-well (non-avalanche) depth sensing sensor, all or any part of the readout circuit (including the AFE / TDC) may be co-located on the same integrated circuit chip as the photodetector cell(s). Alternatively, the readout circuit may be disposed in whole or in part on a logic chip bonded or otherwise attached within a stacked configuration having a sensor chip carrying the photodetector cells (e.g., wafer bonding of a first wafer including the readout circuit and a second wafer including the photodetector, followed by singulation into a two-die stack where the exposed outer surface of the photodetector chip forms the back-illuminated surface).

[0025] The various detectors, readout circuits, and physical configurations disclosed herein can be described using computer-aided design tools and represented (or displayed) as data and / or instructions embodied in various computer-readable media, from the perspective of their operations, register transfers, logic components, transistors, layout geometries, and / or other characteristics. File and other object formats that can implement such circuit representations include, but are not limited to, formats that support behavioral languages such as C, Verilog, and VHDL, formats that support register-level description languages such as RTE, formats that support geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES, and any other suitable formats and languages. Computer-readable media in which such formatted data and / or instructions can be embodied include, but are not limited to, various forms of computer storage media (e.g., optical, magnetic, or semiconductor storage media, whether so independently distributed or stored "in situ" within an operating system).

[0026] When received within a computer system via one or more computer-readable media, such data- and / or instruction-based representations of the above-described circuits are processed in conjunction with the execution of one or more other computer programs, including but not limited to a netlist generation program, a placement and routing program, etc., by a processing entity (e.g., one or more processors) within the computer system to generate a display or image of a physical representation of such a circuit. Thereafter, such a display or image can be used in device manufacturing, for example, by enabling the generation of one or more masks used to form the various components of the circuit in a device manufacturing process.

[0027] The foregoing description and the accompanying drawings include specific terms and drawing symbols to provide a complete understanding of the disclosed embodiments. In some cases, the terms and symbols may imply details that are not necessary to implement those embodiments. For example, any of a particular threshold level, amplification level, conversion gain, number of components, interconnection topology, sensor implementation, components, etc. may be different from the above in alternative embodiments. A signal path depicted or described as an individual signal line may instead be implemented by a multi-conductor signal bus, and vice versa, and may include multiple conductors for each transmitted signal (e.g., differential or pseudo-differential signaling). The term "coupled" is used herein to represent direct connection as well as connection through one or more intervening functional components or structures. Device configuration or programming can include, for example, but not limited to, loading control values into registers or other storage circuits within an integrated circuit device in response to host instructions (thus controlling the operating mode of the device and / or establishing the device configuration), and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also referred to as strapping) to establish a particular device configuration or operating mode of the device (e.g., amplification factor, latch threshold, etc.). The terms "exemplary" and "embodiment" are used to represent examples rather than preferences or requirements. Also, the terms "may" and "can" are used interchangeably to indicate optional (permissible) subject matter. The absence of either term should not be construed to mean that a given feature or technique is required.

[0028] Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of the present disclosure. For example, the features or aspects of any embodiment can be applied in combination with, or instead of, the corresponding features or aspects of any other embodiment. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a limiting sense.

Claims

1. 1. A sensing device comprising: a light source for emitting light; an optical sensor for detecting reflection of the light emitted by the light source, the optical sensor comprising: a photodetector having a photocharge storage capacity of greater than one electron; and an output circuit for generating an output signal in response to detection of a photon in the photodetector in reflection of the light emitted by the light source, the output signal transitioning between voltage levels within 100 nanoseconds of the photon detection; a circuit for measuring an elapsed time based on a transition of the output signal in response to the photon detection, and a circuit for determining a distance between the sensing device and a surface that caused a reflection of the light emitted by the light source based on the elapsed time.

2. 2. The sensing device of claim 1, wherein the circuitry for measuring the elapsed time comprises circuitry for measuring the elapsed time between emission of the light from the light source and a transition in the output signal in response to the photon detection.

3. 3. The sensing device of claim 2, wherein the light source for emitting light comprises a light source that emits a pulse of light, and the circuit for measuring the elapsed time comprises circuitry for measuring the elapsed time between emission of the pulse of light from the light source and a transition in the output signal in response to the photon detection.

4. 3. The sensing device of claim 2, wherein the circuit for measuring the elapsed time comprises a counter that increments or decrements a count output over time in response to transitions of a clock signal, and a latch circuit for latching the output of the counter in response to transitions between voltage levels of the output signal.

5. 2. The sensing device of claim 1, wherein the output circuit for generating the output signal in response to a photon detection, the output signal transitioning between voltage levels within 100 nanoseconds of the photon detection, comprises circuitry for causing the output signal to transition between voltage levels within 10 nanoseconds of a photon detection in a photodiode of the photodetector.

6. 2. The sensing device of claim 1, wherein the photodetector comprises a pin photodiode, a floating diffusion node having a pin region therein, and a transfer gate to enable formation of a conductive channel between the pin photodiode and the floating diffusion node.

7. 7. The sensing device of claim 6, wherein the output circuit comprises a metal-oxide-semiconductor (MOS) transistor having a gate terminal coupled to a floating diffusion node and a signal output terminal for generating a voltage transition in response to a change in potential of the floating diffusion node as the output signal that transitions between voltage levels within 100 nanoseconds of photon detection.

8. 2. The sensing device of claim 1, wherein the photodetector comprises a photodiode having a photowell, and the output circuit comprises a junction field effect transistor (JFET) having a channel disposed adjacent to the photowell of the photodiode.

9. 9. The sensing device of claim 8, wherein the JFET comprises doped source and drain regions electrically exposed at a surface of a semiconductor substrate and interconnected by a conductive channel, and the photodiode extends deeper below the surface of the semiconductor substrate below the conductive channel.

10. 10. The sensing device of claim 9, wherein the conductivity of the conduction channel of the JFET changes as photocharge accumulates in the photowell of the photodiode.

11. 9. The sensing device of claim 8, wherein the JFET comprises doped source and drain regions electrically exposed at a surface of a semiconductor substrate and interconnected by a conductive channel, and the photodetector further comprises an oxide trench for electrically isolating the JFET from the semiconductor substrate.

12. 2. The sensing device of claim 1, wherein the output circuitry for generating the output signal comprises circuitry for generating an output signal that transitions between voltage levels within 5 nanoseconds of detecting a photon of reflection of the light emitted by the light source.

13. 2. The sensing device of claim 1, wherein the output circuitry for generating the output signal comprises circuitry for generating an output signal that transitions between voltage levels within 1 nanosecond of photon detection of a reflection of the light emitted by the light source.

14. 2. The sensing device of claim 1, wherein the photodetector included within the photosensor comprises a first photodetector, the photosensor additionally including a plurality of other photodetectors each having a respective storage capacity of greater than one electron, the first photodetector and the plurality of other photodetectors being arranged in a two-dimensional array.

15. 1. A method of operation in a sensing device, comprising: emitting light from the sensing device; and detecting reflections of the emitted light in a photodetector having a photocharge storage capacity of greater than one electron; generating an output signal in response to detecting a reflection of the emitted light within the photodetector, the output signal transitioning between voltage levels within 100 nanoseconds of said detection; measuring an elapsed time based on a transition of the output signal in response to detecting a photon; and determining a distance between the sensing device and a surface that caused the reflection of the light emitted by a light source based on the elapsed time.

16. The method of claim 15 , wherein measuring the elapsed time comprises measuring the elapsed time between emission of the light from the light source and a transition in the output signal in response to the photon detection.

17. 17. The method of claim 16, wherein emitting light from the sensing device comprises emitting a pulse of light from the sensing device, and generating the measurement of elapsed time comprises generating a measurement of elapsed time between emission of the pulse of light from the sensing device and detection of photons in the light detector in reflection of the emitted pulse of light.

18. 16. The method of claim 15, wherein generating an output signal in response to detecting reflected light that transitions between voltage levels within 100 nanoseconds of said detection comprises generating an output signal in response to detecting reflected light that transitions between voltage levels within 10 nanoseconds of said detection.

19. 16. The method of claim 15, wherein detecting reflections of the emitted light in the photodetector includes accumulating photocharges in a pin photodiode, and generating the output signal includes: (i) transferring the photocharges from the pin photodiode to a floating diffusion node having a pin region therein; and (ii) generating the output signal responsive to a voltage level of the floating diffusion node after transferring the photocharges from the pin photodiode to the floating diffusion node.

20. 16. The method of claim 15, wherein detecting reflections of the emitted light in the photodetector comprises accumulating photocharge in a photodiode disposed adjacent to a channel of a junction field effect transistor (JFET), and generating the output signal comprises generating the output signal at a terminal of the JFET coupled to the channel, the output signal having a voltage level responsive to an amount of photocharge accumulated in the photodiode.

21. 1. A sensing device comprising: means for emitting light; a means for detecting reflection of the emitted light, the means having a photocharge storage capacity of greater than one electron; and means for generating an output signal in response to detecting a reflection of the emitted light within the means for detecting, the output signal transitioning between voltage levels within 100 nanoseconds of the detection; means for measuring elapsed time based on a transition of the output signal in response to detection of a photon; and means for determining a distance between the sensing device and a surface that caused the reflection of the light emitted by a light source based on the elapsed time.

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