Photoresist development with halide chemistries

Abstract

SOLUTION: Development of resists are useful, for example, to form a patterning mask in the context of high-resolution patterning. Development can be accomplished using a halide- containing chemistry such as a hydrogen halide. A metal -containing resist film may be deposited on a semiconductor substrate using a dry or wet deposition technique. The resist film may be an EUV-sensitive organo-metal oxide or organo-metal-containing thin film resist. After exposure, the photopatterned metal-containing resist is developed using wet or dry development.SELECTED DRAWING: Figure 4B

Description

Background Art

[0001] [Incorporation by Reference] As part of this application, a PCT application is filed simultaneously with this specification. As confirmed in the PCT application filed simultaneously, each of the applications for which this application claims the benefit of priority is hereby incorporated by reference in its entirety for all purposes.

[0002] The manufacture of semiconductor devices such as integrated circuits is a multi-step process involving photolithography. Generally, this process includes depositing materials on a wafer and patterning the materials using lithography techniques to form the structural features (e.g., transistors and circuits) of the semiconductor device. The steps of a typical photolithography process known in the art include preparing a substrate; applying a photoresist by spin coating or the like; exposing the photoresist in a desired pattern to render the exposed areas of the photoresist, to some extent, soluble in a developer; developing by applying the developer to remove either the exposed or unexposed areas of the photoresist; and subsequently processing the areas of the substrate where the photoresist has been removed, for example, by etching or material deposition, to form features.

[0003] The evolution of semiconductor design has created a need to fabricate ever finer features on semiconductor substrate materials, and has been driven by the ability to do so. Such progress in technology is characterized by "Moore's Law," which states that the transistor density in high-density integrated circuits doubles every two years. In fact, chip design and manufacturing have advanced to the point that the latest microprocessors may include billions of transistors and other circuit functions on a single chip. Individual features on such chips may be on the order of 22 nanometers (nm) or less, and in some cases less than 10 nm.

[0004] One of the challenges in manufacturing devices with such small features is the ability to reliably and reproducibly create photolithography masks with sufficient resolution. Current photolithography processes typically use ultraviolet (UV) light at a wavelength of 193 nm to expose photoresist. The fact that light has a wavelength significantly larger than the desired size of the features created on the semiconductor substrate creates inherent problems. Achieving feature sizes smaller than the wavelength of light requires the use of complex resolution enhancement techniques such as multipatterning. Therefore, there has been great interest and research effort in developing photolithography techniques that use light with shorter wavelengths, such as extreme ultraviolet (EUV) light with a wavelength of 10 nm - 15 nm, for example 13.5 nm.

[0005] However, EUV photolithography processes can present challenges including low light output and light loss during patterning. Conventional chemically amplified resists (CARs) similar to those used in 193 nm UV lithography have potential drawbacks when used in EUV lithography. In particular, they have low absorption coefficients in the EUV region, and diffusion of photoactivated species can cause blurring or line edge roughness. Furthermore, the fine features patterned in conventional CAR materials can result in high aspect ratios that carry a risk of pattern collapse in order to provide the etching resistance necessary to pattern the underlying device layer. Therefore, there remains a need for improved EUV photoresist materials having properties such as reduced thickness, greater absorbance, and greater etching resistance.

[0006] The description of "Background Art" provided herein is intended to present a general outline of the context of the present technology. The achievements of the inventors named herein within the scope described in the "Background Art" of this specification, as well as aspects of this specification that may not be considered prior art at the time of filing, are not recognized as prior art to the present technology, either explicitly or implicitly.

Summary of the Invention

[0007] The development of a photoresist can be useful, for example, in forming a patterning mask in connection with high-resolution patterning. Development can selectively remove either the exposed or unexposed portions of the resist using a particular developer chemical. The developer chemical includes halides such as hydrogen halide, or a mixture of hydrogen and halide gas. In some embodiments, the development is dry development. In some embodiments, the resist is a photo-patterned metal-containing EUV resist. In some embodiments, the dry development process is a thermal process that does not use plasma.

[0008] Disclosed herein are a method and a system for processing a semiconductor substrate. The method for processing a semiconductor substrate includes providing a photo-patterned metal-containing resist on a substrate layer of the semiconductor substrate in a process chamber, and developing the photo-patterned metal-containing resist to form a resist mask by selectively removing a portion of the resist by exposure to a developer chemical containing a halide.

[0009] In some embodiments, the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist. In some embodiments, developing the photopatterned metal-containing EUV resist involves selectively removing, by a developing chemical, the non-EUV-exposed portion of the EUV resist relative to the EUV-exposed portion to form a resist mask. In some embodiments, the developing chemical includes hydrogen halide, hydrogen gas and halide gas, organic halide, acyl halide, carbonyl halide, thionyl halide, or a mixture thereof. In some embodiments, the developing chemical includes hydrogen fluoride, hydrogen chloride, hydrogen bromide, or hydrogen iodide. In some embodiments, developing the photopatterned metal-containing resist by exposure to the developing chemical includes dry-developing the photopatterned metal-containing resist by exposure to a dry-developing chemical. In some embodiments, dry-developing the photopatterned metal-containing resist includes applying a remote plasma containing halide radicals to the resist. In some embodiments, dry-developing the photopatterned metal-containing resist is performed at a temperature of -60°C to 120°C, a chamber pressure of 0.1 mTorr to 500 mTorr or about 0.5 Torr to about 760 Torr, and a gas flow rate of the halide of 100 sccm to 2000 sccm, and the etching selectivity of the resist mask is adjustable based at least in part on the temperature, chamber pressure, gas flow rate, or a combination thereof. In some embodiments, the temperature is -20°C to 20°C. In some embodiments, the photopatterned metal-containing resist includes an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. In some embodiments, the method further includes exposing the photopatterned metal-containing resist to an inert gas plasma after developing the photopatterned metal-containing resist.In some embodiments, the method further includes non-selectively removing the metal-containing EUV resist film from the semiconductor substrate without removing the substrate layer before providing the photopatterned metal-containing resist on the semiconductor substrate.

[0010] Disclosed herein is an apparatus for resist development. The apparatus includes a process chamber having a substrate support, a vacuum line coupled to the process chamber, and a developer chemical line coupled to the process chamber. The apparatus further includes a controller configured to have instructions for processing a semiconductor substrate, the instructions including code for providing a photopatterned metal-containing resist on a substrate layer of the semiconductor substrate within the process chamber, and code for developing the photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the resist by exposure to a developer chemical containing a halide.

[0011] In some embodiments, the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist, and the controller is configured with instructions that include code for developing the photopatterned metal-containing EUV resist, and the developing chemical selectively removes the EUV unexposed portions of the EUV resist relative to the EUV exposed portions to form a resist mask. In some embodiments, the apparatus further includes one or more heaters coupled to a substrate support, and the one or more heaters include a plurality of independently controllable temperature control zones. In some embodiments, the interior of the process chamber is coated with a corrosion inhibitor. In some embodiments, the apparatus further includes a cold trap coupled to the process chamber, and the cold trap is configured to remove water from the process chamber. In some embodiments, the apparatus further includes a UV or IR lamp coupled to the process chamber, and the UV or IR lamp is configured to cure the photopatterned metal-containing resist or remove excess halides from the process chamber.

[0012] Disclosed herein is a method of processing a semiconductor substrate. The method includes providing, within a process chamber, a dry deposited photopatterned metal oxide EUV resist on a substrate layer of a semiconductor substrate, and dry developing the photopatterned metal oxide EUV resist by selectively removing the EUV unexposed portions of the EUV resist by exposure to a dry developing chemical containing hydrogen halide to form a resist hard mask from the EUV exposed portions.

[0013] In some embodiments, the dry development is performed in a thermal process without using plasma, and the exposure to the dry developing chemical is performed at a temperature of about -20°C to about 20°C. In some embodiments, the photopatterned metal oxide EUV resist includes an organotin oxide.

[0014] These features and other features of the disclosed embodiments will be described in detail below with reference to the accompanying drawings.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0031] The present disclosure generally relates to the field of semiconductor processing. In certain aspects, the present disclosure is directed to processes and apparatuses for developing photoresists (e.g., EUV-sensitive metal-containing photoresists and / or metal oxide-containing photoresists) using halogenated chemical substances for forming patterning masks, e.g., in connection with EUV patterning.

[0032] In this specification, specific embodiments of the present disclosure are referred to in detail. Examples of specific embodiments are shown in the accompanying drawings. Although the present disclosure is described in connection with these specific embodiments, it will be understood that the present disclosure is not intended to be limited to such specific embodiments. Rather, the present disclosure is intended to cover alternative forms, modifications, and equivalents that may be included within the spirit and scope of the present disclosure. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0033] Introduction Patterning of thin films in semiconductor processing is often an important step in semiconductor manufacturing. Patterning involves lithography. In conventional lithography such as 193nm photolithography, photons from a photon source are emitted onto a mask, and a pattern is printed onto a photosensitive photoresist, causing a chemical reaction within the photoresist. After development, a pattern is formed by removing specific portions of the photoresist.

[0034] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include 22nm, 16nm, and subsequent nodes. For example, at the 16nm node, the typical width of a via or line in a damascene structure is typically about 30nm or less. The scaling of features on advanced semiconductor integrated circuits (ICs) and other devices has driven the improvement of lithography resolution.

[0035] Extreme ultraviolet (EUV) lithography can extend lithography technology by shifting to shorter imaging light source wavelengths than can be achieved with conventional photolithography methods. EUV light sources with wavelengths of about 10 to 20 nm, or 11 to 14 nm, for example 13.5 nm, can be used in state-of-the-art lithography tools, also called scanners. Since EUV radiation is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor, it operates in a vacuum.

[0036] EUV lithography utilizes EUV resist patterned to form a mask for use in etching underlying layers. The EUV resist can be a polymer-based chemically amplified resist (CAR) manufactured by liquid-based spin-on technology. An alternative to CAR is a metal oxide-containing film that can be directly photopatterned, which is available, for example, from Inpria (Corvallis, OR) and is described, for example, in U.S. Patent Publications Nos. 2017 / 0102612, 2016 / 021660, and 2016 / 0116839, which are hereby incorporated by reference herein with respect to the disclosure of at least photopatternable metal oxide-containing films. Such films can be manufactured by spin-on technology or dry vapor deposition. The metal oxide-containing film can be directly (i.e., without using a separate photoresist) patterned by EUV exposure in a vacuum environment, as described, for example, in U.S. Patent No. 9,996,004, issued June 12, 2018, entitled "PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS," and / or International Application No. PCT / US19 / 31618, filed May 9, 2019, entitled "METHODS FOR MAKING EUV PATTERNABLE HARD MASKS," providing a patterning resolution of less than 30 nm, and the portions of these disclosures related to at least the composition, deposition, and patterning of directly photopatternable metal oxide films are hereby incorporated by reference herein. Generally, patterning involves exposing the EUV resist to EUV radiation to form a photopattern in the resist, followed by development to remove a portion of the resist according to the photopattern to form a mask.

[0037] Also, although the present disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, it should be understood that it is also applicable to other next-generation lithography techniques. In addition to EUV including the standard 13.5 nm EUV wavelength currently used and developed, the radiation sources most relevant to such lithography generally refer to DUV (deep-UV) which uses an excimer laser light source of 248 nm or 193 nm, X-rays including EUV within the low-energy range of the X-ray range formally, and electron beams that can cover a wide energy range. The specific method may depend on the specific materials and applications used in the semiconductor substrate and the final semiconductor device. Therefore, the methods described in this application are merely examples of methods and materials that may be used in this technology.

[0038] EUV resists that can be directly photo-patterned may be composed of, or include, metals and / or metal oxides mixed in an organic component. The metal / metal oxide is very promising in terms of enhancing EUV photon adsorption, generating secondary electrons, and / or increasing the etching selectivity for the underlying layer stack and the device layer. So far, these resists have been developed using wet (solvent) techniques, in which the wafers need to be moved to a track where the wafers are exposed to the developing solvent, dried, and baked. Wet development not only limits productivity but also may cause line collapse due to surface tension and / or delamination between layers.

[0039] To overcome these problems by eliminating delamination and interface defects in the substrate, dry development techniques have been proposed. Dry development can improve performance (e.g., prevent line collapse due to surface tension and delamination in wet development) and increase throughput (e.g., by avoiding wet development tracks). Other advantages may include eliminating the use of organic solvent developers, reducing sensitivity to adhesion problems, increasing EUV absorption to improve dose efficiency, and having no solubility-based limitations. Dry development can also offer greater tunability and provide further critical dimension (CD) control and scum removal.

[0040] Dry development has unique challenges compared to wet development, including dose-to-size requirements for effective resist exposure and etching selectivity between unexposed resist material and EUV-exposed resist material. If the selectivity is not optimal, corner rounding of the PR corner may occur due to longer exposure under the etching gas, which may increase the variation in line CD in subsequent transfer etching steps.

[0041] Development of EUV Resist According to various aspects of the present disclosure, a photopatterned metal-containing photoresist is developed by exposure to a halide-containing chemical. A film containing an EUV-sensitive metal or metal oxide, such as an organotin oxide, is disposed on a semiconductor substrate. The film containing an EUV-sensitive metal or metal oxide is directly patterned by EUV exposure in a vacuum environment. A developer chemical is then used to develop the pattern to form a resist mask. In some embodiments, the developer chemical is a dry developer chemical. In some embodiments, the dry developer chemical includes hydrogen and a halide. Such dry development techniques may be performed while flowing a dry developer chemical of hydrogen and a halide and using either a gentle plasma (high pressure, low power) or a thermal process. The present disclosure provides a process and apparatus configured to develop a metal-containing resist as part of a resist mask formation process. Various embodiments include combinations of all dry operations by vapor deposition, EUV lithography patterning, and dry development. Various other embodiments include combinations of wet and dry processing operations, for example, spin-on EUV photoresist (wet process) may be combined with dry development or other wet or dry processes as described herein. Also described are various post-deposition (or post-application) processes such as bevel and backside cleaning, chamber cleaning, descumming, planarization, curing to change and enhance film characteristics, and photoresist rework processing.

[0042] FIG. 1 shows a flow diagram of an exemplary method of depositing and developing a photoresist according to some embodiments. The operations of process 100 may be performed in a different order and / or with different, fewer, or additional operations. Aspects of process 100 may be described with reference to FIGS. 2A-2C, 3, and 4A-4B. One or more operations of process 100 may be performed using the apparatus described in any one of FIGS. 12-15. In some embodiments, the operations of process 100 may be implemented, at least in part, in accordance with software stored on one or more non-transitory computer-readable media.

[0043] In block 102 of process 100, a layer of photoresist is deposited. This may be either a dry deposition process such as a vapor deposition process or a wet process such as a spin-on deposition process.

[0044] The photoresist may be a metal-containing EUV resist. A film containing an EUV-sensitive metal or metal oxide may be deposited on a semiconductor substrate by any suitable technique including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, the processes described have been demonstrated for EUV photoresist compositions based on organotin oxides and are applicable to both those commercially spin-coatable formulations (e.g., available from Inpria Corp (Corvallis, OR)) and those applied using the dry vacuum deposition techniques further described below.

[0045] The semiconductor substrate may include any material structure suitable for photolithography processing, particularly suitable for the manufacture of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer, on which features having an irregular surface topography are fabricated ("underlying features"). As referred to herein, "surface" is the surface on which the film of the present disclosure will be deposited, or the surface that will be exposed to EUV during processing. The underlying features may include regions where material has been removed (e.g., by etching) or regions where material has been added (e.g., by deposition) during processing prior to performing the method of the present disclosure. Such pretreatment may include the method of the present disclosure or other processing methods in an iterative process in which two or more layers of features are formed on the substrate.

[0046] An EUV-sensitive thin film may be deposited on the semiconductor substrate, and such a film can be used as a resist for subsequent EUV lithography and processing. Such an EUV-sensitive thin film undergoes changes such as the loss of bulky pendant substituents bonded to metal atoms in a low-density M-OH-rich material when exposed to EUV, enabling crosslinking to a higher-density M-O-M-bonded metal oxide material. EUV patterning forms regions of the film with changed physical or chemical properties compared to the unexposed regions. These properties can be utilized in subsequent processing to, for example, dissolve either the unexposed region or the exposed region, or selectively deposit material on either the exposed region or the unexposed region. In some embodiments, under the conditions under which such subsequent processing is performed, the unexposed film has a more hydrophobic surface than the exposed film. For example, the removal of material may be performed by exploiting differences in chemical composition, density, and crosslinking of the film. The removal may be performed by wet processing or dry processing, as further described below.

[0047] In various embodiments, the thin film is an organometallic material, such as an organotin material containing tin oxide or other metal oxide materials / portions. The organometallic compound can be formed by a gas-phase reaction of an organometallic precursor and a reactant. In various embodiments, the organometallic compound is formed by mixing a specific combination of an organometallic precursor having a bulky alkyl group or fluoroalkyl group and a reactant, and polymerizing the mixture in the gas phase to produce a low-density EUV photosensitive material that is deposited on a semiconductor substrate.

[0048] In various embodiments, the organometallic precursor contains at least one alkyl group for each metal atom that can withstand a gas-phase reaction, while the ligand or ion coordinated to the metal atom can be replaced by a reactant. The organometallic precursors include those having the following chemical formulas. M a R b L c (Formula 1) Wherein M is an element having a high patterning radiation absorption cross-section; R is alkyl, such as C n H 2n+1 and preferably n≧2; L is a ligand, ion, or other moiety that reacts with the reactant, and a≧1, b≧1, and c≧1.

[0049] In various embodiments, M has an atomic absorption cross-section of 1x10 7 cm 2 / mol or more. M may be selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, M is tin. R may be fluorinated, for example, having the chemical formula C n F x H (2n+1)has. In various embodiments, R has at least one beta hydrogen or beta fluorine. For example, R may be selected from the group consisting of ethyl, i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec-butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L may be any moiety that is readily replaced by a reactant to produce an M-OH moiety, such as a moiety selected from the group consisting of amines (dialkylamino, monoalkylamino, etc.), alkoxy, carboxylic acid, halogen, and mixtures thereof.

[0050] The organometallic precursor may be any of a wide variety of candidates for metal-organic precursors. For example, when M is tin, such precursors include t-butyltris(dimethylamino)tin, i-butyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, i-propyl(tris)dimethylaminotin, n-propyltris(dimethylamino)tin, ethyltris(dimethylamino)tin, and similar alkyl(tris)(t-butoxy)tin compounds such as t-butyltris(t-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0051] The reactant has the ability to replace a reactive moiety, ligand, or ion (e.g., L of Formula 1 above) to bond at least two metal atoms by chemical bonding. The reactant may include water, peroxides (e.g., hydrogen peroxide), dihydroxy alcohols or polyhydroxy alcohols, fluorinated dihydroxy alcohols or fluorinated polyhydroxy alcohols, fluorinated glycols, and other sources of hydroxyl moieties. In various embodiments, the reactant reacts with the organometallic precursor by forming an oxygen bridge between adjacent metal atoms. Other potential reactants include hydrogen sulfide and hydrogen disulfide, which may crosslink metal atoms by sulfur bridges.

[0052] The thin film may include optional materials in addition to the organometallic precursor and the reactant to modify the chemical or physical properties of the film, for example, to modify the film's photosensitivity to EUV or to increase the etching resistance. Such optional materials may be introduced by doping during vapor phase formation, for example, before deposition of the thin film onto the semiconductor substrate, after deposition of the thin film, or both. In some embodiments, gentle remote H is used to replace some Sn-L bonds with Sn-H 2 Plasma may be introduced, thereby increasing the reactivity of the resist under EUV.

[0053] In various embodiments, the EUV-patternable film is fabricated and deposited on a semiconductor substrate using vapor deposition equipment and processes known in the art. In such processes, the polymeric organometallic material is formed in the vapor phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD processes that include CVD elements, for example, discontinuous ALD-like processes in which the metal precursor and the reactant are separated either in time or in space.

[0054] Generally, the method includes mixing a vapor stream of an organometallic precursor with a vapor stream of a reactant to form a polymeric organometallic material and depositing the organometallic material on the surface of the semiconductor substrate. In some embodiments, two or more organometallic precursors are included in the vapor stream. In some embodiments, two or more reactants are included in the vapor stream. As will be appreciated by those skilled in the art, aspects related to mixing and deposition of the process may be simultaneous in a substantially continuous process.

[0055] In an exemplary continuous CVD process, two or more gas streams of an organometallic precursor and a reactant source are introduced into the deposition chamber of a CVD apparatus through separate inlet paths, where they are mixed and react in the gas phase to form an agglomerated polymeric material (e.g., metal-oxygen-metal bond formation). These streams may be introduced, for example, using separate inlets or a dual-plenum showerhead. The apparatus is configured such that the organometallic precursor stream and the reactant stream are mixed within the chamber and the organometallic precursor and the reactant react to produce a polymeric organometallic material. Without limiting the mechanism, function, or utility of the present technology, the product from such a gas-phase reaction is thought to have a higher molecular weight as metal atoms are cross-linked by the reactant and then condense or deposit onto a semiconductor substrate. In various embodiments, the steric hindrance of bulky alkyl groups prevents the formation of a densely packed network and forms a smooth and porous low-density film.

[0056] The CVD process is generally carried out under reduced pressure, such as from 10 millitorr to 10 torr. In some embodiments, the process is carried out at 0.5 to 2 torr. In some embodiments, the temperature of the semiconductor substrate is below the temperature of the reactant stream. For example, the substrate temperature may be from 0 °C to 250 °C, or from ambient temperature (e.g., 23 °C) to 150 °C. In various processes, the deposition of the polymeric organometallic material onto the substrate occurs at a rate inversely proportional to the surface temperature.

[0057] In some embodiments, the EUV-patternable film is fabricated and deposited onto a semiconductor substrate using wet deposition equipment and processes known in the art. For example, the organometallic material is formed by spin-coating onto the surface of the semiconductor substrate.

[0058] The thickness of the EUV-patternable film formed on the surface of the semiconductor substrate may vary depending on the surface characteristics, the materials used, and the processing conditions. In various embodiments, the thickness of the film may range from 0.5 nm to 100 nm and may be thick enough to absorb most of the EUV light under the conditions of EUV patterning. The EUV-patternable film may be adapted to absorb 30% or more, whereby significantly fewer available EUV photons reach the bottom of the EUV-patternable film. Higher EUV absorption leads to more cross-linking and densification near the upper part of the EUV exposure film compared to the lower part of the EUV exposure film. If the cross-linking is insufficient, the resist may float or be prone to collapse during wet development, but such risks do not exist in dry development. A fully dry lithography technique can promote more efficient utilization of EUV photons by a more opaque resist film. Efficient utilization of EUV photons can occur with an EUV-patternable film with higher overall absorption, although it will be understood that in some cases the EUV-patternable film may be less than about 30%. For comparison, the maximum overall absorption of most other resist films is less than 30% (e.g., 10% or less, or 5% or less), so the resist material at the bottom of the resist film is sufficiently exposed. In some embodiments, the thickness of the film is from 10 nm to 40 nm, or from 10 nm to 20 nm. Without limiting the mechanism, function, or utility of the present disclosure, unlike wet spin coating processes in the art, the process of the present disclosure is considered to have fewer restrictions on the surface adhesion characteristics of the substrate and can thus be applied to a wide variety of substrates. Additionally, as described above, the deposited film may closely conform to the surface features, providing the advantage that a mask is formed on a substrate such as a substrate having underlying features without "filling" or planarizing such features.

[0059] In block 104, an optional cleaning process is performed to clean the back surface and / or bevel edge of the semiconductor substrate. Cleaning of the back surface and / or bevel edge can non-selectively etch the EUV resist film to evenly remove films with various levels of oxidation or crosslinking on the back surface and bevel edge of the substrate. During the application of the EUV patterning-capable film by either wet deposition or dry deposition processes, unintended deposition of resist material may occur on the bevel edge and / or back surface of the substrate. Due to the unintended deposition, unwanted particles may later move to the top surface of the semiconductor substrate and become particle defects. Moreover, this deposition on the bevel edge and back surface can cause downstream processing problems, including contamination of patterning (scanner) and development tools. Conventionally, the removal of this deposition on the bevel edge and back surface has been performed by wet cleaning techniques. In the case of spin-coated photoresist materials, this process is called edge bead removal (EBR) and is performed by directing a flow of solvent from above and below the bevel edge while the substrate is rotating. The same process can be applied to soluble organic tin oxide-based resists deposited by vapor deposition techniques.

[0060] Cleaning of the bevel edge and / or back surface of the substrate may also be a dry cleaning process. In some embodiments, the dry cleaning process uses the following gases, namely HBr, HCl, BCl 3 , SOCl 2 , Cl 2 , BBr 3 , H 2 , O 2 , PCl 3 , CH 4 , methanol, ammonia, formic acid, NF 3It involves vapor and / or plasma having one or more of HF. In some embodiments, the dry cleaning process may use the same chemicals as the dry development process described herein. For example, bevel edge and backside cleaning may use hydrogen halide development chemicals. In the backside and bevel edge cleaning process, to ensure that only the backside and bevel are removed without any degradation of the film on the surface of the substrate, the vapor and / or plasma must be limited to specific regions of the substrate.

[0061] The process conditions may be optimized for bevel edge and backside cleaning. In some embodiments, higher temperature, higher pressure, and / or a greater flow rate of reactants may lead to an increase in the etching rate. Suitable process conditions for dry bevel edge and backside cleaning depend on the photoresist film and composition and properties, with the flow rate of reactants being 100 - 10000 sccm (e.g., 500 sccm of HCl, HBr, HI, or H 2 and Cl 2 or Br 2 , BCl 3 or H 2 ), the temperature being 20 - 140 °C (e.g., 80 °C), the pressure being 20 - 1000 mTorr (e.g., 100 mTorr), the plasma power being 0 - 500 W at high frequency (e.g., 13.56 MHz), and the time being about 10 - 20 seconds. These conditions are suitable for some processing reactors, such as the Kiyo etching tool available from Lam Research Corporation (Fremont, CA), but it should be understood that a wider range of process conditions may be used depending on the capabilities of the processing reactor.

[0062] Alternatively, the dry cleaning operation may be extended to a complete photoresist removal or photoresist "rework" where the applied EUV photoresist is removed, and to semiconductor substrates prepared for photoresist reapplications such as when the original photoresist is damaged or defective. Since the photoresist rework needs to be performed without damaging the underlying semiconductor substrate, oxygen-based etching should be avoided. Instead, modified forms of the halide-containing chemicals described herein may be used. It will be understood that the photoresist rework operation may be applied at any stage during Process 100. Thus, the photoresist rework operation may be applied after photoresist deposition, after bevel edge and backside cleaning, after PAB treatment, after EUV exposure, after PEB treatment, or after development. In some embodiments, the photoresist rework may be performed for removal that is non-selective with respect to the exposed and unexposed regions of the photoresist but selective with respect to the underlying layer.

[0063] In some embodiments, the photoresist rework process involves a vapor and / or plasma having one or more of the following gases: HBr, HCl, HI, BCl 3 , Cl 2 , BBr 3 , H 2 , PCl 3 , CH 4 , methanol, ammonia, formic acid, NF 3 , HF. In some embodiments, the photoresist rework process may use the same chemicals as the dry development process described herein. For example, the photoresist rework may use a hydrogen halide development chemical.

[0064] The process conditions may be optimized for photoresist rework. In some embodiments, higher temperature, higher pressure, and / or greater flow rate of reactants may lead to an increase in the etching rate. The process conditions suitable for photoresist rework depend on the photoresist film and composition and properties, and the flow rate of reactants sufficient to completely remove the EUV photoresist is 100 - 500 sccm (e.g., 500 sccm of HCl, HBr, HI, BCl 3 , or H 2 and Cl 2 or Br 2 ), the temperature is 20 - 140 °C (e.g., 80 °C), the pressure is 20 - 1000 mTorr (e.g., 300 mTorr), the plasma power at high frequency (e.g., 13.56 MHz) is 300 - 800 W (e.g., 500 W), the wafer bias is 0 - 200 V b (higher bias can be used as the underlying substrate material is harder), and the time may be about 20 seconds to 3 minutes. These conditions are suitable for some processing reactors, such as the Kiyo etching tool available from Lam Research Corporation (Fremont, CA), but it should be understood that a wider range of process conditions may be used depending on the capabilities of the processing reactor.

[0065] In block 106 of process 100, after the deposition of the EUV-patternable film and before EUV exposure, an optional post-application bake (PAB) is performed. The PAB process may involve a combination of heat treatment, chemical exposure, and moisture to increase the EUV photosensitivity of the EUV-patternable film, thereby reducing the EUV dose required to develop a pattern in the EUV-patternable film. The PAB process temperature may be adjusted and optimized to increase the sensitivity of the EUV-patternable film. For example, the process temperature may be from about 90°C to about 200°C, or from about 150°C to about 190°C. In some embodiments, the PAB process may be performed at a pressure between atmospheric pressure and vacuum and for a process duration of about 1 to 15 minutes, such as about 2 minutes. In some embodiments, the PAB process is performed at a temperature of about 100°C to 200°C for about 1 to 2 minutes.

[0066] In block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally speaking, EUV exposure causes changes in chemical composition and crosslinking in the metal-containing EUV resist film, generating a contrast in etching selectivity that can then be utilized in subsequent development.

[0067] The metal-containing EUV resist film may then be patterned, typically under a relatively high vacuum, by exposing regions of the film to EUV light. EUV devices and imaging methods useful herein include methods known in the art. Specifically, as described above, EUV patterning results in the formation of exposed regions of the film having physical or chemical properties that have changed compared to the unexposed regions. For example, in the exposed regions, metal-carbon bond cleavage may occur, such as through the elimination of beta hydrides, leaving reactive and accessible metal hydride functional groups that can be converted to hydroxides and crosslinked metal oxide moieties via metal-oxygen bridges during a subsequent post-exposure bake (PEB) step. This process can be used to create a chemical contrast for development as a negative resist. Generally, the greater the number of beta Hs in the alkyl group, the higher the sensitivity of the film. This can also be explained in terms of weaker Sn-C bonds with more branching. Following exposure, the metal-containing EUV resist film may be baked to cause additional crosslinking in the metal oxide film. In subsequent processing, the difference in properties between the exposed and unexposed regions may be exploited, such as by dissolving the unexposed regions or depositing material on the exposed regions. For example, dry methods can be used to develop the pattern to form a metal oxide-containing mask.

[0068] Specifically, in various embodiments, the hydrocarbyl-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed regions of the imaging layer, particularly when the exposure is performed in a vacuum using EUV. However, removing the exposed imaging layer from the vacuum and introducing it into air, or controlling the introduction of oxygen, ozone, H 2 O 2 , or water, may oxidize the surface Sn-H to Sn-OH. For example, by reacting the irradiated region, the non-irradiated region, or both with one or more reagents to selectively add material to or remove material from the imaging layer, the difference in properties between the exposed and unexposed regions may be exploited in subsequent processing.

[0069] Without limiting the mechanism, function, or utility of the present technology, for example, EUV exposure at a dose of 10 mJ / cm 2 ~100 mJ / cm 2 results in cleavage of the Sn-C bond, and as a result, the alkyl substituent disappears, steric hindrance is alleviated, and collapse of the low-density film becomes possible. In addition, the reactive metal-H bond generated in the beta-hydrogen elimination reaction reacts with adjacent active groups such as hydroxyl in the film, resulting in further crosslinking and densification, and a chemical contrast can occur between the exposed and unexposed regions.

[0070] Exposing a metal-containing EUV resist film to EUV light results in a photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist includes an EUV exposure region and an unexposed region.

[0071] In block 110 of process 100, an optional post-exposure bake (PEB) is performed to further increase the contrast in the etching selectivity of the photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist is heat-treated in the presence of various chemical species to promote crosslinking in the EUV exposure region, or can simply be baked on a hot plate in ambient air, for example, at 150 °C to 250 °C for 1 to 5 minutes (e.g., 2 minutes at 190 °C).

[0072] In various embodiments, the bake strategy includes careful control of the bake environment, introduction of reactive gases, and / or careful control of the ramp rate of the bake temperature. Examples of useful reactive gases include, for example, air, H 2 O, H 2 O 2 vapor, CO 2 、CO、O 2 、O 3 、CH 4 、CH 3 OH、N 2 、H 2 、NH 3 、N 2It contains O, NO, alcohol, acetylacetone, formic acid, Ar, He, or a mixture thereof. The PEB treatment is designed to (1) promote complete evaporation of organic fragments generated during EUV exposure, (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated in the metal hydroxide by EUV exposure, and (3) promote cross-linking between adjacent Sn-OH groups to form a more highly cross-linked SnO 2 network as such. The bake temperature is carefully selected to achieve optimal EUV lithography performance. If the PEB temperature is too low, cross-linking will be insufficient, and as a result, at a given dose, the chemical contrast to development will decrease. If the PEB temperature is too high, it will suffer from adverse effects including severe oxidation and film shrinkage in the non-exposed area (in this example, the area that is removed by development of the patterned film to form the mask), and unwanted interdiffusion at the interface between the photopatterned metal-containing EUV resist and the underlying layer, both of which can cause a loss of chemical contrast and an increase in defect density due to insoluble scum. The PEB treatment temperature may be about 100 °C to about 300 °C, about 170 °C to about 290 °C, or about 200 °C to about 240 °C. In some embodiments, the PEB treatment may be carried out at a pressure between atmospheric pressure and vacuum and with a treatment duration of about 1 to 15 minutes, for example about 2 minutes. In some embodiments, the PEB heat treatment may be repeated to further increase the etching selectivity.

[0073] In block 112 of process 100, the photopatterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, the exposed area is removed (positive type) or the unexposed area is removed (negative type). In some embodiments, development may include selective deposition onto either the exposed or unexposed area of the photopatterned metal-containing EUV resist, followed by an etching operation. In various embodiments, these processes may be dry processes or wet processes. In some embodiments, development may be performed without generating a plasma. Or, development may be performed by a flow of hydrogen and halide (e.g., H 2 , and Cl 2 , and / or Br 2 ) activated at a remote plasma source or activated by exposure to remote UV radiation. The photoresist for development may include an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. This element may have a large patterning radiation absorption cross-section. In some embodiments, this element may have a large EUV absorption cross-section. In some embodiments, the metal-containing EUV resist may have an overall absorption rate exceeding 30%. In an all-dry lithography process, this results in more efficient utilization of EUV photons and enables development of a thicker and more opaque resist.

[0074] An example of a development process involves performing EUV exposure dose and post-exposure bake on an organic tin oxide-containing EUV-sensitive photoresist thin film (e.g., 10 - 30 nm thick, e.g., 20 nm thick), and then developing. The photoresist film may be deposited based on a gas-phase reaction of an organic tin precursor such as isopropyl(tris)(dimethylamino)tin and water vapor, or may be a spin-on film containing tin clusters in an organic matrix.

[0075] The photo-patterned metal-containing EUV resist is developed by exposure to a developing chemical, which is a halide-containing chemical. In some embodiments, the developing chemical comprises hydrogen and a halide, such as hydrogen halide (e.g., HBr or HCl), or hydrogen and a halogen gas (e.g., H 2 and Cl 2 ). In some embodiments, the developing chemical comprises hydrogen halide, hydrogen and a halogen gas, boron trichloride, or a combination thereof. Development of the EUV resist can be carried out by wet development using a halide-containing chemical or dry development using a hydrogen halide-containing chemical. In embodiments where the EUV resist is developed using wet development, the wet development may be combined with other wet processing operations such as wet deposition (e.g., spin-on deposition) of the metal-containing EUV resist film. Alternatively, the wet development may be combined with other dry processing operations such as vapor deposition (e.g., CVD) of the metal-containing EUV resist film. In embodiments where the EUV resist is developed using dry development, the dry development may be combined with other dry processing operations such as dry deposition (e.g., CVD) of the metal-containing EUV resist film. In alternative embodiments where the EUV resist is developed using dry development, the dry development may be combined with other wet processing operations such as wet deposition (e.g., spin-on deposition) of the metal-containing EUV resist film.

[0076] In some embodiments, the processing of the semiconductor substrate may combine all dry processes including film formation by vapor deposition, EUV lithography patterning, and dry development. In fact, each of operations 102-112 of process 100 may be a dry processing operation. Such processing operations can avoid the costs of materials and productivity associated with wet processing operations such as wet development. Dry processing can provide higher tunability and can add further critical dimension (CD) control and scum removal. Wet processing generally involves moisture and / or oxygen, which more readily leads to scum formation. Wet development is limited by solubility and cluster size, while dry development is not limited by solubility and cluster size. Wet development tends to cause problems such as pattern collapse and delamination between layers, while dry development avoids these problems. Further, by using all dry processing operations, integration within an interconnected vacuum processing chamber can be facilitated without exposure to ambient air or trace contaminants contained therein and without contamination by these. For example, the PEB heat treatment in which the exposed area undergoes further crosslinking may be performed in the same chamber as the development, although it will be understood that the PEB heat treatment may be performed in a separate chamber.

[0077] The development process can be performed by supplying a development chemical in a liquid phase or a gas phase. In some embodiments, the dry development process can be performed by using either a mild plasma (high pressure, low power) or a thermal process while flowing a hydrogen halide-containing dry development chemical such as HF, HCl, HBr, or HI. For example, dry development can be performed in a thermal process using a dry development chemical such as HCl or HBr. In some embodiments, the hydrogen halide-containing chemical can rapidly remove non-exposed materials, such that the pattern of the exposed film remains, which can be transferred to the underlying layer by a plasma-based etching process, such as a conventional etching process.

[0078] In a thermal imaging process, the substrate is exposed to a developing chemical (e.g., a Lewis acid) within a process chamber (e.g., an oven). In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a developing chemical line for delivering the developing chemical to the process chamber may be coupled to the process chamber. The process chamber may include one or more heaters for temperature control, such as a heater coupled to a substrate support within the process chamber for substrate temperature control. In some embodiments, the interior of the chamber may be coated with a corrosion-resistant film, such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene (PTFE), e.g., Teflon 1M. Such materials may be used in the thermal processes of the present disclosure without the risk of removal by plasma exposure.

[0079] In a thermal development process, a photopatterned metal-containing EUV resist is exposed to a developing chemical at a temperature optimized for the etching selectivity between the exposed and unexposed regions. When the temperature is low, the contrast of the etching selectivity may increase, and when the temperature is high, the contrast of the etching selectivity may decrease. In some embodiments, the temperature may be from about -60°C to about 120°C, from about -20°C to about 60°C, or from about -20°C to about 20°C, for example, about -10°C. The chamber pressure may be adjusted, and the chamber pressure can affect the etching selectivity between the exposed and unexposed regions during development. In some embodiments, the chamber pressure is relatively low and may be without dilution, and the chamber pressure may be from about 0.1 mTorr to about 300 mTorr, from about 0.2 mTorr to about 100 mTorr, or from about 0.5 mTorr to about 50 mTorr. In some embodiments, the chamber pressure may be from about 20 mTorr to about 800 mTorr, or from about 20 mTorr to about 500 mTorr, for example, about 300 mTorr. In some embodiments, the chamber pressure is relatively high, the flow rate is large, and may be without dilution, and the chamber pressure may be from about 100 Torr to about 760 Torr, or from about 200 Torr to about 760 Torr. The flow rate of the reactant may be adjusted, and the flow of the reactant can affect the etching selectivity between the exposed and unexposed regions during development. In some embodiments, the flow of the reactant may be from about 50 sccm to about 2000 sccm, from about 100 sccm to about 2000 sccm, or from about 100 sccm to about 1000 sccm, for example, about 500 sccm. When the flow rate is high, the flow rate of the reactant may be from about 1 L to about 10 L. The duration of the exposure may be adjusted in the thermal development process. The duration of the exposure may depend, among other factors, on how much resist is desired to be removed, the developing chemical, the amount of cross-linking in the resist, and the composition and properties of the resist. In some embodiments, the duration of the exposure may be from about 5 seconds to about 5 minutes, from about 10 seconds to about 3 minutes, or from about 10 seconds to about 1 minute.

[0080] The thermal imaging process may involve exposing a photopatterned metal-containing EUV resist to a specific halide-containing chemical substance in the gas or liquid phase. In some embodiments, the developing chemical substance includes hydrogen halide, hydrogen and halogen gas, boron trichloride, organic halide, acyl halide, carbonyl halide, thionyl halide, or a mixture thereof. The hydrogen halide may include, but is not limited to, HF, HCl, HBr, and HI. For example, the hydrogen halide may be HCl or HBr. The hydrogen and halogen gas may include, but is not limited to, a mixture of F 2 , Cl 2 , Br 2 , or I 2 mixed with hydrogen gas (H 2 ). Boron trichloride (BCl 3 ) may be used in combination with any of the aforementioned hydrogen halides or hydrogen and halogen gas. The organic halide may include C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z , where x, y, and z are values of 0 or greater. The acyl halide may include, but is not limited to, CH 3 COF, CH 3 COCl, CH 3 COBr, CH 3 COI. The carbonyl halide may include, but is not limited to, COF 2 , COCl 2 , COBr 2 , COI 2 . The thionyl halide may include, but is not limited to, SOF 2 , SOCl 2 , SoBr 2 , and SOI 2 . In some embodiments, the halide-containing chemical substance is He, Ne, Ar, Xe, and N2 It may be flowed with or without an inert gas / carrier gas such as.

[0081] The thermal development process may be carried out without plasma. By applying a non-plasma thermal approach, multiple wafers can be simultaneously batch-developed in a low-cost thermal vacuum chamber / oven, thus significantly improving productivity. However, in some embodiments, exposure to plasma may follow the thermal development process. The subsequent exposure to plasma may occur for desorption, descum treatment, smoothing, or other processing operations.

[0082] In a plasma development process, a photopatterned metal-containing EUV resist is exposed to a development chemical containing radicals / ions of one or more gases. The process chamber for processing the semiconductor substrate may be a plasma generation chamber or may be coupled to a plasma generation chamber remote from the process chamber. In some embodiments, dry development may be performed by a remote plasma. The plasma generation chamber may be an inductively coupled plasma (ICP) reactor, a capacitively coupled plasma (CCP) reactor, or a capacitively coupled plasma (CCP) reactor using equipment and techniques known in the art. An electromagnetic field acts on one or more gases to generate a plasma in the plasma generation chamber. Ions and / or radicals from the remote plasma can interact with the photopatterned metal-containing EUV resist. In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a development chemical line may be coupled to the plasma generation chamber to deliver one or more gases to the plasma generation chamber. The process chamber may include one or more heaters for temperature control, such as a heater coupled to a substrate support within the process chamber for substrate temperature control. In some embodiments, the interior of the process chamber may be coated with a corrosion-resistant film such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene (PTFE), for example, Teflon 1M. Such materials can be used in the thermal processes of the present disclosure without the risk of removal by plasma exposure.

[0083] In a plasma development process, a photopatterned metal-containing EUV resist is exposed to a remote plasma under conditions optimized for the etch selectivity between the exposed and unexposed regions. The conditions may be optimized to produce a mild plasma, which may be characterized by high pressure and low power. The chamber pressure may be adjusted, and the chamber pressure can affect the etch selectivity between the exposed and unexposed regions during development. In some embodiments, the chamber pressure may be about 5 mTorr or more, or about 15 mTorr or more. In some embodiments, the chamber pressure is relatively high, the flow rate is large, and there may be no dilution, and the chamber pressure may be about 100 Torr to about 760 Torr, or about 200 Torr to about 760 Torr. The RF power level may be adjusted, and the RF power can affect the etch selectivity, roughness, descum process, and other development characteristics. In some embodiments, the RF power may be about 1000 W or less, about 800 W or less, or about 500 W or less. The temperature may be adjusted, and the temperature can affect various aspects of development, such as etch selectivity. In some embodiments, the temperature may be about -60 °C to about 300 °C, about 0 °C to about 300 °C, or about 30 °C to about 120 °C. The gas flow rate may be adjusted, and the gas flow can affect the etch selectivity between the exposed and unexposed regions during development. In some embodiments, the gas flow rate may be about 50 sccm to about 2000 sccm, about 100 sccm to about 2000 sccm, or about 200 sccm to about 1000 sccm, for example, about 500 sccm. The duration of the exposure may be adjusted in the plasma development process. The duration of the exposure may depend, among other factors, on how much resist is desired to be removed, the development chemistry, the amount of cross-linking in the resist, and the composition and properties of the resist. In some embodiments, the duration of the exposure may be about 1 second to about 50 minutes, about 3 seconds to about 20 minutes, or about 10 seconds to about 6 minutes.

[0084] The plasma development process may expose a photopatterned metal-containing EUV resist to radicals of a specific halide-containing gas. In some embodiments, the radicals are generated from a remote plasma source. For example, plasma development may expose a photopatterned metal-containing EUV resist to radicals of hydrogen and halide gas generated from a remote plasma source. In some embodiments, the halide-containing gas includes hydrogen halide, hydrogen and halogen gas, boron trichloride, organic halide, acyl halide, carbonyl halide, thionyl halide, or a mixture thereof. The hydrogen halide may include, but is not limited to, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For example, the hydrogen halide may be HCl or HBr. The hydrogen and halogen gas may include, but is not limited to, a mixture of fluorine gas (F 2 ), chlorine gas (Cl 2 ), bromine gas (Br 2 ), or iodine gas (I 2 ) mixed with hydrogen gas (H 2 ). The organic halide may include C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z , where x, y, and z are values of 0 or more. The acyl halide may include, but is not limited to, CH 3 COF, CH 3 COCl, CH 3 COBr, and CH 3 COI. The carbonyl halide may include, but is not limited to, COF 2 , COCl 2 , COBr 2 , and COI 2 . The thionyl halide may include, but is not limited to, SOF 2 , SOCl 2, SoBr 2 , and SOI 2 can include, but are not limited to, He, Ne, Ar, Xe, and N 2 and may be flowed with or without an inert gas / carrier gas such as.

[0085] In addition to, or instead of, plasma activation, the activation of one or more gases in the dry development process can occur by photoactivation. In some embodiments, photoactivation can be achieved by exposure to ultraviolet (UV) radiation. For example, the process chamber may include a lamp, such as a UV lamp, configured to generate UV radiation. When one or more gases are exposed to UV radiation, radicals of the one or more gases may be generated, which can be used in the dry development of a photopatterned metal-containing EUV resist. The one or more gases may be exposed to UV radiation in a form where the photopatterned resist is not exposed to the UV radiation. In other words, the photopatterned resist is not visible from the UV lamp. Thus, the UV lamp may be remote from the process chamber or positioned to avoid exposure of the photopatterned resist to the UV radiation.

[0086] It will be understood that the thermal development, plasma development, and photoactivation development methods described above may be combined together. Such development methods may be applied simultaneously or sequentially. The development method may be applied while flowing the dry development chemical in a liquid phase or a gas phase, and the dry development chemical can include a compound of the formula R x Z y where R = B, Al, Si, C, S, SO, and x > 0, and Z = Cl, H, Br, F, CH 4 , and y > 0. Development can result in a positive or negative type, and the R x Z y species selectively removes either the unexposed material or the exposed material, leaving the corresponding exposed portion or unexposed portion as a mask.

[0087] As described above, the etching selectivity during dry development can be adjusted by controlling process conditions such as temperature, pressure, gas flow, gas composition, and plasma power, among other adjustable process conditions. By adjusting the etching selectivity in a single step or multiple steps, desired patterned characteristics can be achieved. In some embodiments, the etching selectivity during dry development is adjusted over one or more steps that affect the EUV resist profile. More specifically, by applying developing chemistries having different etching selectivities over one or more steps, the amount of taper or the re-entrant angle of the EUV resist profile can be controlled. The descum process, photoresist rework, curing, smoothing, and cleaning operations can also be adjusted according to the adjustable etching selectivity.

[0088] Figures 2A to 2C show schematic cross-sectional views of various processing stages of dry development according to some embodiments. The examples shown in Figures 2A to 2C show negative-type dry development. As shown in Figure 2A, wafer 200 includes substrate 202 and substrate layer 204 to be etched. In some embodiments, substrate layer 204 includes an ashing-capable hard mask such as spin-on carbon (SoC), or other materials such as silicon, silicon oxide, silicon nitride, and silicon carbide. In some embodiments, substrate layer 204 may be a layer stack disposed on substrate 202. Wafer 200 further includes a photopatterned metal-containing EUV resist film 206. For example, the photopatterned metal-containing EUV resist film 206 may be an organometal-containing layer disposed on the substrate layer 204 to be etched. The photopatterned metal-containing EUV resist film 206 may have a thickness of about 5 nm to about 50 nm, or about 10 nm to about 30 nm. The photopatterned metal-containing EUV resist film 206 may be provided in the process chamber after photopatterning with an EUV scanner and / or after PEB treatment, as described above. The photopatterned metal-containing EUV resist film 206 includes a non-EUV exposure region 206a and an EUV exposure region 206b. As shown in Figure 2B, the non-EUV exposure region 206a of the photopatterned metal-containing EUV resist film 206 can be removed in the dry development process by exposing it to a flow of dry development chemical without generating plasma. The dry development chemical may include a halide-containing chemical such as hydrogen halide, or hydrogen and halogen gas. Removal of the non-EUV exposure region 206a forms a resist mask 208 after development. Thereafter, the substrate layer 204 to be etched can be etched using the resist mask 208, resulting in the structure shown in Figure 2C.

[0089] Figure 3 shows an exemplary dry development mechanism of the chemical reaction between HBr and the exposed and unexposed portions of an EUV photoresist according to some embodiments. Although Figure 3 shows the expected dry development mechanism, it will be understood that the present disclosure is not limited by any particular mechanism, function, theory, or utility. The organometallic oxide film may have a tetrahedral coordination structure. The exposed region has a higher level of Sn-O-Sn bridging, resulting in a higher density and lower / lower reactivity with HBr or HCl. The unexposed region has a lower density due to the presence of bulky alkyl substituents that prevent the approach and condensation of Sn-OH moieties. In the unexposed region, hydrogen halide more readily protonates the more "basic" and accessible oxygen lone pairs characteristic of the more tetrahedrally coordinated organotin oxide hydroxide. Volatile by-products of RSnX3 (X = Cl or Br) are rapidly formed and removed from the unexposed region. In Figure 3, HBr selectively protonates the oxygen lone pair to form a volatile by-product of R-Sn-Br. Water is also a by-product. Removal of water can increase the reaction rate. When the alkyl group is isopropyl, at typical EUV patterning doses, at least two out of every three isopropyl substituents are removed, and as a result, after the PEB step, the exposed region condenses to form a tin structure closer to hexagonal coordination with more difficult access to oxygen atoms, resulting in a much lower reactivity with hydrogen halide and a higher density of SnO 2 such materials are formed, resulting in a much slower reactivity with hydrogen halide. In Figure 3, the exposed region has a significantly reduced dry etching rate associated with the loss of isopropyl substituents, allowing condensation to a material where more / most oxygen atoms are bonded to three (rather than two) tin atoms, and the reaction rate with HBr or HCl is significantly reduced.

[0090] In some cases, residues or scum may remain after development. The residues may be due to slower etching components in EUV resist formulations with poor homogeneity, including those applied by spin coating techniques. Such scum may contain high concentrations of metal, which may cause problems during subsequent pattern transfer.

[0091] In addition or alternatively, after development, roughness may be formed on the sidewalls of the etched features in the developed pattern. This may in part be due to the probabilistic or non-optimal Gaussian distribution of light, such that in regions where the resist must remain unexposed, the material may be partially or fully exposed.

[0092] In some embodiments, dry development may involve a descum / smoothing operation. In some embodiments, the descum process and the smoothing operation may be an inert gas plasma stripping operation. For example, the inert gas plasma stripping operation may be a helium plasma stripping operation. The inert gas plasma stripping operation may be performed after dry development or may be repeated in conjunction with dry development.

[0093] FIG. 4A shows a schematic cross-sectional view of dry development without applying an inert gas plasma according to some embodiments. The photopatterned metal-containing EUV resist film includes an exposed region and an unexposed region. As shown in FIG. 4A, particles or clusters of metal oxides (e.g., SnO x ) may occupy the unexposed region. As dry development proceeds, the clusters of metal oxides become more concentrated. The clusters of metal oxides are generally difficult to remove. Development may be selective for the removal of organic materials. After removing the unexposed region, clusters of metal oxides may remain on the substrate surface as scum. Clusters of metal oxides remaining on the sidewalls of the exposed region may lead to roughness.

[0094] Figure 4B shows a schematic cross-sectional view of a dry development iterative inert gas plasma for descum processing according to some embodiments. The first stage involves dry development that removes a substantial portion of the unexposed regions of the photopatterned metal-containing EUV resist film. The dry development chemical may include, for example, HBr. The substantial portion may represent at least more than 70% by volume, more than 80% by volume, or more than 90% by volume of the unexposed region. Clusters of metal oxides concentrate on the surface of the remaining unexposed regions of the EUV resist film. The second stage involves applying an inert gas plasma, such as a helium plasma, at low power and high ion energy for a short period of time. The helium plasma removes the clusters of metal oxides. In addition, the helium plasma removes clusters from the sidewalls and smooths the sidewalls. The helium plasma treatment may also serve to cure or cure the patterned EUV resist film to form a higher density metal oxide such as a hard mask. After the helium plasma treatment, any residues remaining in the unexposed regions of the EUV resist film can be removed using a less selective dry etching step.

[0095] In some embodiments, dry development may be repeated in combination with helium plasma treatment over one or more cycles until the unexposed regions of the EUV resist film are removed. To improve the results, the descum / smoothing of the helium plasma may be repeated in combination with dry development as described above. In this way, for example, most of the organic components in the unexposed regions of the pattern are removed by dry development, and then a portion of the metal concentrated on the surface is removed by a short period of helium plasma operation, allowing access to the remaining underlying organic material, which can then be removed in subsequent dry development operations / cycles. Another cycle of helium plasma may be used to remove any remaining metal, leaving a clean and smooth feature surface. The cycle can continue until all or substantially all of the scum and roughness residues are removed, leaving a clean and smooth feature surface.

[0096] The process conditions of the descum treatment and the smoothing operation may be controlled during or after development. In some embodiments, the flow rate of the reactant may be from about 50 sccm to about 1000 sccm, from about 100 sccm to about 500 sccm, for example, He at about 500 sccm. In some embodiments, the temperature may be from about -60 °C to about 120 °C, from about -20 °C to about 60 °C, or from about 20 °C to about 40 °C, for example, about 20 °C. In some embodiments, the chamber pressure may be from about 1 mTorr to about 300 mTorr, from about 5 mTorr to about 100 mTorr, from about 5 mTorr to about 20 mTorr, for example, about 10 mTorr. The plasma power may be relatively low when the ion energy is high. In some embodiments, the plasma power may be from about 50 W to about 1000 W, from about 100 W to about 500 W, or from about 100 W to about 300 W, for example, about 300 W. In some embodiments, the wafer bias is from about 10 V to about 500 V, from about 50 V to about 300 V, for example, about 200 V. The plasma may be generated using a high RF frequency. In some embodiments, the RF frequency is 13.56 MHz. To avoid excessive exposure to UV radiation during plasma exposure, the duration of exposure to the inert gas plasma may be relatively short. In some embodiments, the duration of exposure is from about 0.5 seconds to about 5 seconds, from about 1 second to about 3 seconds, for example, about 2 seconds.

[0097] The inert gas plasma treatment for descum treatment and cleaning of unexposed resist residues may have the secondary advantage of curing and hardening the exposed resist, thereby enhancing its hard mask function in subsequent operations for etching the underlying substrate. This resist hardening is achieved by exposing the EUV exposure resist to the UV radiation generated by the inert gas plasma, which can be continued with the bias turned off after the descum / smoothing is completed. If descum / smoothing is not required or not performed, inert gas plasma hardening may be performed instead.

[0098] In some embodiments, inert gas plasma stripping and planarization may be used in conjunction with a wet development process. Wet development has been shown to have very high selectivity and exhibit clear on / off behavior, such that regions exposed by "stray" EUV photons cannot be removed in a wet development process. After the wet development process, residual residues remain, resulting in scum and an increase in line edge and width roughness. Interestingly, due to the tunability of dry development processes where etching rate and selectivity can be adjusted based on multiple knobs (e.g., time, temperature, pressure, gas / flow), further application of inert gas plasma and / or dry development can descum and planarize metal-containing resist lines by removing these partially exposed residues.

[0099] Figure 5 shows a graph comparing the etching rates of exposed and unexposed portions of an EUV photoresist using a helium plasma during dry development. The EUV photoresist may be an organotin oxide EUV photoresist. The unexposed portion is etched at a faster rate than the exposed portion. However, as dry development using HBr proceeds, the etching rate decreases. Without being limited by any theory, the presence of tin oxide particles / clusters is thought to slow down the etching rate. By applying helium stripping, more of the unexposed portion of the EUV photoresist can be etched.

[0100] Figures 6A and 6B show SEM images comparing wet development and dry development with respect to line collapse. In Figure 6A, a photopatterned metal-containing EUV resist is exposed to a wet development chemical such as an organic solvent. After the liquid drying step, some pattern line collapse is observed. This may be due in part to the action of surface tension by capillary forces. In Figure 6B, a photopatterned metal-containing EUV resist is exposed to a dry development chemical such as hydrogen halide gas. Dry development by a gas-phase reaction without a liquid drying step prevents pattern line collapse or delamination.

[0101] Figures 7A and 7B show SEM images comparing wet development and dry development with respect to roughness and critical dimension (CD) control. In Figures 7A and 7B, an organotin oxide film is deposited on an ashing-capable hard mask. The organotin oxide film was EUV-exposed at various doses and various focus depths. The organotin oxide film was wet-developed in Figure 7A and dry-developed in Figure 7B. The organotin oxide resist mask had a square profile after wet development, while the organotin oxide resist mask had a tapered profile after dry development. Line bridges were observed after pattern transfer in wet development, but not in dry development. Due to surface tension during solvent drying after wet development, line collapse and wiggling were observed at smaller line widths or lower doses. After dry development, line collapse or wiggling did not occur at narrower line widths or lower doses. In dry development, a larger process window is available over a wider dose and focus range.

[0102] Figure 8 shows SEM images comparing wet development and dry development with respect to scum after opening the hard mask. As shown in Figure 8, more scum is observed after wet development compared to after dry development. Without being limited by any theory, in dry development, scum formation is prevented by using a gas chemical that does not contain an oxygen or moisture oxidation source that prevents metal oxide crosslinking of the unexposed EUV resist. Scum is similar to the exposed EUV resist having metal oxide crosslinking. In Figure 8, descumming and smoothing operations can be performed after wet development or dry development.

[0103] Figures 9A and 9B show graphs representing the influence of the second post-exposure bake operation on the selectivity of dry development for various pressures and temperatures. As shown in Figure 9A, the second post-exposure bake shows improved etching selectivity. As shown in Figure 9B, during dry development, the etching selectivity improves when the temperature is low. In addition, during dry development, the etching selectivity improves when the pressure is low.

[0104] Figure 10 shows SEM images representing the influence of pressure on the EUV resist profile. In the case of dry development, the pressure change affects the EUV resist profile. Generally, a higher pressure enables a greater etching rate. However, at a lower pressure, an improvement in the EUV resist profile was demonstrated. When the pressure was lowered in Figure 10, the EUV resist profile became straighter.

[0105] Figures 11A and 11B show SEM images of EUV resist at different pitches and different thicknesses of line / space. EUV resist masks with 32 nm pitch and 26 nm pitch were developed. The film thickness before development was 15 nm to 40 nm. In the case of the 32 nm pitch, the thickness of the EUV resist mask was in the range of 7.8 nm to 22.5 nm after development. No wiggling was observed. In the case of the 26 nm pitch, the thickness of the EUV resist mask after development was in the range of 7.9 nm to 22.2 nm. Some wiggling was observed when the film thickness was 30 nm or more due to undercut at the bottom of the resist.

[0106] Device The apparatus of the present disclosure is configured to develop EUV resist. The apparatus may be configured to perform other processing operations such as deposition, bevel and backside cleaning, post-application bake, EUV scan, post-exposure bake, photoresist rework, descum, planarization, curing, and other operations. In some embodiments, the apparatus is configured to perform all dry operations. In some embodiments, the apparatus is configured to perform all wet operations. In some embodiments, the apparatus is configured to perform a combination of wet and dry operations. The apparatus may include a single wafer chamber or may include multiple stations within the same process chamber. If there are multiple stations within the same process chamber, various processing operations as described in the present disclosure may be performed at different stations within the same process chamber. For example, PEB heat treatment may be performed at one station and development may be performed at another station.

[0107] An apparatus configured for developing EUV resist includes a process chamber having a substrate support. The apparatus may include a vacuum line coupled to the process chamber for pressure control and a developer chemical line coupled to the process chamber for delivering developer chemicals. In some embodiments, the developer chemical includes a halide-containing gas or radicals of a halide-containing gas. In some embodiments, the process chamber is a plasma generation chamber or is coupled to a plasma generation chamber that functions as a remote plasma source. The plasma generation chamber may be an ICP, TCP, or CCP reactor. The apparatus may include one or more heaters for temperature control. Such heaters may be provided within the process chamber and / or within the substrate support.

[0108] In some embodiments, the interior of the process chamber is coated with a corrosion-resistant film such as a polymer or inorganic coating. In one example, the interior of the process chamber is coated with anodized alumina. In another example, the interior of the process chamber is yttrium oxide (Y2 O 3 is coated with

[0109] In some embodiments, the process chamber is made of an inexpensive material such as plastic. The process chamber does not necessarily have to be made of metal or ceramic. The plastic material may be sufficient to withstand the halide-containing chemicals during development. The vacuum line and / or the development chemical line may be coupled to the plastic chamber.

[0110] In some embodiments, a substrate support may be used to process the substrate using a temperature distribution having a radial component and an azimuthal component. The substrate support may include a plurality of independently controllable temperature control zones configured to be close to the substrate position above the temperature control zone. This allows one or more heaters within the substrate support to control the temperature more accurately and locally. The temperature control zones may be configured in a predetermined pattern, such as a rectangular grid, a hexagonal grid, or other suitable pattern for generating a desired temperature profile. In some embodiments, the temperature control zones may be spatially configured in the electrostatic chuck to correct azimuthal non-uniformities or local CD non-uniformities.

[0111] In some embodiments, the apparatus may further include a showerhead for delivering one or more gases into the process chamber. In some embodiments, the showerhead may supply a plurality of separate gases to the reaction region while generally separating the gases within the showerhead. The showerhead may include a plurality of plenum volumes. This allows for the separation of precursor gases, carrier gases, development gases, and cleaning gases, among other chemicals.

[0112] By removing water and moisture from the process chamber, the reaction between the photopatterned metal-containing EUV resist and the developer chemicals can be accelerated. In some embodiments, a cold trap may be coupled to the process chamber to remove the by-product water vapor. The cold trap may condense the by-product water vapor into a liquid or solid form.

[0113] In some embodiments, the apparatus may further include a UV source such as a UV lamp and / or an IR source such as an IR lamp for resist curing and dehalogenation. The UV source and / or IR source may provide exposure to radiation for curing the EUV resist. Additionally or alternatively, the UV source may assist in the photoactivation of the developer chemicals. Additionally or alternatively, the UV source may assist in halogen removal. Halogen residues may be formed on the semiconductor substrate or on the chamber surface, which can be removed by UV exposure.

[0114] FIG. 12 shows a schematic view of an embodiment of a process station 1200 having a process chamber body 1202 for maintaining a low-pressure environment suitable for the described embodiments of dry development, cleaning, rework, descumming, and planarization. A plurality of process stations 1200 may be included in a common low-pressure process tool environment. For example, FIG. 13 shows an embodiment of a multi-station process tool 1300 such as a VECTOR® processing tool available from Lam Research Corporation (Fremont, CA). In some embodiments, one or more hardware parameters of the process station 1200, including parameters discussed in detail below, may be programmatically adjusted by one or more computer controllers 1250.

[0115] The process station may be configured as a module within a cluster tool. FIG. 15 shows a semiconductor process cluster tool architecture having a vacuum integrated deposition and patterning module suitable for the implementation of the embodiments described herein. Such a cluster process tool architecture can include a resist deposition module, a resist exposure (EUV scanner) module, a resist development module, and an etching module, as described above and as will be described later with reference to FIGS. 14 and 15.

[0116] In some embodiments, certain processing functions, such as dry development and etching, can be performed sequentially within the same module. And embodiments of the present disclosure accommodate a wafer including a photo-patterned EUV resist thin film layer disposed on an etched layer or layer stack in a dry development / etching chamber following photolithography in an EUV scanner, dry develop the photo-patterned EUV resist thin film layer, and then use the patterned EUV resist as a mask to etch the underlying layer, as described herein, and are directed to methods and apparatuses therefor.

[0117] Returning to FIG. 12, the process station 1200 is in fluid communication with a reactant delivery system 1201a for delivering process gas to a distribution showerhead 1206. The reactant delivery system 1201a optionally includes a mixing vessel 1204 for mixing and / or conditioning the process gas for delivery to the showerhead 1206. One or more mixing vessel inlet valves 1220 may control the introduction of process gas into the mixing vessel 1204. If plasma exposure is used, the plasma may be further supplied to the showerhead 1206 or generated at the process station 1200. As described above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0118] FIG. 12 includes an optional vaporization point 1203 for vaporizing the liquid reactant supplied to the mixing vessel 1204. In some embodiments, a liquid flow controller (LFC) may be provided upstream of the vaporization point 1203 to control the mass flow rate of the liquid for vaporization and delivery to the process station 1200. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to a feedback control signal supplied by a proportional-integral-derivative (PID) controller in electrical communication with the MFM.

[0119] The showerhead 1206 distributes the process gas toward the substrate 1212. In the embodiment shown in FIG. 12, the substrate 1212 is shown to be located below the showerhead 1206 and resting on the pedestal 1208. The showerhead 1206 may have any suitable shape and may have any suitable number and configuration of ports for distributing the process gas to the substrate 1212.

[0120] In some embodiments, the pedestal 1208 may be raised or lowered to expose the substrate 1212 to the volume between the substrate 1212 and the showerhead 1206. It will be appreciated that in some embodiments, the height of the pedestal may be programmatically adjusted by a suitable computer controller 1250. In some embodiments, the showerhead 1206 may have a plurality of plenum volumes with multiple temperature controls.

[0121] In some embodiments, the pedestal 1208 may be temperature controlled via a heater 1210. In some embodiments, the pedestal 1208 may be heated to a temperature greater than 0°C and up to and including 300°C or more, such as 50°C to 120°C, such as about 65°C to 80°C, during non-plasma thermal exposure of the photopatterned resist to a hydrogen halide dry development chemical such as HBr or HCl as described in the disclosed embodiments. In some embodiments, the heater 1210 of the pedestal 1208 may include a plurality of independently controllable temperature control zones.

[0122] Further, in some embodiments, pressure control for the process station 1200 may be provided by a butterfly valve 1218. As shown in the embodiment of FIG. 12, the butterfly valve 1218 throttles the vacuum supplied by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of the process station 1200 may also be adjusted by varying the flow rate of one or more gases introduced into the process station 1200.

[0123] In some embodiments, the position of the showerhead 1206 relative to the pedestal 1208 may be adjusted to vary the volume between the substrate 1212 and the showerhead 1206. Further, it will be understood that the vertical position of the pedestal 1208 and / or the showerhead 1206 may be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 1208 may include a rotational axis for rotating the orientation of the substrate 1212. It will be understood that one or more of these exemplary adjustments may be implemented programmatically by one or more suitable computer controllers 1250.

[0124] When plasma is used, for example, in gentle plasma-based dry development embodiments and / or in etching operations performed within the same chamber, the showerhead 1206 and pedestal 1208 communicate electrically with a radio frequency (RF) power source 1214 and a matching network 1216 to supply power to the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the pressure of the process station, the gas concentration, the power of the RF source, the frequency of the RF source, and the plasma power pulse timing. For example, the RF power supply 1214 and the matching network 1216 may be operated at any suitable power to form a plasma having radical species of a desired composition. An example of suitable power is up to about 500 W.

[0125] In some embodiments, the instructions for the controller 1250 may be provided via input / output control (IOC) sequence instructions. In one example, the instructions for setting the conditions for a process phase may be included in the corresponding recipe phase of the process recipe. Optionally, the recipe phases may be configured in sequence such that all instructions for a process step are executed simultaneously with that process step. In some embodiments, the instructions for setting one or more reactor parameters may be included in the recipe phase. For example, the recipe phase may include instructions for setting the flow rate of a dry development chemical reaction gas such as HBr or HCl and time delay instructions for the recipe phase. In some embodiments, the controller 1250 may include any of the features described below with respect to the system controller 1350 of FIG. 13.

[0126] As described above, one or more process stations may be included in a multi-station processing tool. FIG. 13 shows a schematic diagram of an embodiment of a multi-station processing tool 1300 comprising an inbound load lock 1302 and an outbound load lock 1304, either or both of which may include a remote plasma source. A robot 1306 at atmospheric pressure is configured to move wafers from a cassette loaded through a pod 1308 into the inbound load lock 1302 via an atmospheric port 1310. The wafer is placed on a pedestal 1312 within the inbound load lock 1302 by the robot 1306, the atmospheric port 1310 is closed, and the load lock is pumped down. If the inbound load lock 1302 includes a remote plasma source, the wafer may be exposed to remote plasma processing to treat the silicon nitride surface within the load lock before being introduced into the processing chamber 1314. Further, the wafer may also be heated within the inbound load lock 1302, for example, to remove moisture and adsorbed gases. Next, the chamber transfer port 1316 to the processing chamber 1314 is opened and, for processing, another robot (not shown) places the wafer into the reactor and positions it on the pedestal of the first station shown within the reactor. The embodiment shown in FIG. 13 includes load locks, but it will be understood that in some embodiments, direct access of the wafer into the process station may be provided.

[0127] The illustrated processing chamber 1314 includes four process stations numbered from 1 to 4 in the embodiment shown in FIG. 13. Each station has a heated pedestal (designated 1318 for station 1) and a gas line inlet. It will be understood that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, the process station may be switchable between a dry development mode and an etching process mode. Additionally or alternatively, in some embodiments, the processing chamber 1314 may include one or more matched pairs of a dry development station and an etching process station. Although the illustrated processing chamber 1314 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0128] FIG. 13 shows an embodiment of a wafer handling system 1390 for transferring wafers within the processing chamber 1314. In some embodiments, the wafer processing system 1390 may transfer wafers between various process stations and / or between a process station and a load lock. It will be understood that any suitable wafer handling system may be employed. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 13 also shows an embodiment of a system controller 1350 used to control the process conditions and hardware state of the process tool 1300. The system controller 1350 may include one or more memory devices 1356, one or more mass storage devices 1354, and one or more processors 1352. The processor 1352 may include a CPU or computer, analog, and / or digital input / output connections, a stepper motor controller board, and the like.

[0129] In some embodiments, system controller 1350 controls all of the operations of process tool 1300. System controller 1350 executes system control software 1358 that is stored in mass storage device 1354, read into memory device 1356, and executed by processor 1352. Alternatively, the control logic may be hard-coded within controller 1350. For these purposes, application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), etc. may be used. Whenever the term "software" or "code" is used in the following description, functionally equivalent hard-coded logic may be used instead. System control software 1358 may include instructions for controlling timing, gas mixing, gas flow rate, pressure in the chamber and / or station, temperature in the chamber and / or station, wafer temperature, target power level, RF power level, substrate pedestal, position of the chuck and / or susceptor, and other parameters of the particular process implemented by process tool 1300. System control software 1358 may be configured in any suitable manner. For example, subroutines or control objects of various process tool components may be described to control the operation of the process tool components used to implement various process tool processes. System control software 1358 may be coded in any suitable computer readable programming language.

[0130] In some embodiments, system control software 1358 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored in mass storage device 1354 and / or memory device 1356 associated with system controller 1350 may be used. Examples of programs or portions of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0131] The substrate alignment program may include program code for a process tool component that is used to load a substrate onto pedestal 1318 and control the spacing between the substrate and other components of process tool 1300.

[0132] The process gas control program may include code for controlling the composition (e.g., HBr or HCl gas as described herein) and flow rate of a halide-containing gas, and optionally code for flowing the gas into one or more process stations prior to deposition to stabilize the pressure within the process station. The pressure control program may include code for controlling the pressure within the process station by adjusting, for example, a throttle valve of an exhaust system of the process station, the gas flow into the process station.

[0133] The heater control program may include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program may control the supply of a heat transfer gas (e.g., helium) to the substrate.

[0134] The plasma control program may include code for setting the RF power level applied to a process electrode within one or more process stations according to embodiments herein.

[0135] The pressure control program may include code for maintaining the pressure within the reaction chamber according to embodiments herein.

[0136] In some embodiments, there may be a user interface associated with system controller 1350. The user interface may include a display screen, a graphical software display of device and / or process conditions, and user input devices, e.g., a pointing device, a keyboard, a touch screen, a microphone.

[0137] In some embodiments, the parameters adjusted by the system controller 1350 may relate to process conditions. Non-limiting examples include the composition and flow rate of the process gas, temperature, pressure, plasma conditions (e.g., RF bias power level), etc. These parameters may be provided to the user in the form of a recipe that may be input using the user interface.

[0138] Signals for monitoring the process may be provided from various process tool sensors by the analog and / or digital input connections of the system controller 1350. Signals for controlling the process may be output to the analog and digital output connections of the process tool 1300. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with the data from these sensors to maintain process conditions.

[0139] The system controller 1350 may provide program instructions for performing the deposition process described above. The program instructions may control various process parameters such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control parameters for operating development and / or etching processes according to the various embodiments described herein.

[0140] The system controller 1350 will typically include one or more memory devices and one or more processors configured to execute instructions such that the apparatus performs the methods according to the disclosed embodiments. A machine-readable medium containing instructions for controlling process operations according to the disclosed embodiments may be coupled to the system controller 1350.

[0141] In some embodiments, system controller 1350 is part of the system and may be part of the above examples. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as wafer stages, gas flow systems, etc.). These systems may be incorporated into electronics for controlling operations before, during, and after the processing of semiconductor wafers or substrates. The electronics may sometimes be referred to as a "controller" that can control various components or sub-components of the system(s). System controller 1350 may be programmed to control any of the processes disclosed herein, including delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, tools and other transfer tools connected to or interfacing with a particular system, and / or wafer loading and unloading to / from a load lock, depending on the processing conditions and / or the type of system.

[0142] Broadly speaking, system controller 1350 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software, receiving instructions, issuing instructions, controlling operations, enabling cleaning operations, enabling endpoint measurements, etc. The integrated circuits may include a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller executing program instructions (e.g., software). The program instructions are instructions communicated to system controller 1350 in the form of various individual settings (or program files), which may define work parameters for performing a particular process on or for a semiconductor wafer or for the system. In some embodiments, the work parameters may be part of a recipe defined by a process engineer to implement one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0143] In some embodiments, system controller 1350 may be part of a computer that is incorporated into, or coupled to, or network-connected to the system, or a combination thereof, or may be coupled to the computer. For example, system controller 1350 may be within the "cloud" or may be all or part of a fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system, monitor the current progress of manufacturing operations, investigate the history of past manufacturing operations, investigate trends or performance metrics from multiple manufacturing operations to change the parameters of the current process, set the processing steps following the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system via a network that may include a local network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and / or settings, and the parameters and / or settings are then communicated from the remote computer to the system. In some examples, system controller 1350 receives instructions in a data format that specifies parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that system controller 1350 is configured to interface with or control. Thus, as described above, system controller 1350 may be distributed, for example, by including one or more individual controllers that are networked together and aimed at a common purpose such as the processes and controls described herein. An example of a distributed controller for such a purpose may be one or more integrated circuits on a chamber that are in communication with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), and these are combined to control the process in the chamber.

[0144] While not being limiting, exemplary systems may include a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a development chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacture of semiconductor wafers.

[0145] As described above, depending on the process steps performed by the tool, system controller 1350 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, main computers, other controllers, or tools used for material transport to and from tool locations and / or load ports within a semiconductor manufacturing facility.

[0146] In certain embodiments, an inductively coupled plasma (ICP) reactor, which may be suitable for etching operations suitable for the implementation of some embodiments, is described herein. Although the ICP reactor is described herein, it should be understood that capacitively coupled plasma reactors may also be used in some embodiments.

[0147] FIG. 14 schematically shows a cross-sectional view of an inductively coupled plasma apparatus 1400 suitable for implementing certain embodiments or aspects of embodiments, such as dry development and / or etching, an example of which apparatus is the Kiyo® reactor manufactured by Lam Research Corp. (Fremont, CA). In other embodiments, other tools or tool types having the functionality to perform the dry development and / or etching processes described herein may be used to implement.

[0148] The inductively coupled plasma device 1400 includes an overall process chamber 1424 structurally defined by a chamber wall 1401 and a window 1411. The chamber wall 1401 may be manufactured from stainless steel, aluminum, or plastic. The window 1411 may be manufactured from quartz or other dielectric materials. The optional internal plasma grid 1450 divides the overall process chamber into an upper sub-chamber 1402 and a lower sub-chamber 1403. In most embodiments, by removing the plasma grid 1450, the chamber spaces created in the sub-chambers 1402 and 1403 may be utilized. A chuck 1417 is positioned inside the lower sub-chamber 1403 near the inner surface of the bottom. The chuck 1417 is configured to accommodate and hold a semiconductor wafer 1419, and etching and deposition processes are performed on the semiconductor wafer. The chuck 1417 may be an electrostatic chuck for supporting the wafer 1419 when the wafer 1419 is present. In some embodiments, an edge ring (not shown) surrounds the chuck 1417 and has an upper surface that is substantially coplanar with the upper surface of the wafer 1419 when the wafer 1419 is present on the chuck 1417. The chuck 1417 also includes electrostatic electrodes for chucking and de-chucking the wafer 1419. For this purpose, a filter and a DC clamp power supply (not shown) may be provided. Other control systems for lifting the wafer 1419 from the chuck 1417 may also be provided. The chuck 1417 can be charged using an RF power supply 1423. The RF power supply 1423 is connected to a matching circuit 1421 via a connection 1427. The matching circuit 1421 is connected to the chuck 1417 via a connection 1425. In this way, the RF power supply 1423 is connected to the chuck 1417. In various embodiments, the bias power of the electrostatic chuck may be set to about 50V, or may be set to different bias powers depending on the process implemented according to the disclosed embodiments. For example, the bias power may be from about 20V to about 100V, or from about 30V to about 150V.

[0149] The element for plasma generation includes a coil 1433 positioned above the window 1411. In some embodiments, in the disclosed embodiments, the coil is not used. The coil 1433 is manufactured from a conductive material and includes at least one complete turn. In the example of the coil 1433 shown in FIG. 14, it includes three turns. The cross-section of the coil 1433 is indicated by symbols, where the coil with an "X" extends by rotating into the page, and the coil with a dot extends by rotating out of the page. The element for plasma generation also includes an RF power supply 541 configured to supply RF power to the coil 1433. Generally, the RF power supply 1441 is connected to a matching circuit 1439 via a connection portion 1445. The matching circuit 1439 is connected to the coil 1433 via a connection portion 1443. In this way, the RF power supply 1441 is connected to the coil 1433. An optional Faraday shield 1449a is positioned between the coil 1433 and the window 1411. The Faraday shield 1449a may be maintained in a spaced relationship with respect to the coil 1433. In some embodiments, the Faraday shield 1449a is disposed directly above the window 1411. In some embodiments, the Faraday shield 1449b is between the window 1411 and the chuck 1417. In some embodiments, the Faraday shield 1449b is not maintained in a spaced relationship with respect to the coil 1433. For example, the Faraday shield 1449b may be directly below the window 1411 without a gap. The coil 1433, the Faraday shield 1449a, and the window 1411 are each configured to be substantially parallel to each other. The Faraday shield 1449a can prevent metals or other species from depositing on the window 1411 of the process chamber 1424.

[0150] Process gas may flow into the process chamber through one or more main gas inlets 1460 located in the upper sub-chamber 1402 and / or through one or more side gas inlets 1470. Similarly, although not explicitly shown, similar gas inlets may be used to supply process gas to a capacitively coupled plasma processing chamber. A vacuum pump, for example, a single- or two-stage mechanical dry pump and / or a turbomolecular pump 1440 may be used to draw process gas out of the process chamber 1424 to maintain the pressure inside the process chamber 1424. For example, a vacuum pump may be used to evacuate the lower sub-chamber 1403 during the purge operation of ALD. To selectively control the application of the vacuum environment provided by the vacuum pump, a valve control conduit may be used to fluidly connect the vacuum pump to the process chamber 1424. This may be done using a closed-loop control flow restriction device such as a throttle valve (not shown) or a pendulum valve (not shown) during the plasma processing operation. Similarly, a vacuum pump and a valve-controlled fluid connection to the capacitively coupled plasma processing chamber may also be used.

[0151] During operation of apparatus 1400, one or more process gases may be supplied through gas inlets 1460 and / or 1470. In certain embodiments, the process gas may be supplied only through the main gas inlet 1460 or only through the side gas inlet 1470. In some cases, the gas inlets shown in the figure may be replaced with more complex gas inlets, for example, one or more showerheads. The Faraday shield 1449a and / or optional grid 1450 may include internal channels and holes that allow the process gas to be supplied to the process chamber 1424. Either or both of the Faraday shield 1449a and the optional grid 1450 may function as a showerhead for supplying the process gas. In some embodiments, a liquid vaporization and supply system may be disposed upstream of the process chamber 1424 such that when a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process chamber 1424 through the gas inlets 1460 and / or 1470.

[0152] High-frequency power is supplied from the RF power source 1441 to the coil 1433, and an RF current flows through the coil 1433. The RF current flowing through the coil 533 generates an electromagnetic field around the coil 1433. The electromagnetic field generates an induced current inside the upper sub-chamber 1402. The physical and chemical interactions between the generated various ions and radicals and the wafer 1419 etch the features of the wafer 1419 and selectively deposit a layer on the wafer 1419.

[0153] When the plasma grid 1450 is used such that both the upper sub-chamber 1402 and the lower sub-chamber 1403 are present, an induced current acts on the gas present in the upper sub-chamber 1402 to generate an electron-ion plasma in the upper sub-chamber 1402. The optional internal plasma grid 1450 limits the amount of hot electrons in the lower sub-chamber 1403. In some embodiments, the apparatus 1400 is designed and operated such that the plasma present in the lower sub-chamber 1403 is an ion-ion plasma.

[0154] Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, but the ion-ion plasma will have a greater ratio of negative ions to positive ions. By-products from volatile etching and / or deposition may be removed from the lower sub-chamber 1403 via the port 1422. The chuck 1417 disclosed herein may operate at a high temperature in the range of about 10°C to about 250°C. The temperature will depend on the process operation and the specific recipe.

[0155] When the apparatus 1400 is installed in a clean room or a manufacturing facility, the apparatus 1400 may be coupled to the facility (not shown). The facility includes piping that provides process gas, vacuum, temperature control, and environmental particle control. When the apparatus 1400 is installed in a target manufacturing facility, these facilities are coupled to the apparatus 1400. Additionally, the apparatus 1400 may be coupled to a transfer chamber to allow robotics to load and unload semiconductor wafers to and from the apparatus 1400 using typical automation equipment.

[0156] In some embodiments, a system controller 1430 (which may include one or more physical or logical controllers) controls some or all of the operations of the process chamber 1424. The system controller 1430 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 1400 includes a switching system for controlling flow rate and duration when the disclosed embodiments are implemented. In some embodiments, the apparatus 1400 may have a switching time of up to about 500 milliseconds, or up to about 750 milliseconds. The switching time may depend on the flow chemistry, the selected recipe, the reactor architecture, and other factors.

[0157] In some embodiments, system controller 1430 is part of the system, which may be part of the above examples. Such a system may include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as wafer stages, gas flow systems, etc.). These systems may be incorporated into electronics for controlling operations before, during, and after processing of semiconductor wafers or substrates. The electronics may be incorporated into system controller 1430, and system controller 1430 may control various components or sub-parts of the system. The system controller may, depending on the processing parameters and / or the type of system, control any of the processes disclosed herein, including delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, tools and other transfer tools connected to or interfacing with a particular system and / or loading and unloading of wafers to / from a load lock.

[0158] Generally speaking, the system controller 1430 may have various integrated circuits, logic, memory, and / or software, receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc., and may be defined as an electronic device. The integrated circuit may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), and may define work parameters for implementing a specific process on or for a semiconductor wafer, or for the system. In some embodiments, the work parameters may be part of a recipe defined by a process engineer to implement one or more processing steps during the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0159] In some embodiments, system controller 1430 may be part of a computer that is incorporated into, or coupled to, or network-connected to the system, or a combination thereof, or may be coupled to such a computer. For example, the controller may be within the “cloud” or may be all or part of a fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system, monitor the current progress of manufacturing operations, investigate the history of past manufacturing operations, investigate trends or performance metrics from multiple manufacturing operations, change the parameters of the current process, set the process steps following the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system via a network that may include a local network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and / or settings, and the parameters and / or settings are then communicated from the remote computer to the system. In some examples, system controller 1430 receives instructions in a data format that specifies parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, system controller 1430 may be distributed, for example, by including one or more individual controllers that are networked together and aimed at a common purpose such as the processes and controls described herein. An example of a distributed controller for such a purpose may be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), and these are combined to control the process in the chamber.

[0160] While not being limiting, exemplary systems may include a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a dry development chamber or module, and any other semiconductor processing system that may be related to or used in the fabrication and / or manufacture of semiconductor wafers.

[0161] As described above, depending on the process steps performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, main computers, other controllers, or tools used for material transport to and from wafer containers between tool locations and / or load ports within a semiconductor manufacturing facility.

[0162] EUV lithography may be performed using any suitable tool, often referred to as a scanner, such as the TWINSCAN NXE:3300B™ platform provided by ASML (Veldhoven, NL). The EUV lithography tool may be a stand-alone device, and as described herein, substrates enter and exit this tool for deposition and etching. Alternatively, as described below, the EUV lithography tool may be a module of a larger multi-component tool. FIG. 15 shows a semiconductor process cluster tool architecture having deposition, EUV patterning, and dry development / etching modules integrated in a vacuum that interfaces with a vacuum transfer module, suitable for the implementation of the processes described herein. The process may be performed without such a vacuum integration device, although such a device may be advantageous in some embodiments.

[0163] FIG. 15 shows a semiconductor process cluster tool architecture having deposition and patterning modules integrated in a vacuum that interfaces with a vacuum transfer module, suitable for the implementation of the processes described herein. The configuration of the transfer module for "transferring" wafers between a plurality of storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. The deposition and patterning modules are integrated in a vacuum according to the requirements of a particular process. Other modules, such as for etching, may also be included in the cluster.

[0164] A vacuum transfer module (VTM) 1538 interfaces with four processing modules 1520a - 1520d, which may be individually optimized to perform various manufacturing processes. By way of example, the processing modules 1520a - 1520d may be implemented to perform deposition, evaporation, ELD, dry development, etching, strip, and / or other semiconductor processes. For example, module 1520a may be an ALD reactor, which may be operated to perform thermal atomic layer deposition as described herein without plasma, e.g., a Vector tool available from Lam Research Corporation (Fremont, CA). Also, module 1520b may be a PECVD tool such as Lam Vector (registered trademark). It should be understood that the drawings are not necessarily drawn to scale.

[0165] Airlocks 1542 and 1546, also referred to as load locks or transfer modules, interface with the VTM 1538 and the patterning module 1540. For example, as described above, a suitable patterning module may be the TWINSCAN NXE:3300B (trademark) platform supplied by ASML (Veldhoven, NL). This tool architecture enables workpieces such as semiconductor substrates or wafers to be transferred under vacuum so as not to react prior to exposure. 2 O, O 2 Assuming strong optical absorption of incident photons by ambient gases such as O, O, etc., the fact that EUVL also requires a significantly low pressure facilitates the integration of the deposition module and the lithography tool.

[0166] As described above, this integrated architecture is only one of the envisioned embodiments of the tools for implementing the described process. This process may also be implemented stand-alone or integrated as a module into other tools such as etching, stripping, etc. (e.g., Lam Kiyo or Gamma tools) in a stand-alone or cluster architecture using a conventional stand-alone EUVL scanner and deposition reactors such as Lam Vector tools, without, however, an integrated patterning module, as described with reference to FIG. 15 for example.

[0167] The airlock 1542 may be an “outward” load lock, referring to removing the substrate from the VTM 1538 that services the deposition module 1520a and transferring it to the patterning module 1540, and the airlock 1546 may be an “inward” load lock, referring to transferring the substrate back from the patterning module 1540 to the VTM 1538. The inward load lock 1546 may also provide an interface to the outside of the tool for loading and unloading substrates. Each process module has a facet that interfaces the module to the VTM 1538. For example, the deposition process module 1520a has a facet 1536. Inside each facet, sensors, such as sensors 1-18 as illustrated, are used to detect the passage of the wafer 1526 when the wafer 1526 moves between the respective stations. The patterning module 1540, as well as the airlocks 1542 and 1546, may similarly include additional facets and sensors (not shown).

[0168] The main VTM robot 1522 transfers the wafer 1526 between modules including the air locks 1542 and 1546. In one embodiment, the robot 1522 has one arm, and in another embodiment, the robot 1522 has two arms, and each arm has an end effector 1524 for lifting wafers such as the wafer 1526 for conveyance. A front-end robot 1544 is used to transfer the wafer 1526 from the out-going air lock 1542 to the patterning module 1540 and from the patterning module 1540 to the in-coming air lock 1546. The front-end robot 1544 may also convey the wafer 1526 between the in-coming load lock and outside the tool for loading and unloading of substrates. Since the in-coming air lock module 1546 has the ability to match the environment between the atmosphere and the vacuum, the wafer 1526 can move between the two pressure environments without being damaged.

[0169] It should be noted that EUVL tools typically operate at a higher vacuum than deposition tools. In this case, it is desirable to increase the vacuum level of the substrate environment during transfer between the deposition tool and the EUVL tool so that the substrate can be degassed before entering the patterning tool. The out-going air lock 1542 holds the transferred wafer at a lower pressure, i.e., below the pressure inside the patterning module 1540, for a certain period of time and evacuates any exhaust gas, thus providing this function so that the optical system of the patterning tool 1540 is not contaminated by the exhaust gas from the substrate. A suitable pressure for the out-going air lock for exhaust gas is 1E-8 Torr or less.

[0170] In some embodiments, a system controller 1550 (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and / or its discrete modules. The controller can be local to the cluster architecture, or can be located external to the cluster architecture on the manufacturing floor, or can be located remotely and connected to the cluster architecture via a network. It should be noted that the system controller 1550 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor controller board, and other similar components. Instructions for performing appropriate control operations are executed by the processor. These instructions may be stored in a memory device associated with the controller, or these instructions may be provided via a network. In certain embodiments, the system controller executes system control software.

[0171] The system control software may include instructions for controlling the application timing and / or magnitude of any aspect of the tool or module operation. The system control software may be configured in any suitable manner. For example, subroutines or control objects for various process tool components may be described to control the operation of the process tool components required to perform various process tool processes. The system control software may be coded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a semiconductor manufacturing process may include one or more instructions executed by the system controller. Instructions for setting process conditions for condensation, deposition, evaporation, patterning, and / or etching stages may be included, for example, in the corresponding recipe stage.

[0172] In various embodiments, an apparatus for forming a negative mask is provided. The apparatus may include a processing chamber for patterning, deposition, and etching, and a controller including instructions for forming a negative mask. The instructions may include code for patterning features in a chemically amplified (CAR) resist on a semiconductor substrate by EUV exposure to expose the surface of the substrate, developing the photopatterned resist, and using the patterned resist as a mask to etch an underlying layer or stack of layers. The development may be performed using a halide-containing chemical.

[0173] It should be noted that a computer controlling the movement of the wafer can be local to the cluster architecture, or can be located external to the cluster architecture of the manufacturing floor, or can be located remotely and connected to the cluster architecture via a network. A controller as described above with respect to any of FIGS. 12, 13, or 14 may be implemented using the tool of FIG. 15.

[0174] Conclusion For example, a process and apparatus for dry development of a photoresist of metal and / or metal oxide for forming a patterning mask in connection with EUV patterning are disclosed.

[0175] It is understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes will be proposed to those skilled in the art in light of this. Various details are omitted for clarity, but various design alternatives may be realized. Therefore, this example should be regarded as illustrative and not limiting, and the present disclosure is not limited to the details described herein and may be modified within the scope of the present disclosure.

Claims

1. 1. A method for processing a semiconductor substrate, comprising: providing a photopatterned metal-containing resist on a substrate layer of a semiconductor substrate in a process chamber; and developing the photopatterned metal-containing resist by selectively removing portions of the resist by exposure to a halide-containing developer chemistry to form a resist mask.

2. 2. The method of claim 1, wherein the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist.

3. 3. The method of claim 2, wherein developing the photo-patterned metal-containing EUV resist comprises removing non-EUV exposed portions of the EUV resist selectively to EUV exposed portions with the developing chemistry to form the resist mask.

4. 4. The method of claim 3, The method further comprises non-selectively removing the EUV non-exposed and the EUV exposed portions of the photopatterned metal-containing resist without removing the substrate layer.

5. 10. The method of claim 1, wherein the developing chemicals include hydrogen halides, hydrogen gas and halogen gas, organic halides, acyl halides, carbonyl halides, thionyl halides, or mixtures thereof.

6. 6. The method of claim 5, wherein the developing chemicals include hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), or hydrogen iodide (HI).

7. 6. The method of claim 5, wherein the developing chemical is hydrogen gas (H 2 ) and fluorine gas (F 2 ), chlorine gas (Cl 2 ), bromine gas (Br 2 ), or iodine gas (I 2 ) a method comprising:

8. 10. The method of claim 1, wherein the halide is flowed into the process chamber with a carrier gas, the carrier gas being selected from the group consisting of helium (He), neon (Ne), argon (Ar), xenon (Xe), and nitrogen (N 2 ).

9. 2. The method of claim 1, wherein developing the photo-patterned metal-containing resist by exposure to a developing chemical comprises dry developing the photo-patterned metal-containing resist by exposure to a dry developing chemical.

10. 10. The method of claim 9, wherein dry developing the photopatterned metal-containing resist comprises applying a remote plasma containing the halide radicals to the resist.

11. 10. The method of claim 9, wherein dry developing the photopatterned metal-containing resist comprises exposing to at least the halide in a plasma-free thermal process.

12. 10. The method of claim 9, wherein dry developing the photopatterned metal-containing resist is performed at a temperature of about −60° C. to about 120° C., at a chamber pressure of 0.1 mTorr to about 760 Torr, and with a gas flow rate of the halide of 100 sccm to 2000 sccm, and an etch selectivity of the resist mask is tunable based at least in part on the temperature, the chamber pressure, the gas flow rate, or a combination thereof.

13. 13. The method of claim 12, wherein the temperature is from about -20°C to about 20°C.

14. 13. The method of claim 12, wherein a profile of the resist mask is controllable based at least in part on the temperature, the chamber pressure, the gas flow rates, or a combination thereof.

15. The method of any one of claims 1 to 14, wherein the photopatterned metal-containing resist is an organometallic oxide thin film or an organometallic containing thin film.

16. 16. The method of claim 15, wherein the photopatterned metal-containing resist comprises an organotin oxide.

17. 15. The method of any one of claims 1 to 14, wherein the photopatterned metal-containing resist comprises an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium.

18. 15. The method of any one of claims 1 to 14, wherein providing the photopatterned metal-containing resist comprises vapor depositing a metal-containing resist film onto the substrate layer.

19. 15. The method of any one of claims 1 to 14, wherein providing the photopatterned metal-containing resist comprises spin-coating a metal-containing resist film onto the substrate layer.

20. The method of any one of claims 1 to 14, wherein the photopatterned metal-containing resist has a thickness of about 10 nm to about 50 nm.

21. The method according to any one of claims 1 to 14, The method further comprising exposing the photopatterned metal-containing resist to an inert gas plasma after developing the photopatterned metal-containing resist.

22. 22. The method of claim 21, The method further comprising repeating the operations of developing the photopatterned metal-containing resist and exposing the photopatterned metal-containing resist to the inert gas plasma.

23. The method according to any one of claims 1 to 14, The method further comprising baking the photopatterned metal-containing resist at an elevated temperature prior to developing the photopatterned metal-containing resist.

24. 15. The method of any one of claims 1 to 14, wherein providing the photopatterned metal-containing resist comprises: depositing a metal-containing EUV resist film on the semiconductor substrate; non-selectively removing a portion of the metal-containing EUV resist film on a backside and a bevel edge of the semiconductor substrate; exposing the metal-containing EUV resist film to EUV light to form the photopatterned metal-containing resist.

25. The method according to any one of claims 1 to 14, depositing a metal-containing EUV resist film on the semiconductor substrate; The method further comprising non-selectively removing the metal-containing EUV resist film from the semiconductor substrate without removing the substrate layer prior to providing the photopatterned metal-containing resist.

26. An apparatus for developing a resist, the apparatus comprising: a process chamber having a substrate support; a vacuum line coupled to the process chamber; a developer chemistry line coupled to the process chamber; and a controller configured with instructions for processing a semiconductor substrate, the instructions comprising: providing a photopatterned metal-containing resist on a substrate layer of the semiconductor substrate in the process chamber; and code for developing the photopatterned metal-containing resist to form a resist mask by selectively removing portions of the resist by exposure to a developing chemistry that includes a halide.

27. 27. The apparatus of claim 26, wherein the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist, and the controller is configured with instructions including code for developing the photo-patterned metal-containing EUV resist and code for selectively removing EUV non-exposed portions of the EUV resist with the developing chemistry relative to EUV exposed portions to form the resist mask.

28. 27. The apparatus of claim 26, The apparatus further comprising one or more heaters coupled to the substrate support, the one or more heaters including a plurality of independently controllable temperature control zones.

29. 27. The apparatus of claim 26, wherein the interior of the process chamber is coated with a corrosion inhibitor.

30. 27. The apparatus of claim 26, The apparatus further comprising a cold trap coupled to the process chamber, the cold trap configured to remove water from the process chamber.

31. An apparatus according to any one of claims 26 to 30, wherein the process chamber comprises a plastic material.

32. 31. The apparatus of any one of claims 26 to 30, further comprising a UV lamp or an IR lamp coupled to the process chamber, the UV lamp or the IR lamp configured to cure the photopatterned metal-containing resist or remove excess halides from the process chamber.

33. 1. A method for processing a semiconductor substrate, the method comprising: providing a dry deposited photopatterned metal oxide EUV resist on a substrate layer of a semiconductor substrate in a process chamber; and dry developing the photopatterned metal oxide EUV resist by selectively removing non-EUV exposed portions of the EUV resist by exposure to a dry development chemistry comprising HCl and / or HBr to form a resist hard mask from the EUV exposed portions.

34. 34. The method of claim 33, wherein dry developing is performed with a plasma-free thermal process, and exposure to the dry developing chemistry is performed at a temperature of about -20°C to about 20°C.

35. 34. The method of claim 33, wherein the photopatterned metal oxide EUV resist comprises an organotin oxide.

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