Receiver circuit and method of operation thereof

Abstract

To adjust an equalization function applied in normal operation according to the results of checking intersymbol interference in the training operation.SOLUTION: A receiver circuit 1 includes a first decision feedback equalizer 103 which determines whether to activate a first enable signal EN1 depending on the result confirmed in the training mode, and operates only during the activation period of the signal, and removes the first post-cursor component for the first received normal signal through direct calibration for the current received value RV_NM1_t0 on the basis of the first previously received value RV_NM1_t1 of the first received normal signal RV_NM1_t0, and a second decision feedback equalizer 104 which adjusts the driving force according to the pattern of the second to Nth previously received values RV_NM1_t2:tN of the first received normal signal when the first enable signal is in an activated state, and removes the second to Nth post-cursor components for the first received normal signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor circuit, and more particularly, to a receiver circuit having an equalization function and an operation method thereof.

Background Art

[0002] An electronic device includes many electronic components. Among them, a computer system can include many semiconductor devices made of semiconductors. Among various semiconductor devices realized by using semiconductors, in a device that uses a memory system as a storage medium, for example, in a mobile digital electronic device such as a digital camera, a smartphone, and a tablet PC, a volatile memory device and a non-volatile memory device can be provided to store data. A volatile memory device is a memory device in which stored data is erased when the power supply is cut off. Examples of volatile memory devices include SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM). A non-volatile memory device is a memory device in which stored data is maintained even when the power supply is cut off. Examples of non-volatile memory devices include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (registered trademark) (Electrically Erasable and Programmable ROM), flash memory device, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (registered trademark) (Resistive RAM), FRAM (registered trademark) (Ferroelectric RAM), and the like. Flash memory can be roughly classified into NOR flash memory and NAND flash memory.

[0003] Such a memory device can communicate with each other by transmitting and receiving a clock signal and data. The memory device can transmit a signal having information corresponding to the data via a signal bus such as a data bus. The memory device can include a signal transmission circuit for transmitting a signal via the signal bus, and the signal transmission circuit can transmit a signal by transmitting an analog voltage via the signal bus. Generally, the signal transmission circuit can transmit an analog voltage corresponding to a high logic level and an analog voltage corresponding to a low logic level.

[0004] In a signal input / output interface provided in a memory device, a data signal can be transmitted to a receiver via a channel. As the data rate increases, interference signals due to channel effects increase, and a decrease in signal quality may become a problem. To improve the deteriorating SI (signal integrity) characteristics, an equalization function is used. A decision feedback equalizer (DFE), which is one of various types of equalizers that provide an equalization function, can cancel out interference signals, that is, can cancel out post cursors that induce inter-symbol interference (ISI) to improve SI characteristics.

[0005] On one hand, among the equalization functions of the DFE, for the DFE using the Direct Feedback method, there can be a Current-summer DFE and a Gm-control DFE. Here, the Current-summer DFE can be meant as a direct feedback DFE that performs the equalization function in a method of directly calibrating the currently received signal using the value of the previously (post) received signal. Also, the Gm-control DFE can be meant as a direct feedback DFE that performs the equalization function in an indirect method, that is, a method of adjusting the driving force of the transistor to which the currently received signal is input according to the pattern of the value of the previously received signal. The Current-summer DFE has a larger current consumption compared to the Gm-control DFE, but can more effectively improve the SI characteristics of the received signal.

Summary of the Invention

Problems to be Solved by the Invention

[0006] Embodiments of the present invention can provide a receiver circuit and its operation method that confirm inter-symbol interference (ISI) occurring in a signal input through a training operation performed after power-up and before normal operation, and adjust the equalization function applied in normal operation according to the confirmation result.

[0007] The technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those with ordinary knowledge in the technical field to which the present invention belongs from the following description.

Means for Solving the Problems

[0008] The receiver circuit according to an embodiment of the present invention receives, as a first received pattern signal, a first input pattern signal applied via a first pad in a training mode according to a training reference level, and receives, as a first received normal signal, a first input normal signal applied via the first pad in a normal mode entered after exiting the training mode according to a normal reference level; a first input unit; a first enable control unit that determines whether or not to activate a first enable signal according to a result of checking a value of the first received pattern signal in the training mode; a first decision feedback equalizer (DFE) that operates only in an activation section of the first enable signal and removes a first post-cursor component with respect to the first received normal signal through direct calibration for a currently received value based on a value received before the first received normal signal; and a second decision feedback equalizer that, when the first enable signal is in an activated state, adjusts a driving force of a first input transistor to which a currently received value is applied according to a pattern of values received before the second to Nth received values of the first received normal signal, and removes post-cursor components from the second to Nth with respect to the first received normal signal.

[0009] The operation method of the receiver circuit according to still another embodiment of the present invention receives, as a first received pattern signal, a first input pattern signal applied via a first pad in a training mode according to a training reference level, and receives, as a first received normal signal, a first input normal signal applied via the first pad in a normal mode entered after exiting the training mode according to a normal reference level; a first reception step; a first enable control step of determining whether to activate a first enable signal according to a result of checking the value of the first received pattern signal; and, when the first enable signal is in an activated state in the normal mode, removing a first post-cursor component from the first received normal signal through direct calibration of the currently received value based on the immediately previous received value of the first received normal signal, and then adjusting the driving force of a first input transistor to which the currently received value is applied according to a pattern of the second to Nth previous received values, and removing second to Nth post-cursor components from the first received normal signal.

Advantages of the Invention

[0010] This technology can check for inter-symbol interference (ISI) generated in a signal input through a training operation performed after power-up and before normal operation, and adjust an equalization function applied in normal operation according to the check result.

[0011] That is, after including at least two types of decision feedback equalizers (DFEs) inside the receiver circuit, this technology can perform normal operation in a state where a DFE enabled according to the degree of ISI generation in the input signal checked through the training operation is selected. Thereby, the amount of current consumed by the receiver circuit for using the equalization function in a section where normal operation is performed can be minimized.

Brief Description of Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10A

Figure 10B

Embodiments for Carrying Out the Invention

[0013] Hereinafter, a preferred embodiment of the present invention will be described with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below and can be configured in various different forms. However, this embodiment is provided to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge of the scope of the present invention.

[0014] FIG. 1 is a diagram for explaining an example of a receiver circuit according to an embodiment of the present invention.

[0015] As shown in FIG. 1, the receiver circuit 1 according to an embodiment of the present invention can include a first receiver operation unit 100 and a second receiver operation unit 200. The first receiver operation unit 100 can include a first decision feedback equalizer (DFE1, 103, DFE is an abbreviation for Decision Feedback Equalizer, hereinafter referred to as the first equalizer), and a second decision feedback equalizer (DFE2, 104, hereinafter referred to as the second equalizer). The second receiver operation unit 200 can include a third decision feedback equalizer (DFE3, 203, hereinafter referred to as the third equalizer), and a fourth decision feedback equalizer (DFE4, 203, hereinafter referred to as the fourth equalizer).

[0016] Here, the first receiver operation unit 100 receives the first input pattern signal IN_PAT1_t0 applied via the first pad 106 in the training mode as the first received pattern signal RV_PAT1_t0 according to the training reference level, and then checks whether the value of the received first received pattern signal RV_PAT1_t0 has a predetermined pattern value, and can determine whether to activate the first enable signal EN1.

[0017] Then, the second receiver operation unit 200 receives the second input pattern signal IN_PAT2_t0 applied via the second pad 206 in the training mode as the second received pattern signal RV_PAT2_t0 according to the training reference level, and then checks whether the value of the received second received pattern signal RV_PAT2_t0 has a predetermined pattern value, and can determine whether to activate the second enable signal EN2.

[0018] At this time, the training mode is an operation mode that can enter and exit in response to the mode selection signal MD_SEL, and the first receiver operation unit 100 and the second receiver operation unit 200 can enter and exit in parallel. That is, after entering the training mode, each of the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 can be input in parallel to each of the first receiver operation unit 100 and the second receiver operation unit 200, and the first receiver operation unit 100 determines whether to activate the first enable signal EN1 according to the value of the first received pattern signal RV_PAT1_t0, and the second receiver operation unit 200 determines whether to activate the second enable signal EN2 according to the value of the second received pattern signal RV_PAT2_t0. These operations can be performed in parallel.

[0019] However, the first receiver operation unit 100 and the second receiver operation unit 200 can operate in a completely independent manner. For example, after entering the training mode, when the first receiver operation unit 100 determines to activate the first enable signal EN1, the second receiver operation unit 200 can determine to deactivate the second enable signal EN2.

[0020] On the one hand, the first receiver operation unit 100 can receive the first input normal signal IN_NM1_t0 applied through the first pad 106 in the normal mode that enters after exiting the training mode as the first received normal signal RV_NM1_t0 with a normal reference level different from the training reference level. At this time, the first receiver operation unit 100 can enable at least one of the first equalizer 103 and the second equalizer 104 provided inside in order to improve the SI (signal integrity) characteristics of the first received normal signal RV_NM1_t0.

[0021] In particular, the first receiver operation unit 100 can select whether to enable the first equalizer 103 according to whether the first enable signal EN1 is activated in the normal mode, and can change the operation mode of the second equalizer 104 according to whether the first enable signal EN1 is activated in the normal mode.

[0022] For example, in response to the first enable signal EN1 being activated in the training mode, the first receiver operation unit 100 enables the first equalizer 103 in the normal mode, thereby removing the first post-cursor component with respect to the first received normal signal RV_NM1_t0 based on the first previous received value RV_NM1_t1 of the first received normal signal RV_NM1_t0. Also, in response to the first enable signal EN1 being activated in the training mode, the first receiver operation unit 100 enables the second equalizer 104 in the first operation mode in the normal mode, thereby removing the second to Nth post-cursor components with respect to the first received normal signal RV_NM1_t0 based on the second to Nth previous received values RV_NM1_t2:tN of the first received normal signal RV_NM1_t0. Here, N can be a natural number of 2 or more.

[0023] For another example, in response to the inactivation of the first enable signal EN1 in the training mode, the first receiver operation unit 100 can disable the first equalizer 103 in the normal mode. Further, in response to the inactivation of the first enable signal EN1 in the training mode, the first receiver operation unit 100 enables the second equalizer 104 in the second operation mode in the normal mode, thereby removing the first to Nth post-cursor components for the first received normal signal RV_NM1_t0 based on the first to Nth previously received values RV_NM1_t1:tN of the first received normal signal RV_NM1_t0.

[0024] Then, the second receiver operation unit 200 can receive the second input normal signal IN_NM2_t0 applied via the second pad 206 in the normal mode entered after exiting the training mode as the second received normal signal RV_NM2_t0 with a normal reference level different from the training reference level. At this time, the second receiver operation unit 200 can enable at least one of the third equalizer 203 and the fourth equalizer 204 provided therein to improve the SI characteristics of the second received normal signal RV_NM2_t0.

[0025] In particular, the second receiver operation unit 200 can select whether to enable the third equalizer 203 according to whether the second enable signal EN2 is activated in the normal mode, and can change the operation mode of the fourth equalizer 204 according to whether the second enable signal EN2 is activated in the normal mode.

[0026] For example, in response to the second enable signal EN2 being activated in the training mode, the second receiver operation unit 200 enables the third equalizer 203 in the normal mode, thereby removing the first post-cursor component for the second received normal signal RV_NM2_t0 based on the first previously received value RV_NM1_t1 of the second received normal signal RV_NM2_t0. Also, in response to the second enable signal EN2 being activated in the training mode, the second receiver operation unit 200 enables the fourth equalizer 204 in the first operation mode in the normal mode, thereby removing the second to Nth post-cursor components for the second received normal signal RV_NM2_t0 based on the second to Nth previously received values RV_NM1_t2:tN of the second received normal signal RV_NM2_t0.

[0027] As another example, in response to the second enable signal EN2 being deactivated in the training mode, the second receiver operation unit 200 can disable the third equalizer 203 in the normal mode. Also, in response to the second enable signal EN2 being deactivated in the training mode, the second receiver operation unit 200 enables the fourth equalizer 204 in the second operation mode in the normal mode, thereby removing the first to Nth post-cursor components for the second received normal signal RV_NM2_t0 based on the first to Nth previously received values RV_NM1_t1:tN of the second received normal signal RV_NM2_t0.

[0028] For reference, each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 can include one main-cursor component and N post-cursor components. At this time, the main-cursor component is a significant component of each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_, and can represent the target value of the signal applied through the actual pad. And the post-cursor components are meaningless components of each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_, and can be generated by inter-symbol interference (ISI: Inter-Symbol Interference) between the values RV_NM1_t1:tN & RV_NM2_t1:tN of the signals transmitted before each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 is received.

[0029] On the other hand, the first equalizer 103 provided in the first receiver operation unit 100 and the third equalizer 203 provided in the second receiver operation unit 200 can be Current-summer DFE among the DFE using the direct feedback (Direct Feedback) method. At this time, Current-summer DFE can mean a direct feedback DFE that performs an equalization function in a manner of directly calibrating the currently received signal using the values of the previously received signals. That is, when enabled in the normal mode, each of the first equalizer 103 and the third equalizer 203 can perform an operation of removing the first post-cursor component for each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 based on the first previously received values RV_NM1_t1, RV_NM2_t1 of each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_.

[0030] Then, the second equalizer 104 provided in the first receiver operation unit 100 and the fourth equalizer 204 provided in the second receiver operation unit 200 can be a Gm-control DFE among the DFEs using the direct feedback method. At this time, the Gm-control DFE can mean a direct feedback DFE that performs an equalization function in an indirect manner, that is, a method of adjusting the driving force of the transistor to which the currently received signal is input according to the pattern of the values of the previously received signals.

[0031] That is, when enabled in the first method in the normal mode, each of the second equalizer 104 and the fourth equalizer 204 can perform an operation of removing the second to Nth post-cursor components for each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 based on the second to Nth previously received values RV_NM1_t2:tN and RV_NM2_t2:tN of each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_. Also, when enabled in the second method in the normal mode, each of the second equalizer 104 and the fourth equalizer 204 can perform an operation of removing the first to Nth post-cursor components for each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 based on the first to Nth previously received values RV_NM1_t1:tN and RV_NM2_t1:tN of each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_.

[0032] Referring to both FIGS. 10A, an exemplary circuit configuration of the Current-summer DFE applied to each of the first equalizer 103 and the third equalizer 203 can be understood. In FIG. 10A, IN_t0 and / IN_t0 can be either one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 and its inverted signal. Also, in FIG. 10A, IN_t1 and / IN_t1 can be either one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0, the first previous received values RV_NM1_t1, RV_NM2_t1 thereof, and their inverted received values. Also, in FIG. 10A, ENABLE can be either one of the first enable signal EN1 and the second enable signal EN2. As shown in FIG. 10A, it can be understood that in the Current-summer DFE, calibration is directly performed on the currently received signal using the value of the previously received signal.

[0033] Referring to both FIGS. 10B, an exemplary circuit configuration of the Gm-control DFE applied to each of the second equalizer 104 and the fourth equalizer 204 can be understood. In FIG. 10B, IN_t0 and / IN_t0 can be either one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 and its inverted signal. Also, in FIG. 10B, IN_t1...IN_tN and / IN_t1... / IN_tN can be either one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0, the first to Nth previous received values RV_NM1_t1:tN, RV_NM2_t1:tN thereof, and their inverted received values. Also, in FIG. 10B, ENABLE can be either one of the first enable signal EN1 and the second enable signal EN2. As shown in FIG. 10B, it can be understood that in the Gm-control DFE, the equalization function is performed in an indirect manner, that is, by adjusting the driving force of the transistor to which the currently received signal is input according to the pattern of the value of the previously received signal.

[0034] In particular, in FIG. 10B, among the first enable signal EN1 and the second enable signal EN2, according to any one of them, among the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0, it can be seen that the first previous received values RV_NM1_t1 and RV_NM2_t1 of any one of them are selectively used.

[0035] That is, in FIG. 10B, assuming that each of the first enable signal EN1 and the second enable signal EN2 is a signal activated by a logic low, when each of the first enable signal EN1 and the second enable signal EN2 is activated, among the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0, it can be seen that the first previous received values RV_NM1_t1 and RV_NM2_t1 of any one of them are not used for the equalization function. Conversely, when each of the first enable signal EN1 and the second enable signal EN2 is deactivated, among the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0, it can be seen that the first previous received values RV_NM1_t1 and RV_NM2_t1 of any one of them are used for the equalization function.

[0036] FIG. 2 is a diagram for explaining an example of a first receiver operation unit among the components of the receiver circuit according to an embodiment of the present invention.

[0037] As shown in FIG. 2, the first receiver operation unit 100 disclosed in FIG. 1 described above can include a first input unit 101, a first enable control unit 102, a first equalizer 103, a second equalizer 104, and a first signal storage unit 105.

[0038] Here, the first input unit 101 can receive the first input pattern signal IN_PAT1_t0 applied through the first pad 106 in the training mode as the first received pattern signal RV_PAT1_t0 by the training reference level VRT.

[0039] Also, the first input unit 101 can receive the first input normal signal IN_NM1_t0 applied via the first pad 106 in the normal mode that enters after exiting the training mode as the first received normal signal RV_NM1_t0 by the normal reference level VRN.

[0040] And the first enable control unit 102 can determine whether to activate the first enable signal EN1 according to the result of checking the value of the first received pattern signal RV_PAT1_t0 in the training mode.

[0041] More specifically, after activating the first enable signal EN1 in response to entering the training mode, the first enable control unit 102 can deactivate the first enable signal EN1 in response to the value of the first received pattern signal RV_PAT1_t0 being confirmed as the expected pattern value during the entry period of the training mode. In this way, during the entry period of the training mode, the first enable signal EN1 switched from the activated state to the deactivated state can continue to maintain the deactivated state until entering the training mode again and being switched to the activated state. That is, during the entry period of the training mode, the first enable signal EN1 switched from the activated state to the deactivated state can continue to maintain the deactivated state during the entry period of the normal mode that enters after the training mode.

[0042] Also, after activating the first enable signal EN1 in response to entering the training mode, the first enable control unit 102 can continue to activate the first enable signal EN1 in response to the value of the first received pattern signal RV_PAT1_t0 being confirmed as not the expected pattern value during the entry period of the training mode. That is, during the entry period of the training mode, the first enable signal EN1 that continues to maintain the activated state can continue to maintain the deactivated state even during the entry period of the normal mode that enters after the training mode.

[0043] More specifically, the training mode can be divided into a first section and a second section.

[0044] In the first section of the training mode thus divided, the first input pattern signal IN_PAT1_t0 can be set to the first pattern and applied via the first pad 106.

[0045] Also, in the second section of the training mode that enters after the escape in the first section of the training mode, the first input pattern signal IN_PAT1_t0 can be set to a second pattern different from the first pattern and applied via the first pad 106.

[0046] In summary, the first input pattern signal IN_PAT1_t0 can be input in a form having different patterns from each other in the first section and the second section provided in the training mode.

[0047] Thereby, the first input unit 101 can receive the first input pattern signal IN_PAT1_t0 of the first pattern as the first received pattern signal RV_PAT1_t0 by the first training reference level in the first section of the training mode.

[0048] Also, the first input unit 101 can receive the first input pattern signal IN_PAT1_t0 of the second pattern as the first received pattern signal RV_PAT1_t0 by a second training reference level different from the first training reference level in the second section of the training mode.

[0049] According to an embodiment, the first pattern of the first input pattern signal IN_PAT1_t0 can be a pattern including at least one "1" value among a plurality of "0" values. Thus, by setting the first pattern, the first input unit 101 can set the first training reference level to a level higher than the normal reference level VRN by a predetermined level. That is, the first input unit 101 determines the logic level of the first input pattern signal IN_PAT1_t0 via the first training reference level set to a level higher than the normal reference level VRN by a predetermined level in the first section of the training mode, and can receive it as the first received pattern signal RV_PAT1_t0.

[0050] Also, the second pattern of the first input pattern signal IN_PAT1_t0 can be a pattern including at least one "0" value among a plurality of "1" values. Thus, by setting the second pattern, the first input unit 101 can set the first training reference level to a level lower than the normal reference level VRN by a predetermined level. That is, the first input unit 101 determines the logic level of the first input pattern signal IN_PAT1_t0 via the second training reference level set to a level lower than the normal reference level VRN by a predetermined level in the second section of the training mode, and can receive it as the first received pattern signal RV_PAT1_t0.

[0051] In summary, the training reference level VRT can be set to either a level higher than the normal reference level VRN by a predetermined level or a level lower than the normal reference level VRN by a predetermined level depending on whether the first input pattern signal IN_PAT1_t0 is a signal having which pattern.

[0052] By the operation of the first input unit 101 as described above, the first enable control unit 102 activates the first enable signal EN1 in response to entering the first section of the training mode. After that, when the first confirmation count, which is the sum of the value obtained by counting the number of "1" values included in the first received pattern signal RV_PAT1_t0 in the first section of the training mode and the value obtained by counting the number of "0" values of the first received pattern signal RV_PAT1_t0 in the second section of the training mode, is the expected number, the first enable signal EN1 can be deactivated. Also, if the first confirmation count is different from the expected number, the first enable control unit 102 can continue to activate the first enable signal EN1.

[0053] Then, the first equalizer 103 can operate only during the activation period of the first enable signal EN1, and can remove the first post - cursor component for the first received normal signal RV_NM1_t0 through direct calibration for the current received value RV_NM1_t0 based on the previous received value RV_NM1_t1 before the first of the first received normal signal RV_NM1_t0. That is, by adding the signal DFEOUT1 output from the first equalizer 103 to the first received normal signal RV_NM1_t0, the first post - cursor component for the first received normal signal RV_NM1_t0 can be removed.

[0054] Then, when the first enable signal EN1 is in an active state, the second equalizer 104 adjusts the driving force of the first input transistors 701 and 702 (see FIG. 10B) to which the current received value RV_NM1_t0 is applied according to the pattern of the second to Nth previously received values RV_NM1_t2:tN of the first received normal signal RV_NM1_t0, and can remove the second to Nth post-cursor components with respect to the first received normal signal RV_NM1_t0. That is, by adding the signal DFEOUT2 output from the second equalizer 104 to the first received normal signal RV_NM1_t0, the second to Nth post-cursor components with respect to the first received normal signal RV_NM1_t0 can be removed.

[0055] Also, when the first enable signal EN1 is in an inactive state, the second equalizer 104 adjusts the driving force of the first input transistors 701 and 702 (see FIG. 10B below) to which the current received value RV_NM1_t0 is applied according to the pattern of the first to Nth previously received values RV_NM1_t1:tN of the first received normal signal RV_NM1_t0, and can remove the first to Nth post-cursor components with respect to the first received normal signal RV_NM1_t0. That is, by adding the signal DFEOUT2 output from the second equalizer 104 to the first received normal signal RV_NM1_t0, the first to Nth post-cursor components with respect to the first received normal signal RV_NM1_t0 can be removed.

[0056] And the first signal storage unit 105 can store the first received normal signal RV_NM1_t0 up to a maximum of N in the order of input. Therefore, the first to Nth previously received values RV_NM1_t1:tN of the first received normal signal RV_NM1_t0 can be stored in the first signal storage unit 105. That is, when performing the equalization function in the first equalizer 103 and the second equalizer 104, the first to Nth previously received values RV_NM1_t1:tN stored in the first signal storage unit 105 can be used.

[0057] FIG. 3 is a diagram for explaining an example of the first enable control unit among the components of the first receiver operation unit shown in FIG. 2.

[0058] As shown in FIG. 3, the first enable control unit 102 disclosed in FIG. 2 described above can include four AND gates AND1, AND2, AND3, AND4 and a first counter 1021.

[0059] Specifically, the first AND gate AND1 provided in the first enable control unit 102 can generate a first counting clock signal OPC1 in response to a mode selection signal MD_SEL and a first reception pattern signal RV_PAT1_t0. That is, the first AND gate AND1 can output the first reception pattern signal RV_PAT1_t0 as the first counting clock signal OPC1 in the training mode in which the mode selection signal MD_SEL is set to logic high. Also, the first AND gate AND1 can block the input of the first reception pattern signal RV_PAT1_t0 in the normal mode in which the mode selection signal MD_SEL is set to logic low.

[0060] And the first counter 1021 provided in the first enable control unit 102 can up-count a first counting value CNT1<1:0> in response to the first counting clock signal OPC1. For example, the first counter 1021 can up-count the first counting value CNT1<1:0> according to the number of times the first counting clock signal OPC1 transitions from logic low to logic high.

[0061] Further, the first counter 1021 can initialize the first counting value CNT1<1:0> in response to entering the training mode. That is, the first counter 1021 can initialize the first counting value CNT1<1:0> in response to the mode selection signal MD_SEL transitioning from logic low to logic high. For example, the first counting value CNT1<1:0> can be initialized to "00".

[0062] Then, the second AND gate AND2, the third AND gate AND3, and the fourth AND gate AND4 provided in the first enable control unit 102 maintain the first enable signal EN1 at logic low in response to the first counting value CNT1<1:0> being smaller than the planned value, and can transition the first enable signal EN1 from logic low to logic high in response to the first counting value CNT1<1:0> reaching the planned value. For example, as shown in the drawing, the first enable signal EN1 can be transitioned from logic low to logic high in response to the first counting value CNT1<1:0> becoming "11".

[0063] FIG. 4 is a diagram for explaining an example of a second receiver operation unit among the components of the receiver circuit according to an embodiment of the present invention.

[0064] As shown in FIG. 4, the second receiver operation unit 200 disclosed in FIG. 1 described above can include a second input unit 201, a second enable control unit 202, a third equalizer 203, a fourth equalizer 204, and a second signal storage unit 205.

[0065] Here, the second input unit 201 can receive the second input pattern signal IN_PAT2_t0 applied via the second pad 206 in the training mode as the second received pattern signal RV_PAT2_t0 by the training reference level VRT.

[0066] Further, the second input unit 201 can receive, as a second received normal signal RV_NM2_t0, a second input normal signal IN_NM2_t0 applied via a second pad 206 in a normal mode that enters after exiting the training mode, by a normal reference level VRN.

[0067] And the second enable control unit 202 can determine whether to activate a second enable signal EN2 according to the result of checking the value of the second received pattern signal RV_PAT2_t0 in the training mode.

[0068] More specifically, after activating the second enable signal EN2 in response to entering the training mode, the second enable control unit 202 can deactivate the second enable signal EN2 in response to the value of the second received pattern signal RV_PAT2_t0 being confirmed as a predetermined pattern value during the entry period of the training mode. In this way, the second enable signal EN2 switched from the activated state to the deactivated state during the entry period of the training mode can continue to maintain the deactivated state until it enters the training mode again and is switched to the activated state. That is, during the entry period of the training mode, the second enable signal EN2 switched from the activated state to the deactivated state can continue to maintain the deactivated state during the entry period of the normal mode that enters after the training mode.

[0069] Further, after activating the second enable signal EN2 in response to entering the training mode, the second enable control unit 202 can continue to activate the second enable signal EN2 in response to the value of the second received pattern signal RV_PAT2_t0 not being confirmed as the predetermined pattern value during the entry period of the training mode. That is, during the entry period of the training mode, the second enable signal EN2 that continues to maintain the activated state can continue to maintain the deactivated state even during the entry period of the normal mode that enters after the training mode.

[0070] More specifically, the training mode can be divided into a first section and a second section.

[0071] In the first section of the training mode thus divided, the second input pattern signal IN_PAT2_t0 can be set to the first pattern and applied via the second pad 206.

[0072] Also, in the second section of the training mode that enters after the escape from the first section of the training mode, the second input pattern signal IN_PAT2_t0 can be set to a second pattern different from the first pattern and applied via the second pad 206.

[0073] In summary, the second input pattern signal IN_PAT2_t0 can be input in a form having different patterns from each other in the first section and the second section provided in the training mode.

[0074] Thereby, the second input unit 201 can receive the second input pattern signal IN_PAT2_t0 of the first pattern as the second received pattern signal RV_PAT2_t0 by the first training reference level in the first section of the training mode.

[0075] Also, the second input unit 201 can receive the second input pattern signal IN_PAT2_t0 of the second pattern as the second received pattern signal RV_PAT2_t0 by a second training reference level different from the first training reference level in the second section of the training mode.

[0076] According to an embodiment, the first pattern of the second input pattern signal IN_PAT2_t0 can be a pattern in which at least one "1" value is included among a plurality of "0" values. In this way, by setting the first pattern, the second input unit 201 can set the first training reference level to a level higher than the normal reference level VRN by a level expected in advance. That is, the second input unit 201 can determine the logic level of the second input pattern signal IN_PAT2_t0 via the first training reference level set to a level higher than the normal reference level VRN by a level expected in advance in the first section of the training mode, and receive it as the second received pattern signal RV_PAT2_t0.

[0077] Also, the second pattern of the second input pattern signal IN_PAT2_t0 can be a pattern in which at least one "0" value is included among a plurality of "1" values. In this way, by setting the second pattern, the second input unit 201 can set the first training reference level to a level lower than the normal reference level VRN by a level expected in advance. That is, the second input unit 201 can determine the logic level of the second input pattern signal IN_PAT2_t0 via the second training reference level set to a level lower than the normal reference level VRN by a level expected in advance in the second section of the training mode, and receive it as the second received pattern signal RV_PAT2_t0.

[0078] In summary, the training reference level VRT can be set to either one of a level higher than the normal reference level VRN by a level expected in advance and a level lower than the normal reference level VRN by a level expected in advance depending on whether the second input pattern signal IN_PAT2_t0 is a signal having which pattern.

[0079] By the operation of the second input unit 201 as described in the foregoing explanation, the second enable control unit 202 activates the second enable signal EN2 in response to entering the first section of the training mode. After that, when the second confirmation count, which is the sum of the value obtained by counting the number of "1" values included in the second received pattern signal RV_PAT2_t0 in the first section of the training mode and the value obtained by counting the number of "0" values of the second received pattern signal RV_PAT2_t0 in the second section of the training mode, is the expected number, the second enable signal EN2 can be deactivated. Also, when the second confirmation count is different from the expected number, the second enable control unit 202 can continue to activate the second enable signal EN2.

[0080] And the third equalizer 203 can operate only during the activation period of the second enable signal EN2, and can remove the first post-cursor component for the second received normal signal RV_NM2_t0 through direct calibration for the current received value RV_NM2_t0 based on the first previously received value RV_NM2_t1 of the second received normal signal RV_NM2_t0. That is, by adding the signal DFEOUT3 output from the third equalizer 203 to the second received normal signal RV_NM2_t0, the first post-cursor component for the second received normal signal RV_NM2_t0 can be removed.

[0081] Then, when the second enable signal EN2 is in the active state, the fourth equalizer 204 adjusts the driving force of the second input transistors 701 and 702 (see FIG. 10B below) to which the current received value RV_NM2_t0 is applied according to the pattern of the second to Nth previous received values RV_NM2_t2:tN of the second received normal signal RV_NM2_t0, and can remove the second to Nth post-cursor components with respect to the second received normal signal RV_NM2_t0. That is, by adding the signal DFEOUT4 output from the fourth equalizer 204 to the second received normal signal RV_NM2_t0, the second to Nth post-cursor components with respect to the second received normal signal RV_NM2_t0 can be removed.

[0082] Also, when the second enable signal EN2 is in the inactive state, the fourth equalizer 204 adjusts the driving force of the second input transistors 701 and 702 (see FIG. 10B below) to which the current received value RV_NM2_t0 is applied according to the pattern of the first to Nth previous received values RV_NM2_t1:tN of the second received normal signal RV_NM2_t0, and can remove the first to Nth post-cursor components with respect to the second received normal signal RV_NM2_t0. That is, by adding the signal DFEOUT2 output from the fourth equalizer 204 to the second received normal signal RV_NM2_t0, the first to Nth post-cursor components with respect to the second received normal signal RV_NM2_t0 can be removed.

[0083] And the second signal storage unit 205 can store the second received normal signal RV_NM2_t0 up to a maximum of N in the order of input. Therefore, the first to Nth previous received values RV_NM2_t1:tN of the second received normal signal RV_NM2_t0 can be stored in the second signal storage unit 205. That is, when performing the equalization function in the third equalizer 203 and the fourth equalizer 204, the first to Nth previous received values RV_NM2_t1:tN stored in the second signal storage unit 205 can be used.

[0084] FIG. 5 is a diagram for explaining an example of a second enable control unit among the components of the second receiver operation unit shown in FIG. 2.

[0085] As shown in FIG. 5, the second enable control unit 202 disclosed in FIG. 4 described above can include four AND gates AND5, AND6, AND7, AND8 and a second counter 2021.

[0086] Specifically, the fifth AND gate AND5 provided in the second enable control unit 202 can generate a second counting clock signal OPC2 in response to a mode selection signal MD_SEL and a second reception pattern signal RV_PAT2_t0. That is, the fifth AND gate AND5 can output the second reception pattern signal RV_PAT2_t0 as the second counting clock signal OPC2 in the training mode in which the mode selection signal MD_SEL is set to logic high. Also, the fifth AND gate AND5 can block the input of the second reception pattern signal RV_PAT2_t0 in the normal mode in which the mode selection signal MD_SEL is set to logic low.

[0087] And the second counter 2021 provided in the second enable control unit 202 can up-count a second counting value CNT2<1:0> in response to the second counting clock signal OPC2. For example, the second counter 2021 can up-count the second counting value CNT2<1:0> according to the number of times the second counting clock signal OPC2 transitions from logic low to logic high.

[0088] Also, the second counter 2021 can initialize the second counting value CNT2<1:0> in response to entering the training mode. That is, the second counter 2021 can initialize the second counting value CNT2<1:0> in response to the mode selection signal MD_SEL transitioning from logic low to logic high. For example, the second counting value CNT2<1:0> can be initialized to "00".

[0089] Then, the sixth AND gate AND6, the seventh AND gate AND7, and the eighth AND gate AND8 provided in the second enable control unit 202 maintain the second enable signal EN2 at logic low in response to the second counting value CNT2<1:0> being smaller than the expected value, and can transition the second enable signal EN2 from logic low to logic high in response to the second counting value CNT2<1:0> reaching the expected value. For example, as shown in the drawing, the second enable signal EN2 can be transitioned from logic low to logic high in response to the second counting value CNT2<1:0> becoming "11".

[0090] FIG. 6 is a diagram for explaining an example of the first signal storage unit or the second signal storage unit among the components of the receiver circuit according to an embodiment of the present invention.

[0091] As shown in FIG. 6, the first signal storage unit 105 disclosed in FIG. 2 or the second signal storage unit 205 disclosed in FIG. 4 described above can include N signal storage latches LF1, LF2,..., LFN.

[0092] The currently received signal IN_t0 input to the first signal storage unit 105 or the second signal storage unit 205 can be stored in the first signal storage latch LF1 among the N signal storage latches LF1, LF2, ..., LFN. In this way, when the currently received signal IN_t0 is input to the first signal storage latch LF1, the signal stored in the first signal storage latch LF1 can be transmitted to the second signal storage latch LF2 as the first previously received signal IN_t1 and then stored. Similarly, when the first previously received signal IN_t1 is input to the second signal storage latch LF2, the signal stored in the second signal storage latch LF2 can be transmitted to the third signal storage latch LF3 as the second previously received signal IN_t2 and then stored. In such a manner, a maximum of N received signals IN_t0:tN can be stored in each of the N signal storage latches LF1, LF2, ..., LFN.

[0093] Here, the currently received signal IN_t0 can be the first received normal signal RV_NM1_t0 or the second received normal signal RV_NM2_t0. Also, the first to Nth previously received signals IN_t1:tN can be the first to Nth previously received signals RV_NM1_t1:tN, RV_NM2_t1:tN of each of the first received normal signal RV_NM1_t0 or the second received normal signal RV_NM2_.

[0094] FIG. 7 is a diagram for explaining an example of a training operation performed in a receiver circuit according to an embodiment of the present invention.

[0095] As shown in FIG. 7, at time point S1, it is possible to enter the training mode while the mode selection signal MD_SEL transitions from logic low to logic high.

[0096] At time point S1, while entering the training mode, the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can be initialized together, and thereby, the first enable signal EN1 and the second enable signal EN2 can be activated to logic low together. Thus, in response to the first enable signal EN1 and the second enable signal EN2 being activated to logic low together at time point S1, the first equalizer 103 provided in the first receiver operation unit 100 and the third equalizer 203 provided in the second receiver operation unit 200 can be set to the enabled state together. From time point S1 to time point S3, it can be the first section of the training mode.

[0097] In the first section of the training mode, each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be set to the first pattern (assuming it is a pattern having at least one "1" value among a plurality of "0" values) and applied.

[0098] After determining the logic level of each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 via the first training reference level VRT<1> that is higher than the normal reference level VRN by a level VIHL expected, whether the determined logic level has the first pattern, that is, whether each of the first received pattern signal RV_PAT1_t0 or the second received pattern signal RV_PAT2_t0 has the first pattern, can determine whether the value of the first counting value CNT1<1:0> or the second counting value CNT2<1:0> can be up-counted.

[0099] In the drawings, it is assumed that in the first section of the training mode, the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 are both received in a state of having the first pattern. Therefore, the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can both be up-counted from "00" to "01".

[0100] At time point S3, the first section of the training mode ends and it is possible to enter the second section. Thereby, the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be changed from the first pattern to the second pattern, and thereby, the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can each be up-counted from "01" to "10".

[0101] Thus, time point S3, which is the time when the first section of the training mode ends and at the same time enters the second section, can be a preset time point. For example, after time point S1, the time point when a predetermined time or the toggling of a predetermined system clock (not shown) is repeated can be set as time point S3. Therefore, when the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 are changed from the first pattern to the second pattern at time point S3, the operation of up-counting the first counting value CNT1<1:0> and the second counting value CNT2<1:0> from "01" to "10" respectively can be an operation that has already been reflected in the design of the first receiver operation unit 100 and the second receiver operation unit 200.

[0102] From time point S3 to time point S4, it can be the second section of the training mode.

[0103] In the second section of the training mode, each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be set to and applied with a second pattern (assuming it is a pattern having at least one "0" value among a plurality of "1" values).

[0104] After determining the logic level of each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_ through a second training reference level VRT<2> that is lower than the normal reference level VRN by a level VIHL scheduled, whether the determined logic level has the second pattern, that is, whether each of the first received pattern signal RV_PAT1_t0 or the second received pattern signal RV_PAT2_t0 has the second pattern, can determine whether the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can be up-counted.

[0105] In the drawings, it is assumed that in the second section of the training mode, both the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 are received in a state of having the second pattern. Therefore, both the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can be up-counted from "10" to "11".

[0106] Thus, when the second section of the training mode ends at time point S4, the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can each become the scheduled value "11". Therefore, at time point S4, each of the first enable signal EN1 and the second enable signal EN2 can transition from the logic low in the activated state to the logic high in the deactivated state. That is, in response to both the first enable signal EN1 and the second enable signal EN2 being deactivated to logic high at time S4, both the first equalizer 103 provided in the first receiver operation unit 100 and the third equalizer 203 provided in the second receiver operation unit 200 can be set to a disabled state.

[0107] For reference, unlike in the drawings, it can be assumed that in the first section of the training mode, the first received pattern signal RV_PAT1_t0 is received in a state having the first pattern, and the second received pattern signal RV_PAT2_t0 is received in a state not having the first pattern. In such a case, the first counting value CNT1<1:0> is up-counted from "00" to "01", but the second counting value CNT2<1:0> can maintain "00". In such a case, even if both the first counting value CNT1<1:0> and the second counting value CNT2<1:0> are up-counted at each of time S3 and time S4, only the first counting value CNT1<1:0> can become "11", and the second counting value CNT2<1:0> can become "10". Thereby, the first enable signal EN1 transitions from logic low, which is the activated state, to logic high, which is the deactivated state, but the second enable signal EN2 can maintain logic low, which is the activated state. That is, when the second section of the training mode ends, the first equalizer 103 provided in the first receiver operation unit 100 is set to a disabled state, but the third equalizer 203 provided in the second receiver operation unit 200 can maintain the enabled state.

[0108] FIG. 8 is a diagram for explaining another example of a training operation performed in a receiver circuit according to an embodiment of the present invention.

[0109] As shown in FIG. 8, it is possible to enter the training mode while the mode selection signal MD_SEL transitions from logic low to logic high at time S5.

[0110] At time point S5, while entering the training mode, the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can be initialized together, and thereby, the first enable signal EN1 and the second enable signal EN2 can be activated to logic low together. Thus, in response to the first enable signal EN1 and the second enable signal EN2 being activated to logic low together at time point S1, the first equalizer 103 provided in the first receiver operation unit 100 and the third equalizer 203 provided in the second receiver operation unit 200 can be set to the enabled state together. From time point S5 to time point S7, it can be the first section of the training mode.

[0111] In the first section of the training mode, each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be set to the first pattern (assuming it is a pattern having at least one "1" value among a plurality of "0" values) and applied.

[0112] After determining the logic level of each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 via the first training reference level VRT<1> that is higher than the normal reference level VRN by a level VIHL planned, whether the determined logic level has the first pattern, that is, whether each of the first received pattern signal RV_PAT1_t0 or the second received pattern signal RV_PAT2_t0 has the first pattern, can determine whether the first counting value CNT1<1:0> or the second counting value CNT2<1:0> can be up-counted.

[0113] In the drawings, it is assumed that in the first section of the training mode, the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 are both received in a state having the first pattern. Therefore, both the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can be up-counted from "00" to "01".

[0114] At time point S7, the first section of the training mode ends and it is possible to enter the second section. Thereby, the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be changed from the first pattern to the second pattern, and thereby, the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can be up-counted from "01" to "10" respectively.

[0115] Thus, the time point S7, at which the first section of the training mode ends and at the same time enters the second section, can be a preset time point. For example, after time point S5, the time point at which a predetermined time or the toggling of a predetermined system clock (not shown) is repeated can be set as time point S7. Therefore, when the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 are changed from the first pattern to the second pattern at time point S7, the operation in which the first counting value CNT1<1:0> and the second counting value CNT2<1:0> are up-counted from "01" to "10" respectively can be an operation already reflected in the design of the first receiver operation unit 100 and the second receiver operation unit 200.

[0116] From time point S7 to time point S8, it can be the second section of the training mode.

[0117] In the second section of the training mode, each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be set to and applied with a second pattern (assuming it is a pattern having at least one "0" value among a plurality of "1" values).

[0118] After determining the logic level of each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_ through a second training reference level VRT<2> that is lower than the normal reference level VRN by a level VIHL planned, whether the determined logic level has the second pattern, that is, whether each of the first received pattern signal RV_PAT1_t0 or the second received pattern signal RV_PAT2_t0 has the second pattern, can determine whether the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can be up-counted.

[0119] In the drawings, it is assumed that each of the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 is input in a state (Not Receiving) where it does not have the second pattern in the second section of the training mode. Therefore, the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can both continue to maintain "10" without being up-counted (Not Counting) from "10".

[0120] Thus, when the second section of the training mode ends at time point S8, the first counting value CNT1<1:0> and the second counting value CNT2<1:0> can each become "10" different from the planned values. Therefore, each of the first enable signal EN1 and the second enable signal EN2 at time point S8 can continue to maintain a logic low in the activated state.

[0121] That is, in response to the first enable signal EN1 and the second enable signal EN2 both continuing to be activated at logic low at time S8, the first equalizer 103 provided in the first receiver operation unit 100 and the third equalizer 203 provided in the second receiver operation unit 200 can both continue to be set to the enabled state.

[0122] For reference, unlike the drawings, it can be assumed that in the second section of the training mode, the first received pattern signal RV_PAT1_t0 is received in a state having the second pattern, and the second received pattern signal RV_PAT2_t0 is received in a state not having the second pattern. In such a case, the first counting value CNT1<1:0> is up-counted from "10" to "11", but the second counting value CNT2<1:0> can maintain "10". Thereby, the first enable signal EN1 transitions from logic low which is the activated state to logic high which is the inactivated state, but the second enable signal EN2 can maintain logic low which is the activated state. That is, when the second section of the training mode ends, the first equalizer 103 provided in the first receiver operation unit 100 is set to the disabled state, but the third equalizer 203 provided in the second receiver operation unit 200 can maintain the enabled state.

[0123] FIG. 9 is a diagram for explaining the order of the training operation performed in the receiver circuit according to the embodiment of the present invention.

[0124] As shown in FIG. 9, when entering the training mode, the first equalizer 103 and the second equalizer 104 provided in the first receiver operation unit 100 and the third equalizer 203 and the fourth equalizer 204 provided in the second receiver operation unit 200 can both be set to the enabled state (K10).

[0125] Next, the training reference level VRT can be set to a first training reference level VRT<1> that is higher than the normal reference level VRN by a level VIHL planned in advance (K20).

[0126] After K20, the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 having a first pattern (assumed to be a pattern having at least one "1" value among a plurality of "0" values) can be input into the first section of the training mode (K30).

[0127] After K30, the first training reference level VRT<1> is compared with the potential levels of each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_, and the logic levels of each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_ are determined, and the first received pattern signal RN_PAT1_t0 and the second received pattern signal RN_PAT2_t0 can be generated according to the logic levels corresponding to the determined results (K40).

[0128] It is possible to confirm whether the first received pattern signal RN_PAT1_t0 and the second received pattern signal RN_PAT2_t0 generated at K40 have the first pattern (K50). At this time, since it is assumed that the first pattern is a pattern having at least one "1" value among a plurality of "0" values, at K50, it can be an operation of confirming whether there is a logic high glitch between the logic levels of each of the first received pattern signal RN_PAT1_t0 and the second received pattern signal RN_PAT2_t0 being logic low.

[0129] If the first received pattern signal RN_PAT1_t0 or the second received pattern signal RN_PAT2_t0 is different from the first pattern and does not toggle at K50 (NO in K50), the first equalizer 103 or the third equalizer 203 set to the enabled state at K10 can be enabled (K60).

[0130] When the first received pattern signal RN_PAT1_t0 or the second received pattern signal RN_PAT2_t0 toggles according to the first pattern at K50 (YES of K50), the training reference level VRT can be set to a second training reference level VRT<2> that is lower than the normal reference level VRN by a level VIHL expected (K70).

[0131] After K70, enter the first section of the training mode, and a first input pattern signal IN_PAT1_t0 and a second input pattern signal IN_PAT2_t0 having a second pattern (assumed to be a pattern having at least one "0" value among a plurality of "1" values) can be input (K80).

[0132] After K80, compare the potential levels of the second training reference level VRT<2> with each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_, determine the logic levels of each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_, and generate the first received pattern signal RN_PAT1_t0 and the second received pattern signal RN_PAT2_t0 according to the logic levels corresponding to the determined results (K90).

[0133] It is possible to check whether the first received pattern signal RN_PAT1_t0 and the second received pattern signal RN_PAT2_t0 generated at K90 have the second pattern (K100). At this time, since it is assumed that the second pattern is a pattern having at least one "0" value among a plurality of "1" values, at K100, it can be an operation of checking whether there is a logic low toggle while the logic levels of each of the first received pattern signal RN_PAT1_t0 and the second received pattern signal RN_PAT2_t0 are logic high.

[0134] If the first received pattern signal RN_PAT1_t0 or the second received pattern signal RN_PAT2_t0 at K100 is different from the second pattern and does not toggle (NO of K100), the first equalizer 103 or the third equalizer 203 set to the enabled state at K10 can be enabled (K110).

[0135] If the first received pattern signal RN_PAT1_t0 or the second received pattern signal RN_PAT2_t0 at K100 is toggled by the second pattern (YES of K100), the first equalizer 103 or the third equalizer 203 set to the enabled state at K10 can be disabled (K120).

[0136] According to an embodiment, the first received pattern signal RN_PAT1_t0 at K50 described above is different from the first pattern and does not toggle, and the second received pattern signal RN_PAT2_t0 can be toggled by the first pattern. In such a case, the first equalizer 103 can continue to maintain the enabled state via K60, and the operations corresponding to K70 to K120 can be performed only for the second received pattern signal RN_PAT2_t0.

[0137] According to an embodiment, the second received pattern signal RN_PAT2_t0 at K100 described above is different from the second pattern and does not toggle, and the first received pattern signal RN_PAT1_t0 can be toggled by the second pattern. In such a case, the second equalizer 203 can continue to maintain the enabled state via K110, and the first equalizer 103 can be disabled via K120.

[0138] The present invention described above is not limited by the above-described embodiments and the attached drawings, and it will be apparent to those having ordinary knowledge in the technical field to which the present invention pertains that various substitutions, modifications, and changes are possible without departing from the technical idea of the present invention.

[0139] For example, the logic gates and transistors exemplified in the foregoing embodiments should be realized such that their positions and types differ depending on the polarity of the input signal.

Claims

1. a first input unit that receives a first input pattern signal applied through a first pad in a training mode as a first received pattern signal according to a training reference level, and receives a first input normal signal applied through the first pad in a normal mode entered after exiting the training mode as a first received normal signal according to a normal reference level; a first enable control unit that determines whether to activate a first enable signal according to a result of checking a value of the first receiving pattern signal in the training mode; a first decision feedback equalizer (DFE) that operates only during an activation period of the first enable signal and removes a first post-cursor component of the first received normal signal through direct calibration of a current received value based on a first previous received value of the first received normal signal; a second decision feedback equalizer for adjusting a driving force of a first input transistor to which a currently received value is applied according to a pattern of second through Nth previous received values ​​of the first received normal signal when the first enable signal is in an active state, and removing second through Nth post-cursor components of the first received normal signal; Equipped with N is a receiver circuit that is a natural number equal to or greater than two.

2. The second decision feedback equalizer comprises:

2. The receiver circuit of claim 1, wherein when the first enable signal is in an inactive state, the driving force of a first input transistor to which a currently received value is applied is adjusted according to a pattern of the first to Nth previous received values ​​of the first received normal signal, and the first to Nth post-cursor components for the first received normal signal are removed.

3. The first enable control unit includes:

3. The receiver circuit of claim 2, wherein the first enable signal is activated in response to entering the training mode, and then the first enable signal is deactivated in response to a value of the first received pattern signal being confirmed as a predetermined pattern value during an entry period of the training mode.

4. a second input unit that receives a second input pattern signal applied through a second pad in the training mode as a second received pattern signal according to the training reference level, and receives a second input normal signal applied through the second pad in the normal mode as a second received normal signal according to the normal reference level; a second enable control unit that determines whether to activate the second enable signal according to a result of checking the value of the second receiving pattern signal in the training mode; a third decision feedback equalizer that operates only during an activation period of the second enable signal and removes a first post-cursor component for the second received normal signal through direct calibration of a current received value based on a first previously received value of the second received normal signal; a fourth decision feedback equalizer for adjusting a driving force of a second input transistor to which a currently received value is applied according to a pattern of second through Nth previous received values ​​of the second received normal signal when the second enable signal is in an active state, and removing second through Nth post-cursor components of the second received normal signal; The receiver circuit of claim 2 further comprising:

5. The fourth decision feedback equalizer comprises:

5. The receiver circuit of claim 4, further comprising: a second input transistor having a current received value applied thereto, the second input transistor being adjusted in accordance with a pattern of the first through Nth previous received values ​​of the second received normal signal when the second enable signal is in an inactive state; and a first through Nth post-cursor components of the second received normal signal being removed.

6. The second enable control unit includes:

6. The receiver circuit of claim 5, further comprising: a second enable signal activating means for activating the second enable signal in response to entering the training mode, and then deactivating the second enable signal in response to a value of the second received pattern signal being confirmed to be the predetermined pattern value during an entry period of the training mode.

7. each of the first and second input pattern signals is set to a first pattern in a first period of the training mode and applied in parallel through each of the first and second pads, and subsequently set to a second pattern different from the first pattern in a second period of the training mode and applied in parallel through each of the first and second pads; In a first period of the training mode, the first and second input units receive the first and second input pattern signals as the first and second received pattern signals, respectively, according to a first training reference level; 6. The receiver circuit of claim 5, wherein in a second section of the training mode, each of the first and second input sections receives each of the first and second input pattern signals as each of the first and second received pattern signals at a second training reference level different from the first training reference level.

8. the first pattern is a pattern including at least one "1" value among a plurality of "0" values, the second pattern is a pattern including at least one "0" value among a plurality of "1" values, the first training reference level is higher than the normal reference level by a predetermined level; 8. The receiver circuit of claim 7, wherein the second training reference level has a level lower than the normal reference level by the predetermined level.

9. The first enable control unit includes:

9. The receiver circuit of claim 8, further comprising: a first confirmation number obtained by adding a counted number of “1” values ​​included in the first receiving pattern signal in a first period of the training mode to a counted number of “0” values ​​included in the first receiving pattern signal in a second period of the training mode after activating the first enable signal in response to entering the training mode, and then deactivating the first enable signal when the first confirmation number is a predetermined number.

10. The second enable control unit includes:

10. The receiver circuit of claim 9, further comprising: a second enable signal activating means for activating the second enable signal in response to entering the training mode; and a second confirmation number obtained by adding a counted number of “1” values ​​included in the second receiving pattern signal in a first period of the training mode to a counted number of “0” values ​​included in the second receiving pattern signal in a second period of the training mode, the second enable signal being deactivated when the second confirmation number is equal to the expected number.

11. a first receiving step of receiving a first input pattern signal applied through a first pad in a training mode as a first received pattern signal according to a training reference level, and receiving a first input normal signal applied through the first pad in a normal mode entered after exiting the training mode as a first received normal signal according to a normal reference level; a first enable control step of determining whether or not to activate a first enable signal depending on a result of checking the value of the first reception pattern signal; When the first enable signal is in an active state in the normal mode, removing a first post-cursor component of the first received normal signal through direct calibration of a current received value based on a first previous received value of the first received normal signal, and then adjusting a driving force of a first input transistor to which a current received value is applied according to a pattern of second through Nth previous received values, thereby removing second through Nth post-cursor components of the first received normal signal; Including, A method of operating a receiver circuit, where N is a natural number greater than or equal to 2.

12. 12. The method of claim 11, further comprising the steps of: adjusting a driving force of a first input transistor to which a currently received value is applied according to a pattern of 1st to Nth previous received values ​​of the first received normal signal when the first enable signal is in an inactive state in the normal mode; and removing 1st to Nth post-cursor components for the first received normal signal.

13. The first enable control step includes: activating the first enable signal in response to entering the training mode; deactivating the first enable signal in response to a value of the first received pattern signal being confirmed as a predetermined pattern value during an entry section of the training mode; maintaining an activated state of the first enable signal in response to a value of the first received pattern signal being determined not to be the predetermined pattern value during an entry period of the training mode; 13. A method of operating a receiver circuit as claimed in claim 12, comprising:

14. a second receiving step of receiving a second input pattern signal applied through a second pad in the training mode as a second received pattern signal according to the training reference level, and receiving a second input normal signal applied through the second pad in the normal mode as a second received normal signal according to the normal reference level; a second enable control step of determining whether or not to activate a second enable signal depending on a result of checking the value of the second reception pattern signal; When the second enable signal is in an active state in the normal mode, removing a first post-cursor component of the second received normal signal through direct calibration of a current received value based on a first previous received value of the second received normal signal, and then adjusting a driving force of a second input transistor to which a current received value is applied according to a pattern of second through Nth previous received values, thereby removing second through Nth post-cursor components of the second received normal signal; The method of operating a receiver circuit of claim 12 further comprising:

15. 15. The method of claim 14, further comprising the steps of: adjusting a driving force of the second input transistor to which a currently received value is applied according to a pattern of 1st to Nth previous received values ​​of the second received normal signal when the second enable signal is in an inactive state in the normal mode; and removing 1st to Nth post-cursor components for the second received normal signal.

16. The second enable control step includes: activating the second enable signal in response to entering the training mode; deactivating the second enable signal in response to a value of the second received pattern signal being confirmed as a predetermined pattern value during an entry section of the training mode; maintaining an activated state of the second enable signal in response to a value of the second received pattern signal being determined not to be the predetermined pattern value during an entry period of the training mode; 20. A method of operating a receiver circuit as claimed in claim 15, comprising:

17. each of the first and second input pattern signals is set to a first pattern in a first period of the training mode and applied in parallel through each of the first and second pads, and subsequently set to a second pattern different from the first pattern in a second period of the training mode and applied in parallel through each of the first and second pads; The first receiving step includes: receiving the first input pattern signal as the first received pattern signal according to a first training reference level in a first period of the training mode; receiving the first input pattern signal as the first received pattern signal according to a second training reference level different from the first training reference level in a second period of the training mode; Including, The second receiving step includes: receiving the second input pattern signal as the second received pattern signal according to the first training reference level in a first period of the training mode; receiving the second input pattern signal as the second received pattern signal according to the second training reference level in a second period of the training mode; 20. A method of operating a receiver circuit as claimed in claim 15, comprising:

18. the first pattern is a pattern including at least one "1" value among a plurality of "0" values, the second pattern is a pattern including at least one "0" value among a plurality of "1" values, the first training reference level is higher than the normal reference level by a predetermined level; 20. The method of claim 17, wherein the second training reference level has a level lower than the normal reference level by the predetermined level.

19. The first enable control step includes: activating the first enable signal in response to entering the training mode; a first counting step of counting the number of "1" values ​​included in the first reception pattern signal during a first period of the training mode; a second counting step of counting the number of '0' values ​​included in the first receiving pattern signal in a second period of the training mode; deactivating the first enable signal when a first confirmation number obtained by adding the values ​​counted in the first and second counting steps is a predetermined number; maintaining an active state of the first enable signal if the first confirmed number is different from the expected number; 20. A method of operating a receiver circuit as claimed in claim 18, comprising:

20. The second enable control step includes: activating the second enable signal in response to entering the training mode; a third counting step of counting the number of "1" values ​​included in the second receiving pattern signal during the first period of the training mode; a fourth counting step of counting the number of '0' values ​​included in the second receiving pattern signal during a second period of the training mode; deactivating the second enable signal when a second confirmed number obtained by adding the values ​​counted in the third and fourth counting steps is equal to the predetermined number; maintaining an active state of the second enable signal if the second confirmed number is different from the expected number; 20. A method of operating a receiver circuit as claimed in claim 19, comprising:

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