PMOS transistor, manufacturing method thereof, CMOS circuit and manufacturing method thereof

Abstract

To provide a manufacturing method of a PMOS transistor in which a line width of a source / drain structure is less than 40 nm, the PMOS transistor, a CMOS circuit and a manufacturing method of the CMOS circuit.SOLUTION: The method includes the steps of: providing a base and forming a source / drain trench isolation on the base; growing an SiGe material in the source / drain trench isolation to form an SiGe layer and growing an Si thin film layer on a surface of the SiGe layer to form a multilayer structure of the SiGe layer and the Si thin film layer; and growing a first Co thin film layer on the multilayer structure and then performing anneal processing so as to form a first CoSi2 thin film layer by reacting Co in the first Co thin film layer and Si in the Si thin film layer. An entire structure formed in the source / drain trench isolation is a source / drain, and the first CoSi2 thin film layer is an upper structure of the source / drain.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a PMOS transistor and a manufacturing method thereof, a CMOS circuit and a manufacturing method thereof.

Background Art

[0002] The silicon cobalt alloy consists of three phases of Si2Co / SiCo / CoSi2. Since CoSi2 is a low-resistance phase while Co2Si / CoSi are high-resistance phases, the resistance of the source / drain of the PMOS increases. In the thin film deposition process, first, a Co thin film is deposited. After RTP (250°C to 410°C), the Co thin film diffuses as a diffusion source to Si, and first Co2Si is formed. As the temperature of RTP (410°C to 510°C) increases, the Co thin film further diffuses, and CoSi is gradually formed. When the temperature of RTP (>750°C) further increases, Si begins to diffuse into the CoSi thin film, and finally a single low-resistance phase CoSi2 is formed.

[0003] On the other hand, when the CoSi2 process method is adopted, in the PMOS region, especially in the PMOS with a small line width (the line width of the source / drain structure is less than 40 nm), when SiGe is epitaxially grown on the source / drain, the Si content in the SiGe epitaxial structure decreases with respect to the pure Si content. As a result, there is insufficient Si for reacting with Co, and the temperature required to form the low-resistance phase CoSi2 increases. If the temperature is too high, CoSi2 is likely to agglomerate, leading to wire breakage and affecting the product quality.

[0004] In logic circuits of 28 nm or less, most semiconductor manufacturers have started development in the direction of NiSi. However, NiSi begins to undergo a phase transition at a high temperature (>650°C) and becomes the high-resistance phase NiSi2. Therefore, the requirement in the post-process of NiSi is less than 650°C. When the post-process requires a high temperature, it is difficult to use the NiSi alloy. In other words, for processes that require a high temperature, the CoSi2 process scheme is still required.

[0005] Therefore, there is a need for a new process scheme that solves the problem of insufficient Si content in the SiGe epitaxial structure of the source / drain of a PMOS with a small line width and reliably forms CoSi2 with a low-resistance phase on the surface of the SiGe epitaxial structure.

Summary of the Invention

[0006] Embodiments of the present invention aim to solve the technical problem that in the CoSi2 process, when the line width is small, the Si content in SiGe is insufficient, so that the silicon cobalt alloy cannot be converted into a low-resistance phase at a low temperature, and provide a method for manufacturing a PMOS transistor.

[0007] Embodiments of the present invention are realized by a method for manufacturing a PMOS transistor. The method is applicable to the manufacture of a PMOS transistor with a source / drain structure having a line width of less than 40 nm. The method includes: providing a base, and forming source / drain trench isolation on the base; growing a SiGe material in the source / drain trench isolation to form a SiGe layer, growing a Si thin film layer on the surface of the SiGe layer, and forming a stacked structure of the SiGe layer and the Si thin film layer; growing a first Co thin film layer on the stacked structure, and then performing an annealing process to react Co in the first Co thin film layer with Si in the Si thin film layer to form a first CoSi2 thin film layer. Here, the overall structure formed in the source / drain trench isolation is the source / drain, and the first CoSi2 thin film layer is the upper structure of the source / drain.

[0008] Furthermore, the manufacturing method further includes: fabricating a first gate layer made of polycrystalline silicon on the base; A step of growing a second Co thin film layer on the first gate layer, and then annealing the Co in the second Co thin film layer and the Si in the first gate layer to react to form a second CoSi2 thin film layer, is included. Here, the overall structure of the formed first gate layer and the second CoSi2 thin film layer is the first gate, and the second CoSi2 thin film layer is the upper structure of the first gate.

[0009] Furthermore, the first Co thin film layer and the second Co thin film layer are grown simultaneously, and then annealed, and the first CoSi2 thin film layer and the second CoSi2 thin film layer formed by the reaction are respectively used as the upper structure of the source / drain and the upper structure of the first gate.

[0010] Furthermore, in the step of growing a Si thin film layer on the surface of the SiGe layer, the thickness of the Si thin film layer is such that in the formation of the first CoSi2 thin film layer by the subsequent reaction with the first Co thin film layer, all the Si contained in the Si thin film layer is consumed by Co, satisfying that there is no shortage of Si supply, and the shortage of Si supply refers to the remaining unreacted Co after the annealing process.

[0011] Furthermore, the thickness of the Si thin film layer is less than 20 nm.

[0012] The present invention further provides a PMOS transistor manufactured by using the method for manufacturing a PMOS transistor according to any one of the above.

[0013] The present invention further a base, at least one NMOS transistor formed on the base, and at least one PMOS transistor according to any one of the above formed on the base, and provides a CMOS circuit including the same.

[0014] Furthermore, the NMOS transistor An active region including a source / drain region for forming the source / drain of the NMOS transistor, A second gate dielectric layer formed on the active region, A second gate formed on the second gate dielectric layer, The source / drain region is located on both sides of the second gate, and the second gate includes a second gate layer, Here, the material of the second gate layer is polycrystalline silicon.

[0015] The present invention further provides a method for manufacturing a CMOS circuit for manufacturing the CMOS circuit according to any one of the above, and the method includes: Providing a base, and forming at least two active regions on the base - two adjacent active regions are isolated by a shallow trench isolation structure, Forming a source / drain trench isolation of the PMOS transistor in the active region corresponding to the PMOS transistor, Growing a SiGe material in the source / drain trench isolation to form a SiGe layer, growing a Si thin film layer on the surface of the SiGe layer, and forming a stacked structure of the SiGe layer and the Si thin film layer, Growing a first Co thin film layer on the stacked structure, and performing annealing treatment to react the first Co thin film layer with Si in the Si thin film layer to form a first CoSi2 thin film layer.

[0016] Furthermore, the NMOS transistor includes: An active region including a source / drain region for forming the source / drain of the NMOS transistor, A second gate dielectric layer formed on the active region, A second gate formed on the second gate dielectric layer, The source / drain region is located on both sides of the second gate, and the second gate includes a second gate layer, Here, the materials of the first gate layer and the second gate layer are both polycrystalline silicon.

[0017] Furthermore, the method includes: providing a base, and forming at least two active regions on the base, where two adjacent active regions are isolated by a shallow trench isolation structure; simultaneously forming a first gate layer of the PMOS transistor and a second gate layer of the NMOS transistor on each of the active regions; forming a source / drain trench isolation of the PMOS transistor in the active region corresponding to the PMOS transistor; growing a SiGe material in the source / drain trench isolation of the PMOS transistor to form a SiGe layer, growing a Si thin film layer on the surface of the SiGe layer, and forming a stacked structure of the SiGe layer and the Si thin film layer; simultaneously growing a first Co thin film layer, a second Co thin film layer, a third Co thin film layer, and a fourth Co thin film layer on the stacked structure, on the first gate layer, on the second gate layer, and on the source / drain region of the NMOS transistor, respectively; annealing the first Co thin film layer, the second Co thin film layer, the third Co thin film layer, and the fourth Co thin film layer to react with the corresponding Si to form a first CoSi2 thin film layer, a second CoSi2 thin film layer, a third CoSi2 thin film layer, and a fourth CoSi2 thin film layer.

[0018] In the method for manufacturing a PMOS transistor of the present invention, the SiGe layer is formed by epitaxial growth in the base. Since the lattice constant of SiGe is different from that of Si in the base, the stress in the channel region is increased, compressive stress is applied to the PMOS transistor, and its carrier mobility is improved. On the other hand, since the Ge material itself has a higher carrier mobility compared to the Si material, the drive current of the PMOS transistor can be increased, and the object of improving the electrical performance of the PMOS transistor can be achieved.

[0019] Furthermore, epitaxially growing Si on the SiGe layer to form a Si thin film layer aims to supply sufficient Si to promote the formation of low-resistance-phase CoSi2 in the subsequent CoSi2 process. In the subsequent CoSi2 process, it effectively avoids the problem that the silicon cobalt alloy cannot be converted into the low-resistance phase due to insufficient Si content in the SiGe layer, and also avoids the problem of CoSi2 aggregation caused by the need to increase the reaction temperature to convert the silicon cobalt alloy into the low-resistance phase, optimizing the process of the PMOS transistor and SiGe epitaxial growth.

Brief Description of the Drawings

[0020]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Embodiments for Carrying Out the Invention

[0021] Hereinafter, in order to make the object, technical solution and advantages of the present invention clearer and easier to understand, the present invention will be described in more detail in conjunction with the accompanying drawings and embodiments. Examples of the embodiments to be described are shown in the accompanying drawings, and the same or similar reference numerals from beginning to end indicate the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only for the purpose of explaining the present invention, and should not be construed as limiting the present invention. Furthermore, it should be understood that the specific embodiments described herein are for the sole purpose of explaining the present invention and are not intended to limit the present invention.

[0022] In the description of the present invention, the directions or positional relationships shown in the description of the directions or positional relationships are based on the directions or positional relationships shown in the drawings, and are merely for facilitating the description of the present invention and simplifying the description, and do not indicate or imply that the devices or elements mentioned must be configured and operated in a specific direction or a specific direction. It should be understood that it cannot be construed as a limitation of the present invention.

[0023] Furthermore, the terms "first" and "second" are used only for illustrative purposes and are not to be understood as indicating, implying, or implicitly designating the number of technical features showing relative importance. Therefore, the features defined by the terms "first" and "second" may include one or more of the described features, explicitly or implicitly. In the description of the present invention, "a plurality" means two or more unless explicitly and specifically limited.

[0024] The following disclosure provides a number of different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, these are merely examples and do not limit the present invention. In addition, the present invention may repeat reference numerals and / or reference characters in different embodiments, but such repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings being discussed. Furthermore, the present invention provides various specific examples of processes and materials, but those skilled in the art can implement the application of other processes and / or the use of other materials.

[0025] From the content of the above background art section, it can be seen that (1) when the NiSi process is adopted in the prior art solution, it cannot adapt to the high-temperature process in the subsequent process; (2) when the CoSi2 process of the conventional structure is used, the small linewidth effect existing in the CoSi2 process cannot be solved; (3) for the source / drain region of the PMOS transistor, in order to solve the problem of insufficient Si content in the SiGe epitaxial structure in the process of forming CoSi2 on the SiGe surface, it is necessary to design a new SiGe process solution.

[0026] Referring to FIGS. 1 and 2, taking the above-mentioned point (3) as an example, the structure of the conventional PMOS transistor 101 and the process scheme of the conventional PMOS transistor 101 will be described.

[0027] As shown in FIG. 1, in the conventional CoSi2 process, a Co thin film is directly deposited on the surface of the base 2 on both sides of the gate structure 1 and reacts with the Si in the base 2. However, since the Si content in the base 2 is high, SiGe is not deposited on the source / drain region of the PMOS transistor either, and since there is no small linewidth effect, the Co thin film can directly react sufficiently with the base 2 to form a low-resistance phase CoSi2 layer 3 to meet the usage requirements.

[0028] As shown in FIG. 2, when SiGe layers 4 are epitaxially formed on bases 2 on both sides of gate structure 1 in order to increase the compressive stress of PMOS transistor 101, in the process of reacting with the Co thin film deposited on the surface of SiGe layer 4 to form a silicon cobalt alloy, due to the limitation that the Si content in SiGe layer 4 is low and the linewidth effect is small, Si2Co layer or SiCo layer 5 can only be formed in a high-resistance phase, and as a result, the performance of PMOS transistor 101 is affected.

[0029] Different from the prior art, in the technical solution of the present invention, at the end of SiGe epitaxy, Si epitaxy is increased, and by controlling the thickness of Si epitaxy so that Si is completely consumed when reacting with the Co film to form low-resistance-phase CoSi2, not only is the supply of Si sufficiently ensured in the process of forming CoSi2, but also the low-resistance-phase CoSi2 does not increase the resistance at the source / drain position, guaranteeing the performance of the PMOS transistor.

[0030] That is, this solution ensures the stress supply to the PMOS by epitaxially growing SiGe on base 10, improving the carrier mobility, and at the same time, supplies sufficient Si for the subsequent CoSi process of forming low-resistance-phase CoSi2 by epitaxially growing Si on SiGe, effectively optimizing the PMOS transistor and the SiGe epitaxial process.

[0031] Referring to FIGS. 3 and 5 to 11, the manufacturing method of PMOS transistor 100 according to the embodiment of the present invention is applicable to the manufacturing of PMOS transistor 100 with a source / drain structure linewidth less than 40 nm.

[0032] Specifically, as shown in FIG. 3, the manufacturing method includes the following steps: Step S101: Provide base 10 and form source / drain trench isolation 11 on base 10; Step S102: Grow a SiGe material in the source / drain trench isolation 11 to form a SiGe layer 30, grow a Si thin film layer 40 on the surface of the SiGe layer 30, and form a stacked structure of the SiGe layer 30 and the Si thin film layer 40; and, Step S103: Grow a first Co thin film layer 50 on the stacked structure in the source / drain trench isolation 11, and then perform an annealing process so that Co in the first Co thin film layer 50 reacts with Si in the Si thin film layer 40 to form a first CoSi2 thin film layer 60; Here, the entire structure formed in the source / drain trench isolation 11 is the source / drain, and the first CoSi2 thin film layer 60 is the upper structure of the source / drain.

[0033] Specifically, in step S101, the material of the base 10 may be single-crystalline silicon (Si), single-crystalline germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or silicon on insulator (SOI), germanium on insulator (GOI), or other materials such as III-V group compounds such as gallium arsenide.

[0034] In this embodiment, the material of the base 10 is single-crystalline silicon (Si).

[0035] Please refer to FIGS. 5 to 7 together. Exemplarily, the step of forming the source / drain trench isolation 11 in step S101 may specifically include the following steps: Step S1011: Pattern the base 10; Step S1012: Form an opening 12 in the base 10 (this opening 12 may be a U-shaped recess of the source / drain as shown in FIG. 6); Step S1013: Etch the base 10 along the opening 12 to form the source / drain trench isolation 11.

[0036] In one embodiment, the process for forming the above-described opening 12 may be dry etching or wet etching.

[0037] In one embodiment, the shape of the source / drain trench isolation 11 may be square, U-shaped, or Σ (sigma) shaped.

[0038] More preferably, in a general process, the shape of the source / drain trench isolation 11 is Σ shaped.

[0039] Specifically, the Σ-shaped source / drain trench isolation 11 has sidewalls that are recessed inward toward the direction of the device channel, and this shape can effectively shorten the length of the device channel and meet the requirement of miniaturization of the device size.

[0040] Furthermore, the Σ-shaped source / drain trench isolation 11 has a large undercut below the gate gap body, and by forming a stress material in the source / drain trench isolation 11 of this shape, a larger stress can be generated in the device channel region.

[0041] In one embodiment, the process for forming the source / drain trench isolation 11 may be dry etching, wet etching, or a combination of dry etching and wet etching.

[0042] Exemplarily, the formation of the Σ-shaped source / drain trench isolation 11 will be described: Using a reactive ion etching (RIE) dry etching process, the base 10 can be etched along the opening 12 to form an inverted trapezoidal source / drain trench isolation, and then, using a wet etching process with tetramethylammonium hydroxide (TMAH) or aqueous ammonia (NH4OH), the source / drain trench isolation can be continuously etched to form a Σ-shaped source / drain trench isolation 11.

[0043] As shown in FIG. 7, due to the limitations of other structures (e.g., shallow trench isolation structure 15 and liner 16) within the base 10, the shape of the source / drain trench isolation 11 in embodiments of the present invention is not square, U-shaped, or sigma (Σ)-shaped, but is partially Σ-shaped such that the portion of the source / drain trench isolation 11 close to the gate is Σ-shaped and the other portions are irregularly shaped.

[0044] Combining FIGS. 7 and 8, in step S102, after etching the base 10 to form the source / drain trench isolation 11, the SiGe layer 30 is grown to fill the source / drain trench isolation 11.

[0045] The SiGe layer 30 may be a single-layer structure or a multi-layer structure, thereby increasing the stress acting on the channel region of the PMOS transistor 100, increasing the carrier mobility of the PMOS transistor 100, and optimizing the performance of the PMOS transistor 100.

[0046] In one embodiment, the SiGe layer 30 can be formed using a selective epitaxial process.

[0047] In one embodiment, after filling the Σ-shaped source / drain trench isolation 11 with SiGe, the SiGe layer 30 may be substantially hexagonal in shape.

[0048] As shown in FIG. 7, since the source / drain trench isolation 11 in this embodiment is not a complete Σ shape, the SiGe layer 30 formed epitaxially in the source / drain trench isolation 11 is not a regular hexagon either. However, as shown in FIG. 8, the SiGe layer 30 has a relatively distinct regular hexagonal contour at the top and one side surface, and still has the function of the regular hexagonal SiGe layer in the conventional process.

[0049] Since it is understood that Si and Co are formed before the first CoSi2 thin film layer 60 is formed, referring to FIG. 9, in this embodiment, first, as shown in FIGS. 10 and 11, a Si thin film layer 40 with a set thickness is formed on the surface of the SiGe layer 30 by step S102. Then, in step S103, a first Co thin film layer 50 is formed on the Si thin film layer 40, and the two are reacted by an annealing reaction to form a first CoSi layer 30.

[0050] Here, the set thickness of the Si thin film layer 40 is guaranteed to be completely consumable during the reaction process in order to ensure sufficient supply of Si during the formation of the first CoSi2 thin film layer and avoid extra Si increasing the resistance at the source and drain positions.

[0051] It can be understood that if the thickness of the Si thin film layer 40 is too small, in the subsequent reaction process with the first Co thin film layer 50, there will be insufficient Si to react with Co, which will affect the formation of the low-resistance phase CoSi2 and the performance of the PMOS transistor 100.

[0052] If the thickness of the Si thin film layer 40 is too large, although it does not affect the conversion to the low-resistance phase of the silicon cobalt alloy, there are the following effects: First, the reaction with Co takes too much time, and the deposition amount of the first Co thin film layer 50 is too large, which is disadvantageous to the formation efficiency of the PMOS transistor 100; Second, the first CoSi2 thin film layer 60 formed by the reaction becomes thick, which not only affects the size of the PMOS transistor 100, but also the loss of Si in the source-drain region is too large, the leakage of the device increases, and the performance of the PMOS transistor is affected.

[0053] Therefore, in step S102, in the process of growing the Si thin film layer 40 on the surface of the SiGe layer 30, it is a preferred embodiment that the thickness of the Si thin film layer 40 satisfies the following conditions: When the Si thin film layer 40 is subsequently reacted with the first Co thin film layer 50 to form the first CoSi2 thin film layer 60, all the Si contained in the Si thin film layer 40 is consumed by Co, and there is no shortage of Si supply. Here, the shortage of Si supply can be understood as the remaining Co that has not reacted after the annealing process, that is, Si reacts sufficiently with Co and neither of them remains.

[0054] Furthermore, in step S102, the thickness of the Si thin film layer 40 formed by deposition on the surface of the SiGe layer 30 is less than 20 nm.

[0055] More preferably, the thickness of the Si thin film layer 40 is about 12 nm.

[0056] In one embodiment, the Si thin film layer 40 can be formed using a selective epitaxial process.

[0057] In one embodiment, the first Co thin film layer 50 can be formed on the surface of the Si thin film layer 40 by physical vapor deposition.

[0058] In another embodiment, the first Co thin film layer 50 can also be formed on the surface of the Si thin film layer 40 by magnetron sputtering.

[0059] In this embodiment, the first Co thin film layer 50 is formed by physical vapor deposition. It will be understood that any suitable process may be employed to form the Si thin film layer 40 and the first Co thin film layer 50.

[0060] Referring to FIG. 10 in combination with FIG. 11, after depositing the first Co thin film layer 50 on the surface of the Si thin film layer 40, the Si thin film layer 40 is reacted with the first Co thin film layer 50 to form the first CoSi2 thin film layer 60.

[0061] Generally, the Si thin film layer 40 may be reacted with the first Co thin film layer 50 to form the first CoSi2 thin film layer 60 by a heat treatment process, such as laser annealing, etc., and the temperature of the heat treatment may be 500°C to 750°C.

[0062] In the embodiment of the present invention, the overall structure formed in the source / drain trench isolation 11 is the source / drain of the PMOS transistor 100, and the first CoSi2 thin film layer 60 is the upper structure of the source / drain. That is, the source / drain includes the SiGe layer 30 in the source / drain trench isolation 11 and the first CoSi2 thin film layer 60 thereon, and the distance between the source / drains is less than 40 nm.

[0063] In particular, the gate 20 may be first formed on the surface of the base 10, and then the source / drain trench isolation 11 may be formed on the base 10 on both sides of the gate 20, and then other subsequent processes may be performed.

[0064] In the manufacturing method of the PMOS transistor 100 according to the embodiment of the present invention, first, SiGe epitaxial growth is performed on the base 10 to form the SiGe layer 30. By making the lattice constant of SiGe different from the lattice constant of Si in the base 10, the stress acting on the channel region is increased, compressive stress is applied to the PMOS transistor 100, and the carrier mobility is improved.

[0065] On the one hand, since the carrier mobility of the Ge material itself is higher than that of the Si material, the drive current of the PMOS transistor 100 can be improved, and the object of improving the electrical performance of the PMOS transistor 100 can be achieved. By epitaxially growing the SiGe by a certain thickness and then epitaxially growing the Si thin film layer 40, sufficient Si can be supplied to form the first CoSi2 thin film layer 60 in the subsequent CoSi2 process. At the same time, the problem of CoSi2 aggregation caused by increasing the reaction temperature to convert the silicon cobalt alloy into a low-resistance phase can be avoided, and the PMOS transistor 100 and the SiGe epitaxial process can be optimized.

[0066] Referring to FIGS. 4, 10, and 11, the method for manufacturing a PMOS transistor according to an embodiment of the present invention further includes the following steps: Step S104: Fabricate a first gate layer 22 on the base 10, and the material of the first gate layer 22 is polycrystalline silicon; Step S105: Grow a second Co thin film layer 70 on the first gate layer 22, and then perform an annealing process so that Co in the second Co thin film layer 70 reacts with Si in the first gate layer 22 to form a second CoSi2 thin film layer 23; Here, the overall structure of the formed first gate layer 22 and the second CoSi2 thin film layer 23 is the first gate 20, and the second CoSi2 thin film layer 23 is the upper structure of the first gate 20.

[0067] Also, in the embodiment of the present invention, as shown in FIG. 11, after the first Co thin film layer 50 and the second Co thin film layer 70 are simultaneously grown, an annealing process is performed, and the first CoSi2 thin film layer 60 and the second CoSi2 thin film layer 23 formed by the reaction are respectively used as the upper structure of the source / drain of the PMOS transistor and the upper structure of the gate 20. Fabricating the first gate layer 22 on the base 10 is a technique mature in the art and will not be repeated herein.

[0068] Conventionally, first, a first gate dielectric layer 21 is formed on the surface of a base 10, and the first gate 20 can include a first gate layer 22 formed on the surface of the first gate dielectric layer 21 and a second CoSi2 thin film layer 23 formed on the surface of the first gate layer 22.

[0069] Specifically, the material of the first gate dielectric layer 21 may be SiO2 or a High-k dielectric material. Here, the High-k dielectric material may be one or a combination of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, and HfO2 - Al2O3.

[0070] In one embodiment, the process for forming the first gate dielectric layer 21 may be chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0071] It will be understood that any suitable materials and deposition processes may be used to form the first gate dielectric layer 21.

[0072] In this embodiment, the material of the first gate layer 22 is polycrystalline silicon.

[0073] In one embodiment, the process for forming the first gate layer 22 may be chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0074] It will be understood that any suitable materials and deposition processes may be used to form the first gate layer 22.

[0075] Furthermore, the line width of the first gate 20 in this embodiment is less than 40 nm, that is, the line width of the first gate layer 22 is less than 40 nm, controlling the size of the first gate 20 and thus the size of the entire PMOS transistor 100.

[0076] Furthermore, as is well known to those skilled in the art, when the line width of the first gate 20 is less than 40 nm, the resistance due to the line width effect is extremely high. By forming the first CoSi2 thin film layer 60 in a low-resistance phase, it is possible to control the resistance between the gate / source / drain while improving the performance of the device.

[0077] In the process of the conventional PMOS transistor 100, the surface of the first gate 20 is a mask layer, that is, the surface of the first gate layer 22 is a mask layer. However, in the embodiment of the present invention, in order to enhance the conductivity between the metal conductor and the polycrystalline silicon gate and promote ohmic contact, the mask layer on the first gate 20 is removed. Instead, a second CoSi2 thin film layer 23 is formed on the surface of the first gate layer 22, which is different from the conventional process.

[0078] Since the first gate layer 22 in this embodiment is made of polycrystalline silicon, it will be understood that when the second Co thin film layer 70 is deposited on the surface of the first gate layer 22, there is a sufficient amount of Si in the first gate layer 22 to react with the second Co thin film layer 70 to form the second CoSi2 thin film layer 23.

[0079] Furthermore, the deposition of the second Co thin film layer 70 on the surface of the first gate layer 22 is performed in the same step as the deposition of the first Co thin film layer 50 on the surface of the Si thin film layer 40, so the production efficiency of the PMOS transistor 100 is improved.

[0080] Referring to FIGS. 5 to 11, the PMOS transistor 100 according to the embodiment of the present invention is fabricated using the method for fabricating the PMOS transistor 100 according to any of the above embodiments.

[0081] In the PMOS transistor 100 according to the embodiment of the present invention, the beneficial effects, specific structural configurations, descriptions, etc. brought about by the method for fabricating the PMOS transistor 100 according to any of the above embodiments have been described above in relation to the method for fabricating the PMOS transistor 100, so they will not be repeated here.

[0082] Referring to FIGS. 12 to 22, the CMOS circuit 1000 of the embodiment of the present invention includes the following: At least one NMOS transistor 200 formed on the base 10; At least one PMOS transistor 100 formed on the base 10 according to any of the above embodiments.

[0083] In the CMOS circuit 1000 according to the embodiment of the present invention, the beneficial effects, specific structural configurations, descriptions, etc. of the PMOS transistor 100 according to the above embodiments have been described above with respect to the PMOS transistor 100, and thus will not be repeated here.

[0084] The CMOS circuit 1000 includes a PMOS transistor 100 and an NMOS transistor 200, which are also well-known to those skilled in the art, and their operating principles and related structural features will not be described in this specification.

[0085] Hereinafter, the content of the NMOS transistor 200 part of the CMOS circuit 1000 and the content of the part related to the fabrication of the NMOS transistor in the fabrication of the PMOS transistor 100 will be mainly described.

[0086] Here, the NMOS transistor 200 is a conventional planar transistor, and for the content related to the source / drain, reference may be made to the content related to the formation of the source / drain in the above PMOS transistor 100, and the difference lies in the difference in ion implantation.

[0087] Furthermore, referring to FIGS. 5 to 11, the first gate 20 in the present embodiment has first sidewalls 25 formed on both sides of the first gate 20, and the first sidewalls 25 are disposed on the surface of the base 10 and are attached to the surfaces on both sides of the first gate 20.

[0088] In this embodiment, the first sidewall 25 is used to protect the sidewall of the first gate 20 from damage and ensure the performance of the first gate 20 when etching or ion implantation is performed later.

[0089] The material of the first sidewall 25 may be silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, or the like.

[0090] In one embodiment, the first sidewall 25 may have a silicon oxide - silicon nitride laminated structure, or a silicon nitride - silicon oxide - silicon nitride laminated structure, or a silicon oxide - silicon nitride - silicon oxide laminated structure.

[0091] In one embodiment, the formation process of the first sidewall 25 may be chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0092] It will be understood that any suitable material and deposition process may be used to form the first sidewall 25.

[0093] Also, in order to prevent the hot electron degradation effect, a lightly doped drain (LDD) may be formed in the base 10 on both sides of the gate 20 before forming the first sidewall 25.

[0094] Referring to FIGS. 5 to 9 together, before growing the second Co thin film layer 70 on the surface of the first gate layer 22, a first gate mask layer 24 is formed on the surface of the first gate layer 22. Further, the preparation step S105 of the first gate 20 according to the embodiment of the present invention may specifically include the following steps: Step S1051: Remove the first gate mask layer 24 to expose the upper surface of the first gate layer 22; and, Step S1052: Grow the second Co thin film layer 70 on the surface of the first gate layer 22, and then perform annealing treatment so that Co in the second Co thin film layer 70 reacts with Si in the first gate layer 22 to form the second CoSi2 thin film layer 23.

[0095] In the conventional process, the material of the first gate mask layer 24 may be silicon nitride, which does not react with inorganic acids other than hydrofluoric acid, has high corrosion resistance, and silicon nitride does not penetrate or corrode many molten metals or alloys such as aluminum, copper, or nickel. Therefore, the first gate layer 22 can be effectively protected from being damaged in the process.

[0096] In one embodiment, the process for forming the first gate mask layer 24 may be chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0097] In another embodiment, the process for forming the first gate mask layer 24 may be low-pressure atomic layer deposition.

[0098] It will be understood that any suitable materials and deposition processes may be used to form the first gate mask layer 24.

[0099] Embodiments of the present invention differ from the conventional process in that the first gate mask layer 24 on the first gate 20 is removed, and instead, a second CoSi2 thin film layer 23 is formed on the surface of the first gate layer 22 to increase the electrical conductivity between the metal conductor and the polycrystalline silicon gate and to promote ohmic contact.

[0100] Referring to FIGS. 12 to 22, further, in the present embodiment, a second gate 210 is formed on the surface of the active region of the base 10 corresponding to the NMOS transistor 200, and a second gate dielectric layer 211 separating the second gate 210 and the active region is formed on the surface of the base 10. Specifically, the second gate 210 includes a second gate layer 212 disposed on the surface of the second gate dielectric layer 211 and a third CoSi2 thin film layer 213 formed on the surface of the second gate layer 212. Further, a fourth CoSi2 thin film layer 216 is formed on the surface of the base 10 corresponding to the NMOS transistor 200.

[0101] Specifically, the specific configuration of the second gate 210 is the same as that of the first gate 20, and the materials and process steps used are also basically the same. Regarding the second gate 210, reference can be made to the content regarding the first gate 20 in the above PMOS transistor 100.

[0102] Second sidewalls 215 are formed on two sidewalls of the second gate 210. Regarding the content of the second sidewalls 215, reference can be made to the content regarding the first sidewalls 24 above, and detailed description is omitted here.

[0103] In this embodiment, the second gate mask layer 214 is also removed in the same way. Instead, after growing a third Co thin film layer 80 on the surface of the second gate layer 212 and reacting, a third CoSi2 thin film layer 213 is formed. After growing a fourth Co thin film layer 90 on the surface of the base 10 corresponding to the NMOS transistor 200, a fourth CoSi2 thin film layer 216 is formed. Therefore, the third CoSi2 thin film layer 213 and the fourth CoSi2 thin film layer 216 enhance the conductivity between the metal conductor and the polycrystalline silicon gate, promote ohmic contact, and further improve the device performance.

[0104] Here, the removal of the second gate mask layer 214 can be achieved in the same steps as the removal of the first gate mask layer 24, that is, the first gate mask layer 24 and the second gate mask layer 214 can be removed simultaneously.

[0105] How to remove the gate mask layer is a mature technology in this field and will not be elaborated here.

[0106] The formation of the third CoSi2 thin film layer 213 and the fourth CoSi2 thin film layer 216 can also be achieved in the same steps as the formation of the first CoSi2 thin film layer 60 and the formation of the second CoSi2 thin film layer 23.

[0107] That is, after removing the first gate mask layer 24 and the second gate mask layer 214, a Co thin film layer is deposited on the entire CMOS circuit 1000, and Co thin films are respectively deposited and reacted on the surfaces of the Si thin film layer 40, the first gate layer 22, the second gate layer 212, and the source / drain regions of the NMOS transistor 200, so as to form the first CoSi2 thin film layer 60, the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213, and the fourth CoSi2 thin film layer 216 at the same time or within the same time period, further improving the production efficiency of the CMOS circuit 1000.

[0108] The second gate layer 212 in this embodiment is made of polycrystalline silicon, similar to the first gate layer 22, and the base 10 is also a silicon base 10. Therefore, when a Co thin film layer is deposited on the surface of the second gate layer 212 and the surfaces of the source / drain regions of the NMOS transistor 200, there is a sufficient amount of Si in the second gate layer 212 and the source / drain regions of the NMOS transistor 200 to react with the Co thin film layer. Thus, it is understood that the third CoSi2 thin film layer 213 and the fourth CoSi2 thin film layer 216 are formed.

[0109] Furthermore, in one embodiment, in order to further improve the electrical performance of the CMOS circuit 1000, SiGe layers 30 can also be formed on the bases 10 on both sides of the second gate 210 of the NMOS transistor 200.

[0110] Specific details for forming the SiGe layers 30 on the bases 10 on both sides of the first gate 20 can be referred to the above, and will not be elaborated here.

[0111] In the CMOS circuit 1000, for the PMOS transistor 100 portion, a first gate dielectric layer 21 is formed on the surface of the base 10, and the first gate 20 includes a first gate layer 22 disposed on the surface of the first gate dielectric layer 21 and a second CoSi2 thin film layer 23 disposed on the surface of the first gate layer 22.

[0112] Referring to FIGS. 12 to 22, for the portion of the NMOS transistor 200, a second gate dielectric layer 211 is formed on the surface of the base 10, and the second gate 210 includes a second gate layer 212 disposed on the surface of the second gate dielectric layer 211 and a third CoSi2 thin film layer 213 disposed on the surface of the second gate layer 212.

[0113] In the conventional process, before growing the third Co thin film layer 80 on the surface of the second gate layer 212, a second gate mask layer 214 is formed on the surface of the second gate layer 212, and a first mask layer 13 is formed on the surfaces of the base 10 on both sides of the second gate 210.

[0114] Referring to FIGS. 17 to 22, based on the above basic structure, after the step S102 of growing the Si thin film layer 40 on the SiGe layer 30 in the manufacturing process of the PMOS transistor 100, the following steps may be included: Step S106: Forming a photoresist layer 14 on the surfaces of the first gate mask layer 24 and the Si thin film layer 40; Step S107: Removing the first mask layer 13 to expose the source / drain regions of the NMOS transistor 200; Step S108: Removing the photoresist layer 14 to expose the surfaces of the first gate mask layer 24 and the Si thin film layer 40; Step S109: Removing the first gate mask layer 24 and the second gate mask layer 214 to expose the surfaces of the first gate layer 22 and the second gate layer 212; and, Step S110: Depositing a second Co thin film layer 70, a third Co thin film layer 80, and a fourth Co thin film layer 90 on the surfaces of the first gate layer 22, the second gate layer 212, and the source / drain regions of the NMOS transistor 200, respectively, and then annealing to react and form a second CoSi2 thin film layer 23, a third CoSi2 thin film layer 213, and a fourth CoSi2 thin film layer 216, respectively.

[0115] In step S201, first, when removing the first mask layer 13 from the surface of the base 10, the first gate mask layer 24 and the Si thin film layer 40 are covered with photoresist so as not to damage the Si thin film layer 40. Here, the first mask layer 13 can be formed during the process of forming the first gate 20 on the base 10, and its material and composition can refer to the content regarding the material and composition of the first gate mask layer 24, which will not be described in detail here.

[0116] In one embodiment, the process of removing the photoresist layer 14 may be a wet cleaning or ashing process.

[0117] When the photoresist layer 14 is removed by an ashing process, after the ashing process is completed, residual photoresist and by-products of the ashing process exist on the surface of the base 10, and wet cleaning of the surface of the base 10 is also required.

[0118] Therefore, in this embodiment, an example is given of removing the photoresist layer 14 on the first gate mask layer 24 and the Si thin film layer 40 by using wet cleaning.

[0119] Specifically, the wet chemical substance that can be used for wet cleaning is an aqueous solution of ammonia water and hydrogen peroxide water. The CMOS circuit 1000 having the photoresist layer 14 on its surface is placed in a reaction chamber, and the photoresist layer 14 is removed by spraying the aqueous solution of ammonia water and hydrogen peroxide water on the surface of the photoresist layer 14.

[0120] In this embodiment, the first gate mask layer 24 and the second gate mask layer 214 on the second gate 210 are removed simultaneously. Instead, a second CoSi2 thin film layer 23 is formed on the surface of the first gate layer 22, a third CoSi2 thin film layer 213 is formed on the surface of the second gate layer 212, and a fourth CoSi2 thin film layer 216 is formed in the source-drain region of the NMOS transistor 200. By doing so, the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213, and the fourth CoSi2 thin film layer 216 enhance the conductivity between the metal conductor and the polycrystalline silicon gate, promote ohmic contact, and thereby improve the device performance.

[0121] In this embodiment, the formation of the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213, and the fourth CoSi2 thin film layer 216 can be achieved in the same steps as the formation of the first CoSi2 thin film layer 60, as shown in FIG. 21. That is, after removing the first gate mask layer 24 and the second gate mask layer 214, a Co thin film layer is deposited on the entire surface of the CMOS circuit 1000, and Co thin film layers are respectively deposited and reacted on the surfaces of the Si thin film layer 40, the first gate layer 22, the second gate layer 212, and the base 10 of the source-drain region of the NMOS transistor 200, so as to form the first CoSi2 thin film layer 60, the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213, and the fourth CoSi2 thin film layer 216 at the same time or within the same time period, further improving the production efficiency of the CMOS circuit 1000.

[0122] Since the Si thin film layer 40 in this embodiment is formed by Si epitaxial growth, the first gate layer 22 and the second gate layer 212 are made of polycrystalline silicon, and the base 10 is a silicon base, when Co thin film layers are simultaneously deposited on the surfaces of the Si thin film layer 40, the first gate layer 22, the second gate layer 212, and the base 10, there is sufficient Si in the Si thin film layer 40, the first gate layer 22, the second gate layer 212, and the base 10 to react with the Co thin film layer to form the first CoSi2 thin film layer 60, the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213, and the fourth CoSi2 thin film layer 216.

[0123] Referring to FIG. 23 in combination with FIGS. 12 to 22, a manufacturing method of a CMOS circuit 1000 according to an embodiment of the present invention for manufacturing the CMOS circuit 1000 according to any of the above embodiments will be described. This manufacturing method may include the following steps: Step S201: Provide a base 10, form at least two active regions on the base 10, and two adjacent active regions are isolated by a shallow trench isolation structure 15; Step S202: In the active region corresponding to the PMOS transistor 100, form a source / drain trench isolation 11 of the PMOS transistor 100; Step S203: Grow a SiGe material in the source / drain trench isolation 11 to form a SiGe layer 30, and grow a Si thin film layer 40 on the surface of the SiGe layer 30 to form a stacked structure of the SiGe layer 30 and the Si thin film layer 40; and Step S204: Grow a first Co thin film layer 50 on the surface of the stacked structure, and perform an annealing process so that the first Co thin film layer 50 reacts with the Si of the Si thin film layer 40 to form a first CoSi2 thin film layer 60.

[0124] For the specific content of each step of the manufacturing method of the CMOS circuit 1000 according to the embodiment of the present invention and the specific structure related thereto, reference can be made to the content related to the manufacturing of the PMOS transistor 100 and the structural configuration of the CMOS circuit 1000, etc., which will not be repeated here. Hereinafter, the new technical features described in the above manufacturing method will be appropriately explained.

[0125] Continuing to refer to FIGS. 12 to 22, in an embodiment of the present invention, a plurality of Shallow Trench Isolation (STI) isolation structures 15 are formed at intervals on the base 10. The base 10 is divided into a plurality of active regions by the shallow trench isolation. The first gate 20 of the PMOS transistor 100 and the second gate 210 of the NMOS transistor 200 are respectively disposed between two adjacent shallow trench isolation structures 15, that is, the first gate 20 and the second gate 210 are respectively disposed on the corresponding active regions.

[0126] Specifically, the shallow trench isolation structure 15 can be formed by first etching a shallow trench isolation at a set position on the base 10 and then filling the shallow trench isolation with an insulating material.

[0127] Here, the insulating material may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon dioxide.

[0128] In this embodiment, the material filled in the shallow trench isolation structure 15 is silicon dioxide.

[0129] Different from the conventional process, the shallow trench isolation structure 15 of this embodiment of the present invention also has a liner 16 formed between the base 10, and the SiGe layer 30 is in contact with the side surface of the liner 16. The liner 16 is mainly used to isolate the shallow trench isolation structure 15 from the SiGe layer 30 and prevent the SiGe layer 30 from extending into the base 10 of the adjacent transistor when the SiGe layer 30 is epitaxially formed in the source / drain trench isolation 11.

[0130] Exemplarily, after the formation of the shallow trench isolation, the liner 16 can be formed by depositing an insulating isolation material such as one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon dioxide on the base 10, whereby the insulating isolation material adheres to the shallow trench isolation to form a layer with a set thickness, and then the remaining space of the shallow trench isolation is continuously filled with an insulating material to form the shallow trench isolation structure 15, whereby the liner 16 is disposed between the base 10 and the shallow trench isolation structure 15.

[0131] In one embodiment, the liner 16 may be a thermal oxide layer that can be formed by a furnace tube thermal oxidation process.

[0132] Furthermore, since the SiGe layer 30 is in contact with the liner 16 in the base 10, the portion of the SiGe layer 30 disposed on the surface of the base 10 extends to cover a part of the surface of the shallow trench isolation structure 15, thereby increasing the volume and surface area of the SiGe layer 30 for the purpose of increasing the contact area, and thereby increasing the volume and surface area of the first CoSi2 thin film layer 60 formed on the surface of the SiGe layer 30.

[0133] Based on the fact that the above-described CMOS circuit 1000 can be fabricated, furthermore, the NMOS transistor 200 specifically includes an active region including a source / drain region for forming the source / drain of the NMOS transistor 200; a second gate dielectric layer 211 formed on the active region; a second gate 210 formed on the second gate dielectric layer 211, and may include the source / drain region is disposed on both sides of the second gate 210, the second gate 210 includes a second gate layer 212, and the material of the second gate layer 212 is the same as the material of the first gate layer 22, and both are polycrystalline silicon.

[0134] Based on the structure of the NMOS transistor 200 described above, referring to FIGS. 24 in combination with FIGS. 12 to 22, another embodiment of the method for fabricating the CMOS circuit 1000 of the present invention may include the following steps: Step S301: Provide a base 10, form at least two active regions on the base 10, and isolate two adjacent active regions by a shallow trench isolation structure 15; Step S302: Simultaneously form a first gate layer 22 of the PMOS transistor 100 and a second gate layer 212 of the NMOS transistor 200 on each active region; Step S303: Form a source / drain trench isolation 11 of the PMOS transistor 100 in the corresponding active region of the PMOS transistor 100; Step S304: Grow a SiGe material in the source / drain trench isolation 11 to form a SiGe layer 30, grow a Si thin film layer 40 on the surface of the SiGe layer 30, and form a laminated structure of the SiGe layer 30 and the Si thin film layer 40; Step S305: Simultaneously grow a first Co thin film layer 50, a second Co thin film layer 70, a third Co thin film layer 80, and a fourth Co thin film layer 90 on the laminated structure, on the first gate layer 22, on the second gate layer 212, and on the source / drain region of the NMOS transistor 200; and, Step S306: Anneal the first Co thin film layer 50, the second Co thin film layer 70, the third Co thin film layer 80, and the fourth Co thin film layer 90 to react with the corresponding Si to form a first CoSi2 thin film layer 60, a second CoSi2 thin film layer 23, a third CoSi2 thin film layer 213, and a fourth CoSi2 thin film layer 216.

[0135] For the specific content of each step of the method for fabricating the CMOS circuit 1000 of this embodiment and the specific structures related thereto, please refer to the content related to the fabrication of the PMOS transistor 100 and the structural configuration of the CMOS circuit 1000, etc., so it will not be repeated here.

[0136] Furthermore, in order to realize the electrical connection between the CMOS circuit 1000 and the peripheral circuits or devices, etc., it is also necessary to perform the contact process of the CMOS circuit 1000 and connect it to the signal lines provided to the peripheral circuits. Specifically, the contact process may include the following steps: Step S401: Deposit a first insulating layer on the surface of the CMOS circuit 1000 shown in FIG. 22. The material of the first insulating layer may be silicon nitride, and the deposition process may refer to the process of depositing each of the above layers; Step S402: Deposit a HARP (High Aspect Ratio Process) thin film on the surface of the insulating layer. The material of the HARP thin film may be silicon dioxide; Step S403: Deposit an oxide layer on the surface of the HARP thin film. This deposition step can be achieved by an HDP (High-Density Plasma)-CVD process, and the material of the oxide layer may be silicon dioxide; Step S404: Deposit a second insulating layer on the surface of the oxide layer. The material of the second insulating layer may be silicon nitride; Step S405: Form a photoresist layer on the surface of the second insulating layer, and form a plurality of openings in the photoresist layer. The plurality of openings correspond to the positions of the plurality of contact holes that need to be formed in the CMOS circuit 1000. The plurality of contact holes respectively correspond to the gates, sources, and drains of the PMOS transistor 100 and the NMOS transistor 200; Step S406: Etch the CMOS circuit 1000 through the plurality of openings to form a plurality of contact holes that penetrate the second insulating layer, the oxide layer, the HARP thin film, and the first insulating layer from top to bottom, and contact the first CoSi2 thin film layer 60, the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213, and the fourth CoSi2 thin film layer 216; Step S407: Remove the photoresist layer to expose the second insulating layer with the plurality of contact holes formed; Step S408: Deposit a metal layer on the surface of the second insulating layer, such that the metal of the metal layer is deposited along the plurality of contact holes, and comes into contact with the first CoSi2 thin film layer 60, the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213, and the fourth CoSi2 thin film layer 216 respectively. The metal that realizes the contact is understood as a metal signal line, and the material of the metal layer is titanium nitride; Step S409: Remove the metal layer on the surface of the second insulating layer, and retain the plurality of metal signal lines in the plurality of contact holes that are in contact with the first CoSi2 thin film layer 60, the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213, and the fourth CoSi2 thin film layer 216 respectively, thereby realizing the contact of the CMOS circuit 1000.

[0137] In the description of this specification, the reference to terms such as "Embodiment 1" and "Embodiment 2" means that the specific features, structures, materials, or characteristics described in relation to the embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any one or more of the embodiments or examples in an appropriate manner.

[0138] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention shall all be included within the protection scope of the present invention.

Claims

1. A method for fabricating a PMOS transistor, the method being adapted for fabricating a PMOS transistor having a line width of a source / drain structure less than 40 nm, The method comprises: providing a base and forming a source / drain trench isolation on the base; growing a SiGe material in the source / drain trench isolation to form a SiGe layer, and growing a Si thin film layer on a surface of the SiGe layer to form a stacked structure of the SiGe layer and the Si thin film layer; A first Co thin film layer is grown on the laminated structure, and then Co in the first Co thin film layer and Ｓｉ The first CoSi is reacted with the Si in the thin film layer. ２ and annealing to form a thin film layer; The entire structure formed in the source / drain trench isolation is a source / drain, and the first CoSi ２ The thin film layer is the upper structure of the source / drain.

13. A method for fabricating a PMOS transistor comprising the steps of:

2. The method comprises: forming a first gate layer on the base, the first gate layer being made of polycrystalline silicon; A second Co thin film layer is grown on the first gate layer, and then Co in the second Co thin film layer is reacted with Si in the gate layer to form a second CoSi ２ and annealing to form a thin film layer. The first gate layer and the second CoSi ２ The entire structure of the thin film layer is a first gate, and the second CoSi ２ The thin film layer is a superstructure of the first gate.

2. The method of claim 1, wherein the PMOS transistor is formed by a first insulating layer.

3. The first CoSi thin film layer is formed by simultaneously growing the first Co thin film layer and the second Co thin film layer and then annealing the first CoSi thin film layer. ２ The thin film layer and the second CoSi ２ The thin film layers are respectively the upper structure of the source / drain and the upper structure of the first gate.

3. The method for fabricating a PMOS transistor according to claim 2.

4. In the step of growing a Si thin film layer on the surface of the SiGe layer, the thickness of the Si thin film layer is Then, the first CoSi is formed by reaction with the first Co thin film layer. ２ During the formation of the thin film layer, all of the Si contained in the thin film layer is consumed by Co, and there is no shortage of Si. The shortage of Si refers to the remaining unreacted Co after the annealing process.

2. The method of claim 1, wherein the PMOS transistor is formed by a first insulating layer.

5. The thickness of the Si thin film layer is less than 20 nm.

5. The method for producing a PMOS transistor according to claim 4.

6. A PMOS transistor produced using the method according to any one of claims 1 to 5.

7. 1. A CMOS circuit comprising: With the base, at least one NMOS transistor formed on the base; and at least one PMOS transistor according to claim 6 formed on the base.

1. A CMOS circuit comprising:

8. The NMOS transistor is an active region including source / drain regions for forming the source / drain of the NMOS transistor; a second gate dielectric layer formed over the active region; a second gate formed on the second gate dielectric layer; the source / drain regions are located on either side of the second gate, the second gate including a second gate layer; The material of the second gate layer is polycrystalline silicon.

8. The CMOS circuit of claim 7.

9. 8. A method for fabricating a CMOS circuit as claimed in claim 7, said method comprising the steps of: providing a base and forming at least two active regions in the base, wherein two adjacent active regions are isolated by a shallow trench isolation structure; forming a source / drain trench isolation for the PMOS transistor in the active area corresponding to the PMOS transistor; growing a SiGe material in a source / drain trench isolation of the PMOS transistor to form a SiGe layer, and growing a Si thin film layer on a surface of the SiGe layer to form a stacked structure of the SiGe layer and the Si thin film layer; A first Co thin film layer is grown on the surface of the laminated structure, and the first Co thin film layer is reacted with Si in the Si thin film layer to form a first CoSi ２ and annealing to form a thin film layer.

1. A method for fabricating a CMOS circuit comprising:

10. The NMOS transistor is an active region including source / drain regions for forming the source / drain of the NMOS transistor; a second gate dielectric layer formed over the active region; a second gate formed on the second gate dielectric layer; the source / drain regions are located on either side of the second gate, the second gate including a second gate layer; The first gate layer and the second gate layer are both made of polycrystalline silicon.

10. A method for fabricating a CMOS circuit according to claim 9.

11. The method comprises: providing a base and forming at least two active regions in the base, wherein two adjacent active regions are isolated by a shallow trench isolation structure; simultaneously forming a first gate layer of the PMOS transistor and a second gate layer of the NMOS transistor on each of the active regions; forming a source / drain trench isolation for the PMOS transistor in the active area corresponding to the PMOS transistor; growing a SiGe material in a source / drain trench isolation of the PMOS transistor to form a SiGe layer, and growing a Si thin film layer on a surface of the SiGe layer to form a stacked structure of the SiGe layer and the Si thin film layer; simultaneously growing a first Co thin film layer, a second Co thin film layer, a third Co thin film layer and a fourth Co thin film layer on the stacked structure, the first gate layer, the second gate layer and the source / drain region of the NMOS transistor, respectively; The first Co thin film layer, the second Co thin film layer, the third Co thin film layer and the fourth Co thin film layer are reacted with corresponding Si to form a first CoSi ２ Thin film layer, second CoSi ２ Thin film layer, third CoSi ２ The thin film layer and the fourth CoSi ２ and annealing to form a thin film layer.

11. A method for fabricating a CMOS circuit according to claim 10.

Images