Printed circuit board and manufacturing method thereof

Abstract

To provide a printed circuit board and a manufacturing method thereof, which can form a fine circuit pattern in a required area without side effects such as undercut and can improve adhesion between insulating layers.SOLUTION: The present disclosure relates to a printed circuit board and a manufacturing method thereof, and includes a first insulating layer, and a plurality of first metal patterns disposed on the first insulating layer, the first insulating layer includes at least one recessed portion, the recessed portion is disposed between the plurality of first metal patterns, each of the plurality of first metal patterns includes a first seed metal layer disposed on the first insulating layer, a second seed metal layer disposed on the first seed metal layer, and a patterned metal layer disposed on the second seed metal layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board and a method for manufacturing the same.

Background Art

[0002] Currently, one of the development directions of the semiconductor industry is to closely arrange a plurality of chips in a single package to increase the driving speed. In this regard, in order to overcome the limitations of the fine wiring of packages manufactured using an organic material as a substrate, a technique has been developed in which an interposer manufactured using an inorganic material as a substrate is used as a rewiring layer for connecting between chips. However, in the case of such an interposer manufactured using an inorganic material as a substrate, since other parts also have to be formed in addition to the parts necessary for the interconnection, the process becomes somewhat complicated, and there is a possibility that the cost may increase due to unnecessary area expansion or the like.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objects of the present disclosure is to provide a printed circuit board and a method for manufacturing the same, which can form a fine circuit pattern in a necessary area without side effects such as undercut.

[0004] Another one of the various objects of the present disclosure is to provide a printed circuit board and a method for manufacturing the same, which can improve the adhesion between insulating layers.

Means for Solving the Problems

[0005] One of the various solutions proposed through the present disclosure is to form first and second seed metal layers on an insulating layer, form a patterned metal layer based thereon, and then remove the remaining second seed metal layer between the patterns by wet etching and remove the first seed metal layer by dry etching to form a fine circuit pattern. On the other hand, such dry etching can form a recess in the region between the patterns of the insulating layer, and a surface roughness can be formed on the bottom surface of the recess as required.

[0006] For example, a printed circuit board according to an example includes a first insulating layer and a plurality of first metal patterns disposed on the first insulating layer. The first insulating layer has at least one recess, and the recess is disposed between the plurality of first metal patterns. Each of the plurality of first metal patterns can include a first seed metal layer disposed on the first insulating layer, a second seed metal layer disposed on the first seed metal layer, and a patterned metal layer disposed on the second seed metal layer.

[0007] For example, a method for manufacturing a printed circuit board according to an example includes forming a first seed metal layer on an insulating layer, forming a second seed metal layer on the first seed metal layer, forming a patterned metal layer on the second seed metal layer, removing at least a part of the second seed metal layer exposed from the patterned metal layer, and removing at least a part of the first seed metal layer exposed from the patterned metal layer and the second seed metal layer. In the step of removing at least a part of the first seed metal layer, at least a part of the insulating layer can be removed to form at least one recess.

Advantages of the Invention

[0008] As one of the various effects of the present disclosure, it is possible to provide a printed circuit board and a method for manufacturing the same that can form a fine circuit pattern in a required region without side effects such as undercut.

[0009] Among the various effects of the present disclosure, another effect is to provide a printed circuit board capable of improving the adhesion between insulating layers and a method for manufacturing the same.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4a

Figure 4b

Figure 4c

Figure 4d

Figure 4e

Figure 4f

Figure 4g

Figure 4h

Figure 5a

Figure 5b

Figure 6a

Figure 6b

Figure 7a

Figure 7b

Figure 8a

Figure 8b

Figure 9

Figure 10

Mode for Carrying Out the Invention

[0011] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape, size, etc. of the elements in the drawings may be enlarged, reduced (or emphasized or simplified) for clearer explanation.

[0012] Electronic device FIG. 1 is a block diagram that schematically shows an example of an electronic device system.

[0013] Referring to the drawings, the electronic device 1000 houses a main board 1010. On the main board 1010, chip - related components 1020, network - related components 1030, and other components 1040 are physically and / or electrically connected. These, in combination with other electronic components described later, form various signal lines 1090.

[0014] Examples of chip-related components 1020 include memory chips such as volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), and flash memories, application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers, and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). However, the invention is not limited thereto, and other forms of chip-related electronic components may also be included. Furthermore, these chip-related components 1020 can be combined with each other. The chip-related components 1020 can also be in a package form including the above-described chips or electronic components.

[0015] Examples of network-related components 1030 include Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated as such and later. However, the invention is not limited thereto, and any of a number of other wireless or wired standards or protocols may also be included. Also, the network-related components 1030 can be combined with the chip-related components 1020 with each other.

[0016] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (Low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, MLCC (Multi-Layer Ceramic Condensers), etc. However, it is not limited to these, and passive elements in the form of chip components used for various other purposes may also be included. Further, other components 1040 can be combined with chip-related components 1020 and / or network-related components 1030 with each other.

[0017] Depending on the type of the electronic device 1000, the electronic device 1000 can include other electronic components that are physically and / or electrically connected or not connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, it is not limited to these, and audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. can also be mentioned. In addition, other electronic components used for various purposes depending on the type of the electronic device 1000 can also be included.

[0018] The electronic device 1000 can be, for example, a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive, etc. However, it is not limited to these, and it can also be any other electronic device that processes data.

[0019] FIG. 2 is a perspective view schematically showing an example of an electronic device.

[0020] Referring to the drawings, the electronic device can be, for example, a smart phone 1100. Inside the smart phone 1100, a motherboard 1110 is housed, and various components 1120 are physically and / or electrically connected to such a motherboard 1110. Further, other components that are physically and / or electrically connected or not connected to the motherboard 1110, such as a camera module 1130 and / or a speaker 1140, are housed inside. Some of the components 1120 can be the chip-related components described above, for example, a component package 1121, but it is not limited thereto. The component package 1121 can be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Or, the component package 1121 can also be in the form of a printed circuit board with built-in active components and / or passive components. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and it can also be other electronic devices as described above.

[0021] Printed circuit board FIG. 3 is a cross-sectional view schematically showing an example of a printed circuit board.

[0022] Referring to the drawings, a printed circuit board 500A according to an example can include an insulating layer 110 and a plurality of metal patterns 120 disposed on the upper surface of the insulating layer 110. The insulating layer 110 can have at least one recessed portion R. The recessed portion R can be disposed between the plurality of metal patterns 120. Each of the plurality of metal patterns 120 can include a first seed metal layer 121 disposed on the insulating layer 110, a second seed metal layer 122 disposed on the first seed metal layer 121, and a pattern metal layer 123 disposed on the second seed metal layer 122. On the upper surface of the insulating layer 110, the pattern metal layer 123 can be thicker than each of the first seed metal layer 121 and the second seed metal layer 122.

[0023] On the other hand, the process for forming a multilayer fine circuit pattern during the manufacturing process of the fine circuit board can have the following procedure. First, titanium (Ti) and copper (Cu) can be sequentially deposited on the insulating layer with a seed metal layer. Next, copper (Cu) plating can be performed using a photoresist. Next, the photoresist can be removed, and then, the seed metal layer at unnecessary positions can be sequentially removed. By repeating such a process, a multilayer fine circuit pattern can be formed. At this time, wet etching can be used by a method of etching a titanium (Ti) layer which is one of the seed metal layers, but not only vertical etching due to the isotropic characteristics of wet etching, but also lateral etching commonly called undercut occurs simultaneously, and the width of the titanium (Ti) layer in the wiring can be narrowed. In terms of design, when the width of the wiring is wide, such undercut may not be a big problem in some cases, but in the case of a fine circuit pattern, since the line width of the wiring is very narrow, when undercut occurs, it may be narrowed to less than 1 / 2 of the width of the wiring, so the titanium (Ti) layer may disappear or remain very small, resulting in peeling.

[0024] On the other hand, as in the process described later, the first seed metal layer 121 can be removed by dry etching after the wet etching of the second seed metal layer 122 in the printed circuit board 500A according to one example. In the case of dry etching, anisotropic characteristics can be obtained as compared with wet etching, and thus the occurrence of undercut in the first seed metal layer 121 can be prevented. For example, even when the plurality of metal patterns 120 include a plurality of fine circuit patterns with L (Line) / S (Space) of 5 μm / 5 μm or less, or 2 μm / 2 μm or less, the above-described problems do not occur. As a result, peeling failure of the fine wiring can be prevented in advance, and quality defects such as short circuits, open circuits, and signal noise caused by wiring peeling can be improved. In addition, a fine circuit board with minimized area can be provided, and thus a large-area interposer can be replaced. Therefore, cost reduction is also possible.

[0025] On the other hand, when such dry etching is performed, a recess portion R can be formed in the insulating layer 110 in the region where the first seed metal layer 121 is removed. For example, the recess portion R can penetrate a part of the first insulating layer 110 in the thickness direction from the upper surface of the insulating layer 110 between the plurality of metal patterns 120. Therefore, the upper surface of the insulating layer 110 in the region where the plurality of metal patterns 120 are arranged and the upper surface of the insulating layer 110 in the region where the recess portion R is arranged can have a step with each other. If necessary, roughness can be formed on the upper surface of the insulating layer 110 in the region where the recess portion R is arranged by such dry etching. For example, the upper surface of the insulating layer 110 in the region where the recess portion R is arranged can have a larger surface roughness than the upper surface of the insulating layer 110 in the region where the plurality of metal patterns 120 are arranged. In this case, when the printed circuit board 500A is applied to a multilayer substrate and an insulating layer is further formed on the insulating layer 110, the contact area between the insulating layers can be increased to improve the adhesion.

[0026] Hereinafter, with reference to the drawings, the components of the printed circuit board 500A according to one example will be described in more detail.

[0027] The insulating layer 110 can include an insulating material. The insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or an organic material including an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with the resin. For example, the insulating material can be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film), PPG (Prepreg), or a photosensitive insulating material such as PID (Photo Imagable Dielectric), but is not limited thereto. If necessary, the insulating material can also include an inorganic material including SiO2, Si3N4, etc.

[0028] The metal pattern 120 can include a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. The metal pattern 120 can perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc. Preferably, it can include a signal pattern, but is not limited thereto. These patterns can each have various forms such as a line, a plane, a pad, etc.

[0029] The first seed metal layer 121 can enhance the adhesion between the insulating layer 110 and the metal pattern 120. The first seed metal layer 121 can contain titanium (Ti). For example, it can contain pure titanium (pure Ti). Pure titanium (pure Ti) can be purely titanium (Ti) without including alloys or oxides containing it. For example, the first seed metal layer 121 can be formed by a deposition process such as sputtering, and thus, materials such as titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), etc. can be used, but considering dry etching, titanium (Ti) can be the most preferable. However, it is not limited to this, and it can also contain copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc.

[0030] The second seed metal layer 122 can provide a conductive region for electroplating (or electrolytic plating). The second seed metal layer 122 can be formed by a deposition process such as sputtering. When considering the adhesion, conductivity, cost, etc. with the patterned metal layer 123, it can contain copper (Cu), for example, pure copper (pure Cu). Pure copper (pure Cu) can be purely copper (Cu) without including alloys or oxides containing it. However, it is not limited to this, and it can also contain copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. The second seed metal layer 122 can be thicker than the first seed metal layer 121.

[0031] The patterned metal layer 123 can substantially provide the functions of the metal pattern 120. The patterned metal layer 123 can be formed by a plating process such as electroplating (electrolytic plating), and can contain copper (Cu), for example, pure copper, when considering conductivity, cost, etc. On the other hand, pure copper can contain purely copper (Cu), rather than an alloy or oxide containing this. However, it is not limited to this, and can also contain copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. The patterned metal layer 123 can be thicker than each of the first and second seed metal layers 121 and 122.

[0032] The recessed portion R can have a substantially angled bottom surface and wall surface. For example, the recessed portion R can have a substantially constant depth. For example, when not considering the surface roughness, the bottom surface and wall surface of the recessed portion R can each be substantially flat. For example, the wall surface of the recessed portion R can have an inclination that is substantially perpendicular or nearly perpendicular to the bottom surface. For example, since the recessed portion R can be formed in the process of removing a pure metal layer such as titanium (Ti) by dry etching, it can have a substantially vertical shape rather than a round shape. Therefore, since it can have a larger area, it can be effective by improving the adhesion between the above-described insulating layers. The depth of the recessed portion R can be larger than the thickness of the first seed metal layer 121.

[0033] Figures 4a to 4h are process cross-sectional views schematically showing an example of the manufacture of the printed circuit board of FIG. 3.

[0034] Referring to FIG. 4a, the insulating layer 110 can be prepared. The insulating layer 110 can contain an organic material or an inorganic material as described above.

[0035] Referring to FIG. 4b, a first seed metal layer 121 can be formed on the insulating layer 110. As described above, the first seed metal layer 121 can be formed by a deposition process such as sputtering using titanium (Ti) or the like as a material.

[0036] Referring to FIG. 4c, a second seed metal layer 122 can be formed on the first seed metal layer 121. As described above, the second seed metal layer 122 can be formed by a deposition process such as sputtering using copper (Cu) or the like as a material.

[0037] Referring to FIG. 4d, a resist layer 150 having a plurality of openings h can be formed on the second seed metal layer 122. The resist layer 150 can include a photosensitive insulating material. The plurality of openings h can be formed by a photolithography process. The plurality of openings h can each expose at least a part of the second seed metal layer 122.

[0038] Referring to FIG. 4e, a patterned metal layer 123 can be formed in each of the plurality of openings h. For example, in a plating process such as electroplating (or electrolytic plating), at least a part of each of the plurality of openings h can be filled with copper (Cu).

[0039] Referring to FIG. 4f, the resist layer 150 can be removed. The resist layer 150 can be removed by a physical method or a chemical method. For example, a stripping solution or the like can be used, but it is not limited thereto.

[0040] Referring to FIG. 4g, at least a part of the second seed metal layer 122 exposed from the patterned metal layer 123 can be removed. For example, at least a part of the exposed second seed metal layer 122 can be removed by wet etching. Each of the exposed second seed metal layers 122 is removed so that at least a part of the first seed metal layer 121 can be exposed from the second seed metal layer 122 and the patterned metal layer 123, respectively.

[0041] Referring to FIG. 4h, at least a part of the first seed metal layer 121 exposed from the pattern metal layer 123 and the second seed metal layer 122 can be removed. For example, at least a part of the exposed first seed metal layer 121 can be removed by dry etching. Each of the exposed first seed metal layers 121 is removed, and at least a part of the insulating layer 110 can be exposed from the first and second seed metal layers 121, 122 and the pattern metal layer 123, respectively. On the other hand, at least a part of the insulating layer 110 exposed during the dry etching process can be removed to form at least one recess portion R. If necessary, roughness can be formed on the surface of the insulating layer 110 in which the recess portion R is formed.

[0042] Through a series of processes, a printed circuit board 500A according to an example can be manufactured. Other descriptions can be substantially the same as those described for the printed circuit board 500A according to the above example, and duplicate descriptions thereof are omitted.

[0043] FIGS. 5a, 6a, 7a, and 8a are cross-sectional images taken by an electron microscope schematically showing the dry etching process of the first seed metal layer, and FIGS. 5b, 6b, 7b, and 8b are top view images of the respective cross-sectional images.

[0044] Referring to the drawings, in the dry etching of a titanium (Ti) layer with a thickness of about 50 nm, it can be confirmed that the insulating layer below the titanium (Ti) layer can maintain its shape until about 30 seconds and 60 seconds after etching. For example, in FIGS. 5a, 5b, 6a, and 6b. On the other hand, as the etching time elapses to about 90 seconds and 120 seconds, for example, in FIGS. 7a, 7b, 8a, and 8b, it can be confirmed that the insulating layer is also partially etched to form steps, such as recesses. For example, in addition to a physical reaction etching gas such as argon gas for the insulating layer of an organic substrate, a mixed gas in which a fluorine-based gas (CF4, CHF3, SF6, etc.) or a chlorine-based gas (Cl2, BCl3, etc.), which is a chemical reaction etching gas, is mixed may be used for etching, and an etching step may occur. This can be the same for the insulating layer of an inorganic substrate. For example, in an etching process for removing a specific substance, in order to cope with fluctuations in the etching rate due to fluctuations in the etching solution and spatial dispersion occurring in the substrate, an additional etching time can be provided for the required etching time. At this time, in the case of dry etching, since etching is performed downward due to the anisotropic directionality, the above-described recesses, such as recess steps, can be formed.

[0045] FIG. 9 is an electron microscope image schematically showing the wiring shape after dry etching of the first seed metal layer and the shape of the recess formed in the insulating layer.

[0046] Referring to the drawings, it can be seen that when removing the titanium (Ti) layer, which is a seed metal layer, by dry etching, no undercut occurs in the titanium (Ti) layer, and it can also be seen that a recess is formed in the insulating layer. Also, it can be seen that roughness can be formed on the surface of the insulating layer in which the recess is formed, if necessary. Therefore, it can also be seen that a sufficient width can be ensured below the wiring, and the above-described technical effects can be achieved thereby. It can also be seen that the adhesion between insulating layers can be improved.

[0047] FIG. 10 is a cross-sectional view schematically showing another example of a printed circuit board.

[0048] Referring to the drawings, a printed circuit board 500B according to another example includes a first insulating layer 110, a plurality of first metal patterns 120 disposed on the upper surface of the first insulating layer 110, a plurality of second metal patterns 220 disposed below the first insulating layer 110, at least one first via pattern 130 filling at least one via hole V penetrating between the upper and lower surfaces of the first insulating layer 110 between at least a part of each of the plurality of first and second metal patterns 120, 220, a second insulating layer 210 disposed on the upper surface of the first insulating layer 110 and covering at least a part of each of the plurality of first metal patterns 120, a plurality of third metal patterns 320 disposed on the upper surface of the second insulating layer 210, and at least one second via pattern 330 penetrating between the upper and lower surfaces of the second insulating layer 210 between at least a part of each of the plurality of first and third metal patterns 120, 320.

[0049] On the other hand, each of the plurality of first metal patterns 120 can include a first seed metal layer 121 disposed on the first insulating layer 110, a second seed metal layer 122 disposed on the first seed metal layer 121, and a first pattern metal layer 123 disposed on the second seed metal layer 122. The first via pattern 130 can include a third seed metal layer 131 disposed on at least a part of the wall surface of the via hole V and on at least a part of the plurality of second metal patterns 220, a fourth seed metal layer 132 disposed on the third seed metal layer 131, and a second pattern metal layer 133 disposed on the fourth seed metal layer 132 and filling at least a part of the via hole V. The first and third seed metal layers 121, 131 can be the same layer formed together in a deposition process or the like, the second and fourth seed metal layers 122, 132 can be the same layer formed together in a deposition process or the like, and the first and second pattern metal layers 123, 133 can be the same layer formed together in a plating process or the like. For example, the same layer can contain the same metal and can be integrated without a boundary therebetween.

[0050] Thus, the printed circuit board 500B according to another example can be a multilayer circuit board. At this time, as an inner layer, it can include the insulating layer 110, the plurality of metal patterns 120, and the recessed portion R of the printed circuit board 100A according to the above-described example. For example, the structure of the printed circuit board 500A according to the above-described example can be applied as an inner layer of a multilayer circuit board such as the printed circuit board 500B according to another example. However, it is not limited thereto, and it can also be applied as an outer layer of the multilayer circuit board or to all of the inner and outer layers. On the other hand, the printed circuit board 500B according to another example can be formed in more layers. For example, it can include a larger number of insulating layers, metal pattern layers, and via pattern layers. Also, the structure of the printed circuit board 100A according to the above-described example can be freely applied to the inner and outer layers according to the design. Further, if necessary, the structure of the printed circuit board 100A according to the above-described example can be partially introduced only to the portions where wiring connection is required. The printed circuit board 500B according to another example of such a multilayer circuit board structure can be used as an FCB (Flip-Chip Board), BGA (Ball Grid Array), an interposer substrate, a package substrate, an interconnect bridge substrate, etc. However, it is not limited thereto, and it can also be applied to various other forms of substrates.

[0051] Hereinafter, with reference to the drawings, the components of the printed circuit board 500B according to another example will be described in more detail.

[0052] The first and second insulating layers 110 and 210 can each contain an insulating material. The insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or an organic material including an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with the resin. For example, the insulating material can be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film), PPG (Prepreg), or a photosensitive insulating material such as PID (Photo Imagable Dielectric), but is not limited thereto. If necessary, the insulating material can also include an inorganic material including SiO2, Si3N4, etc. The first and second insulating layers 110 and 210 can contain the same insulating material as each other and can be integrated with each other without a boundary if necessary. However, it is not limited thereto, and they can contain different insulating materials from each other and the boundaries can be distinguished from each other.

[0053] The first to third metal patterns 120, 220, and 320 can each contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. The first to third metal patterns 120, 220, and 320 can each perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc. These patterns can each have various forms such as a line, a plane, a pad, etc. The second and third metal patterns 220 and 320 can each be formed by a plating process using SAP (Semi Additive Process), MSAP (Modified SAP), TT (Tenting), etc., and can include, for example, an electroless plating layer and an electroplating layer, but is not limited thereto. If necessary, it can include a sputter layer instead of the electroless plating layer, or can include both.

[0054] The plurality of first metal patterns 120 can be finer circuit patterns than each of the plurality of second and third metal patterns 220, 230. For example, the line width, spacing, etc. of the line patterns among the plurality of first metal patterns 120 can be smaller than those of the line patterns among the plurality of second metal patterns 220, and further smaller than those of the line patterns among the plurality of third metal patterns 230. Also, the pitch, etc. of the pad patterns among the plurality of first metal patterns 120 can be smaller than those of the pad patterns among the plurality of second metal patterns 220, and further smaller than those of the pad patterns among the plurality of third metal patterns 230. For example, the plurality of first metal patterns 120 can include higher density patterns than each of the plurality of second and third metal patterns 220, 230.

[0055] The first and second via patterns 130, 330 can each contain metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. The first and second via patterns 130, 330 can each include a filled VIA filling the via hole, but can also include a conformal VIA arranged along the wall surface of the via hole. The first and second via patterns 130, 330 can each perform various functions according to the design. For example, it can include a ground via, a power via, a signal via, etc. The first and second via patterns 130, 330 can each have a shape tapered in the same direction as each other in cross-section. For example, on each cross-section, the upper end portion can be wider than the lower end portion. The second via pattern 330 can be formed by a plating process using SAP (Semi Additive Process), MSAP (Modified SAP), TT (Tenting), etc., and can include, for example, an electroless plating layer and an electroplating layer, but is not limited thereto, and can also include a sputter layer instead of the electroless plating layer, or can include both.

[0056] The first and third seed metal layers 121 and 131 can enhance the adhesion between the first insulating layer 110 and the first metal pattern 120, and between the first insulating layer 110 and the first via pattern 130, respectively. The first and third seed metal layers 121 and 131 can contain the same metal as each other, for example, titanium (Ti). For example, it can contain pure titanium (pure Ti). Pure titanium (pure Ti) can be purely titanium (Ti) without including alloys or oxides containing it. For example, the first and third seed metal layers 121 and 131 can be formed together in a deposition process such as sputtering, and materials such as titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), etc. can be used, but when considering dry etching, titanium (Ti) can be the most preferable. However, it is not limited to this, and it can also contain copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc.

[0057] The second and fourth seed metal layers 122 and 132 can provide a conductive region for electroplating (or electrolytic plating). The second and fourth seed metal layers 122 and 132 can be formed together in a deposition process such as sputtering, and when considering the adhesion, conductivity, cost, etc. with the first and second pattern metal layers 123 and 133, they can contain copper (Cu), for example, pure copper (pure Cu). Pure copper (pure Cu) can be purely copper (Cu) without including alloys or oxides containing it. However, it is not limited to this, and it can also contain copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. The thickness of the second seed metal layer 122 can be thicker than the thickness of the first seed metal layer 121.

[0058] The first and second patterned metal layers 123 and 133 can substantially provide the functions of the first metal pattern 120 and the first via pattern 130. The first and second patterned metal layers 123 and 133 can be formed together in a plating process such as electroplating, and can include the same metal as each other, for example, copper (Cu) when considering conductivity, cost, etc., and can include, for example, pure copper. On the other hand, pure copper can purely include copper (Cu) rather than alloys, oxides, etc. containing the same. However, it is not limited to this, and can also include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. The thickness of the first patterned metal layer 123 can be greater than the respective thicknesses of the first and second seed metal layers 121 and 122.

[0059] The recess R can have a substantially angled bottom surface and wall surface. For example, the recess R can have a substantially constant depth. For example, when not considering surface roughness, the bottom surface and wall surface of the recess R can each be substantially flat. For example, the wall surface of the recess R can have an inclination that is substantially perpendicular or nearly perpendicular to the bottom surface. For example, since the recess R can be formed in the process of removing a pure metal layer such as titanium (Ti) by dry etching, it can have a substantially vertical shape rather than a round shape, and thus can have a larger area, and therefore can be effective in improving the adhesion between the first and second insulating layers 110 and 210. The depth of the recess R can be greater than the thickness of the first seed metal layer 121.

[0060] The via hole V can be formed in the first insulating layer 110 prior to forming the first seed metal layer 121. For example, depending on the material of the first insulating layer 110, the via hole V can be formed by various methods such as mechanical drilling, laser processing, chemical etching, etc. The via hole V can be formed to penetrate the first insulating layer 110. When forming the first seed metal layer 121 after forming the via hole V, the third seed metal layer 131 can be formed in the via hole V. Also, when forming the second seed metal layer 122, the fourth seed metal layer 132 can be formed in the via hole V. Further, when forming the first patterned metal layer 123, the second patterned metal layer 133 can be formed in the via hole V.

[0061] Other explanations can be substantially the same as those described in the printed circuit board 500A according to an example and an example of manufacturing the printed circuit board 500A according to an example, so duplicate explanations thereof are omitted.

[0062] In the present disclosure, the expression "cover" can include not only the case of covering entirely but also the case of covering at least a part, and can include not only the case of directly covering but also the case of indirectly covering. Also, the expression "fill" can include not only the case of completely filling but also the case of filling at least a part, and can include the case of roughly filling. For example, it can include the case where there are some voids or voids. Also, the expression "surround" can include not only the case of completely surrounding but also the case of partially surrounding and the case of roughly surrounding. Further, the expression "adjacent" is not limited to the case of being in contact with each other, meaning the case of being arranged adjacent to substantially the same layer. Also, "exposing" can include not only the case of completely exposing but also the case of partially exposing, and exposure can mean exposing from embedding the corresponding configuration.

[0063] In the present disclosure, it can be determined by substantially including process errors, positional deviations, errors during measurement, etc. that occur during the manufacturing process. For example, being substantially coplanar can include not only the case of being exactly in the same plane but also the case of being approximately in the same plane.

[0064] In the present disclosure, the meaning of cross-section can mean the cross-sectional shape when the object is cut perpendicularly, or the cross-sectional shape when the object is cut perpendicularly, or the cross-sectional shape when the object is viewed in a side view. Also, the meaning of plane can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed in a top view or a bottom view.

[0065] In the present disclosure, terms such as lower side, lower part, lower surface, etc. are used to mean the downward direction based on the cross-section of the drawing for convenience, and terms such as upper side, upper part, upper surface, etc. are used to mean the opposite direction. However, this is only to define the direction for the convenience of explanation, and it goes without saying that the scope of rights in the claims is not particularly limited by the description of such a direction, and the concept of up / down can change at any time.

[0066] In the present disclosure, the meaning of being connected includes not only the case of being directly connected but also the case of being indirectly connected via an adhesive layer or the like. Also, the meaning of being electrically connected includes all cases of being physically connected and not being connected. Furthermore, expressions such as first, second, etc. are used to distinguish one component from another component, and do not limit the order and / or importance of the said components. In some cases, without departing from the scope of rights, the first component can also be named the second component, and similarly the second component can also be named the first component.

[0067] In the present disclosure, thickness, width, length, depth, line width, interval, pitch, etc. can be measured by a scanning microscope, an optical microscope, etc. based on the cross-section obtained by polishing or cutting a printed circuit board. The cut cross-section can be a vertical cross-section or a horizontal cross-section, and numerical values can be measured based on the required cut cross-section. For example, the width of the upper end and / or the lower end of a via can be measured on the cross-section obtained by cutting the central axis of the via. At this time, when the numerical values are not constant, the numerical values can be determined as the average value of the values measured at any five points. On the other hand, the minimum numerical value can be determined as the numerical value measured as the smallest value in the corresponding layer, the corresponding region, etc.

[0068] The expression of "an example used in the present disclosure" does not mean the same embodiments as each other, but is provided to emphasize and explain their respective different unique features. However, the above-presented example does not exclude being implemented in combination with the features of another example. For example, even if a matter described in a specific example is not described in another example, it can be understood as an explanation related to the other example as long as there is no explanation contrary to or conflicting with that matter in the other example.

[0069] The terms used in the present disclosure are merely used to explain an example and are not intended to limit the present disclosure. At this time, the singular expression includes plural expressions unless it clearly means something different in the context.

Description of Reference Numerals

[0070] 1000 Electronic device 1010 Main board 1020 Chip-related components 1030 Network-related components 1040 Other components 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 Signal line 1100 Smartphone 1110 Motherboard 1120 Components 1121 Component Package 1130 Camera Module 1140 Speaker 500A, 500B Printed Circuit Board 110, 210 Insulation Layer 120, 220, 320 Metal Pattern 130, 330 Via Pattern 121, 122, 131, 132 Seed Metal Layer 123, 133 Pattern Metal Layer 150 Resist Layer R Recess Portion V Via Hole h Opening

Claims

1. A first insulating layer; a plurality of first metal patterns disposed on the first insulating layer; the first insulating layer has at least one recess; the recessed portion is disposed between the first metal patterns; each of the plurality of first metal patterns includes a first seed metal layer disposed on the first insulating layer, a second seed metal layer disposed on the first seed metal layer, and a pattern metal layer disposed on the second seed metal layer.

2. the first seed metal layer comprises titanium (Ti); the second seed metal layer comprises copper (Cu); The printed circuit board of claim 1 , wherein the patterned metal layer comprises copper (Cu).

3. the first metal patterns are disposed on an upper surface of the first insulating layer; on an upper surface of the first insulating layer, The printed circuit board of claim 1 , wherein the patterned metal layer is thicker than each of the first seed metal layer and the second seed metal layer.

4. 4. The printed circuit board according to claim 3, wherein an upper surface of the first insulating layer in the region where the plurality of first metal patterns are arranged and an upper surface of the first insulating layer in the region where the recessed portion is arranged have a step with each other.

5. The printed circuit board of claim 3 , wherein the upper surface of the first insulating layer in the region where the recessed portion is arranged has a surface roughness greater than that of the upper surface of the first insulating layer in the region where the plurality of first metal patterns are arranged.

6. The printed circuit board according to claim 3 , wherein the recessed portion penetrates a portion of the first insulating layer in a thickness direction from an upper surface of the first insulating layer between the plurality of first metal patterns.

7. a plurality of second metal patterns disposed under the first insulating layer; at least one via pattern filling at least one via hole penetrating between the upper surface and the lower surface of the first insulating layer between at least a portion of each of the plurality of first metal patterns and the plurality of second metal patterns; 4. The printed circuit board of claim 3, wherein the via pattern includes the first seed metal layer disposed on wall surfaces of the via holes and at least a portion of the plurality of second metal patterns, the second seed metal layer disposed on the first seed metal layer, and the pattern metal layer disposed on the second seed metal layer and filling at least a portion of the via holes.

8. a second insulating layer disposed on an upper surface of the first insulating layer and covering at least a portion of each of the first metal patterns; 4. The printed circuit board of claim 3, further comprising a plurality of third metal patterns disposed on a top surface of the second insulating layer.

9. The printed circuit board of claim 1 , wherein the recess has a bottom surface and a wall surface that form a substantial angle with each other.

10. The printed circuit board of claim 9 , wherein the recess has a substantially constant depth.

11. The printed circuit board of claim 1 , wherein the first metal patterns include a plurality of fine circuit patterns having an L (Line) / S (Space) ratio of 5 μm / 5 μm or less.

12. forming a first seed metal layer on the insulating layer; forming a second seed metal layer on the first seed metal layer; forming a patterned metal layer on the second seed metal layer; removing at least a portion of the second seed metal layer exposed from the patterned metal layer; removing at least a portion of the first seed metal layer exposed from the patterned metal layer and the second seed metal layer; In the step of removing at least a portion of the first seed metal layer, At least a portion of the insulating layer is removed to form at least one recess.

13. In the step of forming the first seed metal layer, The first seed metal layer is formed by depositing titanium (Ti); In the step of forming the second seed metal layer, The second seed metal layer is formed by depositing copper (Cu); In the step of forming a patterned metal layer, 13. The method for manufacturing a printed circuit board according to claim 12, wherein the pattern metal layer is formed by forming a resist layer having a plurality of openings on the second seed metal layer, then filling the plurality of openings with copper (Cu) by plating, and then removing the resist layer.

14. In the step of removing at least a portion of the second seed metal layer, removing at least a portion of the second seed metal layer by wet etching; In the step of removing at least a portion of the first seed metal layer, removing at least a portion of the first seed metal layer by dry etching; The method for manufacturing a printed circuit board according to claim 12 , wherein the recessed portion is formed by dry etching.

15. In the step of removing at least a portion of the first seed metal layer, The method of claim 12 , wherein a surface of the insulating layer in a region where the recess is formed has a surface roughness greater than a surface of the insulating layer in a region where the patterned metal layer is formed.

16. Prior to forming the first seed metal layer, forming a via hole penetrating the insulating layer, In the steps of forming the first seed metal layer, forming the second seed metal layer, and forming the patterned metal layer, The method for manufacturing a printed circuit board according to claim 12 , wherein at least a portion of the first seed metal layer, at least a portion of the second seed metal layer, and at least a portion of the patterned metal layer are each formed in the via hole.

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