Semiconductor device manufacturing method and pattern formation method

Abstract

To form a fine pattern exceeding a limit resolution of a lithography process.SOLUTION: A semiconductor device manufacturing method includes: forming a first hard mask pattern including a second hole pattern by transferring a first hole pattern to a first hard mask layer; forming a first cylindrical spacer pattern arranged in the position of the second hole pattern by forming a first spacer layer in the sidewall of the second hole pattern and removing the first hard mask pattern; and forming a fourth hole pattern including a second hole pattern composed of the first spacer pattern and a third hole pattern composed of the second spacer pattern by forming a second spacer layer covering the upper surface of a second hard mask layer outside the first spacer pattern and forming a second spacer pattern including a third hole pattern by removing the second spacer layer which overlaps a first region defined by the minimum distances connecting the center points of the first spacer patterns.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a method for forming a pattern.

Background Art

[0002] With the miniaturization of semiconductor devices, the requirement for forming patterns such as holes finely has been increasing. As a fine hole pattern, a hexagonal closest packing in which holes are arranged at each vertex of a regular hexagon and at the center point of the regular hexagon when viewed from above may be adopted.

[0003] In order to form the above-described hexagonal closest packing with a pitch finer than the limit resolution of lithography while using lithography technology, for example, a technique called cross-point processing has been proposed. However, in cross-point processing, there are many problems to be solved, such as a large number of processes and laborious pattern alignment.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to provide a method for manufacturing a semiconductor device and a method for forming a pattern that can form a fine pattern exceeding the limit resolution of a lithography process.

Means for Solving the Problems

[0006] The manufacturing method of the semiconductor device according to the embodiment includes forming, above a layer to be processed, first and second hard mask layers in the order of the second hard mask layer and the first hard mask layer from the layer-to-be-processed side; forming, above the first hard mask layer, a resist mask pattern having a first hole pattern formed using lithography; transferring the first hole pattern to the first hard mask layer to form a first hard mask pattern having a second hole pattern; forming a first spacer layer on sidewalls of the second hole pattern and removing the first hard mask pattern, thereby forming a cylindrical first spacer pattern disposed at a position of the second hole pattern; forming a second spacer layer covering an upper surface of the second hard mask layer outside the first spacer pattern; removing the second spacer layer overlapping with a first region composed of a minimum distance connecting center points of the first spacer patterns to form a second spacer pattern having a third hole pattern, thereby forming a fourth hole pattern including the second hole pattern composed of the first spacer patterns and the third hole pattern composed of the second spacer patterns; transferring the fourth hole pattern to the second hard mask layer to form a second hard mask pattern having a fifth hole pattern; forming a third spacer layer on sidewalls of the fifth hole pattern and removing the second hard mask pattern, thereby forming a cylindrical third spacer pattern disposed at a position of the fifth hole pattern; forming a fourth spacer layer covering an upper surface of the layer to be processed outside the third spacer pattern; removing the fourth spacer layer overlapping with a second region composed of a minimum distance connecting center points of the third spacer patterns to form a fourth spacer pattern having a sixth hole pattern, thereby forming a seventh hole pattern including the fifth hole pattern composed of the third spacer patterns and the sixth hole pattern composed of the fourth spacer patterns; and transferring the seventh hole pattern to the layer to be processed.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 7

Figure 8

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Figure 10

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited by the following embodiments. Also, the constituent elements in the following embodiments include those that can be easily assumed by those skilled in the art or those that are substantially the same.

[0009] [Embodiment 1] Hereinafter, Embodiment 1 will be described in detail with reference to the drawings.

[0010] (Example of Configuration of Semiconductor Device) FIG. 1 is a diagram showing an example of the configuration of the semiconductor device 1 according to the embodiment. FIG. 1(a) is a top view of the semiconductor device 1 of the embodiment, and FIG. 1(b) is a perspective view of the semiconductor device 1 of the embodiment. The semiconductor device 1 of the embodiment is configured as, for example, a DRAM (Dinamic Random Access Memory).

[0011] As shown in FIG. 1, the semiconductor device 1 includes a plurality of word lines WL extending in a predetermined direction at a predetermined distance from each other, a plurality of bit lines BL extending on the word lines WL in a direction intersecting the word lines WL at a predetermined distance from each other, and a plurality of pillar-type capacitors PC arranged in the same number as the intersections of the word lines WL and the bit lines BL on the bit lines BL. Further, an active region AA in which a predetermined dopant is diffused is formed in a semiconductor substrate (not shown) below these configurations.

[0012] In the semiconductor device 1 of the embodiment, each pillar-type capacitor PC functions as a memory cell capable of holding data by accumulating electric charges. Therefore, the closer the pitch between the pillar-type capacitors PC is reduced and the more closely they are arranged, the higher the storage capacity of the semiconductor device 1 can be increased.

[0013] For this reason, in the semiconductor device 1, when viewed from above, each pillar-type capacitor PC is arranged, for example, at each vertex of a regular hexagon and at the center point of the regular hexagon. By adopting such an arrangement, the pillar-type capacitors PC can be arranged closely. Such an arrangement of the pillar-type capacitors PC will be hereinafter referred to as a hexagonal closest packing arrangement following the hexagonal closest packing structure of the crystal structure.

[0014] (Method of manufacturing a semiconductor device) Next, with reference to FIGS. 2 to 10, the method of manufacturing the semiconductor device 1 of the embodiment will be described.

[0015] In the semiconductor device 1 of the embodiment, in order to form the pillar-type capacitor PC, a fine hole pattern having a hexagonal close-packed arrangement is formed. At this time, it is important how to reduce the pitch of the hole pattern. First, FIG. 2 shows a schematic manufacturing method of the semiconductor device 1.

[0016] FIG. 2 is a schematic top view for explaining the outline of the manufacturing method of the semiconductor device 1 according to the embodiment. In the manufacturing method of the semiconductor device 1 of the embodiment, it is an object to form a hole pattern having a hexagonal close-packed arrangement with a pitch finer than the limit resolution of lithography.

[0017] As shown in FIG. 2(a), a resist mask pattern having a hexagonal close-packed arrangement is formed on the layer to be processed, which is the object of forming the hole pattern, using lithography technology. At this time, the resist mask pattern is preferably formed so as to have a pitch close to the limit resolution of lithography.

[0018] Thereby, a resist mask pattern in which hole patterns are arranged at each vertex of a regular hexagon and at the center point of the regular hexagon is formed. In FIG. 2(a), a regular hexagon is shown superimposed on the hole pattern having a hexagonal close-packed arrangement.

[0019] Note that the pitch between these hole patterns having a hexagonal close-packed arrangement is three times the pitch of the finally obtained hole pattern. Also, the equilateral triangle shown in FIG. 2(a) is composed of the minimum distance connecting the center points of the hole patterns included in the resist mask pattern.

[0020] As shown in FIG. 2(b), the hole pattern of FIG. 2(a) is transferred to a hard mask pattern. Also, additional hole patterns are formed between the transferred hole patterns. More specifically, additional hole patterns are arranged at the center portions of the hole patterns overlapping each vertex of the equilateral triangle shown in FIG. 2(a). At this time, the diameter of the additional hole pattern is made smaller than the diameter of the hole pattern in FIG. 2(a), and the diameter of the hole pattern in FIG. 2(a) is also reduced in accordance with the additional hole pattern.

[0021] As a result, in the hard mask pattern of FIG. 2(b), the hole pattern will have a pitch that is √3 times that of the finally obtained hole pattern. In FIG. 2(b), a regular hexagon that is reduced from the regular hexagon shown in FIG. 2(a) is shown superimposed on the hole pattern having a hexagonal close-packed arrangement. Also shown is an equilateral triangle formed by the minimum distance connecting the center points of the hole patterns in FIG. 2(b), which is an equilateral triangle reduced from the equilateral triangle shown in FIG. 2(a).

[0022] As shown in FIG. 2(c), the hole mask pattern of FIG. 2(b) is transferred to a different hard mask layer to newly form a hard mask pattern, and additional hole patterns are arranged at the central portions of the hole patterns that overlap the respective vertices of the equilateral triangle shown in FIG. 2(b). By repeating the process shown in FIG. 2(b) again in this way, a final hole pattern having a desired pitch can be obtained.

[0023] It can be seen that the regular hexagon overlapping the hole pattern of FIG. 2(c) having a hexagonal close-packed arrangement is further reduced from the regular hexagons shown in FIGS. 2(a) and 2(b). Also, it can be seen that the equilateral triangle formed by the minimum distance connecting the center points of the hole patterns in FIG. 2(c) is further reduced from the equilateral triangles shown in FIGS. 2(a) and 2(b).

[0024] As described above, by forming a pattern with a 3-fold pitch of the finally obtained hole pattern and performing the process of reducing the pitch of that hole pattern to 1 / √3 twice, a fine hole pattern with a hexagonal close-packed arrangement having a pitch that is 1 / 3 of the pitch obtained at the limit resolution of lithography is formed in one lithography process.

[0025] In addition, the process of forming additional hole patterns at the central portions of the hole patterns that overlap the respective vertices of the equilateral triangle and reducing the pitch of the hole pattern to 1 / √3 will hereinafter also be referred to as STP (Self-aligned Triangle Patterning).

[0026] A more detailed manufacturing method of the semiconductor device 1 according to the embodiment will be described below.

[0027] FIGS. 3 to 10 are diagrams sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device 1 according to the embodiment. (Aa) to (Ca) in FIGS. 3 to 10 are top views of the semiconductor device 1 during manufacturing. (Ab) to (Cb) in FIGS. 3 to 10 are cross-sectional views taken along line A-A' of (Aa) to (Ca) in FIGS. 3 to 10 of the semiconductor device 1 during manufacturing. In (Aa) to (Ca) in FIGS. 3 to 10, the finally obtained hole pattern is indicated by a broken line.

[0028] As shown in FIG. 3(Ab), the layer to be processed 10, four hard mask layers 21 to 24, and the resist mask layer 30 are formed in this order from the lower layer side.

[0029] The layer to be processed 10 is a layer on which the final hole pattern HPfn shown in FIG. 3(Aa) is transferred, and the above-described pillar-type capacitor PC is formed. As the hard mask layers 21 to 24, a silicon layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, various metal layers, or a metal oxide layer, etc. can be appropriately used.

[0030] As will be described later, since selectivity with respect to the etching process is required between these layers to be processed 10 and the hard mask layers 21 to 24, it is preferable that different materials are used for at least adjacent layers. Also, as will be described later, since the layer thicknesses of the hard mask layers 21 to 24 affect the size etc. of the finally obtained hole pattern HPfn, it is preferable that they are adjusted to appropriate layer thicknesses in advance.

[0031] For example, a photoresist or the like is used for the resist mask layer 30.

[0032] It is assumed that the active region AA, the word line WL, and the bit line BL have already been formed below the layer to be processed 10.

[0033] As shown in FIGS. 3(Ba) and (Bb), a resist mask pattern 30p having a hole pattern HPaa with a pitch close to the limit resolution in the lithography technique is formed while using a high-resolution lithography technique. As the high-resolution lithography technique, at present, for example, immersion exposure using an ArF laser as a light source can be used. Thereby, the lower hard mask layer 24 is exposed on the bottom surface of the hole pattern HPaa.

[0034] As described above, the hole pattern HPaa formed in this way has a hexagonal closest packing having a pitch three times that of the finally obtained hole pattern HPfn, for example. The resist mask pattern 30p having the hole pattern HPaa corresponds to the resist mask pattern having the hexagonal closest packing shown in FIG. 2(a) above.

[0035] In addition, the hole pattern HPaa of the resist mask pattern 30p has a diameter larger than that of the finally obtained hole pattern HPfn. As will be described later, the hole pattern HPaa of the resist mask pattern 30p is sequentially transferred to the hard mask layers 24 to 21, and at that time, the hole diameter of the hole pattern HPaa is gradually reduced. In this way, since the hole diameter of the hole pattern HPaa also affects the size of the finally obtained hole pattern HPfn, etc., it is preferably adjusted to an appropriate size in advance.

[0036] As shown in FIGS. 4(Aa) and (Ab), the hole pattern HPaa included in the resist mask pattern 30p is transferred to the hard mask layer 24 using reactive ion etching (RIE) or the like. Thereby, a hard mask pattern 24p having a hole pattern HPab is formed. Also, the lower hard mask layer 23 is exposed from the bottom surface of the hole pattern HPab.

[0037] Thereafter, the resist mask pattern 30p is removed by ashing using oxygen plasma or the like.

[0038] As shown in FIGS. 4(Ba) and (Bb), a spacer layer 41 covering the hard mask pattern 24p is formed. The spacer layer 41 can also be selected from a predetermined layer among the above-described silicon layer, silicon oxide layer, silicon nitride layer, silicon oxynitride layer, various metal layers, or metal oxide layer, etc. and used. Also in this case, it is preferable that a material capable of obtaining selectivity with respect to the hard mask pattern 24p and the hard mask layer 23 exposed from the hard mask pattern 24p is used for the spacer layer 41.

[0039] The spacer layer 41 covers the upper surface of the hard mask pattern 24p, as well as the side walls and the bottom surface of the hole pattern HPab of the hard mask pattern 24p. At this time, the layer thickness of the spacer layer 41 is adjusted so that the hole pattern HPab is not completely filled. In addition, as described above, when initially forming the resist mask pattern 30p, the hole size of the hole pattern HPaa is adjusted in advance, and the layer thickness of the hard mask 24 is adjusted.

[0040] In FIG. 4(Ba), the interface of the hard mask pattern 24p covered with the spacer layer 41 with the spacer layer 41 is indicated by a broken line.

[0041] As shown in FIGS. 4(Ca) and (Cb), the spacer layer 41 is etched back over the entire surface to remove the spacer layer 41 from the upper surface of the hard mask pattern 24p and the upper surface of the hard mask layer 23 exposed from the hole pattern HPab. Thereby, a hole pattern HPac having a spacer pattern 41p on the side walls is obtained. The underlying hard mask layer 23 is exposed from the bottom surface of the hole pattern HPac.

[0042] The hole pattern HPac has a diameter smaller than twice the thickness of the spacer pattern 41p and smaller than that of the above-described hole pattern HPab. However, the arrangement and pitch of the hole pattern HPac are substantially the same as those of the hole pattern HPab. That is, like the hole patterns HPaa, HPab, etc., the hole pattern HPac has a hexagonal close-packed arrangement with a pitch three times that of the finally obtained hole pattern HPfn.

[0043] As shown in FIGS. 5(Aa) and (Ab), the hard mask pattern 24p is removed by wet etching or the like. Thereby, a hole pattern HPad in which the spacer pattern 41p remains cylindrically on the hard mask layer 23 is obtained.

[0044] As shown in FIGS. 5(Ba) and (Bb), a spacer layer 42 is formed to cover the spacer pattern 41p and the hard mask layer 23 exposed from the spacer pattern 41p. The spacer layer 42 can also be formed by selecting a predetermined layer from among the above-described silicon layer, silicon oxide layer, silicon nitride layer, silicon oxynitride layer, various metal layers, or metal oxide layer. Also in this case, it is preferable that a material having selectivity with respect to the spacer pattern 41p and the hard mask layer 23 is used for the spacer layer 42.

[0045] The spacer layer 42 covers the upper surface of the spacer pattern 41p and the upper surface of the hard mask layer 23. At this time, the formation conditions of the spacer layer 42 are controlled so that the void in the cylinder (hole) of the hole pattern HPad of the spacer pattern 41p is maintained without being filled by the spacer layer 42. Also, the layer thickness and etch-back amount of the spacer layer 41, the hole size of the hole pattern HPaa in the resist mask pattern 30p, and the layer thickness of the hard mask 24 are adjusted in advance so that the inner diameter of the hole pattern HPad becomes sufficiently small. Thereby, an air gap AGa covered with the spacer layer 42 at the upper part is formed in the cylinder (hole) of the hole pattern HPad.

[0046] Further, by forming the spacer layer 42 along the shape of the hole pattern HPad that protrudes cylindrically, irregularities are formed on the surface of the spacer layer 42. As a result, recesses RCa are formed at the surface positions of the spacer layer 42 that correspond to the center points of the equilateral triangles formed by the minimum distances connecting the center points of the hole pattern HPad having a hexagonal close-packed arrangement.

[0047] Note that in FIG. 5(Ba), the spacer pattern 41p, which is the portion covered by the spacer layer 42, and the hard mask layer 23 exposed on the bottom surface of the air gap AGa are shown by broken lines.

[0048] As shown in FIGS. 5(Ca) and (Cb), the spacer layer 42 is etched back over the entire surface to remove the spacer layer 42 from the upper surface of the spacer pattern 41p and the upper surface of the hard mask layer 23 exposed from the spacer pattern 41p. As a result, the air gap AGa within the cylinder (hole) of the hole pattern HPad is exposed. Also, substantially the entire outer hard mask layer 23 of the hole pattern HPad is covered, and a hole pattern HPae is formed with the again-exposed air gap AGa as the hole portion.

[0049] The hole pattern HPae has substantially the same pattern as the above-described hole pattern HPac having the spacer pattern 41p on its sidewalls. That is, the hole pattern HPae has a configuration in which the hard mask pattern 24p portion of the above-described hole pattern HPac is replaced with the spacer pattern 42p.

[0050] Further, by the back-etching of the entire surface of the spacer layer 42, the recesses RCa formed at the center points of the equilateral triangles formed by the minimum distances connecting the center points of the hole pattern HPad penetrate the spacer layer 42, and a hole pattern HPba is formed so as to be mixed with the hole pattern HPae. More specifically, the hole pattern HPba is arranged at the center points of the equilateral triangles formed by the minimum distances connecting the center points of the hole pattern HPae having a hexagonal close-packed arrangement.

[0051] In this way, an additional hole pattern HPba can be self-alignedly formed with respect to the hole pattern HPae.

[0052] Also, thereby, the hole pattern HPca including the hole pattern HPae and the hole pattern HPba forms a hexagonal closest packing having a pitch that is 1 / √3 times that of the hole pattern HPaa that the original resist mask pattern 30p had. In other words, the hole pattern HPca has a pitch that is √3 times that of the finally obtained hole pattern HPfn.

[0053] As shown in FIGS. 6(Aa)(Ab), the hole pattern HPca composed of the spacer patterns 41p, 42p is transferred to the hard mask layer 23 using, for example, RIE or the like. Thereby, a hard mask pattern 23p having the hole pattern HPcb is formed. Also, the underlying hard mask layer 22 is exposed from the bottom surface of the hole pattern HPcb.

[0054] The hard mask pattern 23p having the hole pattern HPcb corresponds to the hard mask pattern having the additional hole pattern shown in FIG. 2(b) above. Thereafter, as described in FIG. 2 above, the processes after FIGS. 4(Aa)(Ab) are repeated to further reduce the hole pattern HPcb by 1 / √3 times.

[0055] Note that, in consideration of ease of understanding of the drawings, near the ends of the four sides of the top views of FIGS. 5(Ba), 5(Ca), and 6(Aa), the illustration of the configuration formed by the spacer layer 42 and the spacer layer 42 is partially omitted.

[0056] As shown in FIGS. 7(Aa)(Ab), the spacer patterns 41p, 42p are removed by wet etching or the like. Thereby, the hard mask pattern 23p having the hole pattern HPcb is exposed.

[0057] As shown in FIGS. 7(Ba) and (Bb), a spacer layer 43 covering the hard mask pattern 23p is formed. The spacer layer 43 can also be formed by selecting a predetermined layer from among the above-described silicon layer, silicon oxide layer, silicon nitride layer, silicon oxynitride layer, various metal layers, or metal oxide layer. Also in this case, it is preferable that the spacer layer 43 be made of a material that provides selectivity with respect to the hard mask pattern 23p and the hard mask layer 22 exposed from the hard mask pattern 23p.

[0058] The spacer layer 43 covers the upper surface of the hard mask pattern 23p, as well as the side walls and bottom surface of the hole pattern HPcb of the hard mask pattern 23p. At this time, the layer thickness of the spacer layer 43 is adjusted so that the hole pattern HPcb is not completely filled, and the layer thickness of the hard mask 23 is adjusted in advance. In addition, the hole size of the hole pattern HPaa in the resist mask pattern 30p described above, the layer thickness of the hard mask 24, etc. are adjusted in consideration of the processes of FIGS. 7(Ba) and (Bb).

[0059] In FIG. 7(Ba), the interface of the hard mask pattern 23p covered with the spacer layer 43 with the spacer layer 43 is indicated by a dashed line.

[0060] As shown in FIGS. 7(Ca) and (Cb), the spacer layer 43 is etched back over the entire surface to remove the spacer layer 43 from the upper surface of the hard mask pattern 23p and the upper surface of the hard mask layer 22 exposed from the hole pattern HPcb. As a result, a hole pattern HPcc having a spacer pattern 43p on its side walls is obtained. The underlying hard mask layer 22 is exposed from the bottom surface of the hole pattern HPcc.

[0061] The hole pattern HPcc has a diameter that is twice the thickness of the spacer pattern 43p and is smaller than that of the hole pattern HPcb described above. However, the arrangement and pitch of the hole pattern HPcc are substantially the same as those of the hole pattern HPcb. That is, like the hole patterns HPca, HPcb, etc., the hole pattern HPcc has a hexagonal closest packing with a pitch that is √3 times that of the finally obtained hole pattern HPfn.

[0062] As shown in FIGS. 8(Aa) and (Ab), the hard mask pattern 23p is removed by wet etching or the like. As a result, a hole pattern HPcd is obtained in which the spacer pattern 43p remains cylindrically on the hard mask layer 22.

[0063] As shown in FIGS. 8(Ba) and (Bb), a spacer layer 44 is formed to cover the spacer pattern 43p and the hard mask layer 22 exposed from the spacer pattern 43p. The spacer layer 44 can also be formed by selecting a predetermined layer from among the above-described silicon layer, silicon oxide layer, silicon nitride layer, silicon oxynitride layer, various metal layers, or metal oxide layer. Also in this case, it is preferable that a material having selectivity with respect to the spacer pattern 43p and the hard mask layer 22 is used for the spacer layer 44.

[0064] The spacer layer 44 covers the upper surface of the spacer pattern 43p and the upper surface of the hard mask layer 22. At this time, the formation conditions of the spacer layer 44 are controlled so that the void in the cylinder (hole) of the hole pattern HPcd of the spacer pattern 43p is maintained without being filled by the spacer layer 44. Also, the layer thickness and etch-back amount of the spacer layer 43 are adjusted in advance so that the inner diameter of the hole pattern HPcd becomes sufficiently small. In addition, the hole size of the hole pattern HPaa in the resist mask pattern 30p described above, and the layer thicknesses of the hard masks 23 and 24 are adjusted in consideration of the processes shown in FIGS. 8(Ba) and (Bb).

[0065] As a result, an air gap AGb with its upper part covered by the spacer layer 44 is formed inside the cylinder (hole) of the hole pattern HPcd.

[0066] Further, by forming the spacer layer 44 along the shape of the hole pattern HPcd where the spacer layer 44 protrudes in a cylindrical shape, irregularities are formed on the surface of the spacer layer 44. As a result, recesses RCb are respectively formed at the surface positions of the spacer layer 44 corresponding to the center points of the equilateral triangles formed by the minimum distances connecting the center points of the hole pattern HPcd having a hexagonal closest packing.

[0067] Note that in Fig. 8(Ba), the spacer pattern 43p, which is the part covered by the spacer layer 44, and the hard mask layer 22 exposed on the bottom surface of the air gap AGb are shown by broken lines.

[0068] As shown in Figs. 8(Ca)(Cb), the spacer layer 44 is etched back over the entire surface to remove the spacer layer 44 from the upper surface of the spacer pattern 43p and the upper surface of the hard mask layer 22 exposed from the spacer pattern 43p. As a result, the air gap AGb inside the cylinder (hole) of the hole pattern HPcd is exposed. Also, substantially the entire hard mask layer 22 outside the hole pattern HPcd is covered, and a hole pattern HPce is formed with the re-exposed air gap AGb as the hole part.

[0069] The hole pattern HPce has substantially the same pattern as the above-described hole pattern HPcc having the spacer pattern 43p on its sidewalls. That is, the hole pattern HPce has a configuration in which the hard mask pattern 23p part of the above-described hole pattern HPcc is replaced by the spacer pattern 44p.

[0070] Further, due to the overall etch-back of the spacer layer 44, the recess RCb formed at the center point of the equilateral triangle formed by the minimum distance connecting the center points of the hole pattern HPcd penetrates the spacer layer 44 and the hole pattern HPda is formed so as to be mixed with the hole pattern HPce. More specifically, the hole pattern HPda is arranged at the center point of the equilateral triangle formed by the minimum distance connecting the center points of the hole pattern HPce having a hexagonal close-packed arrangement.

[0071] In this way, an additional hole pattern HPda can be formed self-aligned with respect to the hole pattern HPce.

[0072] Also, thereby, the hole pattern HPea including the hole pattern HPce and the hole pattern HPda has a hexagonal close-packed arrangement with a pitch that is 1 / 3 times that of the hole pattern HPaa that the original resist mask pattern 30p had. In other words, in the hole pattern HPea, a pitch equivalent to that of the finally obtained hole pattern HPfn is obtained.

[0073] As shown in FIGS. 9(Aa) and (Ab), the hole pattern HPea composed of the spacer patterns 43p and 44p is transferred to the hard mask layer 22 using, for example, RIE or the like. Thereby, a hard mask pattern 22p having the hole pattern HPeb is formed. Also, the underlying hard mask layer 21 is exposed from the bottom surface of the hole pattern HPeb.

[0074] The hard mask pattern 22p having the hole pattern HPeb corresponds to the hard mask pattern having the further additional hole pattern shown in FIG. 2(c) above.

[0075] Note that, in consideration of ease of understanding of the drawings, near the ends of the four sides of the top views of FIGS. 8(Ba), 8(Ca), and 9(Aa), the illustration of the spacer layer 44 and the configuration formed by the spacer layer 44 is partially omitted.

[0076] As described above, the repetition process of the processes after FIGS. 4(Aa)(Ab) ends. That is, the processes from FIGS. 7(Aa)(Ab) to 9(Aa)(Ab) are repetitions of the processes from FIGS. 4(Aa)(Ab) to 6(Aa)(Ab).

[0077] The process shown in FIGS. 9(Ba)(Bb) is performed as necessary to finely adjust the size of the finally obtained hole pattern PCfn.

[0078] As shown in FIGS. 9(Ba)(Bb), wet etching or the like is performed on the hard mask pattern 22p in which the hole pattern HPeb is formed to expand the diameter of the hole pattern HPeb. Thereby, a hole pattern HPec with the size of the hole pattern HPeb finely adjusted is obtained. However, if a hole pattern having a desired size is obtained at the end of the process in FIGS. 9(Aa)(Ab), the process shown in FIGS. 9(Ba)(Bb) can be skipped.

[0079] Note that in FIG. 9(Ba), the hole pattern PCec of the hard mask pattern 22p covered with the spacer patterns 43p, 44p is shown by a broken line.

[0080] Also, between the process of forming the hole pattern HPeb in the hard mask pattern 22p in FIGS. 9(Aa)(Ab) and the process of adjusting the size of the hole pattern HPeb in FIGS. 9(Ba)(Bb), the lowermost hard mask layer 21 functions as a protective layer for protecting the layer to be processed 10.

[0081] As shown in FIGS. 10(Aa)(Ab), the spacer patterns 41p, 42p are removed by wet etching or the like. Thereby, the hard mask pattern 22p having the hole pattern HPec is exposed.

[0082] As shown in FIGS. 10(Ba) and (Bb), the hole pattern HPec formed in the hard mask pattern 22p is transferred to the hard mask layer 21 using, for example, RIE or the like. Thereby, a hard mask pattern 21p having a hole pattern HPed is formed. Also, from the bottom surface of the hole pattern HPed, the underlying layer to be processed 10 is exposed.

[0083] Thereafter, as described below, the layer to be processed 10 is processed using the hard mask patterns 22p and 21p as masks. The hole patterns HPec and HPed respectively possessed by these hard mask patterns 22p and 21p correspond to the finally obtained hole pattern HPfn.

[0084] As shown in FIGS. 10(Ba) and (Bb), by processing the layer to be processed 10 exposed from the hole pattern HPfn of the hard mask patterns 22p and 21p using, for example, RIE or the like, a plurality of holes HL having a pitch that is 1 / 3 times that of the hole pattern HPaa originally possessed by the resist mask pattern 30p and taking a hexagonal close-packed arrangement are formed in the layer to be processed 10.

[0085] Thereafter, pillar-type capacitors PC are respectively formed in the plurality of holes HL.

[0086] As described above, the semiconductor device 1 of the embodiment is manufactured.

[0087] (Summary) For example, when forming a memory cell in a semiconductor device such as a DRAM, in order to increase the bit density per unit area, a pillar-type capacitor having a hexagonal close-packed arrangement may be formed. In forming a pillar-type capacitor with a hexagonal close-packed arrangement, for example, a hole pattern with a hexagonal close-packed arrangement is formed by lithography. In recent years, there has been an increasing demand for obtaining a hole pattern having a pitch exceeding the limit resolution of lithography.

[0088] In order to form a hole pattern with a pitch exceeding the limit resolution of lithography, cross-point processing is used, in which two types of L / S patterns are formed obliquely to each other and a hole pattern is formed at the intersection, or the sidewall process used for forming a fine L / S pattern is applied to a circular pattern.

[0089] In cross-point processing, after forming the first type of L / S pattern by lithography and transferring it to the hard mask layer, the second type of L / S pattern formed by lithography is transferred to the newly formed hard mask layer on this hard mask layer so as to be obliquely intersecting the first type of L / S pattern at an angle of 60°. As a result, the overlapping portion of the patterns transferred to the two hard mask layers respectively becomes, for example, a rhombic hole pattern in a hexagonal close-packed arrangement.

[0090] In the above cross-point processing, a sidewall process is also combined to devise a way to obtain an even finer hole pattern. That is, after forming a spacer layer on the sidewall of a resist mask pattern with an L / S ratio of 1:3, sidewall processing (SADP: Self-Aligned Double Patterning) for removing the resist mask pattern is used. As a result, an L / S pattern with a pitch that is half that of the pattern obtained by lithography is obtained. Also, double sidewall processing (SAQP: Self-Aligned Quadrope Patterning) in which sidewall processing is repeated twice may be performed to use an L / S pattern with a quarter pitch.

[0091] However, for example, in order to obtain a hexagonal closest-packed hole pattern by cross-point processing using two-sidewall processing twice, in order to process two hard mask layers, a high-precision lithography process using an expensive apparatus is required twice. Further, since the two-sidewall processing is performed twice, the sidewall processing is effectively performed four times, leading to an increase in the number of film deposition times and etching steps. Furthermore, in each individual process, high specifications are also required for dimensional variation accuracy and overlay accuracy. As a result, the man-hours, TAT (Turn Around Time), and the number of apparatuses used for forming the hole pattern increase, making it difficult to suppress the manufacturing cost.

[0092] Also, for example, in Patent Document 1 described above, the sidewall process is applied to a circular pattern. That is, in the circular sidewall processing of Patent Document 1, a hexagonal closest-packed hole pattern is formed by lithography, a sacrificial layer is embedded in the hole pattern, and a pillar pattern is formed by the sacrificial layer. After covering this pillar pattern with a spacer layer and then etching back, a new hole pattern is formed at the center point of an equilateral triangle composed of the minimum distance between the pillar patterns. Thereafter, by removing the sacrificial layer of the pillar pattern, a hexagonal closest-packed hole pattern having a pitch 1 / √3 times that of the hole pattern obtained by the initial lithography is obtained.

[0093] However, in the circular sidewall processing of Patent Document 1, in addition to the formation of the spacer layer, the formation of a sacrificial layer for obtaining a pillar pattern that serves as the core material of the spacer layer is required. As a result, the man-hours, TAT, and the number of apparatuses used for forming the hole pattern increase, leading to an increase in the manufacturing cost.

[0094] According to the manufacturing method of the semiconductor device 1 of the embodiment, a spacer layer 42 covering the upper surface of the hard mask layer 23 outside the spacer pattern 41p is formed, and the spacer layer 42 overlapping with the region composed of the minimum distance connecting the center points of the spacer patterns 41p is removed to form a spacer pattern 42p having a hole pattern HPba, thereby forming a hole pattern HPca including the hole pattern HPae composed of the spacer pattern 41p and the hole pattern HPba composed of the spacer pattern 42p.

[0095] Thereby, a fine pattern exceeding the limit resolution of the lithography process can be formed.

[0096] According to the manufacturing method of the semiconductor device 1 of the embodiment, a spacer layer 44 covering the upper surface of the hard mask layer 22 outside the spacer pattern 43p is formed, and the spacer layer 44 overlapping with the region composed of the minimum distance connecting the center points of the spacer patterns 43p is removed to form a spacer pattern 44p having a hole pattern HPda, thereby forming a hole pattern HPea including the hole pattern HPce composed of the spacer pattern 43p and the hole pattern HPda composed of the spacer pattern 44p.

[0097] In this way, by repeating the pitch reduction process from FIGS. 4(Aa)(Ab) to FIGS. 6(Aa)(Ab) and the pitch reduction process from FIGS. 7(Aa)(Ab) to FIGS. 9(Aa)(Ab) a plurality of times, a finer pattern can be formed in one lithography process. Therefore, the number of lithography processes can be reduced, and dimensional variation accuracy and overlay accuracy can be easily ensured. Thus, the man-hours, TAT, and number of apparatuses used for forming the hole pattern can be reduced, and the manufacturing cost can be reduced.

[0098] According to the manufacturing method of the semiconductor device 1 of the embodiment, the hole pattern HPaa is designed to have a hexagonal close-packed arrangement in which each pattern is arranged at each vertex of a regular hexagon and at the center point of the regular hexagon when viewed from the stacking direction of the hard mask layers 21 to 25. The hole pattern HPba is formed at the center point of a substantially equilateral triangle region formed by the minimum distance connecting the center points of the spacer patterns 41p.

[0099] Thereby, a hole pattern HPca having a pitch that is 1 / √3 times that of the hole pattern HPaa initially formed by lithography can be obtained.

[0100] According to the manufacturing method of the semiconductor device 1 of the embodiment, the hole pattern HPea has a substantially hexagonal close-packed arrangement when viewed from the stacking direction of the hard mask layers 21 to 25. Thereby, a hole pattern HPea having a pitch that is 1 / √3 times that of the above-described hole pattern HPca and 1 / 3 times that of the initial hole pattern HPaa can be obtained. Also, by repeating the reduction process to a 1 / √3 times pitch twice, a hole pattern HPfn having a pitch that is finally 1 / 3 times that of the initial one can be obtained in one lithography process.

[0101] According to the manufacturing method of the semiconductor device 1 of the embodiment, a spacer layer 42 is formed to cover the upper surface of the hard mask layer 23 outside the spacer pattern 41p and to cover the upper surface of the spacer pattern 41p so that an air gap AGa is formed inside the cylinder of the spacer pattern 41p. Thereby, for example, unlike the circular sidewall processing of Patent Document 1 described above, the process of forming a pillar pattern using a sacrificial layer can be reduced.

[0102] Note that the pattern formation method of the above-described embodiment is applied to the formation of the pillar-type capacitor PC of the semiconductor device 1 configured as a DRAM. However, the pattern formation method of the above-described embodiment can also be appropriately applied when forming other configurations of the semiconductor device or each configuration of a semiconductor device other than a DRAM. Further, the pattern formation method of the above-described embodiment may be applied to the manufacture of a template used for imprint processing.

[0103] Also, in the above-described embodiment, the reduction process to a pitch of 1 / √3 times is repeated a plurality of times. However, even when the reduction process is performed once, the effects of the embodiment of forming a fine pattern that exceeds the limit resolution of the lithography process can be obtained.

[0104] Also, in the above-described embodiment, for example, in order to increase the density of the pillar-type capacitor PC as much as possible, the hole pattern is arranged in a hexagonal close-packed arrangement. However, the arrangement of the hole pattern is not limited to the hexagonal close-packed arrangement. As an example, it is also possible to arrange the hole pattern at each vertex of a square and at the center point of the square. Such an arrangement of the hole pattern will be referred to as a cubic close-packed arrangement following the face-centered cubic packing structure of the crystal structure.

[0105] When forming a hole pattern in a cubic close-packed arrangement, a new hole pattern is added to the center point of an equilateral triangle formed by the minimum distance connecting the center points of the hole patterns in a cubic close-packed arrangement formed by lithography, whereby a hole pattern with a pitch of 1 / √2 times that of the original hole pattern can be obtained. Further, if this is repeated twice, a hole pattern with a pitch of 1 / 2 times that of the original hole pattern can be finally obtained.

[0106] [Supplementary Note] Hereinafter, preferred embodiments of the present invention will be appended.

[0107] (Supplementary Note 1) According to one aspect of the present invention, above the layer to be processed, first and second hard mask layers are formed in the order of the second hard mask layer and the first hard mask layer from the side of the layer to be processed, above the first hard mask layer, a resist mask pattern having a first hole pattern formed using lithography is formed, the first hole pattern is transferred to the first hard mask layer to form a first hard mask pattern having a second hole pattern, By forming a first spacer layer on the sidewall of the second hole pattern and removing the first hard mask pattern, a cylindrical first spacer pattern disposed at the position of the second hole pattern is formed. By forming a second spacer layer covering the upper surface of the second hard mask layer outside the first spacer pattern and removing the second spacer layer overlapping with a first region composed of the minimum distance connecting the center points of the first spacer patterns to form a second spacer pattern having a third hole pattern, a fourth hole pattern including the second hole pattern composed of the first spacer patterns and the third hole pattern composed of the second spacer patterns is formed. Transfer the fourth hole pattern to the second hard mask layer to form a second hard mask pattern having a fifth hole pattern. By forming a third spacer layer on the sidewall of the fifth hole pattern and removing the second hard mask pattern, a cylindrical third spacer pattern disposed at the position of the fifth hole pattern is formed. By forming a fourth spacer layer covering the upper surface of the layer to be processed outside the third spacer pattern and removing the fourth spacer layer overlapping with a second region composed of the minimum distance connecting the center points of the third spacer patterns to form a fourth spacer pattern having a sixth hole pattern, a seventh hole pattern including the fifth hole pattern composed of the third spacer patterns and the sixth hole pattern composed of the fourth spacer patterns is formed. Transfer the seventh hole pattern to the layer to be processed. A method for manufacturing a semiconductor device is provided.

[0108] (Appendix 2) In the method for manufacturing a semiconductor device according to Appendix 1, The first hole pattern When viewed from the stacking direction of the first and second hard mask layers, each pattern is designed to be in a hexagonal close-packed arrangement in which each vertex of a regular hexagon and the center point of the regular hexagon are arranged.

[0109] (Appendix 3) In the method for manufacturing the semiconductor device of Appendix 2, the first region substantially has an equilateral triangle when viewed from the stacking direction, the third hole pattern is substantially formed at the center point of the first region.

[0110] (Appendix 4) In the method for manufacturing the semiconductor device of Appendix 2, the fourth hole pattern substantially has the hexagonal closest packing when viewed from the stacking direction.

[0111] (Appendix 5) In the method for manufacturing the semiconductor device of Appendix 4, the fourth hole pattern substantially has a pitch that is 1 / √3 times that of the first hole pattern.

[0112] (Appendix 6) In the method for manufacturing the semiconductor device of Appendix 4, the second region substantially has an equilateral triangle when viewed from the stacking direction, the sixth hole pattern is substantially formed at the center point of the second region.

[0113] (Appendix 7) In the method for manufacturing the semiconductor device of Appendix 2, the seventh hole pattern substantially has the hexagonal closest packing when viewed from the stacking direction.

[0114] (Appendix 8) In the method for manufacturing the semiconductor device of Appendix 7, the seventh hole pattern substantially has a pitch that is 1 / 3 times that of the first hole pattern.

[0115] (Appendix 9) In the method for manufacturing the semiconductor device of Appendix 1, the second spacer layer is formed to cover the upper surface of the second hard mask layer and to cover the upper surface of the first spacer pattern so that a first air gap is formed inside the cylinder of the first spacer pattern. the second spacer pattern is formed by removing the second spacer layer overlapping the first region and the second spacer layer covering the upper surface of the first spacer pattern.

[0116] (Appendix 10) In the method for manufacturing the semiconductor device of Appendix 1, the fourth spacer layer is formed to cover the upper surface of the layer to be processed and to cover the upper surface of the third spacer pattern so that a second air gap is formed inside the cylinder of the third spacer pattern. the fourth spacer pattern is formed by removing the fourth spacer layer overlapping the second region and the fourth spacer layer covering the upper surface of the third spacer pattern.

[0117] (Appendix 11) According to another aspect of the present invention, a first hard mask layer is formed above the layer to be processed, a resist mask pattern having a first hole pattern formed using lithography is formed above the first hard mask layer, the first hole pattern is transferred to the first hard mask layer to form a first hard mask pattern having a second hole pattern, a first spacer layer is formed on the sidewall of the second hole pattern to remove the first hard mask pattern, thereby forming a cylindrical first spacer pattern disposed at the position of the second hole pattern. Cover the upper surface of the layer to be processed outside the first spacer pattern, and form a second spacer layer that covers the upper surface of the first spacer pattern so that a first air gap is formed inside the cylinder of the first spacer pattern. Remove the second spacer layer that covers the upper surface of the first spacer pattern to open the second hole pattern again, and remove the second spacer layer that overlaps with the first region composed of the minimum distance connecting the center points of the first spacer patterns to form a second spacer pattern having a third hole pattern, thereby forming a fourth hole pattern including the second hole pattern that opens in the first spacer pattern and the third hole pattern that opens in the second spacer pattern. Transfer the fourth hole pattern to the layer to be processed. A method for manufacturing a semiconductor device is provided.

[0118] (Appendix 12) In the method for manufacturing a semiconductor device according to Appendix 11, The first hole pattern When viewed from the stacking direction of the layer to be processed and the first hard mask layer, each pattern is designed to be arranged in a hexagonal closest packing where each vertex of a regular hexagon and the center point of the regular hexagon are arranged.

[0119] (Appendix 13) In the method for manufacturing a semiconductor device according to Appendix 12, The first region Substantially has a regular triangle when viewed from the stacking direction. The third hole pattern Substantially, it is formed at the center point of the first region.

[0120] (Appendix 14) In the method for manufacturing a semiconductor device according to Appendix 12, The fourth hole pattern When viewed from the stacking direction, substantially has the hexagonal closest packing.

[0121] (Supplementary Note 15) In the method for manufacturing a semiconductor device according to Supplementary Note 14, the fourth hole pattern, substantially has a pitch that is 1 / √3 times that of the first hole pattern.

[0122] (Supplementary Note 16) In the method for manufacturing a semiconductor device according to Supplementary Note 11, when forming the first hard mask layer, a second hard mask layer is interposed between the layer to be processed, and the first hard mask layer is formed. When transferring the fourth hole pattern to the layer to be processed, the fourth hole pattern is transferred to the second hard mask layer to form a second hard mask pattern having a fifth hole pattern. A third spacer layer is formed on the sidewalls of the fifth hole pattern to remove the second hard mask pattern, thereby forming a cylindrical third spacer pattern disposed at the position of the fifth hole pattern. A fourth spacer layer is formed to cover the upper surface of the layer to be processed outside the third spacer pattern and to cover the upper surface of the third spacer pattern so that a second air gap is formed inside the cylinder of the third spacer pattern. The fourth spacer layer covering the upper surface of the third spacer pattern is removed to open the fifth hole pattern again, and the fourth spacer layer overlapping with a second region composed of the minimum distance connecting the center points of the third spacer patterns is removed to form a fourth spacer pattern having a sixth hole pattern, thereby forming a seventh hole pattern including the fifth hole pattern opening in the third spacer pattern and the sixth hole pattern opening in the fourth spacer pattern. By transferring the seventh hole pattern to the layer to be processed, the fourth hole pattern is transferred to the layer to be processed via the second hard mask layer.

[0123] (Supplementary Note 17) In the method of manufacturing the semiconductor device of Supplementary Note 16, the first hole pattern is designed such that, when viewed from the stacking direction of the first and second hard mask layers, each pattern is arranged in a hexagonal close-packed arrangement in which each vertex of a regular hexagon and the center point of the regular hexagon are provided with a pattern, the fourth hole pattern is substantially in the hexagonal close-packed arrangement when viewed from the stacking direction.

[0124] (Supplementary Note 18) In the method of manufacturing the semiconductor device of Supplementary Note 17, the seventh hole pattern is substantially in the hexagonal close-packed arrangement when viewed from the stacking direction.

[0125] (Supplementary Note 19) In the method of manufacturing the semiconductor device of Supplementary Note 18, the seventh hole pattern is substantially has a pitch that is 1 / 3 times that of the first hole pattern.

[0126] (Supplementary Note 20) According to still another aspect of the present invention, the first and second hard mask layers are formed in this order, from the lower layer side, of the second hard mask layer and the first hard mask layer, a resist mask pattern having a first hole pattern formed using lithography is formed above the first hard mask layer, the first hole pattern is transferred to the first hard mask layer to form a first hard mask pattern having a second hole pattern, a first spacer layer is formed on sidewalls of the second hole pattern to remove the first hard mask pattern, thereby forming a cylindrical first spacer pattern disposed at the position of the second hole pattern, Form a second spacer layer covering the upper surface of the second hard mask layer outside the first spacer pattern, and remove the second spacer layer overlapping a first region composed of the minimum distance connecting the center points of the first spacer patterns to form a second spacer pattern having a third hole pattern, thereby forming a fourth hole pattern including the second hole pattern composed of the first spacer pattern and the third hole pattern composed of the second spacer pattern, Transfer the fourth hole pattern to the second hard mask layer to form a second hard mask pattern having a fifth hole pattern, Form a third spacer layer on the sidewalls of the fifth hole pattern and remove the second hard mask pattern, thereby forming a cylindrical third spacer pattern disposed at the position of the fifth hole pattern, Form a fourth spacer layer covering the outside of the third spacer pattern, and remove the fourth spacer layer overlapping a second region composed of the minimum distance connecting the center points of the third spacer patterns to form a fourth spacer pattern having a sixth hole pattern, thereby forming a seventh hole pattern including the fifth hole pattern composed of the third spacer pattern and the sixth hole pattern composed of the fourth spacer pattern, A patterning method is provided.

[0127] (Appendix 21) According to still another aspect of the present invention, Form a first hard mask layer above the layer to be processed, Above the first hard mask layer, form a resist mask pattern having a first hole pattern formed using lithography, Transfer the first hole pattern to the first hard mask layer to form a first hard mask pattern having a second hole pattern, A first spacer layer is formed on the sidewall of the second hole pattern to remove the first hard mask pattern, thereby forming a cylindrical first spacer pattern disposed at the position of the second hole pattern. A second spacer layer is formed to cover the upper surface of the layer to be processed outside the first spacer pattern, and the second spacer layer overlapping a first region composed of the minimum distance connecting the center points of the first spacer patterns is removed to form a second spacer pattern having a third hole pattern, thereby forming a fourth hole pattern including the second hole pattern composed of the first spacer patterns and the third hole pattern composed of the second spacer patterns. The fourth hole pattern is transferred to the layer to be processed. A method for manufacturing a semiconductor device is provided.

[0128] Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0129] 1... Semiconductor device, 10... Layer to be processed, 21 - 24... Hard mask layers, 21p - 24p... Hard mask patterns, 30... Resist mask layer, 41 - 44... Spacer layers, 41p - 44p... Spacer patterns, AA... Active region, BL... Bit line, HPaa - HPae, HPba, HPca - HPce, HPda, HPea - HPec, HPfn... Hole patterns, PC... Pillar-type capacitor, WL... Word line.

Claims

1. Above the layer to be processed, first and second hard mask layers are formed in the order of the second hard mask layer and the first hard mask layer from the side of the layer to be processed, Above the first hard mask layer, a resist mask pattern having a first hole pattern formed using lithography is formed, The first hole pattern is transferred to the first hard mask layer to form a first hard mask pattern having a second hole pattern, By forming a first spacer layer on the sidewall of the second hole pattern and removing the first hard mask pattern, a cylindrical first spacer pattern disposed at the position of the second hole pattern is formed, A second spacer layer covering the upper surface of the second hard mask layer outside the first spacer pattern is formed, and the second spacer layer overlapping a first region composed of the minimum distance connecting the center points of the first spacer patterns is removed to form a second spacer pattern having a third hole pattern, thereby forming a fourth hole pattern including the second hole pattern composed of the first spacer patterns and the third hole pattern composed of the second spacer patterns, The fourth hole pattern is transferred to the second hard mask layer to form a second hard mask pattern having a fifth hole pattern, By forming a third spacer layer on the sidewall of the fifth hole pattern and removing the second hard mask pattern, a cylindrical third spacer pattern disposed at the position of the fifth hole pattern is formed, A fourth spacer layer covering the upper surface of the layer to be processed outside the third spacer pattern is formed, and the fourth spacer layer overlapping a second region composed of the minimum distance connecting the center points of the third spacer patterns is removed to form a fourth spacer pattern having a sixth hole pattern, thereby forming a seventh hole pattern including the fifth hole pattern composed of the third spacer patterns and the sixth hole pattern composed of the fourth spacer patterns, Transferring the seventh hole pattern to the layer to be processed, A method for manufacturing a semiconductor device.

2. The first hole pattern is, Designed to be in a hexagonal close-packed arrangement in which each pattern is arranged at each vertex of a regular hexagon and at the center point of the regular hexagon when viewed from the stacking direction of the first and second hard mask layers. The method of manufacturing a semiconductor device according to claim 1.

3. The first region Substantially has a regular triangle when viewed from the stacking direction, The third hole pattern Substantially formed at the center point of the first region, The method of manufacturing a semiconductor device according to claim 2.

4. The seventh hole pattern Substantially has the hexagonal close-packed arrangement when viewed from the stacking direction, The method of manufacturing a semiconductor device according to claim 2.

5. The seventh hole pattern Substantially has a pitch that is 1 / 3 times that of the first hole pattern, The method of manufacturing a semiconductor device according to claim 4.

6. Form a first hard mask layer above the layer to be processed, Form a resist mask pattern having a first hole pattern formed using lithography above the first hard mask layer, Transfer the first hole pattern to the first hard mask layer to form a first hard mask pattern having a second hole pattern, Form a first spacer layer on the sidewall of the second hole pattern and remove the first hard mask pattern to form a cylindrical first spacer pattern disposed at the position of the second hole pattern, Form a second spacer layer that covers the upper surface of the layer to be processed outside the first spacer pattern and covers the upper surface of the first spacer pattern so that a first air gap is formed inside the cylinder of the first spacer pattern, Remove the second spacer layer covering the upper surface of the first spacer pattern to reopen the second hole pattern, and remove the second spacer layer overlapping the first region composed of the minimum distance connecting the center points of the first spacer patterns to form a second spacer pattern having a third hole pattern, thereby forming a fourth hole pattern including the second hole pattern opening in the first spacer pattern and the third hole pattern opening in the second spacer pattern, Transfer the fourth hole pattern to the layer to be processed, The method of manufacturing a semiconductor device.

7. Form the first and second hard mask layers in this order from the lower layer side as the second hard mask layer and the first hard mask layer, Form a resist mask pattern having a first hole pattern formed using lithography above the first hard mask layer, Transfer the first hole pattern to the first hard mask layer to form a first hard mask pattern having a second hole pattern, Form a first spacer layer on the sidewalls of the second hole pattern and remove the first hard mask pattern, thereby forming a cylindrical first spacer pattern disposed at the position of the second hole pattern, Form a second spacer layer covering the upper surface of the second hard mask layer outside the first spacer pattern, and remove the second spacer layer overlapping a first region composed of the minimum distance connecting the center points of the first spacer patterns to form a second spacer pattern having a third hole pattern, thereby forming a fourth hole pattern including the second hole pattern composed of the first spacer patterns and the third hole pattern composed of the second spacer patterns, Transfer the fourth hole pattern to the second hard mask layer to form a second hard mask pattern having a fifth hole pattern, Form a third spacer layer on the sidewalls of the fifth hole pattern and remove the second hard mask pattern, thereby forming a cylindrical third spacer pattern disposed at the position of the fifth hole pattern, Form a fourth spacer layer covering the outside of the third spacer pattern, and remove the fourth spacer layer overlapping a second region composed of the minimum distance connecting the center points of the third spacer patterns to form a fourth spacer pattern having a sixth hole pattern, thereby forming a seventh hole pattern including the fifth hole pattern composed of the third spacer patterns and the sixth hole pattern composed of the fourth spacer patterns, Pattern formation method.

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