Evaluation device and evaluation method of complexity of circuit

Abstract

To provide a technique for evaluating complexity of model data of a circuit.SOLUTION: An evaluation device 10 includes: a model analysis part 110 for analyzing model data 100 of a circuit; a complexity evaluation part 120 for evaluating each complexity of one or more blocks 101 constituting the model data 100 obtained by analysis, and each complexity of routes of one or more signals 102; and a complexity calculation part 130 for calculating the complexity of the circuit, on the basis of each of the complexity of the one or more blocks 101, and each of the complexity of the routes of the one or more signals 102. The model data 100 includes each positional information of the one or more blocks 101 associated with the order of data processing. The model analysis part 110 analyzes the positional information, thereby determines presence / absence of the blocks 101 executed at the same time, and determines each type of the one or more signals 102.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a technique for evaluating the complexity of a circuit, and more specifically, to a technique for evaluating the complexity of circuit model data.

Background Art

[0002] In the development of circuits such as LSI (Large Scale Integration), the complexity of the circuit is used as an index to determine the design quality of the circuit. The complexity of the circuit indicates the difficulty of circuit design. When the complexity of the circuit is extremely high, it becomes difficult to design and ensure the quality of the circuit.

[0003] By quantitatively measuring the complexity of the circuit, the designer can appropriately predict the design quality of the circuit. Also, at the time of newly developing a circuit, the designer can easily estimate the development man-hours by grasping in advance the complexity of the circuit to be designed. Furthermore, the development supervisor can ensure the efficiency and quality of circuit development by having a capable designer take charge of developing a circuit with high complexity.

[0004] Regarding a technique for evaluating the complexity of a circuit, for example, Japanese Unexamined Patent Application Publication No. 2016-081287 (Patent Document 1) discloses a method for evaluating the complexity of a hardware circuit using a computer, wherein a processor included in the computer extracts a substitution type of a combinational circuit description sentence from a source file in which a circuit is designed in a hardware description language stored in a memory included in the computer, and for each of the extracted substitution types, the computer acquires a first complexity of an element related to the combinational circuit description sentence, and based on the relevance, the computer performs a process of acquiring a second complexity for each of the substitution types using the first complexity ([see Summary]).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] According to the technology disclosed in Patent Document 1, it is impossible to evaluate the complexity of model data of a circuit designed by model-based development (MBD) that has been increasingly popular in recent years. Therefore, a technology for evaluating the complexity of circuit model data is required.

[0007] The present disclosure has been made in view of the above background, and an object in one aspect is to provide a technology for evaluating the complexity of circuit model data.

MEANS FOR SOLVING THE PROBLEMS

[0008] According to an embodiment, an evaluation apparatus for a circuit is provided. The evaluation apparatus includes a model analysis unit that analyzes model data of a circuit, a complexity evaluation unit that evaluates the complexity of each of one or more blocks constituting the model data obtained by the analysis and the complexity of each of one or more signals, and a complexity calculation unit that calculates the complexity of the circuit based on the complexity of each of the one or more blocks and the complexity of each of the one or more signals. The model data includes position information of each of one or more blocks associated with the order of data processing. The analysis unit determines the presence or absence of blocks to be executed simultaneously and determines the type of each of the one or more signals by analyzing the position information.

EFFECTS OF THE INVENTION

[0009] According to an embodiment, the complexity of circuit model data can be evaluated.

[0010] The above and other objects, features, aspects and advantages of the present disclosure will become apparent from the following detailed description of the present disclosure understood in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments of the technical idea according to the present disclosure will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed descriptions thereof will not be repeated. Further, each embodiment, each modification example, each software configuration, each hardware configuration, each function, and each process, etc. may be selectively combined as appropriate.

[0013] <A. Configuration Example of Evaluation Device> First, an overview of the circuit evaluation device 10 (see FIG. 1) according to the present embodiment will be described while comparing it with a conventional circuit complexity evaluation device (hereinafter referred to as "conventional device").

[0014] As described above, in recent years, model-based development has become widespread. In the process of circuit design, model data is converted into source code of a hardware description language (HDL (Hardware Description Language)).

[0015] The conventional device can evaluate the complexity of the HDL source code, but cannot evaluate the complexity of the model data. Therefore, when using the conventional device, a circuit developer needs to once convert the model data into source code and input the source code into the conventional device.

[0016] However, when the model data is converted into source code, depending on the specifications of the conversion tool, source code including redundant descriptions or optimized descriptions may be generated. Therefore, the complexity output by the conventional device is affected by the conversion tool. As a result, the complexity output by the conventional device may deviate from the original complexity of the circuit.

[0017] In contrast, the evaluation device 10 directly calculates the complexity from the model data by analyzing each block and each signal included in the model data. Each block included in the model data indicates each function provided by the circuit. Also, each signal included in the model data indicates the input / output of the signal or the signal line. Hereinafter, with reference to FIGS. 1 to 4, the configuration and the outline of the operation of the evaluation device 10 will be described.

[0018] (a. Function of the evaluation device) FIG. 1 is a diagram showing an example of the configuration of the evaluation device 10 for a circuit. The evaluation device 10 evaluates the complexity of the model data 100 of the circuit. The evaluation device 10 includes a model analysis unit 110, a complexity evaluation unit 120, and a complexity calculation unit 130.

[0019] The model data 100 is designed by a model-based development tool such as Simulink (registered trademark). The model data 100 is composed of a block 101 and a signal 102. The block 101 indicates an input, an output, and any other function. The signal 102 indicates the direction of the input / output of the signal or the wiring.

[0020] The model analysis unit 110 analyzes the model data 100. The complexity of the model data 100 is determined by the functions of the respective blocks 101 constituting the model data 100, the number of conditional branches, the number of feedback loops (also referred to as feedback signals), and the like. Therefore, the model analysis unit 110 analyzes the types of the blocks 101 included in the model data 100, the number of conditional branches, the number of feedback loops, and the like. That is, the model analysis unit 110 analyzes the model data 100 based on the functions provided by the circuit indicated by the model data 100. The model analysis unit 110 outputs the analysis result to the complexity evaluation unit 120.

[0021] The complexity evaluation unit 120 individually evaluates the analysis results. More specifically, the complexity evaluation unit 120 individually calculates or evaluates the function complexity, the conditional branch complexity, and the feedback complexity of each block 101. The complexity evaluation unit 120 outputs the function complexity, the conditional branch complexity, and the feedback complexity to the complexity calculation unit 130.

[0022] Based on each complexity obtained from the complexity evaluation unit 120, the complexity calculation unit 130 calculates the complexity of the model data 100 as a complexity calculation result value. In a certain aspect, the complexity calculation unit 130 may sum up each complexity. That is, the complexity calculation unit 130 may sum up the function complexity, the conditional branch complexity, and the feedback complexity.

[0023] In other aspects, the complexity calculation unit 130 may multiply each complexity by an individual coefficient. In this case, the complexity calculation unit 130 multiplies the function complexity by a first coefficient. The complexity calculation unit 130 multiplies the conditional branch complexity by a second coefficient. The complexity calculation unit 130 multiplies the feedback complexity by a third coefficient. Then, the complexity calculation unit 130 sums up the function complexity, the conditional branch complexity, and the feedback complexity after multiplying by the coefficients. The influences of the type of block 101, the number of conditional branches, and the presence or absence of a feedback signal on the complexity of the model data 100 may vary greatly. By multiplying each complexity by an individual coefficient, the complexity calculation unit 130 can calculate the complexity of the entire circuit (model data 100) more accurately.

[0024] FIG. 2 is a diagram showing an example of the configuration of the model analysis unit 110. With reference to FIG. 2, the functions of the model analysis unit 110 will be described in more detail. The model analysis unit 110 includes a block type analysis unit 200, a block position analysis unit 210, and a signal connection analysis unit 220.

[0025] The block type analysis unit 200 analyzes the types or functions of all the blocks 101 included in the input model data 100. As an example, each block 101 has various functions such as input, output, comparison operation, conditional branch, and filter. In other aspects, each block 101 may have a plurality of functions. The block type analysis unit 200 outputs information on the types or functions of all the blocks 101 as an analysis result to the complexity evaluation unit 120. The block type analysis unit 200 may generate a block type table 800 (see FIG. 8) as an analysis result.

[0026] The block position analysis unit 210 analyzes the positions of all the blocks 101 included in the model data 100. The block position analysis unit 210 outputs the position information of each block 101 as an analysis result to the signal connection analysis unit 220.

[0027] Each block 101 is arranged in time series according to the order of execution. Each block 101 in the model data 100 can be arranged based on various formats. As an example, the model data 100 is defined as information including coordinate information as shown in FIG. 5. In this case, the position of each block 101 is represented by coordinates in a two-dimensional space composed of a first axis and a second axis. The first axis indicates the time series of data processing in the circuit (model data 100). The second axis indicates the direction in which one or more blocks are arranged in parallel. In this case, the block position analysis unit 210 analyzes the position of each block 101 based on the coordinates. Also, the block position analysis unit 210 can analyze the execution order of each block 101 and the presence or absence of blocks 101 to be executed simultaneously, etc., based on the position (also called coordinates) of each block 101 in the first axis direction.

[0028] As another example, as shown in FIG. 19, the model data 100 is defined as information indicating only the execution order of each block 101 without using coordinates. In this case, the block position analysis unit 210 analyzes the position of each block 101 based on the execution time (also called delay) of each block. Also, the block position analysis unit 210 can analyze the execution order of each block 101 and the presence or absence of blocks 101 to be executed simultaneously, etc., based on the delay of each block 101.

[0029] In a certain aspect, the block position analysis unit 210 may adjust the coordinates of some of the blocks 101 in the model data 100 based on the result of the analysis. More specifically, the block position analysis unit 210 may align or arrange the positions (coordinates) of the blocks 101 to be executed simultaneously in the first axis direction.

[0030] The signal connection analysis unit 220 analyzes the connection relationships of all the signals 102 based on the position information of each block 101. The signal connection analysis unit 220 outputs information on the connection relationships of all the signals 102 to the complexity evaluation unit 120 as an analysis result. In a certain aspect, the signal connection analysis unit 220 may output the position information of each block 101 and information regarding the blocks 101 that are executed simultaneously to the complexity evaluation unit 120. The signal connection analysis unit 220 may generate a signal connection table 1300 (see FIG. 13) as an analysis result.

[0031] In a certain aspect, the connection relationship of each signal 102 may include information on the source block 101 and the destination block 101 of each signal 102. In another aspect, the connection relationship of each signal 102 may include information on the start coordinates and end coordinates of each signal 102. Further, in another aspect, the connection relationship of each signal 102 may include information on the source block 101, the destination block 101, the start coordinates, and the end coordinates of each signal 102.

[0032] In a certain aspect, the processing of the block type analysis unit 200 may be executed in parallel with the processing of the block position analysis unit 210 and the signal connection analysis unit 220. In another aspect, the processing of the block type analysis unit 200, the processing of the block position analysis unit 210, and the processing of the signal connection analysis unit 220 may be executed in order.

[0033] FIG. 3 is a diagram showing an example of the configuration of the complexity evaluation unit 120. With reference to FIG. 3, the functions of the complexity evaluation unit 120 will be described in more detail. The complexity evaluation unit 120 includes a conditional branch evaluation unit 300, a feedback loop evaluation unit 310, and a function evaluation unit 320.

[0034] In a certain aspect, the processing of the conditional branch evaluation unit 300, the processing of the feedback loop evaluation unit 310, and the processing of the function evaluation unit 320 may be executed in parallel. In another aspect, the processing of the conditional branch evaluation unit 300, the processing of the feedback loop evaluation unit 310, and the processing of the function evaluation unit 320 may be executed with the order swapped.

[0035] Based on the analysis result obtained from the model analysis unit 110, the conditional branch evaluation unit 300 calculates the conditional branch complexity. More specifically, the conditional branch evaluation unit 300 extracts the blocks 101 with one or more conditional branches from the block type table 800. Next, for each block 101 with one or more conditional branches, the conditional branch evaluation unit 300 extracts the number of input signals, the number of output signals, and the number of conditions. Then, based on the number of input signals, the number of output signals, and the number of conditions, the conditional branch evaluation unit 300 calculates the complexity of each block 101 with one or more conditional branches. Furthermore, the conditional branch evaluation unit 300 sums up the complexities of each block 101 with one or more conditional branches. The conditional branch evaluation unit 300 outputs the conditional branch complexity, which is the sum value, to the feedback loop evaluation unit 310.

[0036] Based on the analysis result obtained from the model analysis unit 110, the feedback loop evaluation unit 310 calculates the feedback complexity. More specifically, the feedback loop evaluation unit 310 acquires the start coordinates and end coordinates of each signal 102 from the signal connection table 1300. Then, based on the start coordinates and end coordinates of each signal 102, the feedback loop evaluation unit 310 calculates the number of feedback loops. As an example, the feedback loop evaluation unit 310 may determine a signal 102 whose start coordinate value is greater than or equal to the end coordinate value as a feedback loop. Here, the start coordinates and end coordinates mean the coordinates in the first axis direction indicating the time series of data processing. As another example, assume that the model analysis unit 110 defines groups of simultaneous blocks in order regardless of the positions of each block 101. In this case, the feedback loop evaluation unit 310 determines a signal that goes back in the order of the groups as a feedback loop. Next, the feedback loop evaluation unit 310 calculates the feedback complexity. In one aspect, the feedback complexity may be the number of feedback loops. In other aspects, the feedback complexity may be a value obtained by multiplying the number of feedback loops by a predetermined complexity per feedback loop. The feedback loop evaluation unit 310 outputs the conditional branch complexity and the feedback complexity to the function evaluation unit 320.

[0037] The function evaluation unit 320 calculates the function complexity of all the blocks 101 included in the block type table 800. More specifically, the function evaluation unit 320 determines which block in the function complexity table 1700 (see FIG. 17) each block 101 corresponds to. Then, the function evaluation unit 320 obtains the complexity corresponding to each block 101 from the function complexity table 1700. The function complexity table 1700 is pre-stored in the storage 403 (see FIG. 4) in the evaluation apparatus 10. Next, the function evaluation unit 320 sums up the complexities of each block 101 to calculate the function complexity. Further, the function evaluation unit 320 outputs the conditional branch complexity, the feedback complexity, and the function complexity to the complexity calculation unit 130.

[0038] The complexity calculation unit 130 calculates and outputs the complexity of the entire circuit (model data 100) based on the conditional branch complexity, the feedback complexity, and the function complexity. In one aspect, the complexity calculation unit 130 may sum up the conditional branch complexity, the feedback complexity, and the function complexity. The sum value of the respective complexities becomes the complexity of the entire circuit (model data 100). In another aspect, the complexity calculation unit 130 may multiply each of the conditional branch complexity, the feedback complexity, and the function complexity by an individual coefficient. In this case, the complexity calculation unit 130 sums up the complexities after the multiplication by the coefficient. The sum value of the complexities after the multiplication by the coefficient becomes the complexity of the entire circuit (model data 100).

[0039] As described with reference to FIGS. 1 to 3, the evaluation apparatus 10 according to the present embodiment includes a model analysis unit 110 that analyzes circuit model data 100, and one or more blocks 101 that constitute the model data 100 obtained by the analysis. A complexity evaluation unit 120 that evaluates the complexity of each of them, and a complexity calculation unit 130 that calculates the complexity of the circuit based on the complexity of each of the one or more blocks 101 and the complexity of each of the one or more signals 102. The model data 100 includes position information of each of one or more blocks 101 associated with the order of data processing. The model analysis unit 110 analyzes the position information to determine the presence or absence of simultaneously executed blocks 101 and determines the type of each of the one or more signals 102. The type of the signal 102 here includes a signal 102 of a feedback loop or other signals 102.

[0040] Evaluating (calculating) the complexity of each of the one or more blocks 101 includes summing the complexities of all the blocks 101 that make up the model data 100. Also, evaluating (calculating) the complexity of each of the one or more blocks 101 includes evaluating (calculating) the conditional branch complexity. Further, evaluating the complexity of each of the one or more signals 102 includes evaluating the feedback complexity based on the number of feedback loops. The complexity of the circuit is calculated based on the function complexity, the conditional branch complexity, and the feedback complexity.

[0041] (b. Hardware of the evaluation apparatus) FIG. 4 is a diagram showing an example of the hardware configuration of the evaluation apparatus 10. In one aspect, each functional block shown in FIGS. 1 to 3 can be realized by executing a program on the hardware shown in FIG. 4. In another aspect, each functional block shown in FIGS. 1 to 3 may be realized by dedicated hardware. In this case, the evaluation apparatus 10 includes hardware corresponding to each function in addition to the configuration shown in FIG. 4.

[0042] The evaluation device 10 includes a processor 401, a RAM (Random Access Memory) 402, a storage 403, an external device IF (Interface) 404, an input unit 405, an output unit 406, a communication unit 407, and a bus 408. The processor 401, the RAM 402, the storage 403, the external device IF 404, the input unit 405, the output unit 406, and the communication unit 407 are configured to be communicable with each other via the bus 408.

[0043] The processor 401 can execute a program for realizing various functions of the evaluation device 10. The processor 401 is constituted by, for example, at least one integrated circuit. According to an embodiment, the integrated circuit may include at least one CPU (Central Processing Unit), at least one GPU (Graphics Processing Unit), at least one FPGA (Field Programmable Gate Array), at least one ASIC (Application Specific Integrated Circuit), at least one AI (Artificial Intelligence) chip, or a combination thereof, etc.

[0044] The RAM 402 functions as a workspace for the processor 401. For this purpose, the RAM 402 stores a program executed by the processor 401 and data referred to by the processor 401. In a certain aspect, the RAM 402 can be realized by a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), etc.

[0045] Storage 403 is a non-volatile memory that stores programs executed by processor 401 and data referenced by processor 401. Processor 401 executes the program read from storage 403 into RAM 402 and references the data read from storage 403 into RAM 402. In certain aspects, storage 403 can be implemented by a hard disk drive (HDD), solid state drive (SSD), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, or the like.

[0046] External device IF 404 can be connected to any external device such as a printer, scanner, and external HDD. In certain aspects, external device IF 404 can be implemented by a universal serial bus (USB) terminal or the like.

[0047] Input unit 405 can be connected to any input device such as a keyboard, mouse, touch pad, or game pad. In certain aspects, input unit 405 can be implemented by a USB terminal, PS / 2 terminal, Bluetooth (registered trademark) module, or the like. In other aspects, input unit 405 may be configured integrally with any input device.

[0048] Output unit 406 can be connected to any output device such as a cathode ray tube display, liquid crystal display, or organic electro-luminescence (EL) display. In certain aspects, output unit 406 can be implemented by a USB terminal, D-sub terminal, digital visual interface (DVI) terminal, high-definition multimedia interface (HDMI) (registered trademark) terminal, display port terminal, or the like. In other aspects, output unit 406 may be configured integrally with any output device.

[0049] The communication unit 407 is connected to other devices via a wired network or a wireless network. In one aspect, the communication unit 407 can be implemented by a wired LAN (Local Area Network) port, a Wi-Fi (registered trademark) (Wireless Fidelity) module, etc. In other aspects, the communication unit 407 can transmit and receive data using communication protocols such as TCP / IP (Transmission Control Protocol / Internet Protocol) and UDP (User Datagram Protocol).

[0050] (c. Terms) In this specification, the "device" may be any information processing device such as a personal computer, a workstation, a server device, a tablet, or a smartphone. Also, the device may be a combination of these. According to one embodiment, the device may be connected to input / output devices such as a display and a keyboard and used by a user. According to other embodiments, the device may provide various functions to a user as a service or a web application via a network. In this case, the user can use the functions of the device via a browser or client software installed on their own terminal. In one aspect, the evaluation device 10 can be implemented by one device. In other aspects, the evaluation device 10 can be implemented by multiple devices. In this case, the evaluation device 10 may be expressed as an evaluation system. Furthermore, the evaluation device 10 can be implemented as a virtual machine constructed on a cloud environment.

[0051] In this specification, the "circuit" includes integrated circuits (ICs (Integrated Circuits)), LSIs, FPGAs, CPUs, GPUs, ASICs, AI chips, and any other circuits. Also, the circuit may include circuits manufactured from materials other than semiconductors including newly developed materials in the future.

[0052] In this specification, "model data" is data of a circuit designed by a model-based development method. The model data can be expressed as data in an arbitrary format for each development tool.

[0053] In this specification, "complexity" indicates the complexity of a circuit (model data 100) calculated from various aspects. As an example, the complexity may be an index of the complexity of the circuit function, the complexity of the signal flow, or a combination thereof. Also, as another example, the complexity may be an index for estimating the difficulty of circuit design, the difficulty of circuit manufacturing, or the man-hours required for circuit design or manufacturing.

[0054] <B. Configuration Example of Model Data of Circuit to be Evaluated> FIG. 5 is a diagram showing an example of model data 100 of a circuit to be evaluated. The model data 100 includes inputs 500, 502, 504, 506, 508, 510 as block 101. Also, the model data 100 includes a magnitude comparison 512, an addition 514, a subtraction 516, and a conditional branch 518 as block 101. Further, the model data 100 includes a FIR (Finite Impulse Response) filter 520, an FFT (Fast Fourier Transform) 522, a peak detection 524, a hold 526, and an output 528 as block 101. Similarly, the model data 100 includes signals A, B, C, D, E, F, G, H, I, J, K, L, M, N, O as signal 102. Among these signals 102, signal O is a feedback loop.

[0055] Each block 101 has information on the number of input signals, the number of output signals, the type (function), and the position coordinates. Each signal 102 has information on the blocks 101 to which it is connected. Also, each signal 102 may have information on the start coordinates and the end coordinates. This information possessed by each block 101 and each signal 102 can be included in the model data 100 as metadata or the like. Each block 101 may include a storage circuit such as a flip-flop that holds the state of the signal.

[0056] Each block 101 is arranged according to the order of data processing. In the example of FIG. 5, as indicated by the arrows of each signal 102, each signal 102 passes through each block 101 from left to right. That is, from left to right, each block 101 processes data. Also, each signal is input from the left of each block 101 and output from the right of each block 101. As an example, in the order of input 500, magnitude comparison 512, conditional branch 518, FIR filter 520, FFT 522, peak detection 524, hold 526, output 528, each block 101 functions.

[0057] When the developer defines functions that operate in series, one or more blocks 101 are arranged in the left - right direction. Also, the developer can define functions that operate in parallel by arranging a plurality of blocks 101 in the up - down direction. That is, the left - right direction of the model data 100 corresponds to the first axis indicating the time series of data processing in the circuit. Also, the up - down direction of the model data 100 corresponds to the second axis indicating the direction in which one or more blocks are arranged in parallel. In a certain aspect, the up - down direction of the model data 100 may correspond to the first axis indicating the time series of data processing in the circuit. Also, the left - right direction of the model data 100 may correspond to the second axis indicating the direction in which one or more blocks are arranged in parallel.

[0058] The developer can define the simultaneously executed blocks 101 by arranging a plurality of blocks vertically (in the second axis direction) with their coordinates in the left - right direction (first axis direction) aligned. Hereinafter, the simultaneously executed blocks 101 are referred to as simultaneous blocks. For example, when block A and block B are executed simultaneously, blocks A and B are simultaneous blocks. When defining simultaneous blocks, a certain degree of deviation in the coordinates of the blocks 101 arranged in parallel in the left - right direction (first axis direction) is allowed. As an example, the block position analysis unit 210 can determine whether the deviation in the coordinates of the blocks 101 arranged in parallel in the left - right direction (first axis direction) is less than or equal to a predetermined threshold. Based on the fact that the deviation is less than or equal to the predetermined threshold, the block position analysis unit 210 can determine that the blocks 101 arranged in parallel are simultaneous blocks. In a certain aspect, the simultaneously executed blocks 101 may be configured to be definable as a group in any way regardless of coordinates.

[0059] FIG. 6 is a diagram showing an example of the expression of the configuration of the conditional branch 518. The conditional branch 518 is a function (block) that is one of the major factors that complicate the circuit. With reference to FIG. 6, the information included in the conditional branch 518 will be described.

[0060] The description 600 represents the conditional branch 518 of the model data 100 as source code. According to the description 600, the conditional branch 518 has three branches. Also, as can be seen from FIG. 5, the conditional branch 518 has three inputs and one output. The number of input signals, the number of output signals, and the number of conditions are factors contributing to the complexity of the conditional branch 518.

[0061] In a certain aspect, the conditional branch evaluation unit 300 may convert the conditional branch 518 into the description 600. In this case, the conditional branch evaluation unit 300 extracts the number of input signals, the number of output signals, and the number of conditions of the conditional branch 518 from the description 600. In other aspects, the conditional branch evaluation unit 300 may directly analyze the conditional branch 518 without going through the description 600 and extract the number of input signals, the number of output signals, and the number of conditions of the conditional branch 518.

[0062] FIG. 7 is a diagram showing another example of the expression of the configuration of the conditional branch 518. The conditional branch 518 can also be expressed as a combination of a plurality of blocks other than the source code. The block data 700 expresses the conditional branch 518 of the model data 100 using a combination of blocks.

[0063] In a certain situation, the conditional branch evaluation unit 300 may convert the conditional branch 518 into the block data 700. In this case, the conditional branch evaluation unit 300 extracts the number of input signals, the number of output signals, and the number of conditions of the conditional branch 518 from the block data 700. In another situation, the conditional branch evaluation unit 300 may directly analyze the conditional branch 518 without passing through the block data 700 and extract the number of input signals, the number of output signals, and the number of conditions of the conditional branch 518.

[0064] <C. Analysis Procedure of Model Data> Next, with reference to FIGS. 8 to 14, the analysis procedure of the model data 100 will be described in detail. The analysis procedure of the model data 100 includes three aspects: analysis of the function of the blocks, analysis of the position of the blocks, and analysis of the connection relationship of the signals.

[0065] (a. Analysis of the Function of the Blocks) FIG. 8 is a diagram showing an example of the block type table 800. The block type analysis unit 200 generates the block type table 800 by analyzing the model data 100. The block type analysis unit 200 stores the generated block type table 800 in the storage 403. In a certain situation, the block type table 800 may be expressed as a table of a relational database, or may be expressed in any other data format such as JSON (JavaScript (registered trademark) Object Notation).

[0066] The block type table 800 includes, as items, an item 801 of No (Number), an item 802 of the block, an item 803 of the number of input signals, an item 804 of the number of output signals, an item 805 of the function, and an item 806 of the number of conditions.

[0067] The item 801 of No contains an identifier for uniquely identifying each record. The item 802 of block contains the name or identifier of each block 101. The item 803 of the number of input signals contains the number of input signals of each block 101. The item 804 of the number of output signals contains the number of output signals of each block 101. The item 805 of function contains the function or type of each block 101. The item 806 of the number of conditions contains the number of conditions of each block 101. Blocks 101 other than the conditional branch do not contain conditions. Therefore, 0, blank, NULL, etc. can be stored in the item 806 of the number of conditions in the block 101 other than the conditional branch.

[0068] As an example, the record of No7 is the record of the magnitude comparison 512 in FIG. 5. According to FIG. 5, signals A and O are input to the magnitude comparison 512. Also, signal G is output from the magnitude comparison 512. Also, the magnitude comparison 512 is a function of comparing numerical values. Therefore, referring to the record of No7, the item 803 of the number of input signals is "2", and the item 804 of the number of output signals is "1". Also, the item 805 of the function of the record of No7 is "numerical comparison".

[0069] FIG. 9 is a diagram showing an example of a block classification procedure. The block type analysis unit 200 generates the block type table 800 by executing the process shown in FIG. 9. In a certain aspect, the processor 401 may read a program for performing the process of FIG. 9 from the storage 403 into the RAM 402 and execute the program. In another aspect, part or all of the process may also be realized as a combination of circuit elements configured to execute the process.

[0070] Similarly, the processor 401 may read a program for performing each process shown after FIG. 10 from the storage 403 into the RAM 402 and execute the program. Also, part or all of each process shown after FIG. 10 may also be realized as a combination of circuit elements configured to execute the process.

[0071] In step S910, the block type analysis unit 200 extracts each block 101 from the model data 100. In step S920, the block type analysis unit 200 extracts the number of input signals and output signals of each block 101.

[0072] In step S930, the block type analysis unit 200 determines the type of each extracted block 101. In a certain aspect, the evaluation device 10 may store a block 101 type list in the storage 403 in advance. In this case, the evaluation device 10 can determine the type of each block 101 by comparing each block 101 with the type list. In another aspect, the model data 100 may include the type information of each block 101 as metadata or the like. In this case, the evaluation device 10 can determine the type of each block 101 by acquiring the metadata or the like.

[0073] In step S940, the block type analysis unit 200 determines whether the type of the extracted block 101 is a conditional branch. If the block type analysis unit 200 determines that the type of the extracted block 101 is a conditional branch (YES in step S940), the control is transferred to step S950. Otherwise (NO in step S940), the block type analysis unit 200 transfers the control to step S960. Taking FIG. 5 as an example, since the conditional branch 518 is extracted from the model data 100, the block type analysis unit 200 transfers the control to step S950.

[0074] In step S950, the block type analysis unit 200 extracts the number of conditions of the conditional branch. Taking FIG. 5 as an example, the block type analysis unit 200 extracts the number of conditions "3" from the conditional branch 518.

[0075] In step S960, the block type analysis unit 200 creates a block type table 800. More specifically, the block type analysis unit 200 generates each record of the block type table 800 based on the information obtained by the processing in steps S910 to S950.

[0076] (b. Analysis of Block Positions) FIG. 10 is a diagram showing a part of the model data 100. With reference to FIG. 10, a procedure for the block position analysis unit 210 to determine the presence or absence of simultaneous blocks will be described. The model data 100 is defined in a coordinate space composed of the x-axis 1010 and the y-axis 1020. The x-axis 1010 corresponds to the first axis indicating the time series of data processing in the circuit. The y-axis 1020 corresponds to the second axis indicating the direction in which one or more blocks 101 are arranged in parallel.

[0077] The block position analysis unit 210 acquires the coordinates of the lower left end of all the blocks 101 (hereinafter referred to as "start coordinates"). As an example, the start coordinates of the magnitude comparison 512 are (10, 20). The start coordinates of the addition 514 are (10.5, 15). The start coordinates of the subtraction 516 are (9, 10).

[0078] Also, the block position analysis unit 210 acquires the width of all the blocks 101 in the x-axis 1010 direction. As an example, the widths of the magnitude comparison 512, the addition 514, and the subtraction 516 are all "2". Alternatively, the block position analysis unit 210 may acquire the coordinates of the lower right end of all the blocks 101 (hereinafter referred to as "end coordinates"). The end coordinates of the magnitude comparison 512 are shifted by 2 from the start coordinates, so they are (12, 20). Similarly, the end coordinates of the addition 514 are (12.5, 15). The end coordinates of the subtraction 516 are (11, 10).

[0079] Next, the block position analysis unit 210 determines the presence or absence of the block 101 in the positive direction of the x-axis 1010 from x = 0. The block position analysis unit 210 sets the first detected block 101 as a reference block. In the example of FIG. 10, the block position analysis unit 210 selects the subtraction 516 as the reference block.

[0080] Next, the block position analysis unit 210 determines whether there is a block whose at least a part of the section from the start coordinate to the end coordinate (hereinafter simply referred to as "section") overlaps with the section of the reference block. If at least a part of the section of a certain block 101 overlaps with the section of the reference block, the block position analysis unit 210 determines that a certain block 101 is executed simultaneously with the reference block.

[0081] As an example, the section of the reference block (subtraction 516) is (9 to 11) in the x-axis 1010 direction. The section of the addition 514 is (10.5 to 12.5) in the x-axis 1010 direction. The section of the addition 514 overlaps with the section of the reference block (subtraction 516) in the range of (10.5 to 11) in the x-axis 1010 direction. Therefore, the block position analysis unit 210 determines that the addition 514 and the subtraction 516 are simultaneous blocks.

[0082] Similarly, the section of the magnitude comparison 512 is (10 to 12) in the x-axis 1010 direction. The section of the magnitude comparison 512 overlaps with the section of the reference block (subtraction 516) in the range of (10 to 11) in the x-axis 1010 direction. Therefore, the block position analysis unit 210 determines that the magnitude comparison 512 and the subtraction 516 are simultaneous blocks.

[0083] In a certain situation, the block position analysis unit 210 may determine the presence or absence of simultaneous blocks using another method. For example, the block position analysis unit 210 calculates the deviation of the coordinates in the x-axis 1010 direction between the reference block and other blocks. Then, the block position analysis unit 210 may determine that the reference block and other blocks are simultaneous blocks based on the fact that the deviation is within a predetermined threshold. The coordinates of each block 101 to be compared may be the coordinates of any part of each block 101. As an example, the coordinates of each block 101 to be compared may be the coordinates of the right end, the center, or the left end of each block 101.

[0084] As described above, in the example of FIG. 10, the block position analysis unit 210 determines that the magnitude comparison 512, addition 514, and subtraction 516 are simultaneous blocks. The block position analysis unit 210 may manage the simultaneous blocks as a group.

[0085] After the above processing, the block position analysis unit 210 searches for a block 101 that is not determined to be a simultaneous block and for which the determination process of simultaneous blocks has not been performed in the positive direction of the x-axis 1010 from x = 0. The block position analysis unit 210 selects the block 101 that meets the condition as the next reference block. Then, the above determination process for the presence or absence of simultaneous blocks is repeatedly executed.

[0086] In the example of FIG. 10, since the magnitude comparison 512 and addition 514 are determined to be simultaneous blocks, they cannot be reference blocks. Therefore, the block position analysis unit 210 selects the conditional branch 518 as the next reference block. However, there is no block whose section from the start coordinate to the end coordinate overlaps with the conditional branch 518. Therefore, the block position analysis unit 210 determines that the conditional branch 518 is not a simultaneous block. Similarly, the block position analysis unit 210 selects the block next to the conditional branch 518 as the reference block.

[0087] In a certain situation, the block position analysis unit 210 may determine the presence or absence of simultaneous blocks using another method. As an example, assume that the subtraction 516, addition 514, and magnitude comparison 512 are arranged with a slight shift like a staircase. In this case, the block position analysis unit 210 may determine the subtraction 516, addition 514, and magnitude comparison 512 as simultaneous blocks. The block position analysis unit 210 calculates the coordinate deviation in the x-axis 1010 direction between the reference block and other blocks. Then, based on the deviation being within a predetermined threshold, the block position analysis unit 210 determines that the reference block and other blocks are simultaneous blocks. Next, the block position analysis unit 210 searches for a block 101 that has not been determined to be a simultaneous block in the positive direction of the x-axis 1010 from x = 0. The block position analysis unit 210 selects the block 101 that meets this condition as the next reference block. Then, the block position analysis unit 210 repeatedly executes the above-described determination process for the presence or absence of simultaneous blocks. Finally, the block position analysis unit 210 determines a group of blocks that have been continuously determined to be simultaneous blocks as one simultaneous block.

[0088] As a special example, assume that any of a plurality of blocks arranged in series is in a position where it can be determined to be a simultaneous block with respect to the reference block. In this case, the block position analysis unit 210 selects the block that is executed earliest among the plurality of blocks as a simultaneous block with respect to the reference block. Taking FIG. 10 as an example, assume that the model data 100 includes additions 514A and 514B arranged in series instead of the addition 514. And assume that both the addition 514A and the addition 514B are in positions where they can be determined to be simultaneous blocks with respect to the subtraction 516. In this case, the block position analysis unit 210 determines that the leftmost addition 514A is a simultaneous block with the subtraction 516.

[0089] FIG. 11 is a diagram showing a part of the model data 100 after the alignment process. The block position analysis unit 210 may align a plurality of blocks 101 determined to be simultaneous blocks. As an example, the block position analysis unit 210 aligns other blocks 101 according to the reference block. In the example of FIG. 11, the start coordinates of the magnitude comparison 512 and the addition 514 are aligned with the start coordinates of the subtraction 516 which is the reference block. In this way, the block position analysis unit 210 can improve the readability of the model data 100 by modifying the model data 100.

[0090] FIG. 12 is a diagram showing an example of the analysis procedure of the block positions. The block position analysis unit 210 is included in the model analysis unit 110. Therefore, the block position analysis unit 210 which is the execution subject of each of the following steps may be read as the model analysis unit 110. In step S1205, the block position analysis unit 210 extracts the coordinates of each block from the model data 100. In step S1210, the block position analysis unit 210 starts from the coordinate x = 0. In step S1215, the block position analysis unit 210 determines the presence or absence of the block 101 in the positive direction of the x-axis 1010.

[0091] In step S1220, based on the determination that there is a block 101 in the positive direction of the x-axis 1010 (YES in step S1220), the block position analysis unit 210 transfers the control to step S1225. Otherwise (NO in step S1220), the block position analysis unit 210 transfers the control to step S1260. In step S1225, the block position analysis unit 210 sets the detected block 101 as the reference block.

[0092] In step S1230, the block position analysis unit 210 determines whether there is another block between the start coordinates of the reference block and the width of the reference block. That is, the block position analysis unit 210 determines whether there is a block whose at least a part of the section from the start coordinates to the end coordinates overlaps with the reference block. When the block position analysis unit 210 determines that there is another block between the start coordinates of the reference block and the width of the reference block (YES in step S1230), the control proceeds to step S1235. Otherwise (NO in step S1230), the block position analysis unit 210 moves the control to step S1245.

[0093] In step S1235, the block position analysis unit 210 determines the reference block and other blocks as simultaneous blocks. There may be two or more other blocks. In step S1240, the block position analysis unit 210 sets the next block as the reference block. The next block is the block 101 that has not been determined to be a simultaneous block and for which the determination process of simultaneous blocks has not been performed.

[0094] In step S1245, the block position analysis unit 210 acquires the y coordinates of all the blocks 101 determined as simultaneous blocks with respect to the reference block. In step S1250, the block position analysis unit 210 determines that only the one with the smallest x coordinate among the simultaneous blocks with the same y coordinate is a simultaneous block. Also, the block position analysis unit 210 excludes the other blocks 101 from the simultaneous blocks. The processes of steps S1245 and S1250 correspond to the processes described by taking addition 514A and addition 514B as examples with reference to FIG. 10.

[0095] In step S1255, the block position analysis unit 210 aligns the x coordinates of all the blocks 101 determined as simultaneous blocks with the x coordinate of the reference block. The process of this step corresponds to the process described with reference to FIG. 11.

[0096] In step S1260, the block position analysis unit 210 determines whether or not the determination process for simultaneous blocks has been executed for the block 101 having the maximum x coordinate. If the block position analysis unit 210 determines that the determination process for simultaneous blocks has been executed for the block 101 having the maximum x coordinate (YES in step S1260), the determination process for simultaneous blocks ends. Otherwise (NO in step S1260), the block position analysis unit 210 transfers control to step S1215.

[0097] As described with reference to FIGS. 10 to 12, the model analysis unit 110 can determine the presence or absence of simultaneously executed blocks by analyzing the position information of each block 101. The position information is the arrangement coordinates of each of one or more blocks. In a certain aspect, the position information may be an interval from the start coordinate to the end coordinate of each of one or more blocks. In another aspect, the position information may be the start coordinate and width of each of one or more blocks.

[0098] Also, the arrangement coordinates are coordinates in a two-dimensional space composed of a first axis (x-axis 1010) and a second axis (y-axis 1020). The first axis indicates the time series of data processing in the circuit. The second axis indicates the direction in which one or more blocks 101 are arranged in parallel. Determining the presence or absence of simultaneously executed blocks 101 includes determining the presence or absence of simultaneously executed blocks 101 based on whether or not the difference in coordinates of each of one or more blocks 101 in the direction of the first axis is less than or equal to a predetermined threshold value. In a certain aspect, determining the presence or absence of simultaneously executed blocks 101 may include determining the presence or absence of blocks 101 in which at least a part of the interval from the start coordinate to the end coordinate overlaps with respect to a reference block.

[0099] Also, assume that one or more blocks 101 constituting the model data 100 include a first block, a second block, and a third block. Also, assume that the second block and the third block have the same coordinates in the direction of the second axis (y-axis 1020). Further, assume that the first block and the second and third blocks have different coordinates in the direction of the second axis (y-axis 1020), and that the difference in coordinates of the first block and the second and third blocks in the direction of the first axis (x-axis 1010) is equal to or less than a predetermined threshold value. In this case, the model analysis unit 110 may determine that the block among the second block and the third block with the earlier execution order is the block 101 to be executed simultaneously with the first block.

[0100] Furthermore, based on determining that there are blocks 101 to be executed simultaneously, the model analysis unit 110 may align the coordinates of the blocks 101 to be executed simultaneously in the direction of the first axis (x-axis 1010). More specifically, the model analysis unit 110 may align the x-coordinate values at the start coordinates of each of the blocks 101 to be executed simultaneously.

[0101] (c. Analysis of signal connection relationships) FIG. 13 is a diagram showing an example of a signal connection table 1300. The signal connection analysis unit 220 generates the signal connection table 1300 by analyzing the model data 100. In a certain aspect, the signal connection analysis unit 220 may generate the signal connection table 1300 by analyzing the model data 100 after the process shown in FIG. 11 is executed. The signal connection table 1300 stores the generated signal connection table 1300 in the storage 403. In a certain aspect, the signal connection table 1300 may be represented as a table of a relational database, or may be represented in any other arbitrary data format such as JSON.

[0102] The signal connection table 1300 includes, as items, an item 1301 of No, an item 1302 of signal, an item 1303 of start coordinate, and an item 1304 of end coordinate. The item 1301 of No includes an identifier for uniquely identifying each record. The item 1302 of signal includes the name or identifier of each signal 102. The item 1303 of start coordinate includes the value of the start coordinate of each signal 102. The value of the start coordinate is the value of the x coordinate of the start position of each signal 102. The item 1304 of end coordinate includes the value of the end coordinate of each signal 102. The value of the end coordinate is the value of the x coordinate of the end position of each signal 102.

[0103] FIG. 14 is a diagram showing an example of a procedure for analyzing the connection relationship of signals. The signal connection analysis unit 220 generates the signal connection table 1300 by executing the process shown in FIG. 14.

[0104] In step S1410, the signal connection analysis unit 220 extracts the signals 102 from the model data 100. In the example of FIG. 5, the signal connection analysis unit 220 extracts signals A, B, C, D, E, F, G, H, I, J, K, L, M, N, O.

[0105] In step S1420, the signal connection analysis unit 220 extracts the coordinates of the output source block of each signal 102 as the start coordinate. As an example, the start coordinate of signal A is the coordinate of the input 500 which is the output source block. More specifically, the start coordinate of signal A is the x coordinate of the end coordinate of the input 500.

[0106] In step S1430, the signal connection analysis unit 220 extracts the coordinates of the input destination block of each signal 102 as the end coordinate. As an example, the end coordinate of signal A is the coordinate of the magnitude comparison 512 which is the input destination block. More specifically, the end coordinate of signal A is the x coordinate of the start coordinate of the magnitude comparison 512.

[0107] In step S1440, the signal connection analysis unit 220 creates the signal connection table 1300 based on the information obtained in the processes from step S1410 to S1430.

[0108] <D. Evaluation Procedure for Complexity of Model Data> Next, with reference to FIGS. 15 to 18, the evaluation procedure for the complexity of the model data 100 will be described in detail. The evaluation procedure for the complexity of the model data 100 includes the evaluation of the conditional branch complexity, the evaluation of the feedback complexity, and the evaluation of the complexity for each function of the block 101.

[0109] (a. Evaluation of Conditional Branch Complexity) FIG. 15 is a diagram showing an example of the evaluation procedure for the conditional branch complexity. The conditional branch evaluation unit 300 is included in the complexity evaluation unit 120. Therefore, the conditional branch evaluation unit 300, which is the execution subject of each of the following steps, may be read as the complexity evaluation unit 120.

[0110] In step S1510, the conditional branch evaluation unit 300 extracts the block 101 from the block type table 800. In step S1520, the conditional branch evaluation unit 300 determines whether the type of the extracted block 101 is a conditional branch. If the conditional branch evaluation unit 300 determines that the type of the extracted block 101 is a conditional branch (YES in step S1520), the control is transferred to step S1530. Otherwise (NO in step S1520), the conditional branch evaluation unit 300 transfers the control to step S1550.

[0111] In step S1530, the conditional branch evaluation unit 300 calculates the complexity of the extracted block 101 from the number of input signals, the number of output signals, and the number of conditions. In step S1540, the conditional branch evaluation unit 300 adds the complexity calculated in step S1530 to the calculated conditional branch complexity.

[0112] In step S1550, the conditional branch evaluation unit 300 determines whether the determination processes for all the blocks 101 have been completed. If the conditional branch evaluation unit 300 determines that the determination processes for all the blocks 101 have been completed (YES in step S1550), it transfers the control to step S1560. Otherwise (NO in step S1550), the conditional branch evaluation unit 300 transfers the control to step S1510.

[0113] In step S1560, the conditional branch evaluation unit 300 completes the calculation of the conditional branch complexity. The conditional branch complexity here is the total value of the complexities of the one or more extracted conditional branch blocks.

[0114] As described above, when one or more blocks 101 are conditional branch blocks, the complexity evaluation unit 120 (conditional branch evaluation unit 300) calculates the complexity of the conditional branch blocks based on the number of input signals, the number of output signals, and the number of conditions of the conditional branch blocks.

[0115] (b. Evaluation of feedback complexity) FIG. 16 is a diagram showing an example of the evaluation procedure for feedback complexity. The feedback loop evaluation unit 310 is included in the complexity evaluation unit 120. Therefore, the feedback loop evaluation unit 310, which is the execution subject of each of the following steps, may be read as the complexity evaluation unit 120.

[0116] In step S1610, the feedback loop evaluation unit 310 extracts the signal 102 from the signal connection table 1300. In step S1620, the feedback loop evaluation unit 310 calculates the value of the end coordinate - start coordinate of the extracted signal 102.

[0117] In step S1630, the feedback loop evaluation unit 310 determines whether the value calculated in step S1620 is 0 or less. The start coordinate and end coordinate of signal 102 are coordinates indicating positions in the direction of the first axis (x-axis 1010) showing the time series of data processing. That the value is 0 or less means that the end coordinate of signal 102 exists earlier in time series than the start coordinate. That is, if the value is 0 or less, it can be said that the signal 102 is a feedback loop. If the feedback loop evaluation unit 310 determines that the value is 0 or less (YES in step S1630), it transfers control to step S1640. Otherwise (NO in step S1630), the feedback loop evaluation unit 310 transfers control to step S1660.

[0118] In step S1640, the feedback loop evaluation unit 310 calculates the feedback complexity of the detected feedback loop. In a certain aspect, the feedback complexity may be a fixed value. As an example, the feedback complexity may be the number of feedback loops. In other aspects, the feedback complexity may change based on values such as the end coordinate - start coordinate value of signal 102. In step S1650, the feedback loop evaluation unit 310 adds the feedback complexity calculated in step S1640 to the already calculated feedback complexity.

[0119] In step S1660, the feedback loop evaluation unit 310 determines whether the determination process for all signals 102 has been completed. If the feedback loop evaluation unit 310 determines that the determination process for all signals 102 has been completed (YES in step S1660), it transfers control to step S1670. Otherwise (NO in step S1660), the feedback loop evaluation unit 310 transfers control to step S1610. In step S1670, the feedback loop evaluation unit 310 completes the calculation of the feedback complexity. The feedback complexity here is the total value of one or more extracted feedback complexities.

[0120] As described above, the complexity evaluation unit 120 (feedback loop evaluation unit 310) calculates the complexity of each of the one or more signals 102 based on whether each of the one or more signals 102 represents a feedback loop. In a certain aspect, the complexity of each of the one or more signals 102 may be a fixed value. In other aspects, the complexity of each of the one or more signals 102 may vary based on the start coordinates and the end coordinates. Also, the complexity evaluation unit 120 (feedback loop evaluation unit 310) calculates the sum of the complexities of each of the one or more signals 102.

[0121] (c. Evaluation of Complexity for Each Function of Block) FIG. 17 is a diagram showing an example of a function complexity table 1700. The function complexity table 1700 is a table that defines the complexity for each function that makes up a circuit. The function complexity table 1700 is used to determine the complexity for each block 101. The function complexity table 1700 is pre-stored in the storage 403. In a certain aspect, the function complexity table 1700 may be represented as a table of a relational database or in any other arbitrary data format such as JSON.

[0122] The function complexity table 1700 includes, as items, an item 1701 of No, an item 1702 of function, and an item 1703 of complexity. The item 1701 of No includes an identifier for uniquely identifying each record. The item 1702 of function includes the name or identifier of each function that makes up the circuit. The functions of the circuit correspond to each block 101 in the model data 100. In a certain aspect, each block 101 may have two or more functions. The item 1703 of complexity includes each function complexity. Each function complexity can be calculated in advance by analyzing the man-hours required for the development of past products and the like.

[0123] FIG. 18 is a diagram showing an example of an evaluation procedure for the function complexity of a block. The function evaluation unit 320 is included in the complexity evaluation unit 120. Therefore, the function evaluation unit 320, which is the execution subject of each of the following steps, may be read as the complexity evaluation unit 120.

[0124] In step S1810, the function evaluation unit 320 extracts block 101 from the block type table 800. In step S1820, the function evaluation unit 320 obtains the function complexity corresponding to the extracted block 101 from the function complexity table 1700. Assume that the extracted block 101 has a plurality of functions. In this case, the complexity of the extracted block 101 is the total value of each function complexity. Therefore, the function evaluation unit 320 obtains a plurality of function complexities corresponding to the extracted block 101 from the function complexity table 1700. In step S1830, the function evaluation unit 320 adds the complexity obtained in step S1820 to the calculated function complexity.

[0125] In step S1840, the function evaluation unit 320 determines whether the determination process for all blocks 101 has been completed. If the function evaluation unit 320 determines that the determination process for all blocks 101 has been completed (YES in step S1840), the control is transferred to step S1850. Otherwise (NO in step S1840), the function evaluation unit 320 transfers the control to step S1810. In step S1850, the function evaluation unit 320 completes the calculation of the function complexity. The function complexity here is the total value of the complexities of all blocks 101 included in the model data 100.

[0126] As described above, the complexity evaluation unit 120 (function evaluation unit 320) calculates the complexity of each of the one or more blocks 101 based on the functions of each of the one or more blocks 101. When block 101 has a plurality of functions, the complexity of the block 101 is the total value of the plurality of function complexities. Further, the complexity evaluation unit 120 (function evaluation unit 320) sums up the complexities of each of the one or more blocks.

[0127] The complexity evaluation unit 120 outputs the conditional branch complexity, the feedback complexity, and the function complexity to the complexity calculation unit 130. The complexity calculation unit 130 calculates the overall complexity of the circuit (model data 100) based on the conditional branch complexity, the feedback complexity, and the function complexity.

[0128] In a certain situation, the complexity calculation unit 130 may sum up the conditional branch complexity, the feedback complexity, and the function complexity. In other situations, the complexity calculation unit 130 may multiply each complexity by an individual coefficient. In this case, the complexity calculation unit 130 multiplies the function complexity by a first coefficient. The complexity calculation unit 130 multiplies the conditional branch complexity by a second coefficient. The complexity calculation unit 130 multiplies the feedback complexity by a third coefficient. Then, the complexity calculation unit 130 sums up the function complexity, the conditional branch complexity, and the feedback complexity after multiplying by the coefficients.

[0129] <E. Application Example> FIG. 19 is a diagram showing an example of model data 1900 in another format. With reference to FIG. 19, a procedure for the evaluation device 10 to evaluate the complexity of the model data 1900 will be described.

[0130] Each block in the model data 1900, unlike the block 101 of the model data 100, does not have a value of the x - coordinate indicating the time series. Instead, the model data 1900 includes information on the execution time (also called delay) of each block. Taking FIG. 19 as an example, a plurality of circuits of processes 1 to 3 are arranged in parallel. Each circuit of processes 1 to 3 is composed of a plurality of blocks.

[0131] Process 1 includes, as blocks, input 1901, FIR filter 1902, FFT 1904, peak detection 1906, hold 1908, and output 1910. Also, Process 1 includes signals P, Q, R, S, T, U. Process 2 includes, as blocks, input 1912, input 1914, conditional branch 1916, x2 1918, threshold determination 1920, delay 1922, and output 1924. Also, Process 2 includes signals W, X, Y, Z, AA. Process 3 includes, as blocks, input 1926, +7 1928, delay 1930, and output 1932. Also, Process 3 includes signals BB, CC.

[0132] The model analysis unit 110 compares one or more blocks that make up each process. And when the total delay of the compared blocks is equal, the model analysis unit 110 determines that these blocks are simultaneous blocks. For example, the delay of the FIR filter 1902 in Process 1 is "20". Also, the total delay of the conditional branch 1916 and x2 1918 in Process 2 is "20". Therefore, the model analysis unit 110 sets the FIR filter 1902 in Process 1 and the conditional branch 1916 and x2 1918 in Process 2 as simultaneous blocks.

[0133] Also, assume that the developer wants to execute the output 1910 of Process 1, the output 1924 of Process 2, and the output 1932 of Process 3 simultaneously. In this case, the developer can add a setting to the model data 1900 such that the outputs 1910, 1924, and 1932 are executed simultaneously. When the model analysis unit 110 detects such a setting, it adds delay blocks to each process. In the example of FIG. 19, a delay 1922 is added to Process 2. Also, a delay 1930 is added to Process 3. As a result, the outputs 1910, 1924, and 1932 are executed simultaneously at the timing of a delay of "68" from the start of the process. In this way, the model analysis unit 110 has a function of inserting delay blocks into each process in order to execute a plurality of blocks simultaneously at a specific timing. It can also be said that the model analysis unit 110 makes a plurality of blocks into simultaneous blocks by the function of inserting delay blocks.

[0134] Next, the procedure for calculating the complexity of the model data 1900 will be described. The conditional branch evaluation unit 300 can calculate the conditional branch complexity of the model data 1900 using the procedure shown in FIG. 15. Also, the function evaluation unit 320 can calculate the function complexity of the model data 1900 using the procedure shown in FIG. 18. The feedback loop evaluation unit 310 can calculate the feedback complexity of the model data 1900 using the procedure shown in FIG. 16. However, when determining the presence or absence of a feedback loop in the model data 1900, the feedback loop evaluation unit 310 uses the delay of the block instead of the coordinates of the signal.

[0135] The determination process of the feedback loop will be described using the signal Q and the signal U of Process 1 as examples. The total execution time (delay) of the blocks at the start position of the signal Q is "20". The total execution time (delay) of the blocks at the end position of the signal Q is "20". From this, it can be seen that the signal Q is not input to the blocks executed before the generation of the signal Q. Therefore, the feedback loop evaluation unit 310 determines that the signal Q is not a feedback loop. The total execution time (delay) of the blocks at the start position of the signal U is "68". The total execution time (delay) of the blocks at the end position of the signal U is "52". From this, it can be seen that the signal U is input to the blocks executed before the generation of the signal U. Therefore, the feedback loop evaluation unit 310 determines that the signal U is a feedback loop. Thus, the feedback loop evaluation unit 310 can determine the presence or absence of a feedback loop based on the delay of each block. Alternatively, the feedback loop evaluation unit 310 can determine the presence or absence of a feedback loop based on the delay at the start position and the delay at the end position of each signal. The method for calculating the feedback complexity of the model data 1900 is the same as the method in FIG. 16.

[0136] The complexity calculation unit 130 calculates and outputs the complexity of the entire circuit based on the conditional branch complexity, feedback complexity, and function complexity calculated from the model data 1900. In one aspect, the complexity calculation unit 130 may sum the conditional branch complexity, feedback complexity, and function complexity. The sum value of each of the complexities becomes the complexity of the model data 1900 representing the entire circuit. In another aspect, the complexity calculation unit 130 may multiply each of the conditional branch complexity, feedback complexity, and function complexity by an individual coefficient. In this case, the complexity calculation unit 130 sums the complexities after the coefficients are multiplied. The sum value of the complexities after the coefficients are multiplied becomes the complexity of the model data 1900 representing the entire circuit.

[0137] As described above, when the model analysis unit 110 analyzes the model data 1900, the position information of each block and each signal is the delay from the start point of data processing to the point in time when the processing of one or more blocks has been executed.

[0138] Also, as described with reference to FIG. 19, depending on the format of the model data, determining the presence or absence of simultaneously executed blocks includes determining the presence or absence of simultaneously executed blocks based on whether the delays of each of one or more blocks or a combination of one or more blocks are the same.

[0139] Furthermore, when the model data 1900 includes a plurality of circuits that are executed in parallel and a point for aligning the execution timings of the plurality of circuits is specified, the model analysis unit 110 adds delay blocks (delays 1922, 1930, etc.) to each of the plurality of circuits in order to align the delays at the execution timings of the plurality of circuits.

[0140] <F. Summary> As described above, the evaluation device 10 according to the present embodiment can evaluate the complexity of a circuit by directly analyzing model data. By using the evaluation device 10, a developer does not need to convert the model data into an HDL source code. As a result, the circuit complexity output by the evaluation device 10 is not affected by a tool that converts the model data into source code. That is, the evaluation device 10 can more accurately evaluate (calculate) the complexity of the circuit to be designed.

[0141] The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included. Also, the disclosed content described in the embodiments and each modification example is intended to be implemented, alone or in combination, as much as possible.

Description of Reference Numerals

[0142] 10 Evaluation device, 100, 1900 Model data, 101 Block, 102 Signal, 110 Model analysis unit, 120 Complexity evaluation unit, 130 Complexity calculation unit, 200 Block type analysis unit, 210 Block position analysis unit, 220 Signal connection analysis unit, 300 Conditional branch evaluation unit, 310 Feedback loop evaluation unit, 320 Function evaluation unit, 401 Processor, 402 RAM, 403 Storage, 404 External device IF, 405 Input unit, 406 Output unit, 407 Communication unit, 408 Bus, 500, 502, 504, 506, 508, 510, 1901, 1912, 1914, 1926 Input, 512 Magnitude comparison, 514, 514A, 514B Addition, 516 Subtraction, 518, 1916 Conditional branch, 520, 1902 FIR filter, 522, 1904 FFT, 524, 1906 Peak detection, 526, 1908 Hold, 528, 1910, 1924, 1932 Output, 600 Description, 700 Block data, 800 Block type table, 801, 1301, 1701 No item, 802 Block item, 803 Number of input signals item, 804 Number of output signals item, 805 Function item, 806 Number of conditions item, 1302 Signal item, 1303 Start coordinate item, 1304 End coordinate item, 1702 Function item, 1703 Complexity item, 1010 x-axis, 1020 y-axis, 1300 Signal connection table, 1700 Function complexity table, 1918 x2, 1920 Value determination, 1922, 1930 Delay, 1928 +7.

Claims

1. A model analysis unit that analyzes model data of a circuit, a complexity evaluation unit that evaluates the complexity of each of one or more blocks constituting the model data obtained by the analysis and the complexity of each of one or more signals, a complexity calculation unit that calculates the complexity of the circuit based on the complexity of each of the one or more blocks and the complexity of each of the one or more signals, wherein the model data includes position information of each of the one or more blocks associated with the order of data processing, and the model analysis unit determines the presence or absence of blocks to be executed simultaneously and determines the type of each of the one or more signals by analyzing the position information. An evaluation device.

2. The evaluation device according to claim 1, wherein the position information is the arrangement coordinates of each of the one or more blocks.

3. The arrangement coordinates are coordinates in a two-dimensional space composed of a first axis and a second axis, the first axis indicates the time series of the data processing in the circuit, the second axis indicates the direction in which the one or more blocks are arranged in parallel, and determining the presence or absence of the blocks to be executed simultaneously includes determining the presence or absence of the blocks to be executed simultaneously based on whether a difference in coordinates of each of the one or more blocks in the direction of the first axis is equal to or less than a predetermined threshold. The evaluation device according to claim 2.

4. The one or more blocks include a first block, a second block, and a third block, the second block and the third block have the same coordinates in the direction of the second axis, the first block has different coordinates from the second block and the third block in the direction of the second axis, and when a difference in coordinates of the first block from the second block and the third block in the direction of the first axis is equal to or less than the predetermined threshold, the model analysis unit determines that the block with the earlier execution order among the second block and the third block is a block to be executed simultaneously with the first block. The evaluation device according to claim 3.

5. The evaluation device according to claim 3, wherein the model analysis unit aligns the coordinates of the blocks to be executed simultaneously in the direction of the first axis based on the determination that there are blocks to be executed simultaneously.

6. The evaluation device according to claim 1, wherein the position information of each of the one or more blocks is a delay from the start point of the data processing to the point in time when the processing of each of the one or more blocks is executed.

7. Determining the presence or absence of the concurrently executed blocks includes determining the presence or absence of the concurrently executed blocks based on whether the delays of each of the one or more blocks or a combination of the one or more blocks are the same, the evaluation device according to claim 6.

8. When the model data includes a plurality of circuits that are executed in parallel and a point for aligning the execution timings of the plurality of circuits is specified, the model analysis unit adds delay blocks to each of the plurality of circuits in order to align the delays at the execution timings of the plurality of circuits, the evaluation device according to claim 6.

9. The complexity evaluation unit calculates the complexity of each of the one or more blocks based on the function of each of the one or more blocks, the evaluation device according to any one of claims 1 to 8.

10. When the one or more blocks are conditional branch blocks, the complexity evaluation unit calculates the complexity of the conditional branch blocks based on the number of input signals, the number of output signals, and the number of conditions of the conditional branch blocks, the evaluation device according to any one of claims 1 to 8.

11. The complexity evaluation unit calculates the complexity of each of the one or more signals based on whether each of the one or more signals indicates a feedback loop, the evaluation device according to any one of claims 1 to 8.

12. Analyzing the model data of a circuit; Evaluating the complexity of each of the one or more blocks and each of the one or more signals obtained by the analysis; Calculating the complexity of the circuit based on the complexity of each of the one or more blocks and the complexity of each of the one or more signals, wherein the model data includes position information of each of the one or more blocks associated with the order of data processing, An evaluation method for a circuit, further including determining the presence or absence of concurrently executed blocks and determining the type of each of the one or more signals by analyzing the position information.

Images