Gate drive device

Abstract

To provide a gate drive device capable of reducing a switching loss of a sum of an opposite arm and an own arm.SOLUTION: Each of gate drive devices 60A and 60B comprises: a turn-on detection part 601 as an impedance adjustment part that individually controls an impedance of a gate discharge path of a vertical arm; a turn-off detection part 621; a logical circuit 602; and an impedance adjustment circuit Z. The logical circuit 602 sets the first impedance of the gate discharge path of an own arm in an on-switching period of an opposite arm is set to be higher than a second impedance of the gate discharge path of the own arm in the off switching period of the objective arm.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a gate driving device.

Background Art

[0002] The three-phase switching arms of a power conversion device each have switching elements for the upper and lower arms for each phase. By the way, when one of the switching elements of the upper and lower arms switches, a phenomenon may occur in which the switching element of the other arm self-turns on due to crosstalk. In that case, the upper and lower arms conduct simultaneously, and a short-circuit current flows between the semiconductor elements of the upper and lower arms. This short-circuit current may increase the loss of the switching element.

[0003] Therefore, in Patent Document 1, a method for suppressing self-turn-on has been proposed. In the technique described in Patent Document 1, an impedance adjustment circuit is provided in the gate driving device, and the impedance between the gate and the source during turn-on and turn-off is reduced by the impedance adjustment circuit. Thereby, self-turn-on and negative surges of the gate voltage of the switching element of the other arm when the switching element of one arm turns on and off are suppressed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, as described above, when reducing the impedance on the self-arm side at the time of the complementary-arm turn-on, the linking surge voltage (recovery surge) generated when the freewheeling diode of the self-arm switching element transitions from the conducting state to the blocking state increases. In order to suppress this increase in the recovery surge, it is necessary to reduce the switching speed, which leads to an increase in switching losses.

Means for Solving the Problem

[0006] The gate drive device according to an aspect of the present invention is a gate drive device that drives semiconductor elements of upper and lower arms, and includes an impedance adjustment unit that individually controls the impedance of the gate discharge paths of the upper and lower arms. The impedance adjustment unit sets the first impedance of the gate discharge path of the other arm during the on-switching period of one of the upper and lower arms to be higher than the second impedance of the gate discharge path of the other arm during the off-switching period of the one arm.

Advantages of the Invention

[0007] According to the present invention, at the time of complementary-arm turn-on, it is possible to improve the turn-on speed while suppressing the recovery surge of the self-arm, and to reduce the total switching losses on the complementary-arm and self-arm sides.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 8A

Figure 8B

Figure 8C

Figure 8D

Figure 8E

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Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and for the sake of clarity of explanation, appropriate omissions and simplifications are made. Also, in the following description, the same or similar elements and processes are denoted by the same reference numerals, and redundant explanations may be omitted. Note that the content described below is merely an example of the embodiments of the present invention, and the present invention is not limited to the following embodiments, and can be implemented in various other forms.

[0010] (First Embodiment) FIG. 1 is a diagram showing an example of a power conversion device. In the first embodiment, the power conversion device 20 mounted on the vehicle 1000 will be described as an example. The power conversion device 20 drives an electric motor 30 mounted on the vehicle 1000. The vehicle 1000 is provided with a power storage device 10, and the power conversion device 20 converts the DC power supplied from the power storage device 10 into AC power to drive the electric motor 30.

[0011] The electric motor 30 is, for example, a driving motor for rotating wheels. The electric motor 30 has a three-phase coil connected in a predetermined pattern. The connection pattern is not limited to the Y pattern shown in FIG. 1, and other connection patterns such as a delta pattern may be used. By applying a predetermined energization pattern from the power conversion device 20 to the three-phase coil, the electric motor 30 is rotationally driven.

[0012] The power storage device 10 has a positive electrode terminal 10a and a negative electrode terminal 10b. The power conversion device 20 has a positive electrode bus line 21p, a negative electrode bus line 21n, a smoothing capacitor 11, and a three-phase switching arm 50 (U, V, W). The positive electrode bus line 21p is connected to the positive electrode terminal 10a of the power storage device 10. The negative electrode bus line 21n is connected to the negative electrode terminal 10b of the power storage device 10. Both ends of the smoothing capacitor 11 and the three-phase switching arm 50 (U, V, W) are connected to the positive electrode bus line 21p and the negative electrode bus line 21n.

[0013] Each of the three-phase switching arms 50 (U, V, W) is provided with a switching element 70A in the upper arm and a switching element 70B in the lower arm. The switching elements 70A and 70B are, for example, power switching elements, and for example, IGBTs or MOSFETs are used. Each of the switching elements 70A and 70B has a freewheeling diode (or body diode) connected in parallel. In the embodiment, the case where the switching elements 70A and 70B are MOSFETs will be described as an example.

[0014] The switching element 70A of the upper arm and the switching element 70B of the lower arm are connected in series. The connection point between the switching element 70A of the upper arm and the switching element 70B of the lower arm is connected to one end of the coil of the corresponding phase of the electric motor 30. In the example shown in FIG. 1, one switching element is provided for each of the upper and lower arms, but a configuration in which a plurality of switching elements are used in parallel may also be employed.

[0015] The power conversion device 20 includes a control circuit 40 that controls the gate drive devices 60A and 60B. The control circuit 40 outputs PWM control commands P1 and P2 to the gate drive devices 60A and 60B, and individually controls the switching elements 70A and 70B. The control circuit 40 has, for example, a CPU, a RAM, a ROM, a communication circuit, etc. inside. The PWM control commands P1 and P2 are pulse signals having a predetermined pulse width, and the control circuit 40 performs PWM control on the switching elements 70A and 70B. By the PWM control commands P1 and P2, the switching elements 70A and 70B of the upper and lower arms of the same phase are alternately turned on / off within a range where they are not simultaneously turned on. As a result, the DC power from the power storage device 10 is converted into AC power, and the electric motor 30 is rotationally driven.

[0016] In this embodiment, the power conversion device 20 constituting an inverter as shown in FIG. 1 is described as an example, but the present invention is not limited thereto, and can also be applied to a DC / DC converter, an AC / AC converter, an AC / DC inverter, etc.

[0017] <Explanation of crosstalk phenomenon> Figure 2 is a diagram showing a conventional configuration of a single-phase circuit in a single-phase switching arm 50. The gate drive devices 61A and 61B show a case of a conventional general configuration. The gate drive device 61A and the gate drive device 61B have the same configuration, and include a gate driver IC 610, a gate resistor Ron for controlling the turn-on speed, and a gate resistor Roff for controlling the turn-off speed. In FIG. 2, the gate driver IC 610 of the gate drive device 61A is represented by reference numeral 610a, and the gate driver IC 610 of the gate drive device 61B is represented by reference numeral 610b.

[0018] Each switching element 70A and 70B has a drain electrode D, a source electrode S, and a gate electrode G. The gate electrodes G and the source electrodes S of the respective switching elements 70A and 70B are connected to the gate drive devices 61A and 61B, respectively. Hereinafter, the switching element 70B of the lower arm may be referred to as the self-arm switching element 70B, and the switching element 70A of the upper arm may be referred to as the counter-arm switching element 70A.

[0019] The source electrode S of the counter-arm switching element 70A and the drain electrode D of the self-arm switching element 70B are connected to the AC terminal. Each of the switching elements 70A and 70B switches between conduction (turn-on) and interruption (turn-off) according to the voltage (gate voltage) Vgs between the gate electrode G and the source electrode S. For example, when the gate voltage Vgs is higher than a predetermined turn-on threshold voltage, it becomes a conduction state, and when the gate voltage Vgs is lower than the turn-on threshold voltage, it becomes an interruption state.

[0020] By the way, in the single-phase circuit of FIG. 2, a phenomenon called crosstalk occurs when one arm switches. Here, the crosstalk generated when the counter-arm switching element 70A is turned on will be described. Parasitic capacitances Cgd and Cgs exist between the gate and the drain and between the gate and the source of each of the switching elements 70A and 70B.

[0021] When the complementary-arm switching element 70A turns on as shown in the figure, the potentials of the source electrode S of the complementary-arm switching element 70A and the drain electrode D of the self-arm switching element 70B rise rapidly. In this case, as the potential of the drain electrode D of the self-arm switching element 70B rises, a current of magnitude (dV / dt)×Cgd proportional to the potential change rate (dV / dt) flows to charge the parasitic capacitance Cgd of the self-arm switching element 70B. Also, a part of the current of magnitude (dV / dt)×Cgd flows through the gate resistor Roff to the source electrode S to charge the parasitic capacitance Cgs.

[0022] The magnitude |dVgs / dt| of the change rate of the gate voltage Vgs of the self-arm switching element 70B can be expressed by the following equation (1). In equation (1), Zgs is the impedance between the gate and the source. In this case, the impedance Zgs is mainly the gate resistor Roff. |dVgs / dt| = 1 / Cgs [Cgd×|dV / dt| - (Vgs / Zgs)] …(1)

[0023] Thus, due to the charging of the parasitic capacitances Cgd and Cgs, when the gate voltage Vgs of the self-arm switching element 70B exceeds the turn-on threshold voltage, the self-arm switching element 70B, which has been in the off state until now, becomes conductive. This phenomenon is called parasitic turn-on or self-turn-on. As shown in equation (1), the larger (dV / dt) or the gate resistor Roff is, the easier it is for the gate voltage Vgs to rise and the easier it is for self-turn-on to occur. When self-turn-on occurs, the complementary-arm switching element 70A and the self-arm switching element 70B conduct simultaneously, and a short-circuit current flows between the two switching elements 70A and 70B. This short-circuit current may increase the losses of the complementary-arm switching element 70A and the self-arm switching element 70B.

[0024] Also, although not shown in the drawings, when the anti-arm switching element 70A turns off, the potential of the drain electrode D of the self-arm switching element 70B rapidly decreases ((dV / dt) is a negative value). In this case, current flows from the source electrode S of the self-arm switching element 70B, and the parasitic capacitances Cgd and Cgs are discharged. As a result, the gate voltage Vgs of the self-arm switching element 70B decreases, and a negative surge occurs. In this case, as shown in Equation (1), the larger the magnitude of (dV / dt) or the gate resistance Roff, the easier it is for the gate voltage Vgs to decrease, and the more likely a negative surge is to occur. This negative surge in the gate voltage Vgs stresses the gate oxide film and shortens the life of the switching element. Therefore, it is necessary to take measures to suppress the negative surge.

[0025] As measures for suppressing the self-turn-on and negative surge caused by the above-described (dV / dt), for example, measures such as slowing down the switching speed of the anti-arm switching element 70A, providing a negative bias to the gate electrode G of the self-arm switching element 70B, and reducing the impedance between the gate and the source can be mentioned. In the invention described in Patent Document 1, a circuit for reducing the impedance between the gate and the source of the self-arm switching element 70B has been proposed.

[0026] FIG. 3 is a diagram showing an example of a case where a conventional circuit for reducing the impedance between the gate and the source is provided in the gate driving device. Hereinafter, the configuration shown in FIG. 3 will be referred to as a comparative example with respect to the present embodiment. The gate driving devices 62A and 62B have the same configuration, and here, the configuration of the upper arm side gate driving device 62A will be described as a representative. The gate driving device 62A of the comparative example includes a gate driver IC620a, gate resistors Ron and Roff, and an impedance adjustment circuit Z. A PWM control command P1 is input from the control circuit 40 to the gate driver IC620a of the gate driving device 62A. Note that a PWM control command P2 is input from the control circuit 40 to the gate driver IC620b of the lower arm gate driving device 62B.

[0027] The impedance adjustment circuit Z is a circuit that adjusts the gate-source impedance of the switching element 70A. The impedance adjustment circuit Z is connected to the gate electrode G of the switching element 70A. In the example shown in FIG. 3, the impedance adjustment circuit Z is composed of switching elements. The gate driver IC620a is a circuit that controls the on / off of the switching element 70A based on the PWM control command P1 input from the control circuit 40. The gate driver IC620a includes a turn-off detection unit 621 and a logic circuit 622 as components related to impedance adjustment.

[0028] The turn-off detection unit 621 that detects the turn-off operation of the switching element 70A monitors the gate voltage on the gate-on side. In the example shown in FIG. 3, the turn-off detection unit 621 is composed of a comparator, compares the monitored gate voltage Vgs with the threshold voltage Vamc, and outputs a HIGH signal (detection signal) to the logic circuit 622 when Vgs < Vamc. The logic circuit 622 generates a control signal for the impedance adjustment circuit Z based on the PWM control command P1 and the signal from the turn-off detection unit 621.

[0029] The impedance adjustment circuit Z changes the gate-source impedance according to the control signal from the logic circuit 622. In the example shown in FIG. 3, an ON / OFF signal for turning on / off the switching element of the impedance adjustment circuit Z is input as the control signal. When an ON signal is input to the impedance adjustment circuit Z, the gate-source is short-circuited and the impedance becomes low. On the other hand, when an OFF signal is input to the impedance adjustment circuit Z, the short circuit between the gate and the source is released and the impedance becomes high.

[0030] FIG. 4 is a diagram showing the gate drive devices 60A and 60B of the first embodiment. Both the gate drive devices 60A and 60B have the same configuration, and here, the configuration of the gate drive device 60A will be described as a representative. The gate drive device 60A includes a gate driver IC 600a, gate resistors Ron and Roff, and an impedance adjustment circuit Z. The gate resistors Ron and Roff and the impedance adjustment circuit Z have the same configuration as in the above-described comparative example (FIG. 3). The gate driver IC 600a has a configuration related to impedance adjustment that is different from that of the gate driver IC 620a. Note that the gate driver IC of the gate drive device 60B is denoted by reference numeral 620b, but it has the same configuration as the gate driver IC 620a.

[0031] The gate driver IC 600a includes, as a configuration related to impedance adjustment, a turn-on detection unit 601, a turn-off detection unit 621, and a logic circuit 602. The turn-off detection unit 621 is the same as the turn-off detection unit 621 provided in the above-described gate driver IC 620a. Also, since the control content of the logic circuit 602 is only different from that of the logic circuit 622, the logic circuit 622 of the comparative example can be directly reused.

[0032] The turn-on detection unit 601 that detects the turn-on operation of the switching element 70A monitors the gate voltage on the gate-off side. In the example shown in FIG. 4, the turn-on detection unit 601 is configured by a comparator, compares the monitored gate voltage Vgs with a threshold voltage Vpto, and outputs a HIGH signal (detection signal) to the logic circuit 602 when Vgs > Vpto.

[0033] The logic circuit 602 of the upper arm side driver IC600a receives a PWM control command P1, a signal from the turn-off detection unit 621, a PWM control command P2 of the lower arm side, and a signal from the turn-on detection unit 601 of the lower arm side driver IC600b (gate turn-on signal of the switching element 70B). On the other hand, the logic circuit 602 of the lower arm side driver IC600b receives a PWM control command P2, a signal from the turn-off detection unit 621, a PWM control command P1 of the upper arm side, and a signal from the turn-on detection unit 601 of the upper arm side driver IC600a (gate turn-on signal of the switching element 70A). The logic circuits 602 of the respective driver ICs 600a and 600b generate a control signal for the impedance adjustment circuit Z based on the input signals.

[0034] (1. Description of the impedance control operation) A control example of the logic circuit 602 in the first embodiment will be described in comparison with the control of the logic circuit 622 of the comparative example. FIG. 5 is a diagram for explaining the control operations of the logic circuits 602 and 622, and is a diagram showing waveform examples of respective signals when PWM controlling the switching elements 70A and 70B. In FIG. 5, waveform (A) indicates the PWM control commands P1 and P2 of the upper and lower arms. The waveform indicated by the thick solid line is the waveform of the PWM control command P1, and the waveform indicated by the thin solid line is the waveform of the PWM control command P2.

[0035] Waveform (B) indicates the gate voltages Vgs of the switching elements 70A and 70B. The waveform indicated by the thick solid line is the gate voltage Vgs1 of the switching element 70A, and the waveforms indicated by the thin solid line and the broken line are the gate voltage Vgs2 of the switching element 70B. Note that the waveform of the gate voltage Vgs2 is different between the first embodiment and the comparative example. The broken line indicates the gate voltage Vgs2 in the first embodiment, and the solid line indicates the gate voltage Vgs2 in the comparative example.

[0036] Waveform (C) indicates the main voltage (drain-source voltage) Vds of switching elements 70A and 70B. The thick solid line indicates the main voltage Vds1 of switching element 70A, and the thin solid line and the dashed line indicate the main voltage Vds2 of switching element 70B. Among the waveforms indicating the main voltage Vds2, the dashed line indicates the main voltage Vds2 in the first embodiment, and the solid line indicates the main voltage Vds2 in the comparative example.

[0037] Waveform (D) indicates the gate-source impedance Zgs2 of the switching element 70B in the lower arm. The dashed line indicates the impedance Zgs2 in the first embodiment, and the solid line indicates the impedance Zgs2 in the comparative example. The impedance Zgs2 becomes Low when the gate-source is shorted by the impedance adjustment circuit Z, and the impedance becomes High when the short between the gate-source is released.

[0038] Waveform (E) indicates the main current (drain current) Ids of switching elements 70A and 70B. The thick solid line is the main current Ids1 of switching element 70A, and the thin solid line and the dashed line are the main current Ids2 of switching element 70B. Among the waveforms indicating the main current Ids2, the dashed line indicates the main current Ids2 in the first embodiment, and the solid line indicates the main current Ids2 in the comparative example.

[0039] The PWM control command waveform shown in waveform (A) shows the waveform patterns of the PWM control commands P1 and P2 when turning on and off the switching element 70A in the upper arm for energization. In this case, the period from time t3 to time t5 when the PWM control command P1 is ON is the energization period, and the period when the PWM control command P1 is OFF is the freewheeling period. During the freewheeling period, when the switching element 70B in the lower arm is OFF, a freewheeling current flows through the freewheeling diode, and when the switching element 70B is ON (synchronous rectification), a freewheeling current flows through the switching element 70B.

[0040] In the following operation description, the switching element through which the energizing current flows is the above-described anti-arm switching element, and the switching element through which the reflux current flows is the above-described self-arm switching element. That is, in the energization pattern shown in FIG. 5, the switching element 70A in the upper arm corresponds to the anti-arm switching element, and the switching element 70B in the lower arm corresponds to the self-arm switching element. On the other hand, in the case of the energization pattern in which the energizing current flows from the right side to the left side of the AC terminal in FIG. 2, since the energizing current flows through the switching element 70B, the switching element 70B corresponds to the anti-arm switching element, and the switching element 70A corresponds to the self-arm switching element.

[0041] In the on / off operation of the anti-arm switching element (switching element 70A in FIG. 2) through which the energizing current flows, the period from the time t3 when the PWM control command P1 of the waveform (A) rises to ON to the time t4 when the gate voltage Vgs1 of the waveform (B) becomes the predetermined threshold voltage Vpto is the "on switching period" when the anti-arm switching element 70A turns on. Further, the period from the time t5 when the PWM control command P1 switches from ON to OFF to the time t51 when the main current Ids1 of the waveform (E) becomes zero is the "off switching period" when the anti-arm switching element 70A turns off.

[0042] (1-1. Control of Comparative Example) First, the impedance control operation in the case of the comparative example shown in FIG. 3 will be described. In the comparative example, the impedance between the gate and the source is reduced by the impedance adjustment circuit Z to suppress self-turn-on and negative surges caused by (dV / dt) of the anti-arm switching element (the switching element in the upper arm) 70A. The logic circuit 622 provided in the gate driver IC620b shown in FIG. 3 controls the impedance Zgs2 between the gate and the source of the switching element 70B as shown by the solid line in the waveform (D). That is, the impedance Zgs2 is switched from HIGH to LOW at the time t2 and returned from LOW to HIGH at the time t6.

[0043] As shown in waveform (A), the counter-arm switching element 70A and the self-arm switching element 70B alternately repeat the ON state. In FIG. 5, the self-arm switching element 70B is controlled to be in the OFF state from time t1 to time t6, and the counter-arm switching element 70A is controlled to be in the ON state from time t3 to time t5. At time t1, an OFF PWM control command P2 is input to the gate driver IC620b of the lower arm. After a while, the gate voltage Vgs2 of the self-arm switching element 70B starts to decrease.

[0044] The turn-off detection unit 621 of the gate driver IC620b compares the monitored gate voltage Vgs2 of the self-arm switching element 70B with the threshold voltage Vamc, and outputs a HIGH signal to the logic circuit 622 at time t2 when Vgs2 < Vamc. The logic circuit 622 outputs a signal (i.e., an ON signal) that reduces the impedance Zgs2 in the HIGH state to LOW when the PWM control command P1 is OFF and the output of the turn-off detection unit 621 is HIGH. When the ON signal is input to the impedance adjustment circuit Z, the gate-source of the self-arm switching element 70B is short-circuited, and the impedance Zgs2 is switched from HIGH to LOW.

[0045] When the PWM control command P1 switches from OFF to ON at time t3, the counter-arm switching element 70A starts the turn-on operation. After a while, the gate voltage Vgs1 of the counter-arm switching element 70A starts to rise, and the main voltage Vds1 starts to decrease. In the comparative example, since the impedance Zgs2 of the self-arm switching element 70B is LOW, the increase in the gate voltage Vgs2 due to crosstalk (spike at the location indicated by arrow S1) is suppressed. On the other hand, by setting the impedance Zgs2 to LOW, as shown by the thin solid line in waveform (C), the linking surge voltage (recovery surge of the main voltage Vds2) generated when the freewheeling diode of the self-arm switching element 70B transitions from the conducting state to the blocking state increases. This inhibits the increase in the switching speed and causes an increase in switching losses.

[0046] When the PWM control command P1 switches from ON to OFF at time t5, the counter-arm switching element 70A starts a turn-off operation. After a while, the gate voltage Vgs of the counter-arm switching element 70A begins to decrease, and the main voltage Vds1 begins to increase. In the comparative example, since the impedance Zgs2 of the self-arm switching element 70B is LOW, the negative spike of the gate voltage Vgs2 of the self-arm switching element 70B due to crosstalk (the spike at the location indicated by the arrow S2) is suppressed.

[0047] At time t6, when the PWM control command P1 switches from OFF to ON, the logic circuit 622 of the gate driver IC620b outputs an OFF signal that raises the impedance Zgs2 in the LOW state to HIGH. When the OFF signal is input to the impedance adjustment circuit Z, the short circuit between the gate and source is released and the impedance Zgs2 is switched from LOW to HIGH.

[0048] (1-2. Control of the First Embodiment) Next, the impedance control operation in the case of the first embodiment shown in FIG. 4 will be described. The logic circuit 602 provided in the gate driver ID600b shown in FIG. 4 controls the impedance Zgs2 of the self-arm switching element 70B as shown by the broken line in waveform (D) of FIG. 5. That is, the impedance Zgs2 is switched from HIGH to LOW at time t2, returned from LOW to HIGH at time t3, switched from HIGH to LOW again at time t4, and returned from LOW to HIGH again at time t6.

[0049] Here, the HIGH value of the impedance Zgs2 is set to an impedance such that the gate voltage Vgs2 lifted on the self-arm side by the turn-on of the counter-arm switching element 70A exceeds the threshold voltage Vth (refer to waveform (B) in FIG. 5), that is, the self-arm switching element 70B self-turns on. On the other hand, the LOW value is set to an impedance such that the self-arm switching element 70B does not self-turn on when the counter-arm switching element 70A is turned on.

[0050] The gate voltage Vgs2 of the self-arm switching element 70B when the counter-arm switching element 70A is turned on is represented by integrating the left side of the above-described equation (1). The integration period is the turn-on time (on switching period), and the impedance Zgs2 for which there is a timing during this period when the gate voltage Vgs2 exceeds the threshold voltage Vth corresponds to the impedance HIGH that self-turns on. On the other hand, the impedance Zgs2 when there is no timing to exceed the threshold voltage Vth during the period corresponds to the impedance LOW that does not self-turn on.

[0051] First, after an OFF PWM control command P2 is input to the gate driver IC600b at time t1 in FIG. 5 for a while, the gate voltage Vgs2 of the self-arm switching element 70B starts to decrease. The turn-off detection unit 621 of the gate driver IC600b compares the monitored gate voltage Vgs2 of the self-arm switching element 70B with the threshold voltage Vamc, and outputs a HIGH signal to the logic circuit 602 at time t2 when Vgs2 < Vamc. The logic circuit 602 outputs an ON signal that reduces the impedance Zgs2 in the HIGH state to LOW when the PWM control command P1 is OFF and the output of the turn-off detection unit 621 is HIGH. When the ON signal is input to the impedance adjustment circuit Z, the gate-source of the self-arm switching element 70B is short-circuited and the impedance Zgs2 is switched from HIGH to LOW.

[0052] When the PWM control command P1 switches from OFF to ON at time t3, the logic circuit 602 of the gate driver IC600b outputs an OFF signal that raises the impedance Zgs2 in the LOW state to HIGH. When the OFF signal is input to the impedance adjustment circuit Z, the impedance Zgs2 is switched from LOW to HIGH.

[0053] At time t3, the anti-arm switching element 70A starts the turn-on operation. After a while, the gate voltage Vgs1 of the anti-arm switching element 70A begins to rise, and the main voltage Vds1 begins to decrease. In the case of the first embodiment, since the impedance Zgs2 is HIGH, during the turn-on period of the anti-arm switching element 70A, the spike of the gate voltage Vgs2 generated in the self-arm switching element 70B due to crosstalk exceeds the threshold voltage Vth. As a result, the self-arm switching element 70B is in the conductive state for a while, clamping the linking of the freewheeling diode, and the recovery surge of the main voltage Vds2 is significantly reduced compared to the comparative example.

[0054] The operation after time t4 is controlled such that the impedance Zgs2 is the same as in the comparative example, as shown in waveform (D). Therefore, the negative spike of the self-arm switching element 70B (the spike at the location indicated by arrow S2) generated during the turn-off period after time t5 is suppressed as in the comparative example.

[0055] As described above, in the comparative example, since the impedance Zgs2 is switched to the LOW state from time t2 to time t6, it is possible to prevent the self-turn-on of the self-arm during anti-arm turn-on and suppress the negative surge during anti-arm turn-off. However, the recovery surge of the self-arm during anti-arm turn-on becomes large, which is an inhibiting factor for speeding up the switching.

[0056] On the other hand, in the first embodiment, as shown by the broken line of the waveform (D), control is performed to return the impedance Zgs2 from LOW to HIGH during the complementary arm turn-on period. Thereby, by increasing the gate impedance of the self-arm to HIGH when the complementary arm turns on, the speed at which the carrier of the gate of the self-arm is extracted becomes slower, and self-turn-on can be induced. As a result, the linking of the freewheeling diode is clamped when the spike of the gate voltage Vgs2 due to crosstalk exceeds the threshold voltage Vth, and the recovery surge of the main voltage Vds2 can be greatly reduced. And, while suppressing the self-arm recovery surge when the complementary arm turns on, it becomes possible to increase the turn-on speed, and the total switching loss of the complementary arm side and the self-arm side combined can be reduced. Furthermore, similar to the case of the comparative example, the gate negative surge on the self-arm side when the complementary arm turns off can also be suppressed.

[0057] (Modification 1) FIG. 6 is a diagram showing Modification 1 of the first embodiment in which impedance control is performed as shown by the broken line of the waveform (D) in FIG. 5. In the gate driver ICs 600a and 600b in Modification 1, the turn-on detection unit 601 is omitted, and the signal input to the logic circuit 602A is different from that of the logic circuit 602 described above. The logic circuit 602A of the gate driver IC 600a receives the PWM control command P1, the signal from the turn-off detection unit 621, and the PWM control command P2 on the lower arm side. On the other hand, the logic circuit 602A of the gate driver IC 600b receives the PWM control command P2, the signal from the turn-off detection unit 621, and the PWM control command P1 on the upper arm side. The other configurations of the gate driving devices 60A and 60B are the same as those in the first embodiment shown in FIG. 4.

[0058] The control operation of impedance Zgs2 by logic circuit 602A will be described. Also in Modification 1, the control pattern of impedance Zgs2 is the same as that in the case of the first embodiment described above, and the control is performed as indicated by the broken line in waveform (D) of FIG. 5. At time t2, as in the case of the first embodiment, when the turn-off detection unit 621 detects that Vgs2 < Vamc, the impedance Zgs2 is switched from HIGH to LOW.

[0059] At time t3, as in the case of the first embodiment, when the PWM control command P1 on the counter arm side switches from OFF to ON, the logic circuit 602A outputs an OFF signal that raises the LOW-state impedance Zgs2 to HIGH. Further, when a predetermined delay time Δt1 has elapsed since the logic circuit 602A detects the switch from OFF to ON of the PWM control command P1, the impedance Zgs2 is switched from HIGH to LOW. Here, the delay time Δt1 is equal to or longer than the on-switching period of the counter arm switching element 70A to be turned on and is set within the period until the turn-off start (time t5). At time t6, as in the case of the first embodiment, when the PWM control command P2 on the self-arm side switches from OFF to ON, the impedance Zgs2 is returned from LOW to HIGH.

[0060] (Modification 2) FIG. 7 is a diagram showing a modification 2 of the first embodiment that performs impedance control like the broken line of waveform (D) in FIG. 5. In the gate driver ICs 600a and 600b in the modification 2, the signal input to the logic circuit 602B is different from that of the logic circuit 602 in the case of the first embodiment. The logic circuit 602B of the upper arm side gate driver IC 600a receives the PWM control command P1, the signal from the turn-off detection unit 621, and the signal from the turn-on detection unit 601 of the lower arm side gate driver IC 600b. On the other hand, the logic circuit 602B of the lower arm side gate driver IC 600b receives the PWM control command P2, the signal from the turn-off detection unit 621, and the signal from the turn-on detection unit 601 of the upper arm side gate driver IC 600a. The other configurations of the gate drive devices 60A and 60B are the same as those in the first embodiment shown in FIG. 4.

[0061] The control operation of the impedance Zgs2 by the logic circuit 602B will be described. At time t2, similar to the case of the first embodiment, when the turn-off detection unit 621 detects that Vgs2 < Vamc, the impedance Zgs2 is switched from HIGH to LOW. The logic circuit 602B monitors the upper arm side gate voltage Vgs1 via the upper arm side turn-on detection unit 601, and if the gate voltage Vgs1 starts to increase, the impedance Zgs2 is returned from LOW to HIGH. This timing corresponds to time t3 in FIG. 5.

[0062] After that, if a HIGH signal is input from the upper arm side turn-on detection unit 601 (time t4), the impedance Zgs2 is switched from HIGH to LOW again. And if the lower arm side PWM control command P2 is switched from OFF to ON (time t6), the impedance Zgs2 is returned from LOW to HIGH again.

[0063] (2. Impedance adjustment circuit Z) In the above-described embodiments and modifications, the impedance adjustment circuit Z is composed of a single switching element provided on the wiring. When the switching element is turned on, the impedance becomes LOW, and when it is turned off, the impedance becomes HIGH. Hereinafter, other configurations of the impedance adjustment circuit Z will be described.

[0064] FIG. 8A is a diagram showing a first modification of the impedance adjustment circuit Z. In the first modification, the impedance adjustment circuit Z is a series circuit of a switching element 80 and a capacitor 81. When the switching element 80 is turned on, the impedance becomes HIGH, and when it is turned off, the impedance becomes LOW. Since the impedance of the capacitor 81 is 1 / C with respect to the capacitance C, the smaller the capacitance C, the larger the impedance. Thereby, the recovery surge can be suppressed.

[0065] FIG. 8B is a diagram showing a second modification of the impedance adjustment circuit Z. In the second modification, the impedance adjustment circuit Z is a series circuit of a switching element 80 and a resistor 82. When the switching element 80 is turned on, the impedance becomes LOW, and when it is turned off, the impedance becomes HIGH. The magnitude of the impedance of the impedance adjustment circuit Z depends on the impedance of the resistor 82 and has the same value both when it is on and when it is off.

[0066] FIG. 8C is a diagram showing a third modification of the impedance adjustment circuit Z. In the third modification, the impedance adjustment circuit Z is a series circuit of a switching element 80 and a diode 83. The diode 83 is preferably connected so that the cathode is on the gate side. When the switching element 80 is turned on, the impedance becomes LOW, and when the switching element 80 is turned off, the impedance becomes HIGH.

[0067] When the switching element 80 is turned on at the turn-off of the counter arm, a spike current flows from the source toward the gate when a gate negative spike occurs. The magnitude of the gate negative spike is proportional to the product of this current and the impedance toward the gate, and the gate negative spike can be reduced by reducing the impedance toward the gate by the diode 83.

[0068] FIG. 8D is a diagram showing a fourth modification of the impedance adjustment circuit Z. In the fourth modification, a parallel circuit of a resistor 82 and a diode 83 is connected in series to the switch element 80. Regarding the parallel circuit portion, the impedance becomes that of the resistor 82 with respect to the current flowing from the upper side to the lower side in the figure, and the recovery surge at the time of turn-on of the counter arm is reduced. On the other hand, with respect to the current flowing from the lower side to the upper side, the diode 83 becomes dominant and the impedance becomes zero, so the negative surge at the time of turn-off of the counter arm is reduced. In the third modification of FIG. 8C, the impedance becomes infinite with respect to the current flowing from the upper side to the lower side in the figure, so the configuration of the fourth modification is more preferable. Note that a parallel circuit of three elements, a diode, a resistor, and a capacitor, may also be used.

[0069] FIG. 8E is a diagram showing a fifth modification of the impedance adjustment circuit Z. In the fifth modification, a series circuit of a switch element 80A and a resistor 82A and a series circuit of a switch element 80B and a resistor 82B are connected in parallel. By operating each switch element 80A, 80B as follows, the impedance can be changed in multiple steps.

[0070] When the switch elements 80A and 80B are simultaneously turned off, the impedance becomes the largest Z1. Conversely, when the switch elements 80A and 80B are simultaneously turned on, the impedance becomes the smallest Z4. Let the impedance when the switch element 80A is on and the switch element 80B is off be Z2, and the impedance when the switch element 80A is off and the switch element 80B is on be Z3. Here, the values of the resistors 82A and 82B are set so that Z2 > Z3. That is, by the on / off control of the switch elements 80A and 80B, the impedance can be controlled in four steps of Z1, Z2, Z3, Z4 (Z1 > Z2 > Z3 > Z4).

[0071] From time t3 to time t4 of the waveform (D) in FIG. 5, the impedance of the impedance adjustment circuit Z is set such that the first half is Z1 (corresponding to HIGH) and the second half is set to Z2 or Z3. Then, from time t2 to t3 and from time t4 to t6, the impedance is set to Z4 (corresponding to LOW). In this way, by controlling the impedance from time t3 to t4 according to the states of the switching elements 70A and 70B, an appropriate recovery surge can be suppressed and the loss can be optimized. Thereby, an increase in loss due to excessive surge suppression can be prevented. Note that in FIG. 8E, it is in two parallel, but it may be three parallel or more, enabling finer impedance adjustment.

[0072] Also, as a method of adjusting the impedance value from time t3 to t4, it may be adjusted based on the states (main voltage, main current, junction temperature) of the switching elements 70A and 70B. For example, regarding the junction temperatures T1 and T2 (>T1), at the junction temperature T1, the impedance value from time t3 to t4 is set to Z1, and at the junction temperature T2, the impedance value from time t3 to t4 is set to Z2 or Z3. Such a control method is also acceptable.

[0073] As an example based on the main current Ids, consider a first main current and a second main current higher than the first main current. In this case, a control method in which the impedance value from time t3 to t4 is set to Z1 at the first main current and the impedance value from time t3 to t4 is set to Z2 or Z3 at the second main current is also acceptable.

[0074] (Second Embodiment) FIG. 9 is a diagram showing a second embodiment of the gate drive device. As shown in FIG. 9, the gate driver ICs 600a and 600b include a turn-on detection unit 601 and a logic circuit 602C. In the second embodiment, a control signal for the impedance adjustment circuit Z is generated based on the PWM control command on the self-arm side and the signal of the turn-on detection unit 601 on the counter-arm side.

[0075] The logic circuit 602C of the gate driver IC 600a on the upper arm side generates a control signal for the impedance adjustment circuit Z based on the PWM control command P1 and the output signal of the turn-on detection unit 601 of the gate driver IC 600b on the lower arm side. On the other hand, the logic circuit 602C of the gate driver IC 600a on the lower arm side generates a control signal for the impedance adjustment circuit Z based on the PWM control command P2 and the output signal of the turn-on detection unit 601 of the gate driver IC 600b on the upper arm side.

[0076] In the second embodiment, the following control signal generation method is used to generate a control pattern as shown by the broken line in waveform (D) of FIG. 5. The logic circuit 602C on the self-arm side (lower arm side) switches the impedance Zgs2 from High to LOW at the timing (corresponding to time t2) when a predetermined delay time Δt2 has elapsed from the OFF timing (time t1) of the PWM control command P2 on the self-arm side. Thereafter, the logic circuit 602C monitors the gate voltage Vgs1 on the opposite arm side via the turn-on detection unit 601 on the opposite arm side, and if the gate voltage Vgs1 starts to increase, returns the impedance Zgs2 from LOW to HIGH (corresponding to time t3).

[0077] When a HIGH signal is input from the turn-on detection unit 601 on the opposite arm side to the logic circuit 602C (time t4), the logic circuit 602C switches the impedance Zgs2 from High to LOW. Thereafter, when the PWM control command P2 on the self-arm side switches from LOW to HIGH (time t6), the logic circuit 602C returns the impedance Zgs2 from LOW to High again. As a result, in the case of the second embodiment as well, the same effect as in the case of the first embodiment can be achieved.

[0078] (Third Embodiment) FIG. 10 is a diagram showing a third embodiment of the gate drive device. The PWM control commands P1 and P2 on the self-arm side and the opposite arm side are input to the logic circuit 602D of the gate driver ICs 600a and 600b. The logic circuit 602D generates a control signal for the impedance adjustment circuit Z based on the PWM control commands P1 and P2.

[0079] In the third embodiment, a control pattern as shown by the broken line in waveform (D) of FIG. 5 is generated by the following control signal generation method. The logic circuit 602D on the self-arm side (lower arm side) switches the impedance Zgs2 from High to LOW at the timing (corresponding to time t2) when a predetermined delay time Δt2 has elapsed from the OFF timing (time t1) of the PWM control command P2 on the self-arm side. Thereafter, when the PWM control command P1 on the counter-arm side switches from OFF to ON (time t3), the logic circuit 602D returns the impedance Zgs2 from LOW to High.

[0080] The logic circuit 602D switches the impedance Zgs2 from High to LOW at the timing (corresponding to time t4) when a predetermined delay time Δt1 has elapsed from the timing (time t3) when the PWM control command P1 on the counter-arm side switches to ON. Thereafter, when the PWM control command P2 on the self-arm side switches from LOW to HIGH (time t6), the logic circuit 602D returns the impedance Zgs2 from LOW to High again. As a result, also in the case of the third embodiment, the same effect as in the case of the first embodiment can be obtained.

[0081] (Fourth Embodiment) FIG. 11 is a diagram showing a fourth embodiment of the gate driving device. The gate driver ICs 600a and 600b include a main voltage detection unit 603, a main current detection unit 604, and a logic circuit 602E. The main voltage detection unit 603 and the main current detection unit 604 are each constituted by, for example, a comparator. The main voltage detection unit 603 of each gate driver IC 600a and 600b compares the main voltages (drain-source voltages) Vds1 and Vds2 of the corresponding switching elements 70A and 70B with a reference voltage, and outputs a Vds detection signal to the logic circuit 602E when the main voltages Vds1 and Vds2 are equal to or higher than the reference voltage. The main current detection unit 604 of each gate driver IC 600a and 600b compares the main currents (drain currents) Ids1 and Ids2 of the corresponding switching elements 70A and 70B with a reference current, and outputs an Ids detection signal to the logic circuit 602E when the main currents Ids1 and Ids2 are equal to or lower than the reference current. The logic circuit 602E controls the impedance Zgs2 based on the PWM control command and at least one of the Vds detection signal and the Ids detection signal.

[0082] In the fourth embodiment, a control pattern as shown by the broken line in waveform (D) of FIG. 5 is generated by the following control signal generation method. The logic circuit 602E on the self-arm side (lower arm side) switches the impedance Zgs2 from High to LOW at a timing (corresponding to time t2) when a predetermined delay time Δt2 has elapsed from the OFF timing (time t1) of the PWM control command P2 on the self-arm side. When at least one of the Ids detection signal and the Vds detection signal of the self-arm is input (time t31), the logic circuit 602E returns the impedance Zgs2 from LOW to High again. Here, time t31 corresponds to time t3 in the first embodiment.

[0083] Next, at the timing when a predetermined delay time Δt3 has elapsed from time t31 (corresponding to time t4), the logic circuit 602E switches the impedance Zgs2 from High to LOW again. After that, when the PWM control command P2 on the self-arm side switches from LOW to HIGH (time t6), the logic circuit 602E returns the impedance Zgs2 from LOW to High again. As a result, also in the case of the fourth embodiment, the same effect as in the case of the first embodiment can be achieved.

[0084] The ground potential is different between the counter arm (upper arm) side and the self-arm (lower arm) side. However, in the configuration shown in FIG. 11, the counter arm performs impedance control based on the signal on the counter arm side, while the self-arm performs impedance control based on the signal on the self-arm side, and they are independent between the upper and lower arms. For example, in the configuration shown in FIG. 4, since the upper and lower arms are not independent, an insulating element for signal exchange between the upper and lower arms is required. On the other hand, in the configuration shown in FIG. 11, since the upper and lower arms are independent, such an insulating element is not required, and cost reduction can be achieved.

[0085] (Fifth Embodiment) FIG. 12 is a diagram showing the configuration of a single-phase circuit according to the fifth embodiment. In the fifth embodiment, in the first embodiment, the switching elements of the upper and lower arms are configured by a plurality of switching elements connected in parallel. In the example shown in FIG. 12, switching elements 70A1 and 70A2 connected in parallel are provided on the upper arm side, and switching elements 70B1 and 70B2 connected in parallel are provided on the lower arm side.

[0086] An electronic component (e.g., resistor, inductor) 91a having an impedance Z1a is connected to the gate terminal of the switching element 70A1. Also, an electronic component 91b having an impedance Z1b is connected to the gate terminal of the switching element 70A2. The other ends of the electronic components 91a and 91b are connected to the gate driver IC600a. The impedances Z1a and Z1b are set so that the recovery surges of the switching elements 70A1 and 70A2 during the recovery period become values of the same degree (e.g., the difference is within 50 V).

[0087] Similarly, an electronic component 92a having an impedance Z2a is connected to the gate terminal of the switching element 70B1. Also, an electronic component 92b having an impedance Z2b is connected to the gate terminal of the switching element 70B2. The other ends of the electronic components 92a and 92b are connected to the gate driver IC600b. The impedances Z2a and Z2b are set so that the recovery surges of the switching elements 70B1 and 70B2 during the recovery period become values of the same degree (e.g., the difference is within 50 V).

[0088] Thus, even in a configuration in which a plurality of switching elements are connected in parallel, gate drive devices 60A and 60B similar to those in the first embodiment are provided, and by performing impedance control as shown in waveform (D) of FIG. 5, the same effects as those in the first embodiment described above can be achieved. Note that, for the configurations from the second embodiment to the fourth embodiment, a configuration in which a plurality of switching elements are connected in parallel may be applied in the same manner as in the case of FIG. 12.

[0089] Note that, although FIG. 12 shows the case of two in parallel, it can also be applied to a configuration in which three or more switching elements are connected in parallel. Also in that case, an electronic component whose impedance is set so that the recovery surges in each switching element become values of the same degree is configured to be connected to the gate terminal of each switching element.

[0090] According to the embodiments and modified examples of the present invention described above, the following operational effects are achieved.

[0091] (C1) As shown in FIGS. 4, 5, etc., gate drive devices 60A and 60B for driving the switching elements (semiconductor elements) 70A of the upper and lower arms, comprising a turn-on detection unit 601, a turn-off detection unit 621, a logic circuit 602, and an impedance adjustment circuit Z as an impedance adjustment unit for individually controlling the impedance of the gate discharge paths of the upper and lower arms. The logic circuit 602 sets the first impedance (HIGH) of the gate discharge path of its own arm (the other arm) during the on-switching period of the paired arm (one arm) of the upper and lower arms to be higher than the second impedance (LOW) of the gate discharge path of the other arm during the off-switching period of the one arm.

[0092] By setting the first impedance in this way, when the paired arm turns on, by raising the gate impedance of its own arm to HIGH, the speed of extracting the carriers of the gate of its own arm is slowed down to induce self-turn-on. As a result, while suppressing the recovery surge of its own arm, the turn-on speed of the paired arm can be improved, and the total switching loss of both the paired arm side and its own arm side can be reduced.

[0093] (C2) In the above (C1), as shown in FIG. 5, the logic circuit 602 of the impedance adjustment unit changes the impedance of the gate discharge path of its own arm (the other arm) from HIGH (the first impedance) to LOW (the second impedance) between the completion of turn-on (time t4) and the start of turn-off (time t5) of the paired arm (one arm). Since the impedance of the gate discharge path of its own arm is set to LOW during the turn-off period (off-switching period), damage to the oxide film of the gate can be prevented, and a decrease in the reliability of the gate can be prevented.

[0094] (C3) In the above (C1), as shown in FIG. 4 and the like, the impedance adjustment unit includes a mirror clamp circuit that holds the impedance between the gate and the source of the switching elements 70A and 70B at LOW (second impedance). In the configuration of FIG. 3 which is a comparative example, the turn-off detection unit 621, the logic circuit 622, and the impedance adjustment circuit Z constitute a mirror clamp circuit. Since the impedance adjustment unit in the first embodiment shown in FIG. 5 is configured using this mirror clamp circuit, circuit simplification can be achieved. Of course, a circuit having the function of the above impedance adjustment unit may be configured without using the mirror clamp circuit.

[0095] (C4) In the above (C1), as shown in FIG. 5 and the like, the first impedance (HIGH) is set to the value HIGH at which the switching element 70B of the self-arm (the other arm) self-turns on by the turn-on of the pair arm (one arm). In this way, by causing self-turn-on to occur in the self-arm switching element 70B, the recovery surge of the self-arm can be reduced.

[0096] (C5) In the above (C1), as shown in FIGS. 4, 5, 10 and the like, the logic circuit 602 of the impedance adjustment unit controls the impedance of the gate discharge path of the self-arm (the other arm) to HIGH and LOW based on the gate information of the pair arm (one arm). As an example of the gate information, in the case of the configuration shown in FIG. 4, it is the PWM control command P1 of the pair arm and the signal from the turn-on detection unit 601, and in the case of the configuration shown in FIG. 10, it is the PWM control command P1 of the pair arm. By determining the gate impedance adjustment timing of the self-arm from the gate information of the pair arm in this way, circuit simplification can be achieved.

[0097] (C6) In (C1) above, as shown in FIGS. 5, 11, etc., the impedance adjustment unit includes at least one of a main voltage detection unit 603 that detects the main voltage Vds2 (main voltage information) of its own arm (the other arm) and a main current detection unit 604 that detects the main current Ids2 (main current information) of its own arm. The logic circuit 602E of the impedance adjustment unit controls the impedance of the gate discharge path of its own arm to HIGH (first impedance) and LOW (second impedance) based on at least one of the main voltage Vds2 and the main current Ids2.

[0098] In the configuration shown in FIG. 11, the ground potential is different between the paired arm (upper arm) side and the own arm (lower arm) side. As described above, the paired arm performs impedance control based on the signal on the paired arm side, and the own arm performs impedance control based on the signal on the own arm side, so that it is possible to adopt a configuration in which an insulating element necessary for signal exchange between the upper and lower arms is omitted, and cost reduction can be achieved.

[0099] (C7) In (C1) above, as shown in FIGS. 8A, etc., the impedance adjustment unit includes a capacitor 81 (capacitance element) as an impedance adjustment element. When adjusting the gate impedance, it is generally composed of a resistor (including a 0Ω shunt resistor and a jumper), but as described above, it is also possible to adjust it with a capacitance element (capacitance C). Since the impedance is proportional to 1 / C, the larger the capacitance C, the lower the impedance. Thereby, the recovery surge can be suppressed.

[0100] (C8) In (C1) above, as shown in FIGS. 8C, 8D, etc., the impedance adjustment unit includes a diode 83 as an impedance adjustment element. By providing the diode 83, the impedance toward the gate is reduced, and the gate negative spike can be reduced.

[0101] (C9) In (C1) above, as shown in FIG. 12 and the like, the upper arm is composed of a plurality of switching elements 70A1 and 70A2 connected in parallel, and the lower arm is composed of a plurality of switching elements 70B1 and 70B2 connected in parallel. The impedances (gate impedances) of the respective electronic components 92a and 92b provided in the gate wirings of the plurality of switching elements 70B1 and 70B2 of the self-arm (the other arm) are set so that the recovery surges of the switching elements 70B1 and 70B2 at the time of turn-on of the counter-arm (one arm) become equal.

[0102] When the gate impedances of the switching elements 70B1 and 70B2 connected in parallel as shown in FIG. 12 are adjusted to the same value, different recovery surges may occur. In that case, the switching element with the larger recovery surge may fail prematurely. Therefore, electronic components 92a and 92b for impedance adjustment are provided in the gate wirings of the switching elements 70B1 and 70B2, and the impedances of the electronic components 92a and 92b are set so that the generated recovery surges become equal. Thereby, it is possible to prevent the occurrence of the inconvenience that either one of the switching elements 70B1 and 70B2 fails prematurely.

[0103] The above-described embodiments and various modifications are merely examples, and the present invention is not limited to these contents as long as the features of the invention are not impaired. Also, although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other aspects conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

Description of Reference Numerals

[0104] 10... Energy storage device, 20... Power conversion device, 30... Electric motor, 40... Control circuit, 60A, 60B, 61A, 61B, 62A, 62B... Gate drive device, 70A, 70B... Switching element, 600a, 600b, 610(610a, 610b), 620a, 620b... Gate driver IC, 601... Turn-on detection unit, 602, 602A, 602B, 602C, 602D, 622... Logic circuit, 603... Main voltage detection unit, 604... Main current detection unit, 621... Turn-off detection unit, P1, P2... PWM control command, Z... Impedance adjustment circuit

Claims

1. A gate drive device for driving semiconductor elements of upper and lower arms, comprising: an impedance adjustment unit that individually controls the impedance of the gate discharge paths of the upper and lower arms; the impedance adjustment unit sets a first impedance of the gate discharge path of the other arm during the on-switching period of one of the upper and lower arms to be higher than a second impedance of the gate discharge path of the other arm during the off-switching period of the one arm. A gate drive device.

2. In the gate drive device according to claim 1, the impedance adjustment unit changes the impedance of the gate discharge path of the other arm from the first impedance to the second impedance between the completion of turn-on and the start of turn-off of the one arm. A gate drive device.

3. In the gate drive device according to claim 1, the impedance adjustment unit includes a mirror clamp circuit that holds the impedance between the gate and the source of the semiconductor element at the second impedance. A gate drive device.

4. In the gate drive device according to claim 1, the first impedance is set to a value at which the semiconductor element of the other arm self-turns on when the one arm turns on. A gate drive device.

5. In the gate drive device according to claim 1, the impedance adjustment unit controls the impedance of the gate discharge path of the other arm to the first and second impedances based on the gate information of the one arm. A gate drive device.

6. In the gate drive device according to claim 1, the impedance adjustment unit includes at least one of a main voltage detection unit that detects the main voltage information of the other arm and a main current detection unit that detects the main current information of the other arm; the impedance adjustment unit controls the impedance of the gate discharge path of the other arm to the first and second impedances based on at least one of the main voltage information and the main current information. A gate drive device.

7. In the gate drive device according to claim 1, the impedance adjustment unit includes a capacitive element as an impedance adjustment element. A gate drive device.

8. In the gate drive device according to claim 1, The impedance adjustment unit includes a diode as an impedance adjustment element, and the gate driving device.

9. In the gate driving device according to claim 1, each of the upper and lower arms is composed of a plurality of semiconductor elements connected in parallel, the gate impedance of each of the plurality of semiconductor elements of the other arm is set so that the recovery surge of the plurality of semiconductor elements at the time of turn-on of the one arm becomes equal, and the gate driving device.

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