Semiconductor switch comprising short-circuit detection circuit

Abstract

To provide a semiconductor switch comprising a short-circuit detection circuit.SOLUTION: A semiconductor switch comprising a first main terminal, a second main terminal, and a control terminal, further comprises: a III-nitride high electron mobility transistor (HEMT) that comprises a first source terminal, a first drain terminal and a first gate terminal; a first interface circuit that is operatively connected to a control terminal and to the first gate terminal; and a short-circuit detection circuit that is operatively connected to the first drain terminal and the first surface terminal. The short-circuit detection circuit is configured to: detect a short-circuit across the first drain terminal and the first source terminal; and transmit a short-circuit detection signal to the first interface circuit. The first interface circuit is configured so that, upon receipt of the short-circuit detection signal, to cause the III-nitride HEMT to turn off and / or to cause a voltage across the first gate terminal to be reduced.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to semiconductor switches, and more particularly to semiconductor switches including group III nitride high electron mobility transistors (HEMTs), and semiconductor switches including short-circuit detection circuits.

Background Art

[0002] Gallium nitride (GaN) is a wide-bandgap material with properties suitable for use in several application fields requiring solid-state devices, such as high-frequency electronics, optoelectronics, and power electronics.

[0003] With GaN technology, transistors with high electron mobility and high saturation velocity can be designed. These properties of GaN make it an excellent candidate for high-power high-temperature microwave applications, such as for radar and cellular communication systems.

[0004] Furthermore, GaN's wide bandgap offers the possibility of emitting at higher frequencies, such as in the green, blue, violet, and ultraviolet portions of the electromagnetic spectrum.

[0005] More recently, gallium nitride (GaN) has been considered a very promising material for use in the field of power devices. The application fields range widely from portable household appliances, solar power inverters, electric vehicles, and power supplies. The wide bandgap of the material (Eg = 3.39 eV) results in a high critical electric field (Ec = 3.3 MV / cm), which can lead to the design of devices with a shorter drift region and thus a lower on-state resistance compared to silicon-based devices with the same breakdown voltage.

[0006] By using an aluminum gallium nitride (AlGaN) / GaN heterostructure, a two-dimensional electron gas (2DEG) can also be formed at the heterointerface, where the carriers can reach a very high mobility value (μ = 2000 cm 2 / (Vs)). Furthermore, due to the piezoelectric polarization charges present in the AlGaN / GaN heterostructure, the electron density in the 2DEG layer increases (e.g., 1 × 10 13 cm -2 ). These characteristics enable the development of high electron mobility transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. One of the common parameters used for the comparison of power semiconductor transistors is the specific on-state resistance or specific Rds(ON). The specific Rds(ON) is often the product of the resistance of the device and the area of the device on the wafer. Many studies have focused on the development of power devices using AlGaN / GaN heterostructures.

[0007] However, the 2DEG that inherently exists at the AlGaN / GaN heterointerface poses challenges when attempting to design enhancement-mode devices rather than depletion-mode devices. Nevertheless, several methods that can result in enhancement-mode devices have been proposed, such as the use of metal-insulator-semiconductor structures, the use of fluorine treatment, the use of recessed gate structures, and the use of p-type cap layers. Due to the relatively mature epitaxial growth of the pGaN layer and its ease of control compared to other techniques, pGaN / AlGaN / GaN HEMTs are currently a promising structure for commercialization. The high-frequency operation of GaN helps designers increase the power density of the device, thereby enhancing system efficiency and leading to cost reduction. High power density and system efficiency are particularly advantageous for high-power applications. In high-power applications such as motor control and inverters, enhancing short-circuit immunity is required. However, as the operating frequency increases, challenges arise in the design of short-circuit and overcurrent protection circuits for these GaN HEMTs. In addition, in motor control applications, it is highly desirable to enhance short-circuit durability. For example, in a half-bridge configuration, when the low-side device and the high-side device operate at different times in the on and off states, a short circuit can exist if both devices turn on due to a fault. This can be detected, and a signal to turn off the device can be sent to the controller / driver.

[0008] Conventional methods of short - circuit protection in silicon - based power devices such as IGBTs, by using an external circuit that detects when the device is in a saturated state, e.g., a non - saturated circuit, have a delay time in the range of 2 - 10 μs, which is potentially too large for GaN HEMTs to survive [1]. GaN HEMTs can fail in hundreds of nanoseconds under short - circuit conditions at high DC - link voltages [2]. Compared to other competing technologies such as IGBTs and SiC MOSFETs, the short time to failure of power GaN HEMTs is related to the improved specific Ron of the device and the lateral device configuration. Considering the short time to failure of GaN HEMTs, a method of short - circuit protection that can detect short - circuit events and protect the device in a shorter time is needed.

[0009] Methods of short - circuit detection can involve current or voltage sensing, and current or voltage sensing can have advantages and disadvantages. A shunt - current sensing resistor adds additional parasitic inductance to the circuit, which can adversely affect the switching performance and on - state losses of GaN HEMTs. In GaN circuits, since aggressive measures are taken to reduce stray inductance to improve switching performance without sacrificing on - state losses, voltage sensing across the common - source inductance (or resistance) is not practical for GaN. Therefore, alternative methods of short - circuit and over - current protection are sought for GaN devices. Recent research has proposed individual short - circuit / over - current protection circuits, but they are either limited to low - power circuits or require components that are not realistically achievable. Instead of implementing such functions individually, monolithic integration enables reduction of the overall system size / cost, reduction of the parts list, and improvement in performance due to reduction of parasitic components associated with the interconnection between individual devices.

[0010] Patent Document 1 provides an overcurrent protection and detection circuit that utilizes a current sense transistor (sense HEMT) that can be monolithically integrated with a main power switch. The sense HEMT can communicate with a mirror clamp to lower the voltage of the gate of the GaN power HEMT.

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0012]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0013] For the robust and reliable operation of group III nitride (e.g., GaN) power ICs (also called GaN chips), it is desirable to have a fast and robust short-circuit detection and protection method. The protection circuits proposed by the prior art require adding additional detection components to the circuit and / or have long detection times and protection times that are not suitable for protecting power GaN HEMTs.

[0014] The object of the present disclosure is to provide a short - circuit detection circuit (which may form part of a short - circuit protection circuit) that uses a minimum number of components and provides ultra - fast protection against short - circuit events. This can be achieved by a power integrated circuit including a power HEMT, a mirror clamp, an auxiliary GaN HEMT connected to the gate of the power HEMT, and a short - circuit detection block. Since these components are already monolithically integrated with the power HEMT, the proposed method provides a simple and cost - effective solution.

[0015] The short - circuit detection circuit can turn off the power HEMT via a short - circuit detection signal and / or lower the gate bias of the power HEMT.

[0016] Short - circuit events can be divided into at least two categories, which are generally referred to as type - 1 short - circuit events and type - 2 short - circuit events. An effective short - circuit protection solution needs to be effective in protecting the device against both type - 1 and type - 2. The protection time for type - 2 short - circuit events may need to be shorter than the reaction time for type - 1 short - circuit events. Therefore, additional circuit blocks can be specifically implemented for type - 2 short - circuits.

Means for Solving the Problems

[0017] As used herein, a semiconductor switch including a first main terminal, a second main terminal, and a control terminal, the semiconductor switch further includes a group - III nitride high - electron - mobility transistor (HEMT) including a first source terminal, a first drain terminal, and a first gate terminal, a first interface circuit operably connected to the control terminal and the first gate terminal, and a short - circuit detection circuit operably connected to the first drain terminal and the first source terminal and the short - circuit detection circuit includes detecting a short - circuit across the first drain terminal and the first source terminal, Transmitting a short - circuit detection signal to the first interface circuit A semiconductor switch is described that is configured to perform the above, and when receiving the short - circuit detection signal, the first interface circuit is configured to turn off the group - III nitride HEMT and / or lower the voltage across the first gate terminal.

[0018] The group - III nitride HEMT may be referred to as a "high - voltage HEMT" and / or a "power HEMT".

[0019] It should be understood that the terms "first", "second", "third", etc. used in this specification in relation to terminals and circuits are merely arbitrary designations for clarity.

[0020] As used in this specification, a "group - III nitride" transistor (e.g., HEMT), device, or integrated circuit may generally refer to a transistor or device based on group - III nitride - based materials including GaN, AlN, InN, and their alloys.

[0021] In some examples, the first interface circuit includes a pull - down transistor (e.g., a mirror clamp) and / or a voltage limiter. The pull - down transistor may be a "low - voltage" HEMT. The pull - down transistor may be a group - III nitride transistor.

[0022] In one example, the first interface circuit includes a pull - down transistor, and the pull - down transistor includes a second source terminal and a second drain terminal. The second drain terminal is operably connected to the first gate terminal. The second source terminal is operably connected to the first source terminal. The pull - down transistor is configured to turn on when the first interface circuit receives the short - circuit detection signal.

[0023] The pull-down transistor can be controlled via its gate terminal (referred to herein as the "second gate terminal").

[0024] The short-circuit detection signal can be directly supplied to the second gate terminal to control the pull-down transistor (for example, the first interface circuit can be configured to receive the short-circuit detection signal at the second gate terminal).

[0025] In some examples, the first interface circuit includes a pull-down transistor gate driver (e.g., a gate driver circuit) operably connected to the second gate terminal and configured to drive the second gate terminal. In such a case, the short-circuit detection signal can be supplied to the pull-down transistor gate driver (for example, the first interface circuit can be configured to receive the short-circuit detection signal at the pull-down transistor gate driver).

[0026] The first interface circuit may include an auxiliary gate interface circuit. The auxiliary gate interface circuit may include a voltage limiter. The auxiliary gate interface circuit may include an auxiliary group-III nitride HEMT (which may also be referred to as a low-voltage HEMT). The auxiliary gate interface circuit may include a voltage limiter. The auxiliary group-III nitride HEMT may include a third source terminal operably connected to the first gate terminal, a third drain terminal operably connected to the control terminal, and a third gate terminal operably connected to the voltage limiter. The voltage limiter may be configured to limit the voltage across the first gate terminal and the first source terminal. For example, the short-circuit detection signal can be received by the first interface circuit. When the first interface circuit receives the short-circuit detection signal, it can be configured to cause the voltage limiter to limit the voltage across the first gate terminal and the first source terminal to a certain voltage, for example, a gate voltage lower than that during normal operation. For example, the voltage limiter may be configured to lower the voltage across the first gate terminal and the first source terminal.

[0027] In some examples, it should be understood that the short - circuit detection signal can be received by both a pull - down transistor (the second gate terminal and / or the pull - down transistor gate driver) and an auxiliary gate interface circuit of the first interface circuit.

[0028] The semiconductor switch can include one or more signal conditioning circuits configured to condition the short - circuit detection signal. The signal conditioning circuit can be provided in one or more signal conditioning blocks.

[0029] Examples of signal conditioning circuits include a latch circuit, a diode with its cathode terminal connected to the second gate terminal (i.e., the gate terminal of the pull - down transistor), a diode such as a transistor, a resistor and / or a capacitor, a logic inverter, a buffer, and / or a level shifter.

[0030] In some examples, the semiconductor switch includes a latch circuit. The latch circuit can be configured to condition the short - circuit detection signal. For example, the latch circuit can be configured or arranged to receive and condition the short - circuit detection signal when the short - circuit detection signal is transmitted from the short - circuit detection circuit to the first interface circuit (e.g., the latch circuit can be arranged in the signal path of the short - circuit detection signal).

[0031] The latch circuit can be configured to supply an adjusted short - circuit detection signal that is held in a predetermined state until one or more release conditions are met (i.e., the latch circuit can maintain the adjusted short - circuit detection signal to the interface circuit until one or more release conditions are met, even if the short - circuit state does not exist in the HEMT). The one or more release conditions can include, for example, the expiration of a period (i.e., the latch circuit can hold the adjusted short - circuit detection signal over that period). In some examples, this period can range from 1 to 500 microseconds. Alternatively or additionally, the one or more release conditions can depend on a signal, such as a signal applied to the control terminal of a semiconductor switch. The signal to the control terminal of the semiconductor switch can be supplied from a gate driver (or controller), as is typical in power electronics circuits. The signal from the gate driver of the semiconductor switch that releases the latch can be high - to - low, indicating that the gate driver turns off the semiconductor switch, thereby eliminating the short - circuit state present in the HEMT).

[0032] The short - circuit detection circuit can include an unsaturated circuit configured to detect a voltage drop across a first drain terminal and a first source terminal. The unsaturated circuit can include at least one blanking resistor and at least one blanking capacitor. The time constant of the unsaturated circuit can be defined as the product of the resistance of at least one blanking resistor and the capacitance of at least one blanking capacitor. The unsaturated circuit can be configured to detect when a group - III nitride HEMT (a "high - voltage HEMT") is in a saturated state. The unsaturated circuit can be configured to detect when a specific voltage drop across the first drain terminal and the first source terminal is reached. The specific voltage drop can be significantly greater than the on - state voltage drop (e.g., 2V) but considerably less than the rated blocking voltage (e.g., 650V). For example, the specific voltage drop can be about 10V.

[0033] In some examples, the voltage drop is between 5V and 30V. In some examples, the time constant is between 50ns and 1 microsecond.

[0034] The short - circuit detection circuit may include a resistor - capacitor (RC) network (e.g., resistors and capacitors arranged in a loop). The short - circuit detection circuit may further include a HEMT called a sense HEMT. The sense HEMT may have the same geometry and architecture as the group - III nitride HEMTs (the "high - voltage HEMTs") described herein, but may have a relatively small gate width or area compared to the group - III nitride HEMTs (the "high - voltage HEMTs"). The sense HEMT may include one or more group - III nitride materials.

[0035] The sense HEMT may include a fourth source terminal operably connected to the RC network, a fourth drain terminal operably connected to the first drain terminal, and a fourth gate terminal operably connected to the first gate terminal.

[0036] The fourth source terminal may be further operably connected (e.g., directly or via an interface) to the second gate terminal (i.e., the gate terminal of the pull - down transistor). The sense HEMT may be configured to detect a voltage drop (due to a short - circuit) across the RC network, and when the voltage drop is detected, may be further configured to turn on the pull - down transistor. As an example, the voltage drop may be between 2V and 5V.

[0037] The short - circuit detection circuit may include a voltage detection circuit configured to compare the voltage across the first drain terminal and the first source terminal with a reference voltage and output a high - voltage detection signal when the voltage across the first drain terminal and the first source terminal exceeds the reference voltage, and a blanking - time circuit configured to output a blanking - time signal after a blanking period has elapsed.

[0038] The short - circuit detection circuit may be configured to transmit a short - circuit detection signal based on a high - voltage detection signal and a blanking - time signal (e.g., based on a combination of the high - voltage detection signal and the blanking - time signal). For example, the short - circuit detection circuit may further include a logic - combination circuit configured to receive the high - voltage detection signal and the blanking - time signal and output a short - circuit detection signal based on the combination of the high - voltage detection signal and the blanking - time signal.

[0039] The voltage detection circuit may be enabled to output a high - voltage detection signal indicating a short - circuit by the output of the blanking - time circuit.

[0040] The voltage detection circuit may include a differential - comparator circuit configured to compare the voltage across a first drain terminal and a first source terminal (which may be supplied as an input voltage to the differential - comparator circuit) with a reference voltage.

[0041] Any of the short - circuit detection circuit, pull - down transistor, auxiliary HEMT, interface, and / or voltage limiter may be monolithically integrated.

[0042] Any of the above - mentioned resistors, capacitors, and / or RC networks may be monolithically integrated with the group - III nitride HEMT. In some examples, one or more resistors or capacitors may be provided externally (e.g., one of the resistor and capacitor of the RC network may be provided on - chip and the other may be provided off - chip).

[0043] In one example, the first interface circuit includes an additional pull-down transistor (e.g., the first interface circuit may include an additional pull-down transistor), the additional pull-down transistor includes a fifth source terminal and a fifth drain terminal, the fifth drain terminal is operably connected to the first gate terminal, and the fifth source terminal is operably connected to the first source terminal. The additional pull-down transistor may be configured or optimized for controlling the group-III nitride HEMT and normal switching (e.g., turning off the device) in other states such as avoiding false turn-on events (e.g., operating as an active mirror clamp) when a short-circuit condition does not exist and during the operation of the group-III nitride HEMT. For example, the additional pull-down transistor may have a larger area or gate width compared to (other) pull-down transistors. For example, the additional pull-down transistor may have a lower on-state resistance than (other) pull-down transistors.

[0044] The additional pull-down transistor may be a "low voltage" HEMT. The additional pull-down transistor may be a group-III nitride transistor. The additional pull-down transistor may be a mirror clamp.

[0045] In some examples, the short-circuit detection circuit is configured to detect a fast positive voltage change over time (dV / dt) across the first drain terminal and the first source terminal. Such a fast dV / dt may indicate a type 2 short-circuit event.

[0046] The semiconductor switch may include a second short-circuit detection circuit.

[0047] The second short-circuit detection circuit may be configured to detect a positive voltage change over time across the first drain terminal and the first source terminal, and the second short-circuit detection circuit may be configured to transmit a (e.g., second) short-circuit detection signal when the positive voltage change over time exceeds a reference rate. For example, the reference rate may be 150 V / ns.

[0048] The (second) short-circuit detection signal generated by the second short-circuit detection circuit may be received by the first interface circuit.

[0049] In some examples, the semiconductor switch is a cascode.

[0050] In some examples, the semiconductor switch is a parallel connection of a plurality of group-III nitride switches.

[0051] In some examples, the semiconductor switch is a series connection of a group-III nitride switch with a level shifter.

[0052] In some examples, the semiconductor switch is a low-voltage auxiliary HEMT, a composite switch additionally including a low-voltage auxiliary HEMT including an auxiliary HEMT source terminal, an auxiliary HEMT drain terminal, and an auxiliary HEMT gate terminal, a voltage limiter operably connected to the auxiliary HEMT gate terminal, and a high-voltage transistor device including a first transistor device terminal, a second transistor device terminal, and a transistor device gate terminal, wherein the auxiliary HEMT source terminal is operably connected to the high-voltage HEMT gate terminal, the high-voltage HEMT source terminal and the first transistor device terminal are operably connected to a first main terminal, the high-voltage HEMT drain terminal and the second transistor device terminal are operably connected to a second main terminal, the auxiliary HEMT drain terminal and the high-voltage transistor device gate terminal are operably connected to a control terminal, the voltage limiter is operably connected to the high-voltage HEMT source terminal and the auxiliary HEMT gate terminal, and further, the voltage limiter is configurable to limit the voltage across the high-voltage HEMT gate terminal and the high-voltage HEMT source terminal.

[0053] The high-voltage transistor device may include silicon and / or silicon carbide transistors.

[0054] The high-voltage transistor device may include an insulated-gate bipolar transistor (IGBT). The first transistor device terminal may include the IGBT emitter terminal. The second transistor device terminal may include the IGBT collector terminal.

[0055] The high-voltage transistor device may include a metal-oxide-semiconductor field-effect transistor (MOSFET). The transistor device terminal may include the MOSFET source terminal. The second transistor device terminal may include the MOSFET drain terminal.

[0056] The high-voltage transistor device may include a super junction. The first transistor device terminal may include the super junction source terminal. The second transistor device terminal may include the super junction drain terminal.

[0057] Also described herein is a system that includes the semiconductor switch described herein and an external gate driver (or controller). The external gate driver / controller may be configured to control a Group-III nitride HEMT (e.g., the external gate driver may be operably connected to the first gate terminal). The short-circuit detection circuit may be configured to transmit a short-circuit detection signal to the external gate driver. For example, the short-circuit detection signal may be supplied to the external gate driver / controller as a fault signal. The external gate driver / controller may register that the semiconductor switch is experiencing a short-circuit condition.

[0058] The external gate driver may be configured to turn off the semiconductor switch when the external gate driver receives the short-circuit detection signal. Thus, the external gate driver may provide additional protection to the Group-III nitride HEMT. For example, a short-circuit protection circuit (which may be on-chip and / or monolithically integrated with the Group-III nitride HEMT) may protect the Group-III nitride HEMT until sufficient time has elapsed for the external gate driver / controller to report the fault.

[0059] The short - circuit detection circuit can be configured to reset when receiving a reset signal from an external gate driver / controller. For example, the reset of the latch in the short - circuit detection circuit can depend on the reception of the reset signal. The reset signal can be the first high - to - low signal or the count of the subsequent number of signals.

[0060] In addition, this specification describes a system including a plurality of semiconductor switches connected in parallel. The first semiconductor switch among the plurality of semiconductor switches includes a first parallel - mode detection circuit. The second semiconductor switch among the plurality of semiconductor switches includes a second parallel - mode detection circuit. The short - circuit detection circuit of the first semiconductor switch is configured to send a short - circuit detection signal to the first parallel - mode detection circuit, and the first parallel - mode detection circuit is configured to send the detection signal to the second parallel - mode detection circuit when receiving the short - circuit detection signal. The second parallel - mode detection circuit is configured to turn off the second semiconductor switch when receiving the detection signal.

[0061] For example, a plurality of semiconductor switches are all connected in parallel, each of the semiconductor switches includes a parallel - mode detection circuit, and all the parallel - mode detection circuits can be connected to each other. When the short - circuit detection circuit of any one of the plurality of semiconductor switches detects a short - circuit, the short - circuit detection circuit can turn off each semiconductor switch. At the same time, the signal detection signal is sent to the other semiconductor switches among the plurality of semiconductor switches to also turn off these other semiconductor switches.

[0062] In some examples, the semiconductor switch can include one or more composite switches including a cascode device and / or a group - III nitride switch in parallel with a high - voltage transistor switch made of a material other than group - III nitride.

Brief Description of the Drawings

[0063] Here, the present invention will be described as an example with reference to the following drawings.

[0064]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42

Figure 43

Figure 44

Figure 45

Figure 46

Figure 47

Figure 48

Figure 49

Figure 50

Figure 51

Figure 52

DETAILED DESCRIPTION OF THE INVENTION

[0065] FIG. 1 shows a schematic circuit diagram of an over - current protection circuit according to (Patent Document 1). The content of (Patent Document 1) is hereby incorporated by reference in its entirety. (Patent Document 1) describes a resistor and an active - switching low - voltage depletion - mode transistor (second transistor) that controls the potential of the gate terminal of a main power transistor. The over - current protection circuit includes a first power transistor 19 composed of a current - sensing transistor 16 and a main power transistor 19, a depletion - mode transistor (second transistor) 14, and a current - sensing resistor 15.

[0066] When the current detection transistor 16 detects an excessive drain current state, the circuit operates to lower or limit the gate voltage of the first power transistor 19 by using the above-described depletion mode device 14 and resistor 15 or resistive element. When an overcurrent state is detected, the voltage drop across the current detection resistor 15 increases, and thus the voltage bias to the gate terminal of the transistor 14 increases, rapidly decreasing the resistance of the transistor 14. As a result, the resistance of the path between the gate and the source of the first power devices 16, 19 decreases, and thus the potential of the first gate terminal is limited.

[0067] Figure 2. The semiconductor switch includes a high-voltage group III nitride power HEMT 101, an (first) interface circuit 1000 having at least one connection to a control terminal and at least one connection to an internal gate of the high-voltage HEMT, and a short-circuit detection circuit 300 having at least one connection to the drain of the HEMT, at least one connection to the source of the HEMT, and at least one connection to the interface circuit. In an example according to the present disclosure, the group III nitride power HEMT is a high-voltage lateral GaN HEMT. The interface circuit 1000 is disposed immediately before the gate of the high-voltage lateral GaN HEMT to adapt the drive voltage of the control terminal to be appropriate and acceptable for the GaN HEMT. This interface can preferably be integrated monolithically with the power HEMT to provide low parasitic components, ease of manufacture, and a fast response speed. Alternatively, this interface can be part of another chip (such as a silicon companion chip or a driver chip). For example, the drive voltage on the control terminal can be set to 0V to 20V while keeping the drive voltage directly seen by the gate terminal of the lateral high-voltage GaN HEMT at 0 to 7V.

[0068] As shown in Figure 3, the first interface circuit 1000 may include a mirror clamp transistor 102 and / or an auxiliary gate interface 200.

[0069] The mirror clamp transistor 102 can function as a pull-down device connected between the gate and source of the power HEMT to ensure fast and safe turn-off, enhance immunity to dV / dt, and avoid the need to use a negative gate voltage to turn off the power HEMT. As another example, the output signal of the short-circuit detection block 300 can function as an input to the gate of the mirror clamp transistor (or the gate driver of the mirror clamp transistor, MCD) such that the mirror clamp turns on the power HEMT and turns it off when a short circuit is detected.

[0070] As shown in FIG. 4, the auxiliary gate interface 200 may include a short-circuit protection function. The interface may further include other clamping circuits, sensing and protection functions, and pull-down devices to ensure fast and safe turn-off, enhance immunity to dV / dt, and absorb any transient voltage peaks on the gate. The short-circuit detection block is configured to change its output signal when a short circuit is detected across the power HEMT, for example, to have a low output signal when no short circuit is detected and a high output signal when a short circuit is detected. The short-circuit output signal can function as an input to the auxiliary gate interface block such that the auxiliary gate interface block turns off the power HEMT or adjusts the voltage at the gate terminal of the power HEMT to a low voltage. Reducing the bias at the gate terminal of the power HEMT can be beneficial in extending the time for the power HEMT to survive a short-circuit event, as reducing the gate bias can lead to a decrease in the saturation current of the power HEMT in a short-circuit condition.

[0071] In some examples, as shown in FIG. 5, the short-circuit detection signal can function as an input to both the mirror clamp drive / transistor and the auxiliary gate interface block 200.

[0072] The output of the short - circuit detection block can be applied directly to the above - mentioned circuit block, or can be applied indirectly through some additional circuit blocks, such as signal conditioning blocks and / or latch circuit blocks. Embodiments of these additional circuit blocks will also be described herein. As an example, these additional circuit blocks can be monolithically integrated with the power HEMT devices that form the GaN power IC.

[0073] FIG. 6 shows a schematic example of sub - blocks of the short - circuit detection block 300. The short - circuit detection block can be configured to include a Vds detection block 3001 that can detect whether the drain - source voltage (Vds) across the device exceeds a set reference value, thereby detecting that the power HEMT may be in a short - circuit state. Nevertheless, the state where the drain - source voltage of the device exceeds the set reference value exists not only during a short - circuit event, but rather can also exist during the off - state of the power HEMT. Further, Vds may exceed the set reference value for a short time during the switching event of the device. In order to avoid "false - triggering" the short - circuit detection circuit by detecting a short - circuit event when there is no short - circuit event, a blanking - time block can be configured. The blanking - time block 3002 can output a signal after a set time has elapsed. The control signal of the power HEMT can be used as an input to the blanking - time block such that time measurement starts only when the control signal indicates that the power HEMT is in the on - state.

[0074] The outputs of the Vds detection block and the blanking - time block can be used to detect whether a short - circuit event has occurred in the power HEMT. For example, an AND function may be appropriate such that a short - circuit is detected only when Vds exceeds the reference value and the blanking time has elapsed. The functions of the Vds detection block and the blanking - time block can be combined in a single circuit. Instead, the functions of the Vds detection block 3001, the blanking - time block 3002, and the combination logic function 3003 can be combined in a single circuit.

[0075] FIG. 7 shows an additional example of a sub-block of the short-circuit detection block 300. In this example, the blanking time block 3002a can act on the Vds detection block 3001a to enable the operation of the Vds detection block 3001a so that a high Vds signal can be detected only when the blanking time has elapsed. The logic function block can be an optional block.

[0076] FIG. 8 shows a schematic diagram of an example of a short - circuit detection (SCD) circuit block 300. In this example, the SCD block 300a includes an additional HEMT that functions as a current - sense transistor (sense HEMT) 104, an RC network 301, and a comparator 302. The sense HEMT and the power HEMT can be the same in terms of structure, but the main power HEMT has a much larger active area than the sense HEMT (e.g., 10 times, 100 times, 1000 times). The power HEMT and the sense HEMT have their drains connected together and their gates connected together, but their source terminals are separate. The sense HEMT can be used to detect the current flowing through the source of the main - power transistor to identify the short - circuit state of the power HEMT. The sense HEMT can be driven by a control signal or, as shown in FIG. 9, when an auxiliary - gate interface is used, by the signal that drives the power HEMT. When the control signal is high, i.e., indicating that the power HEMT is in the on - state, the sense HEMT is also on, and the capacitance of the RC network is charging through the sense HEMT. Therefore, since the control signal needs to be high for a certain period of time for the capacitance to be charged to a sufficient level, the RC network can set a blanking time. When a short - circuit occurs, since V(T2)−V(T1) increases significantly, the current flowing through the sense HEMT increases. Since the sense HEMT can enter a saturation state, the current through the device undergoes a limited process. When the RC network is fully charged during the short - circuit, the voltage at the source of the sense HEMT can exceed a reference value (Vref). In this state, the signal at the output of the comparator can change, for example, from low to high. Therefore, the circuits shown in FIGS. 8 and 9 can include all the functions of the SCD block described in FIG. 6.

[0077] FIG. 10 shows a schematic diagram of an additional example of a short - circuit detection (SCD) circuit block 300. The circuit 300b in this example includes a high - voltage diode 305, an RC network 304, a current source 303, and a comparator 302. When V(T2)−V(T1) is low, the HV diode is forward - biased and thus sinks the current from the current source. When V(T2)−V(T1) is high, the HV diode is reverse - biased, and the capacitance in the RC network can be charged up to V(T2)−Vth. Vth is the threshold voltage of the high - voltage diode 305. When C is charged above Vref, the comparator can change from low to high.

[0078] To prevent the RC network from being charged during the off - state of the device and to be charged only during a short - circuit state, a high V(T2)−V(T1) is required and the power HEMT needs to be in the on - state. To add this functionality, a transistor 306 can be included. The transistor 306 is driven by a control signal or a signal - conditioned version of the control signal. Signal - conditioned means, for example, that the signal is level - shifted and / or inverted.

[0079] FIG. 11 shows a schematic diagram of an example of the VDS detection block 3001 of FIG. 6. This circuit 3001a is configured such that when the drain - source voltage (V(T2)−V(T1)) across the power HEMT exceeds a set reference value, the output changes. The detection block 3001a operates as a differential circuit to provide higher accuracy over process and temperature variations. Each leg of the differential circuit includes a HV diode, a current source, and a current - to - voltage converter. The voltage from each leg of the differential circuit is configured as an input to the comparator. In this configuration, when V(T2)−V(T1) exceeds Vref, the output of the comparator changes.

[0080] FIG. 12 shows a schematic diagram of an example of the VDS detection block 3001 in FIG. 7. This circuit 3001a1 is configured such that when the drain-source voltage (V(T2) - V(T1)) across the power HEMT exceeds a set reference value, the output changes. However, the comparator in this block is enabled by the BLK_enable signal, which is the output of the blanking time block, and the BLK_enable signal is output only when the set blanking time has elapsed. Therefore, the output of the VDS detection block changes only after the blanking time.

[0081] FIG. 13 shows an example of a VDS detection block similar to the embodiment in FIG. 11. In this embodiment, the HV diode is implemented using a high-voltage HEMT with the source-gate connected.

[0082] FIG. 14 shows an example of a VDS detection block similar to the above embodiment. Vref is applied directly to the gate of transistor 308.

[0083] FIG. 15 shows an example of a VDS detection block similar to FIG. 14, which includes a glitch filter (low-pass filter) at the input of the comparator. This filter is included to avoid changes in the output of the comparator circuit due to noise or other high-frequency signals in Vds. Similar glitch filters can also be added to other examples of the VDS detection blocks included in this specification.

[0084] FIG. 16 shows an example of a blanking time block 3002 as shown in FIG. 6. The blanking time block 3002a outputs a signal after a certain time has elapsed. The blanking time block 3002a includes an RC blanking circuit connected to the voltage source VDD through respective current sources. The low voltage transistor 313 is connected across the blanking capacitor CBLK. As an example, the transistor 313 can be a low voltage p-GaN gate HEMT. The blanking time block receives, as an input from the control terminal of the power HEMT 101, a control signal or alternatively an adjusted version of the control signal, as shown in FIG. 6. The inverted, preferably level-shifted version of the control signal can be connected to the transistor 313 as a "reset" signal. This signal conditioning of the control signal can be done internally or externally to the blanking time block and is not shown here for simplicity.

[0085] FIG. 17 shows the voltage values at the input of the comparator Comp3 with respect to the reset input level and at the output of the blanking time block. When the control signal is low (reset is high), the transistor 313 turns on and pulls Vcap to ground, discharging the capacitor CBLK. When the control signal goes high, the reset input goes low. The transistor 313 turns off, thereby enabling the charging of the capacitor CBLK by the current source through the voltage source VDD. When Vcap (curve 2 in FIG. 17) exceeds Vref1 (curve 1 in FIG. 17), the output goes high. In summary, the output of the circuit in FIG. 16 does not change from low to high until a predetermined time has elapsed after the control signal changes from low to high. This time can be defined as the blanking time. The blanking time can be made shorter or longer based on the selection of the value of the current source and / or the value of the capacitor. The blanking time defined by the circuit can vary due to process variations in the values of the above-described components.

[0086] As described above, the blanking time is used to define the time during which the SCD circuit cannot detect a short - circuit event at the start of the on - pulse of the power HEMT in order to avoid accidentally triggering the short - circuit protection circuit during normal device switching. Therefore, it may be desirable to match the process variations of the blanking time with the process variations of the switching time of the power HEMT. For example, when used in a circuit that includes a power HEMT for which the completion of a switching event takes a long time, a longer blanking time may be desirable (and vice versa). A circuit that can achieve better process matching between the power HEMT and the blanking - time circuit is shown in FIG. 18.

[0087] FIG. 18 shows another example of the blanking - time block 3002 as shown in FIG. 6. In this example, the blanking - time block 3002b is designed to take into account the process variations of the power HEMT and is configured to calculate the overall blanking time based on the Rdson of the power HEMT. To achieve this, the same small - sized HEMT 315 as the power HEMT is provided across the capacitor CBLK. Thus, the discharge rate of CBLK depends on the Rdson of the small - sized HEMT and thus indirectly on the Rdson of the power HEMT. This is because the small - sized HEMT and the power HEMT are expected to vary in the same way when there are process variations. The small - sized HEMT 315 and the power HEMT may be the same in terms of structure, but the main power HEMT has a much larger active area than the small - sized HEMT (e.g., 10 times, 100 times, 1000 times). The output of logic 1 depends on RBLK2 and CBLK. The output of logic 1 drives the small - sized HEMT 315 and also functions as an enable signal for the comparator Comp3b. Thus, the output of logic 2, which is also the output of the entire blanking - time block 3002b, depends on RBLK1, the small - sized power HEMT 315, and CBLK, similar to the output of logic 1.

[0088] FIG. 19 shows an example of a circuit 500 that can be connected between the output of the SCD block 300 and an auxiliary gate interface and a mirror clamp / mirror clamp drive circuit. The output of the SCD block can indicate whether a short circuit event has occurred in the power HEMT 101, but may require some signal conditioning to be suitable for use as an input to an auxiliary gate interface and a mirror clamp that can function to protect the power HEMT. The signal conditioning blocks 501 and 503 can refer to circuits that cover functions such as level shifting, buffering, filtering, or some combination logic with other detection signals in the power IC. Additionally, a latch circuit block 502 may be required. The function of the latch circuit block 502 is to hold a signal indicating that the power HEMT is in a short circuit event in a set state until another condition is met. This is to avoid oscillation of the short circuit event detection and protection circuit. The additional conditions can be time-dependent, signal-dependent, or both. An example of a time-dependent condition can be that enough time has elapsed for the device to sufficiently dissipate the heat generated during the short circuit event since the short circuit event occurred. An example of a signal-dependent condition can be that a high-to-low control signal pulse is received from the power HEMT gate driver. In one example, a logic function of two conditions, such as both the elapsed time and the high-to-low pulse from the gate driver, may be required for the latch to be released. The above embodiments are only examples of the circuit 500, and it should be noted that the blocks 501, 502, and / or 503 are all optional, so any combination of the blocks 501, 502, and / or 503 may be included.

[0089] FIG. 20 shows an example of a mirror clamp drive (MCD) block 400 that is part of the power integrated circuit shown in FIGS. 3 and 4. The mirror clamp driver 400a is composed of a logic inverter 401 configured to operate an active switching mirror clamp transistor 102 that functions as a pull-down network. The logic inverter 401 can be composed of a resistor or a resistive element (i.e., a load transistor or a current source) and an enhancement mode transistor. FIG. 21 shows an example of an implementation form of the logic inverter 401 in the block 400a. However, this is merely provided as an exemplary configuration, and other logic inverter designs may be used instead of or in addition to this.

[0090] During operation, the logic inverter is operably connected to a control signal from a control terminal or an external gate terminal (i.e., the terminal connected to the gate driver). When the control signal is high, the bias of the gate of the active switching transistor in the mirror clamp 102 is low (and thus its resistance is high), and vice versa.

[0091] FIG. 22 shows an exemplary implementation form of the mirror clamp drive (MCD) block 400 when the mirror clamp drive (MCD) block 400 operates based on a short circuit detection signal (SCD). The mirror clamp driver 400b is composed of a logic inverter 404 and a logic gate (NAND gate) 405. In this scenario, the mirror clamp driver 400b has two input signals, namely a control signal and a short circuit detection signal SCD or an adjusted version of SCD based on FIG. 19 (SCDC). When the SCD / SCDC signal is high or the control signal is low, the drive block 400b outputs a high signal to activate the mirror clamp transistor 102 that functions to pull down the gate of the power HEMT 101.

[0092] FIG. 23 shows an example of an implementation form of the mirror clamped drive block 400b in FIG. 22. However, this is merely provided as an exemplary configuration, and other circuit designs may be used instead of or in addition to this.

[0093] FIG. 24 shows an example of an auxiliary gate interface block 200 which is part of the power integrated circuit shown in FIGS. 2, 3, 4, and 5. The integrated auxiliary gate interface block (200) is preferably composed of an auxiliary GaN HEMT 201 which may be a low-voltage device, and the high-voltage power HEMT has its gate connected to the source of the auxiliary GaN HEMT with the gate integrated, and the auxiliary GaN HEMT has its drain connected to the control terminal of the power integrated circuit (power IC). The auxiliary GaN HEMT is configured to adapt the drive voltage of the control terminal to an appropriate and acceptable value for the GaN HEMT.

[0094] The current control block 202 is connected between the drain terminal and the gate terminal of the auxiliary GaN HEMT 201. The current control block has one connection to the control terminal. The current control block may be a resistive element or may incorporate a resistive element. Alternatively, the current control circuit may be, for example, a current source as shown here or may include a current source. However, this is merely shown as an exemplary configuration, and other circuit designs may be used instead of or in addition to the current source.

[0095] The integrated voltage limiting block 203 is connected between the gate terminal of the auxiliary HEMT and the low voltage terminal of the power integrated circuit. When the voltage signal on the control terminal increases linearly, the voltage drop across the auxiliary gate interface block 200 is non-linear. The low gate leakage current of the high voltage power HEMT is achieved by limiting the potential of the gate (active gate) terminal of the power HEMT. This is achieved by enabling the voltage drop across the integrated auxiliary gate interface block. The limitation of the potential of the power HEMT gate terminal is defined by appropriately designing the current control block and the voltage limiting circuit block such that when the gate signal of the control terminal of the power IC increases beyond a certain level, the gate of the auxiliary GaN HEMT is pulled down. Thus, the gate voltage operating window of the power IC (i.e., the voltage operating window applied to the control terminal) is larger than that of a conventional GaN HEMT.

[0096] Since the auxiliary GaN HEMT is preferably a low voltage device, its source and drain terminals are generally made symmetrically (or similarly) and can therefore be interchangeable. A low voltage device typically means a device that can have a rated breakdown of less than 20V and a limited current capability (less than 100mA). However, it should be understood that the auxiliary gate, while increasing cost and complexity, can also be a high output or high voltage device.

[0097] FIG. 25 shows another implementation form of the auxiliary gate interface block 200 having an exemplary configuration of the voltage limiter 203 with the pull-down HEMT204 in a threshold multiplier configuration. The threshold multiplier configuration in this embodiment includes a voltage divider (R6 and R7) and a pull-down enhancement mode HEMT204, and the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT204. In this embodiment, the upper part of the voltage divider is connected to the drain of the pull-down enhancement mode HEMT204 and the gate terminal of the auxiliary GaN HEMT201. The gate potential of the HEMT204 is controlled to set the voltage drop across the pull-down HEMT204, and this voltage drop can be controlled by the selection of the resistors in the described voltage divider. Thereby, the gate voltage of the auxiliary GaN HEMT201 and the voltage drop across the auxiliary gate block are limited. This function can protect the power HEMT gate terminal from overvoltage events.

[0098] FIG. 26 shows an exemplary implementation form of the auxiliary gate interface block 200 when the auxiliary gate interface block 200 operates based on the short circuit detection signal (SCD). The auxiliary gate interface block 200c includes an additional HEMT205 connected in parallel to the voltage limiter of the circuit shown in FIG. 24. The gate of the additional HEMT205 is connected to the short circuit detection signal SCD or an adjusted version of the SCD (SCDC). When a short circuit is detected and the SCD / SCDC signal is high, the HEMT205 is turned on to pull down the gate of the auxiliary GaN HEMT201 to ground. Thereby, the auxiliary GaN HEMT is turned off, and thus the gate and control terminals of the power HEMT are effectively electrically disconnected. In this state, when the bias of the power HEMT gate is lowered or grounded, a high signal from the control terminal cannot bring about a high signal of the power HEMT gate.

[0099] Figure 27 shows another example of how the auxiliary gate interface block provides protection during a short - circuit condition. In this example, the voltage limiter circuit 206 includes an additional resistor R8 added in series with the voltage divider R6 / R7. An additional HEMT 205 is connected in parallel with resistor R6 such that when SCD / SCDC is high (short - circuit condition), the resistance ratio of the voltage divider changes to short - circuit resistor R6. The changed resistance ratio helps to vary the adjusted voltage applied to the gate of the auxiliary GaN HEMT. Reducing the adjusted voltage of the power HEMT's gate is beneficial in a short - circuit condition because it reduces the saturation current of the power HEMT and allows the power HEMT to survive the short - circuit condition for a longer time until it fails.

[0100] Figure 28 shows another exemplary implementation of how the auxiliary gate interface block provides protection during a short - circuit condition. Here, the voltage divider is connected between the gate of the power HEMT 101 and the low - voltage terminal of the power IC. Thus, when the SCD / SCDC signal goes high, the resistance ratio of the voltage divider changes, thereby changing the adjusted gate voltage of the auxiliary GaN HEMT.

[0101] Figure 29 shows another exemplary implementation of how the auxiliary gate interface block provides protection during a short - circuit condition. This example operates similar to the example of Figure 26 but includes an additional transistor 207 and resistor R9. These components are included to limit the potential across the current source 202 when transistor 205 is turned on when a short - circuit event occurs.

[0102] Figure 30 shows another exemplary implementation of how the auxiliary gate interface block provides protection during a short - circuit condition. This example operates similar to the example of Figure 29 but includes an additional circuit 208. Generally, in the examples of the auxiliary gate interface presented herein, there is a trade - off between bandwidth and power consumption. In this example, by including circuit 208, the power loss of the auxiliary gate interface can be high during normal operation and low during the occurrence of a short - circuit event.

[0103] Figure 31 shows another aspect of the present disclosure. Short-circuit detection and protection can be performed through a series of detection and protection phases, rather than a single short-circuit detection step. A plurality of short-circuit detection circuits that each generate a series of SCD signals with different voltage references for the Vds detection block and different blanking times can be connected between the drain and source of the power HEMT. These signals function with respect to the auxiliary gate interface to adjust the gate voltage of the power HEMT, or function with respect to the mirror clamp to pull down the gate of the power HEMT. The advantage of having a plurality of signals is that the signal from the detection block with a lower reference voltage can adjust the gate voltage by less than the signal from the detection block with a higher reference voltage. Since the blanking times are different for all SCD blocks, these signals will not all go high at the same time. Thus, this provides a mechanism for gradually adjusting the operation of the power device, avoiding the device suddenly and completely turning off at the start of a short-circuit event. If the short-circuit event persists beyond a certain limit over a longer period of time, the gate of the power HEMT is completely pulled down, thereby being able to completely turn off the power HEMT, rather than simply regulating its saturation current during the short-circuit state. The SCD blocks 300_1 to 300_n can be implemented based on any of the previous embodiments.

[0104] FIG. 32 shows an exemplary implementation of the short - circuit detection and protection mechanism described in FIG. 31. This implementation follows the detection mechanism shown in FIG. 8. Here, the sense HEMT includes a series of RC networks, and each RC network can have an output signal that can be compared with its respective reference value to output a series of short - circuit detection signals. As an example, four RC networks that generate SCD signals 1 - 4 are shown in FIG. 32. However, it should be understood that the number of RC networks can be less or more. Based on the values of the RC networks and the reference voltage levels, as the short - circuit state progresses and can increase the drain - source voltage of the power HEMT, the SCD signals shift to high values. These signals or their respective adjusted versions (SCDC) act on voltage limiters (including a plurality of diodes connected in series in this example) at various levels to gradually reduce the gate voltage of the power HEMT, reducing the gate voltage by a larger value each time the SCD signal goes high. Thus, the gate voltage of the power HEMT is then gradually controlled not to completely turn off the operation of the power HEMT, but to reduce its operation. The schematic diagram does not show the application of the SCD signals to the mirror - clamp drive simply for simplicity. If the mirror - clamp should be turned on to pull down the gate of the power HEMT to the low voltage level of T1, any one or more of the SCD / SCDC signals can be applied to the mirror - clamp drive based on the level of SCD.

[0105] FIG. 33 shows another example of the step - by - step adjustment of a power HEMT in a short - circuit state. In this example, instead of a series connection of a resistor with one sense HEMT, a plurality of sense HEMTs are connected in parallel with an RC network connected as a detection load for each sense HEMT. Although three sense HEMTs are shown as an example, it should be understood that fewer or more sense HEMTs can be connected in the same way. The dotted lines connecting the RC network to the SCD signal are shown as placeholders for respective comparators not shown for simplicity. In this configuration, based on each reference value, some of the first SCD signals such as SC5 and SCD6 provide an initial indication of the presence of a short - circuit, and thus these signals or their adjusted versions can be applied to the voltage limiter of the auxiliary HEMT to adjust the operation of the power HEMT at an initial stage. Even after adjustment, a signal compared with a higher reference value (e.g., SCD7) may remain high indicating a short - circuit, in which case this signal can be supplied as an input to a mirror - clamped drive that turns the power HEMT completely off.

[0106] FIGS. 34 and 35 show two examples of the comparators (302, 312) mentioned in the previous embodiments. The comparator circuit receives the voltage measured in each circuit (Vds detection block or blanking circuit block or any other circuit) as one input signal and includes a fixed reference voltage as another input. The reference voltage can be generated on - chip or applied externally. However, it should be understood that these circuits 302a and 302b are provided merely as exemplary configurations, and other circuit designs can be used instead of or in addition to these.

[0107] The comparator circuit 302a shown in FIG. 34 includes an initial inverting differential amplifier stage 302a1, a transconductance amplifier stage 302a2, and a current subtractor stage 302a3. The differential amplifier 302a1 can be implemented using a differential pair (also known as a long-tail pair) that includes two enhancement-mode transistors, two resistors, and a current source. The differential amplifier generally performs two main functions in this circuit. That is, it amplifies the comparator differential input signal and sets the bias point of the next stage to bias the transconductance amplifier stage 302a2 into the high-gain region. The transconductance amplifier 302a2 receives the differential input voltage from the differential amplifier 302a1 and supplies a differential current output (Ix, Iy) to the current subtractor stage 302a3. The transconductance amplifier includes a differential pair having two enhancement-mode transistors and a current source. The current subtractor stage can be implemented using a current mirror block such that V out is high when Ix - Iy is negative and V out is low when Ix - Iy is positive.

[0108] The transconductance amplifier stage and the current subtractor stage enable a rail-to-rail comparator output. In this example, rail-to-rail means that V DD is the high output and V SS is the low output.

[0109] FIG. 35 shows another example of a comparator circuit (302, 312). The comparator circuit 302b includes three stages, namely a differential voltage-to-current conversion stage, a current comparator stage, and a current-to-voltage converter stage. The differential voltage-to-current stage can be implemented using a differential pair of two enhancement-mode transistors and a current source. This stage receives the measured voltage from each circuit as one input and a predetermined voltage reference as the second input, and converts them into respective current signals. The current comparator stage generates a differential current signal equal to the difference between the two inputs. The last stage converts this differential current to generate a voltage output. This example also enables a rail-to-rail comparator output. In this example, rail-to-rail means that V DD is the high output and VSS indicates a low output.

[0110] FIG. 36 shows a schematic example of a power integrated circuit connected to a gate driver. The gate driver is configured to supply a gate drive signal (control signal) to a control terminal of the power IC. The gate driver and the power IC can be powered by a voltage source VDD. The gate driver in this example is provided with a DESAT pin that provides a non-saturation protection function. This function generally exists in gate drivers for in-vehicle inverter applications. When the voltage at the DESAT pin exceeds the threshold voltage, the driver starts a safe turn-off procedure to protect the power semiconductor switch. The short-circuit detection signal SCD can be connected to the DESAT input of the gate driver. When a short-circuit event occurs, the SCD signal goes high and acts on the auxiliary gate interface circuit and / or the mirror clamp driver to internally protect the power HEMT as shown in the above embodiments. At the same time, this signal also triggers a fault detection at the DESAT pin for the driver to start a safe turn-off. The blanking time circuit of the short-circuit detection block helps to avoid unintentional trips of the DESAT protection.

[0111] FIG. 37 shows another example of the connection between the power integrated circuit and the gate driver. In this implementation, the SCD signal is adjusted through a combination of signal conditioning blocks that are part of the 500 shown in the previous embodiment. The adjusted signal SCDC is applied to the DESAT pin of the driver and is also applied to the auxiliary gate interface (200) and / or the mirror clamp driver (400).

[0112] Figure 38 shows an additional example of how a short - circuit event in a power IC can be reported to a gate driver having a DESAT function. In this example, when a short - circuit event occurs, the power IC may have an open - drain output. The open - drain pin can be implemented using a pull - down transistor as shown, which is on when no short - circuit event is occurring and off when a short - circuit event is occurring. This open - drain pin can be connected to the DESAT pin of the gate driver. The gate driver may include an internal pull - up component, such as a current source as shown in Figure 38. When the output of the power IC is open - drain, the gate driver can pull up this node. A capacitor can be connected to this node to set the time it takes to pull up this node to a predetermined voltage. This may be necessary to avoid oscillation and false triggering of the gate - driver protection function. When the voltage of the DESAT pin exceeds the internal reference value of the gate driver, the gate driver can turn off the power IC and supply a low OUT signal to protect the power HEMT. It should be noted that this protection loop implemented by the gate driver may be too slow to protect the power HEMT, so the on - chip protection circuit described in the previous example is still necessary.

[0113] Figure 39 shows a timing graph of the pulse train during a short - circuit event of type 1. Thereby, the blanking - time circuit operates and after the preset blanking time has elapsed, the output of the blanking - time circuit goes high. When the blanking - time signal goes high, a VDS detector as shown in FIG. 7 can be enabled, and Vds across the device goes high when it exceeds the set reference value. The high SCD signal (or an adjusted version of the SCD signal) pulls down the gate of the power HEMT through the auxiliary gate - interface circuit and / or the mirror clamp, even if the output of the external gate driver can be high. Thereby, the power HEMT device is freed from the large current caused by the short - circuit event, avoiding device failure. As shown in FIG. 19, the SCD signal can pass through a series of signal - conditioning blocks and latch circuits. The latch circuit 502 can hold the SCD signal high based on time - dependent conditions and / or until the signal - dependent conditions are met. This adjusted signal (or the direct SCD signal) can be reported off - chip (e.g., as an input to the DESAT pin of the gate driver) to initiate a safe turn - off procedure of the gate driver / controllers in the system, as shown in FIGS. 37 and 36.

[0114] In practice, there can be a delay between short - circuit detection and the turn - off of the power HEMT. This should be minimized as much as possible.

[0115] Similarly, there may be delays between other signals shown in FIG. 39. As discussed, these delays can be minimized by the monolithic integration of the presented circuit blocks to enable overall faster short - circuit detection and protection.

[0116] Figure 40 shows another aspect of the present disclosure, where the power integrated circuit can enable short - circuit detection in a parallel connection. In a parallel implementation, when one of the devices detects a short - circuit state, the power ICs can communicate with each other. The power IC is connected to VDD and is provided with a short - circuit input / output pin (SCIO) that is high during normal operation. For all power ICs connected in parallel, their SCIO pins are connected to each other. Additionally, the power IC may include a parallel - mode detection block (600) that helps each IC take countermeasures based on the other ICs connected in parallel.

[0117] As an example, the parallel - mode detector block may include an e - mode HEMT device with its drain connected to the SCIO pin, as shown in Figure 41. During normal operation, the SCIO pin has the same voltage as VDD and the SCIO signal is high.

[0118] In the event of a short - circuit state, the SCD output of the short - circuit detection block 300 is high as shown in the previous embodiments. The SCD signal can be adjusted in a signal - conditioning block or directly applied to the parallel - mode detector block 600. The high signal at the gate of HEMT601 turns on the HEMT, pulling down the SCIO pin to ground. The SCIO signal can be further adjusted to act on each auxiliary gate interface and / or mirror - clamp drive of the power IC or directly applied to the auxiliary gate interface and / or mirror - clamp drive based on whether these circuits require an inverted signal. The additional adjustment circuit may be included in the parallel - mode detector block 600 or the auxiliary gate interface 200 / mirror - clamp drive 400. This SCIO signal is transmitted to other parallel power ICs through the SCIO connection, as shown in Figure 42.

[0119] FIG. 42 shows an example of a parallel implementation form in which two power ICs are connected in parallel to each other. As shown above, for example, when power IC1 detects a short-circuit state, power IC1 pulls down the SCIO pin to ground. This is transmitted to the parallel mode detection block of power IC2 through the SCIO pin, and the SCIO pin also sets the SCIO signal of IC2 low. This, in turn, acts on the auxiliary gate interface and / or mirror clamp drive of power IC2 to turn off the power HEMT. In this way, all the power HEMTs of the ICs connected in parallel can be turned off simultaneously via the SCIO connection. The SCIO pin can also be used to convey to an external driver / controller a request for appropriate action regarding a short-circuit event.

[0120] FIG. 43 shows another example of a power integrated circuit in which a power HEMT switch is replaced by a composite switch that includes a high voltage transistor (40) in parallel with a high voltage power HEMT device (101). The high voltage transistor device (40) may include materials or material systems other than group III nitride materials. In some examples, the high voltage transistor device is a silicon and / or silicon carbide transistor, such as, but not limited to, a Si IGBT, Si MOSFET, SiC MOSFET, or super junction MOSFET. Generally, while a GaN HEMT can withstand only a few hundred nanoseconds (especially when the rail voltage (DC link) is high and close to the rated voltage), the listed devices have a relatively long short circuit withstand time (also known as hold time) in the range of several microseconds. The short circuit detection circuit is connected across the power HEMT device and outputs a high SCD signal during a short circuit event, as shown in the previous embodiments. This SCD signal is input to the auxiliary gate interface and / or mirror clamp drive to turn off or adjust the gate voltage of the power HEMT until the external driver turns off the control terminal. Lowering the bias of the gate terminal of the power HEMT can be beneficial in extending the time that the power HEMT can survive a short circuit event because reducing the gate bias can lead to a decrease in the saturation current of the power HEMT in a short circuit event. Thus, the short circuit detection and protection circuit of the HEMT device can extend the short circuit withstand time of the entire composite switch. The SCD signal can be conditioned through a series of signal conditioning blocks (500) before being provided as an input to the auxiliary gate interface and mirror clamp drive, as shown in FIG. 44.

[0121] FIG. 45 shows an alternative example of an implementation form of short-circuit detection and protection in a composite switch including a high-voltage GaN HEMT device in parallel with a high-voltage device of another material (e.g., Si IGBT, Si MOSFET, SiC MOSFET, super-junction MOSFET, etc.). This implementation form also provides internal protection for the IGBT switch (40). The auxiliary depletion-mode HEMT (d-HEMT) (201b) is connected between the control terminal and the gate of the high-voltage IGBT (40). The gate of the auxiliary d-HEMT (201b) is connected to a voltage limiter (203b) to control the voltage applied to the gate of the auxiliary d-HEMT switch. Additionally, a mirror clamp (102b) is connected between the gate and the emitter of the IGBT (40), similar to the mirror clamp (102a) connected between the gate and the source of the power HEMT (101). However, the mirror clamp 102b can be biased to operate up to a maximum of 15 to 20 V as required for the IGBT. In this circuit, when the short-circuit detection circuit 300 identifies a short-circuit event, it sets the SCD signal high. The SCD / SCDC signal acts on both the mirror clamps 102a and 102b as well as the voltage limiters 203a and 203b to adjust or pull down the gate voltages of both the power HEMT and the IGBT until the external driver can act to turn off the control terminal, providing on-chip protection against short-circuit events.

[0122] FIG. 46 shows another aspect of the present disclosure in which a short - circuit detection circuit can be integrated with a cascode switch instead of a power HEMT. The cascode device includes a MOSFET (106) in series with a depletion - mode GaN HEMT (105). The gate of the depletion - mode GaN HEMT (105) is connected to the source of the MOSFET (106). The MOSFET (106) may preferably be an n - channel MOSFET in a vertical or quasi - vertical configuration, and its blocking voltage should be much smaller than the blocking voltage of the depletion - mode HEMT. For example, for a 650V HEMT, the blocking voltage of the MOSFET can be 40V. The short - circuit detection circuit monitors the voltage across the high - voltage and low - voltage terminals of the cascode switch to identify a short - circuit event as shown in the previous embodiments. The SCD signal can be adjusted by a combination of signal - conditioning blocks (500) or applied directly to the mirror - clamp drive to pull down the gate of the cascode switch and turn it off. Instead of or in addition to the mirror - clamp drive, an SCD or SCDC signal can be applied to an auxiliary gate interface to protect the cascode switch from a short - circuit condition (although this is not shown simply for simplicity).

[0123] FIG. 47 shows another aspect of the previous embodiment where a composite switch including a cascode device is provided in parallel with a high voltage device (40). The high voltage device (40) can be an IGBT, a silicon carbide MOSFET, or a super junction. The cascode device includes a MOSFET (106) in series with a depletion mode GaN HEMT (105). The gate of the depletion mode GaN HEMT (105) is connected to the source of the MOSFET (106). The MOSFET (106) can preferably be an n-channel MOSFET in a vertical or quasi-vertical configuration, and its blocking voltage should be much smaller than the blocking voltage of the depletion mode HEMT. For example, in the case of a 650V HEMT, the blocking voltage of the MOSFET can be 40V. The gate of the MOSFET (106) can be short-circuited to the gate of the high voltage switch (40) (e.g., an IGBT) and further connected to the control terminal of the composite switch. Alternatively, either gate can be connected to the control terminal via a slew rate structure (which can simply be a resistor or a resistor with a diode).

[0124] The short circuit detection circuit monitors the voltage across the high voltage terminal and the low voltage terminal of the cascode switch to identify a short circuit event as shown in the previous embodiment. The SCD signal can be adjusted by a combination of the signal conditioning block (500) or directly applied to the mirror clamped drive to pull down the gate of the cascode switch and turn it off. Instead of or in addition to the mirror clamped drive, an SCD or SCDC signal can be applied to the auxiliary gate interface to protect the power HEMT from a short circuit state (although this is not shown simply for simplicity). The SCD / SCDC signal can also be transmitted to an external driver as shown in the previous embodiment to initiate a safe turn-off of the devices that protect the cascode switch and the high voltage device in parallel.

[0125] FIG. 48 shows an exemplary implementation of the short-circuit detection circuit shown in FIG. 46. This can be implemented in the example shown in FIG. 47. The short-circuit detection circuit 300c in this example includes an enhancement-mode HEMT 110 that functions as a sense HEMT, an RC network (R1, C1), and a comparator 302. While the drive voltage on the control terminal of the e-HEMT 110 can be 0V to 20V, an auxiliary gate interface circuit 200i is additionally provided to adapt the drive voltage at the gate of the e-HEMT within a specific range (e.g., 0 to 7V). The cascode switch can additionally have a high-voltage Si switch in parallel as shown in FIG. 47.

[0126] This circuit 300c operates in the same manner as the short-circuit detection circuit shown in FIG. 8. The SCD or SCDC signal can be applied to an auxiliary gate interface (although this is not shown simply for simplicity) and / or a mirror-clamped drive to protect the cascode switch from a short-circuit state. The SCD / SCDC signal is transmitted to an external driver as shown in the previous embodiment, also initiating a safe turn-off of the device that protects the cascode switch and the high-voltage device in parallel.

[0127] FIG. 49 shows an alternative example of an implementation form of a sense transistor provided with a short-circuit detection circuit for a cascode switch. The sense transistor is composed of a sense HEMT (107) in a GaN chip and a sense FET (108) in a silicon chip. A capacitor in parallel with the sense FET 108 provides the function of a blanking circuit, and the charge and discharge speed of the capacitor determines the timing of the SCD signal. The cascode switch can additionally have a high-voltage Si switch in parallel as shown in FIG. 47.

[0128] In another example shown in FIG. 50, the power IC may desirably include at least one additional transistor 102_2 connected in the same configuration as the mirror clamp HEMT described in the previous embodiments. The additional transistor may be described as a mirror clamp HEMT or as a pull-down HEMT. Since it can be optimized for different functions, it may be desirable to connect the two transistors in the same way. One of the mirror clamp transistors (102_1) can be optimized to enable fast turn-off of the power HEMT and / or avoid accidental turn-on of the power HEMT during normal operation of the power electronics circuit. In this case, the mirror clamp transistor may preferably have a low on-state resistance (e.g., less than 10 Ω). The second transistor (102_2) can be optimized to turn off the power HEMT to protect the device when a short circuit is detected, as described in the previous example. In this case, the transistor may desirably have an on-state resistance higher (e.g., greater than 10 Ω) than the on-state resistance intended for the mirror clamp transistor to operate during normal operation of the device. This may be desirable to slow down the turn-off of the power HEMT and avoid overvoltage across the power HEMT (e.g., between the drain and source terminals) due to parasitic components in the circuit, such as the L*dI / dt voltage generated across the parasitic inductance in the power loop, if there is any.

[0129] In the example shown in FIG. 51, an additional circuit block (700) optimized to protect the device in the event of a type 2 short circuit may be included. A type 2 short circuit can result in a higher risk of device failure because a fast positive dV / dt appears across the drain-source terminals of the power HEMT during a type 2 short circuit event. This dV / dt can pull up the voltage at the gate of the power HEMT through the Miller capacitance (Cgd). As the gate voltage increases, the saturation current of the power HEMT increases, and thus the power loss increases, which can shorten the maximum time the power HEMT can withstand a short circuit event. Additionally, the increase in gate voltage itself can be a problem for the power HEMT. In certain technologies such as p-GaN gates, the allowable range of gate bias is very narrow, and damage to the gate can occur if a predetermined voltage bias (e.g., 7.5V) is exceeded.

[0130] Contrary to the previous example that relies on a blanking time and Vds exceeding a predetermined value, the type 2 protection circuit block can be designed to detect a fast dV / dt event to trigger device protection. FIG. 51 shows an implementation of this type 2 detection circuit together with the double mirror clamp-based protection mechanism shown in FIG. 50. This is just an example, and it should be understood that this detection block 700 can be implemented with any of the protection mechanisms described in the previous examples.

[0131] FIG. 52 shows an exemplary dV / dt event detection circuit that can be part of the type 2 short circuit detection block 700. This circuit is connected between the drain and source of the power HEMT, and the output is connected to the mirror clamp to protect the power HEMT if a dV / dt event is detected. This circuit can be connected to an additional clamping transistor similar to that in FIG. 51, or to a standard mirror clamp as shown in the previous embodiments, or to a further additional clamping transistor provided in block 700.

[0132] Terms such as "upper" and "lower", "above" and "below", "horizontal" and "vertical", and "downward" and "upward", "front" and "rear", "beneath", etc. may be used herein by convention and it should also be understood that they do not imply a particular physical orientation of the entire device.

[0133] The present disclosure has been described from the perspective of the preferred embodiments as described above, but it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. Those skilled in the art should be able to create modified forms and alternative forms contemplated as being included within the scope of the appended claims by considering the present disclosure. Each feature disclosed or illustrated herein can be incorporated into the present disclosure, whether alone or in appropriate combination with other features disclosed or illustrated herein.

[0134] References [1]https: / / www.powerelectronicsnews.com / ultrafast-discrete-short-circuit-protection-for-gan-hemts [2]https: / / ieeexplore.ieee.org / document / 9861995 [3]U.S. Patent No. 10,818,786 [4]U.S. Patent Application Publication No. 2023 / 0131602

Description of Reference Numerals

[0135] 14 Transistor 15 Current Sensing Resistor 16 Current Sensing Transistor 19 First Power Transistor 101 Power HEMT 102 Mirror Clamp Transistor 102a Mirror Clamp 102b Mirror Clamp 104 Current Sensing Transistor 108 Sense FET 200 Auxiliary Gate Interface Block 200c Auxiliary Gate Interface Block 200i Auxiliary Gate Interface Circuit 201 Auxiliary Group-III Nitride HEMT 202 Current Source 203 Voltage Limiter 203a Voltage Limiter 205 Transistor 206 Voltage Limiter Circuit 207 Transistor 208 Circuit 300 Short-Circuit Detection Block 300a SCD Block 300b Circuit 300c Short-Circuit Detection Circuit 301 RC Network 302 Comparator 302a Comparator Circuit 302a1 Initial Inverting Differential Amplifier Stage 302a2 Transconductance Amplifier Stage 302a3 Current Subtractor Stage 302b Comparator Circuit 303 Current Source 304 RC Network 305 High-Voltage Diode 306 Transistor 308 Transistor 312 Comparator 313 Transistor 400 Mirror-Clamped Drive 400a Mirror-Clamped Driver 400b Mirror-Clamped Driver 401 Logic Inverter 404 Logic Inverter 500 Circuit 501 Signal Conditioning Block 502 Latch Circuit Block 503 Signal Conditioning Block 600 Parallel Mode Detection Block 700 Short-Circuit Detection Block 1000 First interface circuit 3001 Vds detection block 3001a Vds detection block 3001a1 Circuit 3002 Blanking time block 3002a Blanking time block 3002b Blanking time block 3003 Combination logic function

Claims

1. A semiconductor switch including a first main terminal, a second main terminal, and a control terminal, wherein the semiconductor switch further includes a group-III nitride high electron mobility transistor (HEMT) including a first source terminal, a first drain terminal, and a first gate terminal, a first interface circuit operably connected to the control terminal and the first gate terminal, and a short-circuit detection circuit operably connected to the first drain terminal and the first source terminal and including, wherein the short-circuit detection circuit is configured to detect a short circuit across the first drain terminal and the first source terminal, and transmit a short-circuit detection signal to the first interface circuit, and the first interface circuit is configured to turn off the group-III nitride HEMT and / or lower the voltage across the first gate terminal when receiving the short-circuit detection signal.

2. The first interface circuit includes a pull-down transistor including a second source terminal and a second drain terminal, wherein the second drain terminal is operably connected to the first gate terminal, the second source terminal is operably connected to the first source terminal, and the pull-down transistor is configured to turn on when the first interface circuit receives the short-circuit detection signal.

3. The pull-down transistor includes a second gate terminal, and the first interface circuit is configured to receive the short-circuit detection signal at the second gate terminal.

4. The pull-down transistor includes a second gate terminal, and the first interface circuit further includes a pull-down transistor gate driver operably connected to and configured to drive the second gate terminal, and the first interface circuit is configured to receive the short-circuit detection signal by the pull-down transistor gate driver.

5. ​ The first interface circuit includes an auxiliary gate interface circuit, and the auxiliary gate interface circuit includes a voltage limiter and an auxiliary group-III nitride HEMT. The auxiliary group-III nitride HEMT includes a third source terminal operably connected to the first gate terminal, a third drain terminal operably connected to the control terminal, and a third gate terminal operably connected to the voltage limiter. The semiconductor switch according to claim 1, wherein the voltage limiter is configurable to limit a voltage across the first gate terminal and the first source terminal.

6. The first interface circuit is configured to receive the short-circuit detection signal by the auxiliary gate interface circuit, The semiconductor switch according to claim 5, wherein the first interface circuit is configured to lower the voltage across the first gate terminal when receiving the short-circuit detection signal.

7. The semiconductor switch according to claim 5, wherein the auxiliary gate interface circuit is configurable to adjust a voltage applied to the control terminal to be operably compatible with the first gate terminal.

8. The semiconductor switch according to claim 1, comprising a latch circuit configured to adjust the short-circuit detection signal so that the short-circuit detection signal is held in a predetermined state until one or more release conditions are satisfied.

9. The semiconductor switch according to claim 8, wherein the one or more release conditions include expiration of a period.

10. The semiconductor switch according to claim 1, comprising an adjustment circuit configured to adjust the short-circuit detection signal.

11. The adjustment circuit includes one or more of a diode, a resistor, a capacitor, a logic inverter, a buffer, and / or a level shifter.

12. The semiconductor switch according to claim 1, wherein the short-circuit detection circuit includes a non-saturating circuit configured to detect a voltage drop across the first drain terminal and the first source terminal.

13. The semiconductor switch according to claim 12, wherein the voltage drop is 5V to 30V.

14. The short-circuit detection circuit includes a resistor-capacitor network and a sense HEMT. The sense HEMT includes a fourth source terminal operably connected to the RC network. A fourth drain terminal operably connected to the first drain terminal, and a fourth gate terminal operably connected to the first gate terminal The semiconductor switch according to claim 1, comprising:

15. The short-circuit detection circuit, A voltage detection circuit configured to compare a voltage across the first drain terminal and the first source terminal with a reference voltage and output a high-voltage detection signal when the voltage across the first drain terminal and the first source terminal exceeds the reference voltage; A blanking time circuit configured to output a blanking time signal after a blanking period has elapsed Including, The short-circuit detection circuit is configured to transmit the short-circuit detection signal based on the high-voltage detection signal and the blanking time signal. The semiconductor switch according to claim 1.

16. The semiconductor switch according to claim 15, wherein the voltage detection circuit is configured to operate when receiving the blanking time signal.

17. The short-circuit detection circuit further includes a logic combination circuit configured to receive the high-voltage detection signal and the blanking time signal and output the short-circuit detection signal based on a combination of the high-voltage detection signal and the blanking time signal. The semiconductor switch according to claim 15.

18. The short-circuit detection circuit is monolithically integrated with the group III nitride HEMT. The semiconductor switch according to claim 1.

19. Further comprising an additional pull-down transistor, the additional pull-down transistor including a fifth source terminal and a fifth drain terminal, The fifth drain terminal is operably connected to the first gate terminal, The fifth source terminal is operably connected to the first source terminal, The additional pull-down transistor is configured to control the group III nitride HEMT when no short-circuit detection signal is present. The semiconductor switch according to claim 2.

20. Including an additional pull-down transistor gate driver, the additional pull-down transistor including a fifth gate terminal, and the additional pull-down transistor gate driver is operably connected to the fifth gate terminal and the control terminal. The semiconductor switch according to claim 19.

21. including a second short - circuit detection circuit, the second short - circuit detection circuit being configured to detect a positive voltage change across the first drain terminal and the first source terminal, the second short - circuit detection circuit being configured to transmit a second short - circuit detection signal when the positive voltage change exceeds a reference rate, the semiconductor switch according to claim 1.

22. the second short - circuit detection circuit being configured to transmit the second short - circuit detection signal to the first interface circuit, the semiconductor switch according to claim 21.

23. a cascode device, and / or a composite switch including a group - III nitride switch in parallel with a high - voltage transistor switch made of a material other than group - III nitride one or more of, the semiconductor switch according to claim 1.

24. a system including the semiconductor switch according to claim 1, the system further including an external gate driver operably connected to the control terminal, the short - circuit detection circuit being configured to transmit a short - circuit detection signal to the external gate driver, the external gate driver being configured to turn off the semiconductor switch upon receiving the short - circuit detection signal, the system.

25. one of the one or more release conditions includes receiving a reset signal from the external gate driver by the short - circuit detection circuit, the semiconductor switch according to claim 8 or 24.

26. a system including a plurality of the semiconductor switches according to claim 1 connected in parallel, a first semiconductor switch among the plurality of semiconductor switches including a first parallel - mode detection circuit, a second semiconductor switch among the plurality of semiconductor switches including a second parallel - mode detection circuit, the short - circuit detection circuit of the first semiconductor switch being configured to transmit the short - circuit detection signal to the first parallel - mode detection circuit, the first parallel - mode detection circuit being configured to transmit a detection signal to the second parallel - mode detection circuit upon receiving the short - circuit detection signal, the second parallel - mode detection circuit being configured to turn off the second semiconductor switch upon receiving the detection signal, the system.

Images