Method for manufacturing semiconductor device

Abstract

To provide a method for manufacturing semiconductor devices that can properly cut a hexagonal crystal structure from two different directions.SOLUTION: A method for manufacturing a semiconductor device includes the steps of preparing a hexagonal crystal structure, cutting the crystal structure in the m-axis direction of the hexagonal crystal to form a first cut section, and cutting the crystal structure in the a-axis direction of the hexagonal crystal to form a second cut section that crosses the first cut section.SELECTED DRAWING: Figure 25A

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a method for processing a wafer for cutting out a plurality of devices from a single wafer. The wafer is made of silicon carbide (SiC), gallium nitride (GaN), lithium tantalate (LT), lithium niobate (LN), or the like.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] A crystal structure composed of a hexagonal crystal has different physical properties depending on the crystal plane and crystal direction. For example, a crystal structure composed of a hexagonal crystal has a physical property that it is easily cracked along the direction of the arrangement of the nearest atoms (hereinafter, simply referred to as the "nearest atom direction"), and is difficult to crack along the crossing direction (hereinafter, simply referred to as the "crossing direction of the nearest atom direction") that intersects the nearest atom direction.

[0005] The inventors of the present application have intensively studied the process of cutting the crystal structure along the nearest atom direction and then cutting the crystal structure along the crossing direction of the nearest atom direction. As a result, it was discovered that in the second cutting step, a raised portion that bulges along the nearest atom direction is formed at the cutting portion of the crystal structure.

[0006] In particular, this raised portion tends to occur starting from the connection portion between the cut portion formed in the first cutting step and the cut portion formed in the second cutting step. In the second cutting step, the crystal structure is cut in a direction in which the atomic arrangement is discontinuous with respect to the nearest neighbor atom direction. Therefore, it is considered that a force that retains the atomic arrangement acts in the crystal structure, and a raised portion along the nearest neighbor atom direction is formed at the cut portion.

[0007] One embodiment of the present invention provides a method for manufacturing a semiconductor device capable of appropriately cutting a hexagonal crystal structure from two different directions.

[0008] One embodiment of the present invention provides a method for manufacturing a semiconductor device, including a step of preparing a hexagonal crystal structure, a step of cutting the crystal structure in the m-axis direction of the hexagonal crystal to form a first cut portion, and a step of cutting the crystal structure in the a-axis direction of the hexagonal crystal to form a second cut portion that crosses the first cut portion.

[0009] According to this crystal cutting method, the crystal structure is cut along the m-axis direction, which is the intersection direction of the nearest neighbor atom directions, in the step of forming the first cut portion. The crystal structure is cut along the a-axis direction, which is the nearest neighbor atom direction, in the step of forming the second cut portion.

[0010] In the step of forming the first cut portion, since the uncut crystal structure is cut, the stress on the crystal structure does not become discontinuous. Thereby, the generation of raised portions at the first cut portion can be suppressed. On the other hand, in the step of forming the second cut portion, since the crystal structure is cut in the intersection direction of the nearest neighbor atom directions, the stress on the crystal structure becomes discontinuous. However, in the step of forming the second cut portion, stress is applied to the crystal structure along the nearest neighbor atom direction, and the crystal structure is cut along the nearest neighbor atom direction.

[0011] Thereby, the generation of raised portions at the second cut portion can be suppressed, and the flatness of the first cut portion and the second cut portion can be improved. Therefore, a method for manufacturing a semiconductor device capable of appropriately cutting a hexagonal crystal structure from two different directions can be provided.

[0012] One embodiment of the present invention provides a crystal cutting method including: a step of preparing a crystal structure composed of a hexagonal crystal; a first cutting step of cutting the crystal structure along the [1-100] direction of the hexagonal crystal to form a first cutting portion in the crystal structure; and a second cutting step of cutting the crystal structure along the [11-20] direction of the hexagonal crystal to form a second cutting portion that crosses the first cutting portion in the crystal structure.

[0013] According to this crystal cutting method, the crystal structure is cut along the [1-100] direction, which is the cross direction of the nearest neighbor atom direction, in the first cutting step. The crystal structure is cut along the [11-20] direction, which is the nearest neighbor atom direction, in the second cutting step.

[0014] In the first cutting step, since the uncut crystal structure is cut, the stress on the crystal structure does not become discontinuous. Thereby, the generation of ridges at the first cutting portion can be suppressed. On the other hand, in the second cutting step, since the crystal structure is cut in the cross direction of the nearest neighbor atom direction, the stress on the crystal structure becomes discontinuous. However, in the second cutting step, stress is applied to the crystal structure along the nearest neighbor atom direction, and the crystal structure is cut along the nearest neighbor atom direction.

[0015] Thereby, the generation of ridges at the second cutting portion can be suppressed, so that the flatness of the first cutting portion and the second cutting portion can be improved. Therefore, a crystal cutting method capable of appropriately cutting a crystal structure composed of a hexagonal crystal from two different directions can be provided.

[0016] One embodiment of the present invention provides a crystal cutting method including: a step of preparing a SiC crystal structure composed of a hexagonal crystal; a first cutting step of cutting the SiC crystal structure along the [1-100] direction of the hexagonal crystal to form a first cutting portion in the SiC crystal structure; and a second cutting step of cutting the SiC crystal structure along the [11-20] direction of the hexagonal crystal to form a second cutting portion that crosses the first cutting portion in the SiC crystal structure.

[0017] According to this crystal cutting method, the SiC crystal structure is cut along the [1-100] direction, which is the intersection direction of the nearest neighbor atom directions, in the first cutting step. The SiC crystal structure is cut along the [11-20] direction, which is the nearest neighbor atom direction, in the second cutting step.

[0018] In the first cutting step, since the uncut SiC crystal structure is cut, the stress on the SiC crystal structure does not become discontinuous. Thereby, the generation of the raised portion in the first cut portion can be suppressed. On the other hand, in the second cutting step, since the SiC crystal structure is cut in the intersection direction of the nearest neighbor atom directions, the stress on the SiC crystal structure becomes discontinuous. However, in the second cutting step, stress is applied to the SiC crystal structure along the nearest neighbor atom direction, and the SiC crystal structure is cut along the nearest neighbor atom direction.

[0019] Thereby, the generation of the raised portion in the second cut portion can be suppressed, so that the flatness of the first cut portion and the second cut portion can be improved. Therefore, a crystal cutting method capable of appropriately cutting the hexagonal SiC crystal structure from two different directions can be provided.

[0020] One embodiment of the present invention provides a method for manufacturing an SiC semiconductor device, including the steps of preparing a hexagonal SiC crystal structure, setting a rectangular device region having a [1-100] direction side along the [1-100] direction of the hexagonal crystal and a [11-20] direction side along the [11-20] direction of the hexagonal crystal in the SiC crystal structure, forming a functional device in the device region, cutting the SiC crystal structure along the [1-100] direction side of the device region to form a first cut portion in the SiC crystal structure, and cutting the SiC crystal structure along the [11-20] direction side of the device region to form a second cut portion crossing the first cut portion in the SiC crystal structure.

[0021] According to the manufacturing method of this SiC semiconductor device, the SiC crystal structure is cut along the [1-100] direction, which is the intersection direction of the nearest neighbor atom directions, in the first cutting step. The SiC crystal structure is cut along the [11-20] direction, which is the nearest neighbor atom direction, in the second cutting step.

[0022] In the first cutting step, since the uncut SiC crystal structure is cut, the stress on the SiC crystal structure does not become discontinuous. Thereby, the generation of the raised portion in the first cut portion can be suppressed. On the other hand, in the second cutting step, since the SiC crystal structure is cut in the intersection direction of the nearest neighbor atom directions, the stress on the SiC crystal structure becomes discontinuous. However, in the second cutting step, stress is applied to the SiC crystal structure along the nearest neighbor atom direction, and the SiC crystal structure is cut along the nearest neighbor atom direction.

[0023] Thereby, the generation of the raised portion in the second cut portion can be suppressed, so that the flatness of the first cut portion and the second cut portion can be improved. Therefore, a manufacturing method of a SiC semiconductor device capable of appropriately cutting a SiC crystal structure composed of hexagonal crystals from two different directions can be provided.

[0024] One embodiment of the present invention provides a SiC semiconductor device including a SiC semiconductor layer composed of hexagonal crystals, having a first main surface on one side, a second main surface on the other side, a first side surface connecting the first main surface and the second main surface and extending along the [11-20] direction of the hexagonal crystal, and a second side surface connecting the first main surface and the second main surface, extending along the [1-100] direction of the hexagonal crystal, and having an in-plane variation along the [11-20] direction of the hexagonal crystal of 20 μm or less.

[0025] The above-mentioned, or further other objects, features, and effects in the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0027] In an embodiment of the present invention, a crystal structure composed of hexagonal crystals is applied. The crystal structure composed of hexagonal crystals may include material types having a thermal conductivity of 0.35 W / cmK or more and 25 W / cmK or less. The crystal structure composed of hexagonal crystals may include material types having a thermal conductivity exceeding 2.5 W / cmK.

[0028] As the crystal structure composed of hexagonal crystals, various material types constituting hexagonal crystals such as sapphire (Al2O3), gallium nitride (GaN), silicon carbide (SiC), and diamond (C) are applied.

[0029] The thermal conductivity increases in the order of sapphire (Al2O3), gallium nitride (GaN), silicon carbide (SiC), and diamond (C). The thermal conductivity of sapphire (Al2O3) is 0.35 W / cmK or more and 0.45 W / cmK or less (more specifically, about 0.4 W / cmK). The thermal conductivity of gallium nitride (GaN) is 1.5 W / cmK or more and 2.5 W / cmK or less (more specifically, about 2.0 W / cmK).

[0030] The thermal conductivity of silicon carbide (SiC) is 4.5 W / cmK or more and 5.5 W / cmK or less (more specifically, about 4.9 W / cmK). The thermal conductivity of diamond (C) is 10 W / cmK or more and 25 W / cmK or less (more specifically, about 22 W / cmK).

[0031] In an embodiment of the present invention, as an example of the crystal structure composed of hexagonal crystals, an example in which a SiC crystal structure composed of hexagonal crystals is applied will be described. The SiC single crystal composed of hexagonal crystals has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal according to the period of the atomic arrangement. In the embodiment of the present invention, an example in which a 4H-SiC single crystal is applied will be described, but other polytypes and other material types constituting hexagonal crystals are not excluded from the present invention.

[0032] Hereinafter, with reference to FIGS. 1 and 2, the crystal structure of a 4H-SiC single crystal will be described. FIG. 1 is a diagram showing a unit cell (hereinafter simply referred to as "unit cell") of a 4H-SiC single crystal applied to an embodiment of the present invention. FIG. 2 is a plan view showing the silicon plane of the unit cell shown in FIG. 1.

[0033] With reference to FIGS. 1 and 2, the unit cell includes a tetrahedral structure in which four C atoms are bonded to one Si atom in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell has an atomic arrangement in which the tetrahedral structures are stacked with a four-layer period. The unit cell has a hexagonal prism structure having a regular hexagonal silicon plane, a regular hexagonal carbon plane, and six side faces connecting the silicon plane and the carbon plane.

[0034] The silicon plane is a termination plane terminated by Si atoms. In the silicon plane, one Si atom is located at each of the six vertices of the regular hexagon, and one Si atom is located at the center of the regular hexagon.

[0035] The carbon plane is a termination plane terminated by C atoms. In the carbon plane, one C atom is located at each of the six vertices of the regular hexagon, and one C atom is located at the center of the regular hexagon.

[0036] The crystal plane of the unit cell is defined by four coordinate axes (a1, a2, a3, c) including the a1 axis, a2 axis, a3 axis, and c axis. The value of a3 among the four coordinate axes takes the value of -(a1 + a2). Hereinafter, the crystal plane of the 4H-SiC single crystal will be described with reference to the silicon plane as an example of the termination plane of the hexagonal crystal.

[0037] The a1 axis, a2 axis, and a3 axis are each set along the arrangement direction of the nearest Si atoms (hereinafter simply referred to as "nearest neighbor atom direction") with respect to the Si atom located at the center in a plan view when looking at the silicon plane from the c axis. The a1 axis, a2 axis, and a3 axis are each set with an angular shift of 120° following the arrangement of the Si atoms.

[0038] The c-axis is set in the normal direction of the silicon plane with respect to the Si atom located at the center. The silicon plane is the (0001) plane. The carbon plane is the (000-1) plane. The side surface of the hexagonal prism includes six crystal planes along the nearest-neighbor atom direction in a plan view of the silicon plane as seen from the c-axis. More specifically, the side surface of the hexagonal prism includes six crystal planes formed by the nearest-neighboring Si atoms.

[0039] The side surface of the hexagonal prism includes the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01-10) plane, and (10-10) plane in a clockwise direction from the tip of the a1-axis in a plan view of the silicon plane as seen from the c-axis.

[0040] The diagonal that does not pass through the center in the hexagonal prism includes six crystal planes along the intersection direction (hereinafter simply referred to as the "intersection direction of the nearest-neighbor atom direction") that intersects the nearest-neighbor atom direction in a plan view of the silicon plane as seen from the c-axis. When viewed with respect to the Si atom located at the center, the intersection direction of the nearest-neighbor atom direction becomes the orthogonal direction orthogonal to the nearest-neighbor atom direction. More specifically, the diagonal that does not pass through the center in the hexagonal prism includes six crystal planes formed by the non-nearest-neighboring Si atoms.

[0041] The diagonal that does not pass through the center in the hexagonal prism includes the (11-20) plane, (1-210) plane, (-2110) plane, (-1-120) plane, (-12-10) plane, and (2-1-10) plane in a plan view of the silicon plane as seen from the c-axis.

[0042] The crystal direction of the unit cell is defined by the normal direction of the crystal plane. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (-1010) plane is the [-1010] direction. The normal direction of the (-1100) plane is the [-1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

[0043] The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (-2110) plane is the [-2110] direction. The normal direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

[0044] The hexagonal crystal has six-fold symmetry, and there are equivalent crystal planes and equivalent crystal directions every 60°. For example, the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01-10) plane, and (10-10) plane form equivalent crystal planes. Also, the (11-20) plane, (1-210) plane, (-2110) plane, (-1-120) plane, (-12-10) plane, and (2-1-10) plane form equivalent crystal planes.

[0045] Also, the [1-100] direction, [0-110] direction, [-1010] direction, [-1100] direction, [01-10] direction, and [10-10] direction form equivalent crystal directions. Also, the [11-20] direction, [1-210] direction, [-2110] direction, [-1-120] direction, [-12-10] direction, and [2-1-10] direction form equivalent crystal directions.

[0046] The c-axis is the

[0001] direction ([000-1] direction). The a1-axis is the [2-1-10] direction ([-2110] direction). The a2-axis is the [-12-10] direction ([1-210] direction). The a3-axis is the [-1-120] direction ([11-20] direction).

[0047] The

[0001] direction and the [000-1] direction may simply be referred to as the c-axis. The (0001) plane and the (000-1) plane may simply be referred to as the c-plane. The [11-20] direction and the [-1-120] direction may simply be referred to as the a-axis. The (11-20) plane and the (-1-120) plane may simply be referred to as the a-plane. The [1-100] direction and the [-1100] direction may simply be referred to as the m-axis. The (1-100) plane and the (-1100) plane may simply be referred to as the m-plane.

[0048] FIG. 3 is a perspective view showing a 4H-SiC crystal structure 1 including a 4H-SiC single crystal.

[0049] In this form, the 4H-SiC crystal structure 1 is formed in a plate shape or a disk shape. The 4H-SiC crystal structure 1 may be formed in a circular shape (disk shape).

[0050] The thickness of the 4H-SiC crystal structure 1 may be 1 μm or more and 1000 μm or less. The thickness of the 4H-SiC crystal structure 1 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0051] The 4H-SiC crystal structure 1 has a first main surface 2 on one side, a second main surface 3 on the other side, and a side surface 4 connecting the first main surface 2 and the second main surface 3. The first main surface 2 and the second main surface 3 of the 4H-SiC crystal structure 1 may have an off-angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the (0001) plane. The off-angle θ is also the angle between the normal direction N of the first main surface 2 and the second main surface 3 and the c-axis of the 4H-SiC crystal structure 1.

[0052] The off-angle θ may be 0° or more and 4° or less. When the off-angle θ is 0°, it means that the normal direction N and the c-axis coincide. The off-angle θ may be more than 0° and less than 4°. The off-angle θ is typically set in the range of 2° or 4°, more specifically, in the range of 2° ± 10% or 4° ± 10%.

[0053] On the side surface 4 of the 4H-SiC crystal structure 1, an orientation flat 5 is formed as an example of a mark indicating the crystal orientation. The orientation flat 5 is a notch formed on the side surface 4 of the 4H-SiC crystal structure 1. In this form, the orientation flat 5 extends linearly along the [11-20] direction.

[0054] A plurality (for example, two) of orientation flats may be formed on the side surface 4 of the 4H-SiC crystal structure 1. In this case, a first orientation flat and a second orientation flat may be formed on the side surface 4 of the 4H-SiC crystal structure 1. The first orientation flat may be a notch extending linearly along the [11-20] direction. The second orientation flat may be a notch extending linearly along the [1-100] direction.

[0055] Instead of the orientation flat 5, an orientation notch may be formed on the side surface 4 of the 4H-SiC crystal structure 1, which is a notch recessed toward the central portion of the 4H-SiC crystal structure 1.

[0056] The 4H-SiC crystal structure 1 includes a first corner portion 6 connecting the first main surface 2 and the side surface 4, and a second corner portion 7 connecting the second main surface 3 and the side surface 4. The first corner portion 6 has a first chamfered portion 8 that slopes downward from the first main surface 2 toward the side surface 4. The second corner portion 7 has a second chamfered portion 9 that slopes downward from the second main surface 3 toward the side surface 4.

[0057] The first chamfered portion 8 may be formed in a convexly curved shape. The second chamfered portion 9 may be formed in a convexly curved shape. The first chamfered portion 8 and the second chamfered portion 9 suppress cracks in the 4H-SiC crystal structure 1.

[0058] FIG. 4 is a plan view showing the cleavage mode of the 4H-SiC crystal structure 1.

[0059] The 4H-SiC crystal structure 1 has different physical properties depending on the crystal plane and crystal direction. For example, the 4H-SiC crystal structure 1 has the physical property of being easily cracked along the nearest neighbor atom direction and being difficult to crack along the intersection direction of the nearest neighbor atom directions. The intersection direction of the nearest neighbor atom directions is, more specifically, the orthogonal direction orthogonal to the nearest neighbor atom direction.

[0060] Referring to FIG. 4, for example, when an external force is applied to the center of the 4H-SiC crystal structure 1 and the 4H-SiC crystal structure 1 is cleaved, the 4H-SiC crystal structure 1 cleaves along six azimuths with the center of the first main surface 2 as a reference.

[0061] More specifically, the 4H-SiC crystal structure 1 cleaves along the [11-20] direction, the [-12-10] direction, and the [-2110] direction. The [11-20] direction, the [-12-10] direction, and the [-2110] direction are all the nearest neighbor atom directions.

[0062] The 4H-SiC crystal structure 1 is difficult to cleave along the orthogonal directions of the [11-20] direction, the orthogonal direction of the [-12-10] direction, and the orthogonal direction of the [-2110] direction. That is, the 4H-SiC crystal structure 1 is difficult to cleave along the [-1100] direction, the [10-10] direction, and the [01-10] direction. The [-1100] direction, the [10-10] direction, and the [01-10] direction are all the intersection directions of the nearest neighbor atom directions.

[0063] Hereinafter, a processing method performed on the 4H-SiC crystal structure 1 will be described. The following processing method can also be applied to a method for manufacturing a SiC semiconductor device.

[0064] Figures 5A to 5D are cross-sectional perspective views for explaining the SiC processing method according to the first embodiment of the present invention, showing a partial region of the 4H-SiC crystal structure 1 shown in FIG. 3.

[0065] First, referring to FIG. 5A, a 4H-SiC crystal structure 1 as an example of an object to be processed is prepared.

[0066] Next, referring to FIG. 5B, a processing region 10 selectively set on the first main surface 2 of the 4H-SiC crystal structure 1 is heated, and a modified layer 11 in which SiC is modified to other properties is formed. In this step, the modified layer 11 is formed in a strip shape extending along an arbitrary direction.

[0067] The heating of the processing region 10 may be performed by an ablation processing method using laser irradiation. In the ablation processing method, an ultraviolet laser may be used. The laser energy, laser pulse duty ratio, and laser irradiation speed are each set to arbitrary values according to the size, shape, thickness, etc. of the modified layer 11 to be formed.

[0068] In the ablation processing method, a depression 12 recessed from the first main surface 2 toward the second main surface 3 is formed in the surface layer portion of the first main surface 2. The depression 12 includes a bottom portion and side portions. The depression 12 may be formed in a tapered shape in which the opening width narrows from the first main surface 2 toward the bottom portion. The bottom portion of the depression 12 may be formed in a curved shape toward the second main surface 3.

[0069] The depression 12 includes an opening-side corner portion and a bottom-side corner portion. The opening-side corner portion of the depression 12 connects the first main surface 2 and the side portions of the depression 12. The bottom-side corner portion of the depression 12 connects the bottom portion and the side portions of the depression 12.

[0070] The width W of the depression 12 may be more than 0 μm and 10 μm or less. The width W of the depression 12 is the width in the direction orthogonal to the direction in which the depression 12 extends. The width W of the depression 12 may be more than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width W of the depression 12 is preferably more than 0 μm and 5 μm or less.

[0071] The depth D of the depression 12 may be more than 0 μm and 30 μm or less. The depth D of the depression 12 is the distance from the first main surface 2 to the bottommost part of the depression 12 with respect to the normal direction N. The depth D of the depression 12 may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the depth D of the depression 12 is preferably more than 0 μm and 15 μm or less.

[0072] The modified layer 11 is formed in a film shape along the inner wall of the depression 12. The thickness of the portion of the modified layer 11 that covers the bottom wall of the depression 12 may be larger than the thickness of the portion of the modified layer 11 that covers the side wall of the depression 12. The modified layer 11 may be formed with a uniform thickness along the inner wall of the depression 12.

[0073] The modified layer 11 partitions a recess 13 within the depression 12. More specifically, the recess 13 is partitioned by the outer surface of the modified layer 11. The recess 13 includes a bottom portion and side portions. The recess 13 may be formed in a tapered shape in which the opening width narrows from the first main surface 2 toward the bottom. The bottom of the recess 13 may be formed in a curved shape toward the second main surface 3.

[0074] The recess 13 includes an opening-side corner portion and a bottom-side corner portion. The opening-side corner portion of the recess 13 connects the first main surface 2 of the 4H-SiC crystal structure 1 and the side portion of the recess 13. The bottom-side corner portion of the recess 13 connects the bottom portion and the side portions of the recess 13.

[0075] The width WR of the recess 13 is less than the width W of the depression 12. The width WR of the recess 13 may be more than 0 μm and less than 10 μm. The width WR of the recess 13 may be more than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width WR of the recess 13 is preferably more than 0 μm and less than 5 μm.

[0076] The depth DR of the recess 13 is less than the depth D of the depression 12. The depth DR of the recess 13 may be more than 0 μm and less than 30 μm. The depth DR of the recess 13 may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 13 is preferably more than 0 μm and 15 μm or less.

[0077] Next, referring to FIG. 5C, the corners of the modified layer 11 are rounded. More specifically, the outer surface of the modified layer 11 is flattened by removing unevenness from the outer surface of the modified layer 11. A part of the modified layer 11 may be removed by an etching method. The etching method may be a dry etching method or a wet etching method. Here, a part of the modified layer 11 is removed by a plasma etching method as an example of the dry etching method.

[0078] The modified layer 11 has components different from those of the 4H-SiC crystal structure 1. The etching rate (etching selectivity) for the modified layer 11 is different from the etching rate (etching selectivity) for SiC. Therefore, a part of the modified layer 11 can be appropriately removed while leaving the 4H-SiC crystal structure 1. As a result, the corner portion on the opening side of the recess 13 is rounded in a curved shape toward the inside of the recess 13. Also, the corner portion on the bottom side of the recess 13 is rounded in a curved shape toward the outside of the recess 13.

[0079] According to the recess 13 with rounded opening-side corners, stress concentration on the modified layer 11 at the opening-side corners can be alleviated. Further, according to the recess 13 with rounded bottom-side corners, stress concentration on the modified layer 11 at the bottom-side corners can be alleviated. Thereby, undesired cracks caused by stress on the modified layer 11 can be suppressed.

[0080] Next, referring to FIG. 5D, the 4H-SiC crystal structure 1 may be cleaved starting from the processing region 10. More specifically, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved by applying stress to the depression 12. In this step, a step of applying thermal stress to the depression 12 by heating and cooling is performed.

[0081] The heating step of the depression 12 may be performed by a laser irradiation method. The laser irradiation method may be performed by an infrared laser (for example, a CO2 laser). By the heating step of the depression 12, a compressive stress starting from the depression 12 is thermally induced. The laser energy, the laser pulse duty ratio, and the laser irradiation speed are each set to an arbitrary value according to the magnitude of the stress to be applied to the depression 12.

[0082] The cooling step of the depression 12 may include a step of supplying a cooling fluid to the depression 12. The cooling fluid may include water or air, or a mixture of water and air (aerosol). By the cooling step of the depression 12, a tensile stress starting from the depression 12 is thermally induced.

[0083] The step of supplying the cooling fluid may include a step of injecting (spraying) the cooling fluid by a coolant jet method or a cooling gas supply method. The cooling step of the depression 12 may be performed after the heating step of the depression 12, or may be performed simultaneously with the heating step of the depression 12. Due to the compressive stress generated in the heating step of the depression 12 and the tensile stress generated in the cooling step of the depression 12, the 4H-SiC crystal structure 1 is cleaved along the depression 12.

[0084] The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed from the remaining part of the depression 12. A part of the modified layer 11 is exposed at the corner connecting the first main surface 2 and the cleavage plane 14 of the 4H-SiC crystal structure 1. The modified layer 11 is formed along the inclined portion 15.

[0085] FIG. 6 is a cross-sectional view showing the modified layer 11 formed in the process of FIG. 5B. FIG. 7 is a graph showing the composition of the modified layer 11. FIG. 7 shows the results of examining the components of the 4H-SiC crystal structure 1 by Raman spectroscopy.

[0086] In FIG. 6, a first region A, a second region B, and a third region C are shown. The first region A shows the surface layer portion of the modified layer 11. The surface layer portion of the modified layer 11 is a region located on the side of the first main surface 2 of the 4H-SiC crystal structure 1. The second region B shows the bottom portion of the modified layer 11. The bottom portion of the modified layer 11 is a region located on the side of the second main surface 3 of the 4H-SiC crystal structure 1 with respect to the surface layer portion of the modified layer 11. The third region C shows the region outside the modified layer 11 in the 4H-SiC crystal structure 1.

[0087] In FIG. 7, a first curve LA, a second curve LB, and a third curve LC are shown. The first curve LA shows the components of the first region A shown in FIG. 6. The second curve LB shows the components of the second region B shown in FIG. 6. The third curve LC shows the components of the third region C shown in FIG. 6.

[0088] The first curve LA has a peak value derived from Si (silicon) in the wavelength range of 500 nm or more and 550 nm or less. The second curve LB has a peak value derived from Si (silicon) in the wavelength range of 500 nm or more and 550 nm or less, and has a peak value derived from C (carbon) in the wavelength range of 1300 nm or more and 1700 nm or less.

[0089] The third curve LC has a peak value derived from SiC (silicon carbide) in the wavelength range of 750 nm or more and 800 nm or less. Therefore, in the third region C, the modified layer 11 is not formed, and only the 4H-SiC single crystal exists.

[0090] Referring to the first curve LA, the silicon density of the surface layer portion (first region A) of the modified layer 11 is higher than the carbon density of the surface layer portion of the modified layer 11. That is, the surface layer portion of the modified layer 11 includes an Si modified layer in which SiC of the 4H-SiC crystal structure 1 is modified to Si. The Si modified layer may include polycrystalline Si. The Si modified layer may include amorphous Si. The Si modified layer may include polycrystalline Si and amorphous Si. The Si modified layer may mainly include an Si amorphous layer.

[0091] Referring to the second curve LB, the silicon density of the bottom portion (second region B) of the modified layer 11 is higher than the carbon density of the bottom portion of the modified layer 11. The bottom portion of the modified layer 11 includes an Si modified layer in which SiC of the 4H-SiC crystal structure 1 is modified to Si. The Si modified layer may include polycrystalline Si. The Si modified layer may include amorphous Si. The Si modified layer may include polycrystalline Si and amorphous Si. The Si modified layer may mainly include an Si amorphous layer.

[0092] Referring to the first curve LA and the second curve LB, the modified layer 11 has different components in the surface layer portion (first region A) and the bottom portion (second region B). More specifically, the modified layer 11 has different silicon densities along the thickness direction. The silicon density of the bottom portion of the modified layer 11 is lower than the silicon density of the surface layer portion of the modified layer 11. Also, the modified layer 11 has different carbon densities along the thickness direction. The carbon density of the bottom portion of the modified layer 11 is higher than the carbon density of the surface layer portion of the modified layer 11.

[0093] From the results of the first curve LA to the third curve LC, it is understood that the formation process of the modified layer 11 includes a step of heating the processing region 10 to a temperature at which C atoms desorb or sublimate from SiC. Thereby, the modified layer 11 is formed on the first main surface 2 of the 4H-SiC crystal structure 1.

[0094] As described above, according to this SiC processing method, the outer surface of the 4H-SiC crystal structure 1 can be processed by the formation step of the modified layer 11 and the removal step of the modified layer 11. Further, the 4H-SiC crystal structure 1 can be cleaved by using the depression 12 of the modified layer 11.

[0095] In particular, according to the recess 13 with rounded opening-side corners, stress concentration on the modified layer 11 can be alleviated at the opening-side corners. Further, according to the recess 13 with rounded bottom-side corners, stress concentration on the modified layer 11 can be alleviated at the bottom-side corners. Thereby, undesired cracks caused by stress on the modified layer 11 can be suppressed.

[0096] Figs. 8A to 8D are cross-sectional perspective views for explaining the SiC processing method according to the second embodiment of the present invention, which are partial regions of the 4H-SiC crystal structure 1 shown in Fig. 3. Hereinafter, descriptions of the structures and manufacturing steps corresponding to those described in Figs. 5A to 5D will be omitted.

[0097] First, referring to Fig. 8A, a 4H-SiC crystal structure 1 as an example of an object to be processed is prepared.

[0098] Next, referring to Fig. 8B, a modified layer 11, a depression 12, and a recess 13 are formed in a processing region 10 selectively set on the first main surface 2. The modified layer 11, the depression 12, and the recess 13 are formed through the same steps as those in Fig. 5B described above.

[0099] Next, referring to Fig. 8C, while leaving the 4H-SiC crystal structure 1, all of the modified layer 11 is removed. The modified layer 11 is removed through the same steps as those in Fig. 5C described above. Thereby, the depression 12 partitioned by the 4H-SiC crystal structure 1 remains on the first main surface 2.

[0100] In this step, the opening-side corners of the recess 12 are rounded in a curved shape toward the inside of the recess 12. Also, the bottom-side corners of the recess 12 are rounded in a curved shape toward the outside of the recess 12. According to the recess 12 with the rounded opening-side corners, stress concentration on the recess 12 at the opening-side corners can be alleviated. Also, according to the recess 12 with the rounded bottom-side corners, stress concentration on the recess 12 at the bottom-side corners can be alleviated. Thereby, undesired cracks caused by stress on the recess 12 can be suppressed.

[0101] Next, referring to FIG. 8D, the 4H-SiC crystal structure 1 may be cleaved starting from the recess 12. The 4H-SiC crystal structure 1 may be cleaved through the same steps as in FIG. 5D described above. The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed of the remaining portion of the recess 12.

[0102] As described above, according to this SiC processing method, the outer surface of the 4H-SiC crystal structure 1 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. Also, using the recess 12 formed on the outer surface of the 4H-SiC crystal structure 1 through the step of removing the modified layer 11, the 4H-SiC crystal structure 1 can be cleaved.

[0103] In particular, according to the recess 12 with the rounded opening-side corners, stress concentration on the recess 12 at the opening-side corners can be alleviated. Also, according to the recess 12 with the rounded bottom-side corners, stress concentration on the recess 12 at the bottom-side corners can be alleviated. Thereby, undesired cracks caused by stress on the recess 12 can be suppressed.

[0104] FIGS. 9A to 9D are cross-sectional perspective views for explaining the SiC processing method according to the third embodiment of the present invention, showing a partial region of the 4H-SiC crystal structure 1 shown in FIG. 3. Hereinafter, descriptions of the structures and manufacturing steps corresponding to the structures and manufacturing steps described in FIGS. 5A to 5D are omitted.

[0105] First, referring to FIG. 9A, a 4H-SiC crystal structure 1 as an example of a SiC object to be processed is prepared. In this form, the 4H-SiC crystal structure 1 has a laminated structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (e.g., n-type impurity concentration) less than the impurity concentration (e.g., n-type impurity concentration) of the SiC semiconductor wafer 16.

[0106] The first main surface 2 of the 4H-SiC crystal structure 1 is formed by the SiC epitaxial layer 17. The second main surface 3 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16. The side surface 4 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0107] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0108] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0109] The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0110] Next, referring to FIG. 9B, a modified layer 11, a depression 12, and a recess 13 are formed in a processed region 10 selectively provided on the first main surface 2 of the 4H-SiC crystal structure 1. The modified layer 11, the depression 12, and the recess 13 are formed in the SiC epitaxial layer 17. The modified layer 11, the depression 12, and the recess 13 are formed through the same process as in FIG. 5B described above.

[0111] Next, referring to FIG. 9C, while the 4H-SiC crystal structure 1 is left remaining, the modified layer 11 is partially removed and the outer surface of the modified layer 11 is flattened. The modified layer 11 is removed through the same process as in FIG. 5C described above. As a result, the opening-side corner portion of the recess 13 is rounded in a curved shape toward the inside of the recess 13. Also, the bottom-side corner portion of the recess 13 is rounded in a curved shape toward the outside of the recess 13.

[0112] According to the recess 13 with the rounded opening-side corner portion, stress concentration on the modified layer 11 at the opening-side corner portion can be alleviated. Also, according to the recess 13 with the rounded bottom-side corner portion, stress concentration on the modified layer 11 at the bottom-side corner portion can be alleviated. Thereby, undesired cracks caused by stress on the modified layer 11 can be suppressed.

[0113] Next, referring to FIG. 9D, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved through the same process as in FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than the impurity concentration of the SiC epitaxial layer 17, the attenuation rate of the laser light with respect to the SiC semiconductor wafer 16 becomes higher than the attenuation rate of the laser light with respect to the SiC epitaxial layer 17.

[0114] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, the SiC semiconductor wafer 16 can be efficiently heated. Thereby, the compressive stress generated in the heating process of the depression 12 and the tensile stress generated in the cooling process of the depression 12 can be increased. Thus, the cleavage force applied to the 4H-SiC crystal structure 1 can be increased.

[0115] The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed by the remaining part of the depression 12. A part of the modified layer 11 is exposed at the corner connecting the first main surface 2 and the cleavage plane 14 of the 4H-SiC crystal structure 1. The modified layer 11 is formed along the inclined portion 15.

[0116] As described above, according to this SiC processing method, the outer surface of the SiC epitaxial layer 17 can be processed by the formation step of the modified layer 11 and the removal step of the modified layer 11. Also, the 4H-SiC crystal structure 1 can be cleaved using the depression 12.

[0117] In particular, according to the recess 13 with the rounded opening-side corner, stress concentration on the modified layer 11 can be alleviated at the opening-side corner. Also, according to the recess 13 with the rounded bottom-side corner, stress concentration on the modified layer 11 can be alleviated at the bottom-side corner. Thereby, undesired cracks due to stress on the modified layer 11 can be suppressed.

[0118] Figs. 10A to 10D are cross-sectional perspective views for explaining the SiC processing method according to the fourth embodiment of the present invention in a partial region of the 4H-SiC crystal structure 1 shown in Fig. 3. Hereinafter, the description of the structures and manufacturing processes corresponding to those described in Figs. 5A to 5D will be omitted.

[0119] First, referring to Fig. 10A, a 4H-SiC crystal structure 1 as an example of an object to be processed of SiC is prepared. In this form, the 4H-SiC crystal structure 1 has a laminated structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (for example, n-type impurity concentration) lower than the impurity concentration (for example, n-type impurity concentration) of the SiC semiconductor wafer 16.

[0120] The first main surface 2 of the 4H-SiC crystal structure 1 is formed by the SiC epitaxial layer 17. The second main surface 3 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16. The side surface 4 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0121] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0122] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0123] The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0124] Next, referring to FIG. 10B, a modified layer 11, a depression 12, and a recess 13 are formed in the processing region 10 selectively set on the first main surface 2 of the 4H-SiC crystal structure 1. The modified layer 11, the depression 12, and the recess 13 are formed in the SiC epitaxial layer 17. The modified layer 11, the depression 12, and the recess 13 are formed through the same process as in FIG. 5B described above.

[0125] Next, referring to FIG. 10C, while leaving the 4H-SiC crystal structure 1 intact, all of the modified layer 11 is removed. The modified layer 11 is removed through the same process as that of FIG. 5C described above. As a result, the recess 12 defined by the 4H-SiC crystal structure 1 remains on the first main surface 2. In this process, the opening-side corner portions of the recess 12 are rounded in a curved shape toward the inside of the recess 12. Also, the bottom-side corner portions of the recess 12 are rounded in a curved shape toward the outside of the recess 12.

[0126] According to the recess 12 with the rounded opening-side corner portions, stress concentration on the recess 12 at the opening-side corner portions can be alleviated. Also, according to the recess 12 with the rounded bottom-side corner portions, stress concentration on the recess 12 at the bottom-side corner portions can be alleviated. Thereby, undesired cracks due to stress on the recess 12 can be suppressed.

[0127] Next, referring to FIG. 10D, the 4H-SiC crystal structure 1 may be cleaved starting from the recess 12. The 4H-SiC crystal structure 1 may be cleaved through the same process as that of FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than the impurity concentration of the SiC epitaxial layer 17, the attenuation rate of the laser light with respect to the SiC semiconductor wafer 16 becomes higher than the attenuation rate of the laser light with respect to the SiC epitaxial layer 17.

[0128] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, the SiC semiconductor wafer 16 can be efficiently heated. Thereby, the compressive stress generated in the heating process of the recess 12 and the tensile stress generated in the cooling process of the recess 12 can be increased.

[0129] Thus, the cleavage force applied to the 4H-SiC crystal structure 1 can be increased. The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed from the remaining portion of the recess 12.

[0130] As described above, according to this SiC processing method, the outer surface of the SiC epitaxial layer 17 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. Further, the 4H-SiC crystal structure 1 can be cleaved using the depression 12.

[0131] In particular, according to the depression 12 with the rounded opening-side corner, the stress concentration on the depression 12 at the opening-side corner can be alleviated. Further, according to the depression 12 with the rounded bottom-side corner, the stress concentration on the depression 12 at the bottom-side corner can be alleviated. Thereby, undesired cracks caused by the stress on the depression 12 can be suppressed.

[0132] Figs. 11A to 11D are cross-sectional perspective views for explaining the SiC processing method according to the fifth embodiment of the present invention, which are partial regions of the 4H-SiC crystal structure 1 shown in Fig. 3. Hereinafter, the description of the structure and manufacturing process corresponding to the structure and manufacturing process described in Figs. 5A to 5D will be omitted.

[0133] First, referring to Fig. 11A, a 4H-SiC crystal structure 1 as an example of an object to be processed with SiC is prepared. In this form, the 4H-SiC crystal structure 1 has a laminated structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (for example, n-type impurity concentration) less than the impurity concentration (for example, n-type impurity concentration) of the SiC semiconductor wafer 16.

[0134] The first main surface 2 of the 4H-SiC crystal structure 1 is formed by the SiC epitaxial layer 17. The second main surface 3 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16. The side surface 4 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0135] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0136] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0137] The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0138] Next, referring to FIG. 11B, a modified layer 11, a depression 12, and a recess 13 are formed in a processing region 10 selectively provided on the first main surface 2 of the 4H-SiC crystal structure 1. The modified layer 11, the depression 12, and the recess 13 are formed through the same steps as those in FIG. 5B described above.

[0139] The modified layer 11, the depression 12, and the recess 13 are formed in the SiC epitaxial layer 17. More specifically, the modified layer 11, the depression 12, and the recess 13 are also formed in the SiC semiconductor wafer 16 across the boundary between the SiC semiconductor wafer 16 and the SiC epitaxial layer 17 from the SiC epitaxial layer 17.

[0140] Next, referring to FIG. 11C, while the 4H-SiC crystal structure 1 is left intact, the modified layer 11 is partially removed and the outer surface of the modified layer 11 is planarized. The modified layer 11 is removed through the same steps as those in FIG. 5C described above. As a result, the opening-side corner of the recess 13 is rounded in a curved shape toward the inside of the recess 13. Also, the bottom-side corner of the recess 13 is rounded in a curved shape toward the outside of the recess 13.

[0141] According to the recess 13 with rounded opening-side corners, stress concentration on the modified layer 11 at the opening-side corners can be alleviated. Also, according to the recess 13 with rounded bottom-side corners, stress concentration on the modified layer 11 at the bottom-side corners can be alleviated. Thereby, undesired cracks caused by stress on the modified layer 11 can be suppressed.

[0142] Next, referring to FIG. 11D, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved through the same process as in FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than the impurity concentration of the SiC epitaxial layer 17, the attenuation rate of the laser light with respect to the SiC semiconductor wafer 16 becomes higher than the attenuation rate of the laser light with respect to the SiC epitaxial layer 17.

[0143] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, the SiC semiconductor wafer 16 can be efficiently heated. In particular, in this process, the SiC semiconductor wafer 16 can be heated through the modified layer 11 formed in the SiC semiconductor wafer 16.

[0144] Thereby, the compressive stress generated in the heating process of the depression 12 and the tensile stress generated in the cooling process of the depression 12 can be efficiently increased. Thus, the cleavage force applied to the 4H-SiC crystal structure 1 can be efficiently increased.

[0145] The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed of a remaining portion of the depression 12. A part of the modified layer 11 is exposed at the corner connecting the first main surface 2 and the cleavage plane 14 of the 4H-SiC crystal structure 1. The modified layer 11 is formed along the inclined portion 15.

[0146] As described above, according to this SiC processing method, the outer surface of the SiC epitaxial layer 17 can be processed by the formation process of the modified layer 11 and the removal process of the modified layer 11. Also, the 4H-SiC crystal structure 1 can be cleaved using the depression 12.

[0147] In particular, according to the recess 13 with rounded opening-side corners, stress concentration on the modified layer 11 at the opening-side corners can be alleviated. Further, according to the recess 13 with rounded bottom-side corners, stress concentration on the modified layer 11 at the bottom-side corners can be alleviated. Thereby, undesired cracks caused by stress on the modified layer 11 can be suppressed.

[0148] Figs. 12A to 12D are cross-sectional perspective views for explaining an SiC processing method according to a sixth embodiment of the present invention, which are partial regions of the 4H-SiC crystal structure 1 shown in Fig. 3. Hereinafter, descriptions of structures and manufacturing processes corresponding to those described in Figs. 5A to 5D will be omitted.

[0149] First, referring to Fig. 12A, a 4H-SiC crystal structure 1 as an example of an SiC processing target is prepared. In this form, the 4H-SiC crystal structure 1 has a laminated structure including an SiC semiconductor wafer 16 and an SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (for example, n-type impurity concentration) lower than the impurity concentration (for example, n-type impurity concentration) of the SiC semiconductor wafer 16.

[0150] The first main surface 2 of the 4H-SiC crystal structure 1 is formed by the SiC epitaxial layer 17. The second main surface 3 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16. The side surface 4 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0151] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0152] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0153] The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0154] Next, referring to FIG. 12B, a modified layer 11, a depression 12, and a recess 13 are formed in a processing region 10 selectively set on the first main surface 2 of the 4H-SiC crystal structure 1. The modified layer 11 is formed through the same process as that in FIG. 5B described above.

[0155] The modified layer 11, the depression 12, and the recess 13 are formed in the SiC epitaxial layer 17. More specifically, the modified layer 11, the depression 12, and the recess 13 are also formed in the SiC semiconductor wafer 16 across the boundary between the SiC semiconductor wafer 16 and the SiC epitaxial layer 17 from the SiC epitaxial layer 17.

[0156] Next, referring to FIG. 12C, while the 4H-SiC crystal structure 1 is left remaining, all of the modified layer 11 is removed. The modified layer 11 is removed through the same process as that in FIG. 5C described above. As a result, the depression 12 partitioned by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17 remains on the first main surface 2.

[0157] In this step, the opening side corners of the recess 12 are rounded in a curved shape towards the inside of the recess 12. Also, the bottom side corners of the recess 12 are rounded in a curved shape towards the outside of the recess 12. According to the recess 12 with the rounded opening side corners, stress concentration on the recess 12 at the opening side corners can be alleviated. Also, according to the recess 12 with the rounded bottom side corners, stress concentration on the recess 12 at the bottom side corners can be alleviated. Thereby, undesired cracks caused by stress on the recess 12 can be suppressed.

[0158] Next, referring to FIG. 12D, the 4H-SiC crystal structure 1 may be cleaved starting from the recess 12. The 4H-SiC crystal structure 1 may be cleaved through the same steps as those in FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than the impurity concentration of the SiC epitaxial layer 17, the attenuation rate of the laser light with respect to the SiC semiconductor wafer 16 becomes higher than the attenuation rate of the laser light with respect to the SiC epitaxial layer 17.

[0159] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, the SiC semiconductor wafer 16 can be efficiently heated. In particular, in this step, the SiC semiconductor wafer 16 exposed from the bottom of the recess 12 can be directly heated by the laser light.

[0160] Thereby, the compressive stress generated in the heating step of the recess 12 and the tensile stress generated in the cooling step of the recess 12 can be efficiently increased. Thus, the cleavage force applied to the 4H-SiC crystal structure 1 can be efficiently increased. The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed of the remaining portion of the recess 12.

[0161] As described above, according to this SiC processing method, the outer surface of the SiC epitaxial layer 17 can be processed by the formation step of the modified layer 11 and the removal step of the modified layer 11. Also, the 4H-SiC crystal structure 1 can be cleaved using the recess 12 formed in the SiC epitaxial layer 17 through the removal step of the modified layer 11.

[0162] In particular, according to the recess 12 with rounded opening-side corners, stress concentration on the recess 12 at the opening-side corners can be alleviated. Further, according to the recess 12 with rounded bottom-side corners, stress concentration on the recess 12 at the bottom-side corners can be alleviated. Thereby, undesired cracks caused by stress on the recess 12 can be suppressed.

[0163] Figs. 13A to 13D are cross-sectional perspective views for explaining an SiC processing method according to a seventh embodiment of the present invention, which are partial regions of the 4H-SiC crystal structure 1 shown in Fig. 3. Hereinafter, descriptions of structures and manufacturing processes corresponding to those described in Figs. 5A to 5D are omitted.

[0164] First, referring to Fig. 13A, a 4H-SiC crystal structure 1 as an example of an SiC processing target is prepared. In this form, the 4H-SiC crystal structure 1 has a laminated structure including an SiC semiconductor wafer 16 and an SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (for example, an n-type impurity concentration) lower than the impurity concentration (for example, an n-type impurity concentration) of the SiC semiconductor wafer 16.

[0165] The first main surface 2 of the 4H-SiC crystal structure 1 is formed by the SiC epitaxial layer 17. The second main surface 3 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16. The side surface 4 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0166] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0167] The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0168] Next, referring to FIG. 13B, instead of the first main surface 2 of the 4H-SiC crystal structure 1, a modified layer 11, a depression 12, and a recess 13 are formed in a processing region 10 selectively set on the second main surface 3 of the 4H-SiC crystal structure 1. That is, the modified layer 11, the depression 12, and the recess 13 are formed on the SiC semiconductor wafer 16. The modified layer 11, the depression 12, and the recess 13 are formed on the second main surface 3 through the same process as in FIG. 5B described above.

[0169] The depression 12 includes a bottom portion and side portions. The depression 12 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the bottom portion. The bottom portion of the depression 12 may be formed in a curved shape toward the first main surface 2. The depression 12 includes an opening-side corner portion and a bottom-side corner portion. The opening-side corner portion of the depression 12 connects the second main surface 3 and the side portions of the depression 12. The bottom-side corner portion of the depression 12 connects the bottom portion and the side portions of the depression 12.

[0170] The width W of the depression 12 may be more than 0 μm and 10 μm or less. The width W of the depression 12 is the width in a direction orthogonal to the direction in which the depression 12 extends. The width W of the depression 12 may be more than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width W of the depression 12 is preferably more than 0 μm and 5 μm or less.

[0171] The depth D of the depression 12 may be more than 0 μm and 30 μm or less. The depth D of the depression 12 is the distance from the second main surface 3 to the bottommost part of the depression 12 with respect to the normal direction N. The depth D of the depression 12 may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the depth D of the depression 12 is preferably more than 0 μm and 15 μm or less.

[0172] The modified layer 11 is formed in a film shape along the inner wall of the depression 12. The thickness of the portion of the modified layer 11 that covers the bottom wall of the depression 12 may be larger than the thickness of the portion of the modified layer 11 that covers the side wall of the depression 12. The modified layer 11 may be formed with a uniform thickness along the inner wall of the depression 12.

[0173] The modified layer 11 demarcates a recess 13 within the depression 12. More specifically, the recess 13 is demarcated by the outer surface of the modified layer 11. The recess 13 includes a bottom portion and side portions. The recess 13 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the first main surface 2. The bottom of the recess 13 may be formed in a curved shape toward the first main surface 2.

[0174] The recess 13 includes an opening-side corner portion and a bottom-side corner portion. The opening-side corner portion of the recess 13 connects the second main surface 3 and the side portion of the recess 13. The bottom-side corner portion of the recess 13 connects the bottom portion and the side portion of the recess 13.

[0175] The width WR of the recess 13 is less than the width W of the depression 12. The width WR of the recess 13 may be more than 0 μm and less than 10 μm. The width WR of the recess 13 may be more than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and less than 10 μm. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width WR of the recess 13 is preferably more than 0 μm and less than 5 μm.

[0176] The depth DR of the recess 13 is less than the depth D of the depression 12. The depth DR of the recess 13 may be more than 0 μm and less than 30 μm. The depth DR of the recess 13 may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and less than 30 μm. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 13 is preferably more than 0 μm and 15 μm or less.

[0177] Next, referring to FIG. 13C, while the 4H-SiC crystal structure 1 is left intact, the modified layer 11 is partially removed and the outer surface of the modified layer 11 is flattened. The modified layer 11 is removed through the same process as in FIG. 5C described above. As a result, the opening-side corner portion of the recess 13 is rounded in a curved shape toward the inside of the recess 13. Also, the bottom-side corner portion of the recess 13 is rounded in a curved shape toward the outside of the recess 13.

[0178] According to the recess 13 with the rounded opening-side corner portion, stress concentration on the modified layer 11 at the opening-side corner portion can be alleviated. Also, according to the recess 13 with the rounded bottom-side corner portion, stress concentration on the modified layer 11 at the bottom-side corner portion can be alleviated. Thereby, undesired cracks due to stress on the modified layer 11 can be suppressed.

[0179] Next, referring to FIG. 13D, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved through the same process as in FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than the impurity concentration of the SiC epitaxial layer 17, the attenuation rate of the laser light with respect to the SiC semiconductor wafer 16 becomes higher than the attenuation rate of the laser light with respect to the SiC epitaxial layer 17.

[0180] Therefore, by irradiating the SiC semiconductor wafer 16 with laser light so as to reach it, the SiC semiconductor wafer 16 can be efficiently heated. In particular, in this step, the SiC semiconductor wafer 16 can be heated by the laser light through the modified layer 11. Thereby, the compressive stress generated in the heating step of the depression 12 and the tensile stress generated in the cooling step of the depression 12 can be efficiently increased. Therefore, the cleavage force applied to the 4H-SiC crystal structure 1 can be efficiently increased.

[0181] The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed of a remaining portion of the depression 12. A part of the modified layer 11 is exposed at a corner connecting the second main surface 3 and the cleavage plane 14 of the 4H-SiC crystal structure 1. The modified layer 11 is formed along the inclined portion 15.

[0182] As described above, according to this SiC processing method, the outer surface of the SiC semiconductor wafer 16 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. Also, the 4H-SiC crystal structure 1 can be cleaved using the depression 12.

[0183] In particular, according to the recess 13 with the rounded opening-side corner, stress concentration on the modified layer 11 at the opening-side corner can be alleviated. Also, according to the recess 13 with the rounded bottom-side corner, stress concentration on the modified layer 11 at the bottom-side corner can be alleviated. Thereby, undesired cracks caused by stress on the modified layer 11 can be suppressed.

[0184] Figs. 14A to 14D are cross-sectional perspective views for explaining the SiC processing method according to the eighth embodiment of the present invention, which are partial regions of the 4H-SiC crystal structure 1 shown in Fig. 3. Hereinafter, descriptions of the structures and manufacturing steps corresponding to the structures and manufacturing steps described in Figs. 5A to 5D will be omitted.

[0185] First, referring to FIG. 14A, a 4H-SiC crystal structure 1 as an example of a SiC object to be processed is prepared. In this form, the 4H-SiC crystal structure 1 has a laminated structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (for example, an n-type impurity concentration) less than the impurity concentration (for example, an n-type impurity concentration) of the SiC semiconductor wafer 16.

[0186] The first main surface 2 of the 4H-SiC crystal structure 1 is formed by the SiC epitaxial layer 17. The second main surface 3 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16. The side surface 4 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0187] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0188] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0189] The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0190] Next, referring to FIG. 14B, instead of the first main surface 2 of the 4H-SiC crystal structure 1, a modified layer 11, a depression 12, and a recess 13 are formed in a processing region 10 selectively set on the second main surface 3 of the 4H-SiC crystal structure 1. The modified layer 11, the depression 12, and the recess 13 are formed in the SiC semiconductor wafer 16. The modified layer 11, the depression 12, and the recess 13 are formed on the second main surface 3 through the same process as that in FIG. 5B described above.

[0191] The depression 12 includes a bottom portion and side portions. The depression 12 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the bottom portion. The bottom portion of the depression 12 may be formed in a curved shape toward the first main surface 2. The depression 12 includes an opening-side corner portion and a bottom-side corner portion. The opening-side corner portion of the depression 12 connects the second main surface 3 and the side portions of the depression 12. The bottom-side corner portion of the depression 12 connects the bottom portion and the side portions of the depression 12.

[0192] The width W of the depression 12 may be greater than 0 μm and 10 μm or less. The width W of the depression 12 is the width in a direction orthogonal to the direction in which the depression 12 extends. The width W of the depression 12 may be greater than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width W of the depression 12 is preferably greater than 0 μm and 5 μm or less.

[0193] The depth D of the depression 12 may be greater than 0 μm and 30 μm or less. The depth D of the depression 12 is the distance from the second main surface 3 to the lowermost portion of the depression 12 with respect to the normal direction N. The depth D of the depression 12 may be greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the depth D of the depression 12 is preferably greater than 0 μm and 15 μm or less.

[0194] The modified layer 11 is formed in a film shape along the inner wall of the recess 12. The thickness of the portion of the modified layer 11 that covers the bottom wall of the recess 12 may be greater than the thickness of the portion of the modified layer 11 that covers the side wall of the recess 12. The modified layer 11 may be formed with a uniform thickness along the inner wall of the recess 12.

[0195] The modified layer 11 demarcates a recess 13 within the recess 12. More specifically, the recess 13 is demarcated by the outer surface of the modified layer 11. The recess 13 includes a bottom portion and side portions. The recess 13 may be formed in a tapered shape with an opening width that narrows from the second main surface 3 towards the first main surface 2. The bottom of the recess 13 may be formed in a curved shape towards the first main surface 2.

[0196] The recess 13 includes an opening-side corner portion and a bottom-side corner portion. The opening-side corner portion of the recess 13 connects the second main surface 3 and the side portion of the recess 13. The bottom-side corner portion of the recess 13 connects the bottom and the side portion of the recess 13.

[0197] The width WR of the recess 13 is less than the width W of the recess 12. The width WR of the recess 13 may be greater than 0 μm and less than 10 μm. The width WR of the recess 13 may be greater than 0 μm and less than or equal to 2.5 μm, greater than or equal to 2.5 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 7.5 μm, or greater than or equal to 7.5 μm and less than 10 μm. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width WR of the recess 13 is preferably greater than 0 μm and less than 5 μm.

[0198] The depth DR of the recess 13 is less than the depth D of the recess 12. The depth DR of the recess 13 may be greater than 0 μm and less than 30 μm. The depth DR of the recess 13 may be greater than 0 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, greater than or equal to 15 μm and less than or equal to 20 μm, greater than or equal to 20 μm and less than or equal to 25 μm, or greater than or equal to 25 μm and less than 30 μm. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 13 is preferably greater than 0 μm and less than or equal to 15 μm.

[0199] Next, referring to FIG. 14C, while leaving the 4H-SiC crystal structure 1 intact, all of the modified layer 11 is removed. The modified layer 11 is removed through the same process as in FIG. 5C described above. As a result, the recess 12 partitioned by the SiC semiconductor wafer 16 remains on the second main surface 3. In this process, the opening-side corner portion of the recess 12 is rounded in a curved shape toward the inside of the recess 12. Also, the bottom-side corner portion of the recess 12 is rounded in a curved shape toward the outside of the recess 12.

[0200] According to the recess 12 with the rounded opening-side corner portion, stress concentration on the recess 12 at the opening-side corner portion can be alleviated. Also, according to the recess 12 with the rounded bottom-side corner portion, stress concentration on the recess 12 at the bottom-side corner portion can be alleviated. Thereby, undesired cracks due to stress on the recess 12 can be suppressed.

[0201] Next, referring to FIG. 14D, the 4H-SiC crystal structure 1 may be cleaved starting from the recess 12. The 4H-SiC crystal structure 1 may be cleaved through the same process as in FIG. 5D described above. When the impurity concentration of the SiC semiconductor wafer 16 is higher than the impurity concentration of the SiC epitaxial layer 17, the attenuation rate of the laser light with respect to the SiC semiconductor wafer 16 becomes higher than the attenuation rate of the laser light with respect to the SiC epitaxial layer 17.

[0202] Therefore, by irradiating the laser light so as to reach the SiC semiconductor wafer 16, the SiC semiconductor wafer 16 can be efficiently heated. In particular, in this process, the portion of the SiC semiconductor wafer 16 that is exposed from the bottom of the recess 12 can be directly heated by the laser light.

[0203] Thereby, the compressive stress generated in the heating process of the recess 12 and the tensile stress generated in the cooling process of the recess 12 can be efficiently increased. Thus, the cleavage force applied to the 4H-SiC crystal structure 1 can be efficiently increased. The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed from the remaining portion of the recess 12.

[0204] As described above, according to this SiC processing method, the outer surface of the SiC semiconductor wafer 16 can be processed by the step of forming the modified layer 11 and the step of removing the modified layer 11. Further, using the recess 12, the 4H-SiC crystal structure 1 can also be cleaved.

[0205] In particular, according to the recess 12 with the rounded opening-side corner, the stress concentration on the recess 12 at the opening-side corner can be alleviated. Further, according to the recess 12 with the rounded bottom-side corner, the stress concentration on the recess 12 at the bottom-side corner can be alleviated. Thereby, undesired cracks caused by the stress on the recess 12 can be suppressed.

[0206] Figs. 15A to 15D are cross-sectional perspective views for explaining the SiC processing method according to the ninth embodiment of the present invention, which are partial regions of the 4H-SiC crystal structure 1 shown in Fig. 3. Hereinafter, the description of the structure and manufacturing process corresponding to the structure and manufacturing process described in Figs. 5A to 5D will be omitted.

[0207] First, referring to Fig. 15A, a 4H-SiC crystal structure 1 as an example of an object to be processed is prepared. On the first main surface 2 of the 4H-SiC crystal structure 1, in this form, a coating layer 18 covering the first main surface 2 is formed. The coating layer 18 may have a single-layer structure composed of a metal layer or an insulating layer. The coating layer 18 may have a laminated structure including a metal layer and an insulating layer.

[0208] Examples of the insulating material of the coating layer 18 include silicon oxide and silicon nitride. Examples of the metal material of the coating layer 18 include aluminum, copper, gold, titanium, titanium nitride, and the like. The coating layer 18 may be formed by at least one method among an oxidation treatment method, a CVD method, a sputtering method, a vapor deposition method, and a plating method.

[0209] Next, referring to Fig. 15B, a modified layer 11, a recess 12, and a recess 13 are formed in a processing region 10 selectively set on the first main surface 2 of the 4H-SiC crystal structure 1. The modified layer 11, the recess 12, and the recess 13 are formed on the first main surface 2 through the same process as in Fig. 5B described above.

[0210] In this step, the first main surface 2 is irradiated with laser light through the coating layer 18. The coating layer 18 is melted or sublimated by the irradiation of the laser light. Thereby, the first main surface 2 is exposed from the coating layer 18. Further, the portion of the first main surface 2 exposed from the coating layer 18 is continuously irradiated with laser light.

[0211] Thereby, the modified layer 11, the depression 12, and the recess 13 are formed on the first main surface 2. The depression 12 may communicate with the removed portion of the coating layer 18. The modified layer 11 may cover the coating layer 18. The modified layer 11 may cover the removed portion of the coating layer 18.

[0212] Here, an example in which the step of irradiating the 4H-SiC crystal structure 1 with laser light is carried out simultaneously with the step of irradiating the coating layer 18 with laser light has been described. However, the step of irradiating the 4H-SiC crystal structure 1 with laser light may be carried out after changing the irradiation conditions and the like after the step of irradiating the coating layer 18 with laser light.

[0213] The attenuation rate of the laser light with respect to the coating layer 18 is preferably equal to or higher than the attenuation rate of the laser light with respect to the 4H-SiC crystal structure 1. Thereby, the coating layer 18 can be efficiently melted or sublimated by the laser energy with respect to the 4H-SiC crystal structure 1.

[0214] Next, referring to FIG. 15C, the modified layer 11 is partially removed while the 4H-SiC crystal structure 1 and the coating layer 18 are left, and the outer surface of the modified layer 11 is flattened. The modified layer 11 is removed through the same steps as those in FIG. 5C described above.

[0215] The modified layer 11 has components different from those of the coating layer 18. The etching rate (etching selectivity) for the modified layer 11 is different from the etching rate (etching selectivity) for the coating layer 18. Therefore, a part of the modified layer 11 can be removed while leaving the 4H-SiC crystal structure 1 and the coating layer 18. As a result, the opening-side corner of the recess 13 is rounded in a curved shape facing inward of the recess 13. Also, the bottom-side corner of the recess 13 is rounded in a curved shape facing outward of the recess 13.

[0216] According to the recess 13 with the rounded opening-side corner, stress concentration on the modified layer 11 at the opening-side corner can be alleviated. Also, according to the recess 13 with the rounded bottom-side corner, stress concentration on the modified layer 11 at the bottom-side corner can be alleviated. Thereby, undesired cracks due to stress on the modified layer 11 can be suppressed.

[0217] Next, referring to FIG. 15D, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved through the same process as in FIG. 5D described above. The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed by a remaining part of the depression 12. Also, the inclined portion 15 is exposed from the coating layer 18.

[0218] As described above, according to this SiC processing method, the outer surface of the 4H-SiC crystal structure 1 can be processed by the formation process of the modified layer 11 and the removal process of the modified layer 11. Also, using the depression 12 formed on the outer surface of the 4H-SiC crystal structure 1 through the removal process of the modified layer 11, the 4H-SiC crystal structure 1 can be cleaved.

[0219] In particular, according to the recess 13 with the rounded opening-side corner, stress concentration on the modified layer 11 at the opening-side corner can be alleviated. Also, according to the recess 13 with the rounded bottom-side corner, stress concentration on the modified layer 11 at the bottom-side corner can be alleviated. Thereby, undesired cracks due to stress on the modified layer 11 can be suppressed.

[0220] In this embodiment, an example in which a part of the modified layer 11 is removed from the first main surface 2 of the 4H-SiC crystal structure 1 in the process of FIG. 15C has been described. However, in the process of FIG. 15C, all of the modified layer 11 may be removed. The manufacturing method in which the coating layer 18 is formed is also applicable to the first to eighth embodiments described above.

[0221] FIGS. 16A to 16D are cross-sectional perspective views for explaining the SiC processing method according to the tenth embodiment of the present invention, which are partial regions of the 4H-SiC crystal structure 1 shown in FIG. 3. Hereinafter, descriptions of the structures and manufacturing processes corresponding to the structures and manufacturing processes described in FIGS. 5A to 5D will be omitted.

[0222] First, referring to FIG. 16A, a 4H-SiC crystal structure 1 as an example of an object to be processed is prepared. In this form, the 4H-SiC crystal structure 1 has a laminated structure including a SiC semiconductor wafer 16 and a SiC epitaxial layer 17. The SiC epitaxial layer 17 may have an impurity concentration (for example, n-type impurity concentration) lower than the impurity concentration (for example, n-type impurity concentration) of the SiC semiconductor wafer 16.

[0223] The first main surface 2 of the 4H-SiC crystal structure 1 is formed by the SiC epitaxial layer 17. The second main surface 3 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16. The side surface 4 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 16 and the SiC epitaxial layer 17.

[0224] The SiC epitaxial layer 17 is formed by epitaxially growing SiC from the SiC semiconductor wafer 16. The thickness of the SiC epitaxial layer 17 is less than the thickness of the SiC semiconductor wafer 16.

[0225] The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor wafer 16 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0226] The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 17 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less.

[0227] On the second main surface 3 of the 4H-SiC crystal structure 1, in this form, a coating layer 18 covering the second main surface 3 is formed. The coating layer 18 may have a single-layer structure composed of a metal layer or an insulating layer. The coating layer 18 may have a laminated structure including a metal layer and an insulating layer.

[0228] Examples of the insulating material of the coating layer 18 include silicon oxide or silicon nitride. Examples of the metal material of the coating layer 18 include aluminum, copper, gold, titanium, titanium nitride, etc. The coating layer 18 may be formed by at least one method among an oxidation treatment method, a CVD method, a sputtering method, a vapor deposition method, and a plating method.

[0229] Next, referring to FIG. 16B, instead of the first main surface 2 of the 4H-SiC crystal structure 1, a modified layer 11, a depression 12, and a recess 13 are formed in a processing region 10 selectively set on the second main surface 3 of the 4H-SiC crystal structure 1. The modified layer 11, the depression 12, and the recess 13 are formed on the second main surface 3 through the same process as in FIG. 5B described above.

[0230] In this step, the second main surface 3 is irradiated with laser light through the coating layer 18. The coating layer 18 is melted or sublimated by the irradiation of the laser light. As a result, the second main surface 3 is exposed from the coating layer 18. Further, the exposed portion of the second main surface 3 from the coating layer 18 is continuously irradiated with laser light. Thereby, the modified layer 11, the recess 12, and the recess 13 are formed on the second main surface 3.

[0231] Here, an example in which the step of irradiating the 4H-SiC crystal structure 1 with laser light is performed simultaneously with the step of irradiating the coating layer 18 with laser light has been described. However, the step of irradiating the 4H-SiC crystal structure 1 with laser light may be performed after changing the irradiation conditions or the like after the step of irradiating the coating layer 18 with laser light.

[0232] The attenuation rate of the laser light with respect to the coating layer 18 is preferably equal to or higher than the attenuation rate of the laser light with respect to the 4H-SiC crystal structure 1. Thereby, the coating layer 18 can be efficiently melted or sublimated by the laser energy with respect to the 4H-SiC crystal structure 1.

[0233] The recess 12 includes a bottom portion and side portions. The recess 12 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the bottom portion. The bottom portion of the recess 12 may be formed in a curved shape toward the first main surface 2. The recess 12 includes an opening-side corner portion and a bottom-side corner portion. The opening-side corner portion of the recess 12 connects the second main surface 3 and the side portions of the recess 12. The bottom-side corner portion of the recess 12 connects the bottom portion and the side portions of the recess 12. The recess 12 may communicate with the removed portion of the coating layer 18.

[0234] The width W of the recess 12 may be more than 0 μm and 10 μm or less. The width W of the recess 12 is the width in a direction orthogonal to the direction in which the recess 12 extends. The width W of the recess 12 may be more than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width W of the recess 12 is preferably more than 0 μm and 5 μm or less.

[0235] The depth D of the depression 12 may be more than 0 μm and 30 μm or less. The depth D of the depression 12 is the distance from the second main surface 3 to the lowermost part of the depression 12 with respect to the normal direction N. The depth D of the depression 12 may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the depth D of the depression 12 is preferably more than 0 μm and 15 μm or less.

[0236] The modified layer 11 is formed in a film shape along the inner wall of the depression 12. The thickness of the portion covering the bottom surface of the depression 12 in the modified layer 11 may be larger than the thickness of the portion covering the side wall of the depression 12 in the modified layer 11. The modified layer 11 may be formed with a uniform thickness along the inner wall of the depression 12. The modified layer 11 may cover the coating layer 18. The modified layer 11 may cover the removed portion of the coating layer 18.

[0237] The modified layer 11 partitions the recess 13 in the depression 12. More specifically, the recess 13 is partitioned by the outer surface of the modified layer 11. The recess 13 includes a bottom portion and side portions. The recess 13 may be formed in a tapered shape in which the opening width narrows from the second main surface 3 toward the first main surface 2. The bottom of the recess 13 may be formed in a curved shape toward the first main surface 2.

[0238] The recess 13 includes an opening-side corner portion and a bottom-side corner portion. The opening-side corner portion of the recess 13 connects the second main surface 3 and the side portion of the recess 13. The bottom-side corner portion of the recess 13 connects the bottom portion and the side portion of the recess 13.

[0239] The width WR of the recess 13 is less than the width W of the depression 12. The width WR of the recess 13 may be more than 0 μm and less than 10 μm. The width WR of the recess 13 may be more than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width WR of the recess 13 is preferably more than 0 μm and less than 5 μm.

[0240] The depth DR of the recess 13 is less than the depth D of the depression 12. The depth DR of the recess 13 may be more than 0 μm and less than 30 μm. The depth DR of the recess 13 may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 13 is preferably more than 0 μm and 15 μm or less.

[0241] Next, referring to FIG. 16C, while the 4H-SiC crystal structure 1 and the coating layer 18 are left intact, the modified layer 11 is partially removed and the outer surface of the modified layer 11 is planarized. The modified layer 11 is removed through the same process as in FIG. 5C described above.

[0242] The modified layer 11 has a component different from that of the coating layer 18. The etching rate (etching selectivity) with respect to the modified layer 11 is different from the etching rate (etching selectivity) with respect to the coating layer 18. Therefore, while the 4H-SiC crystal structure 1 and the coating layer 18 are left intact, a part of the modified layer 11 can be removed. As a result, the corner portion on the opening side of the recess 13 is rounded in a curved shape inward of the recess 13. Also, the corner portion on the bottom side of the recess 13 is rounded in a curved shape outward of the recess 13.

[0243] According to the recess 13 with rounded opening-side corners, stress concentration on the modified layer 11 at the opening-side corners can be alleviated. Also, according to the recess 13 with rounded bottom-side corners, stress concentration on the modified layer 11 at the bottom-side corners can be alleviated. Thereby, undesired cracks caused by stress on the modified layer 11 can be suppressed.

[0244] Next, referring to FIG. 16D, the 4H-SiC crystal structure 1 may be cleaved starting from the depression 12. The 4H-SiC crystal structure 1 may be cleaved through the same process as in FIG. 5D described above. The cleaved 4H-SiC crystal structure 1 has a cleavage plane 14. The cleavage plane 14 is continuous with an inclined portion 15 formed of the remaining portion of the depression 12. Also, the inclined portion 15 is exposed from the coating layer 18.

[0245] As described above, according to this SiC processing method, the outer surface of the 4H-SiC crystal structure 1 can be processed by the modified layer 11 formation step and the modified layer 11 removal step. Also, the 4H-SiC crystal structure 1 can be cleaved using the depression 12 formed on the outer surface of the 4H-SiC crystal structure 1 through the modified layer 11 removal step.

[0246] In particular, according to the recess 13 with rounded opening-side corners, stress concentration on the modified layer 11 at the opening-side corners can be alleviated. Also, according to the recess 13 with rounded bottom-side corners, stress concentration on the modified layer 11 at the bottom-side corners can be alleviated. Thereby, undesired cracks caused by stress on the modified layer 11 can be suppressed.

[0247] In this embodiment, an example in which a part of the modified layer 11 is removed in the process of FIG. 16C has been described. However, in the process of FIG. 16C, all of the modified layer 11 may be removed. The manufacturing method in which the coating layer 18 is formed is also applicable to the first to eighth embodiments described above.

[0248] FIG. 17 is a perspective view showing a schematic configuration of the SiC semiconductor device 21 according to the 11th embodiment of the present invention. FIG. 18 is a plan view of the SiC semiconductor device 21 shown in FIG. 17. FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 18. FIG. 20 is an enlarged view of region XX shown in FIG. 19. The SiC semiconductor device 21 is a device manufactured using the aforementioned 4H-SiC crystal structure 1.

[0249] Referring to FIGS. 17 to 20, the SiC semiconductor device 21 includes an SiC semiconductor layer 22. The thickness of the SiC semiconductor layer 22 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor layer 22 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0250] The SiC semiconductor layer 22 has a first main surface 23 on one side, a second main surface 24 on the other side, and side surfaces 25A, 25B, 25C, 25D connecting the first main surface 23 and the second main surface 24. In this embodiment, the side surfaces 25A to 25D are all cut surfaces. More specifically, the side surfaces 25A to 25D are cleavage surfaces.

[0251] The first main surface 23 and the second main surface 24 are formed in a rectangular shape (a rectangular shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") as viewed from their normal directions N. The side surface 25A faces the side surface 25C. The side surface 25B faces the side surface 25D.

[0252] The SiC semiconductor layer 22 includes a 4H-SiC single crystal. The first main surface 23 and the second main surface 24 face the c-plane of the 4H-SiC single crystal. The first main surface 23 faces the (0001) plane, and the second main surface 24 faces the (000-1) plane.

[0253] The first major surface 23 and the second major surface 24 have an off-angle θ that is inclined at an angle of 10° or less in the [11-20] direction with respect to the (0001) plane. The off-angle θ may be 0° or more and 2° or less, 2° or more and 4° or less, 4° or more and 6° or less, 6° or more and 8° or less, or 8° or more and 10° or less. It is preferable that the off-angle θ is 0° or more and 4° or less.

[0254] That the off-angle θ is 0° means that the normal direction N and the c-axis coincide. The off-angle θ may be more than 0° and less than 4°. The off-angle θ is typically set in the range of 2° or 4°, more specifically, in the range of 2° ± 10% or 4° ± 10%.

[0255] The side surfaces 25A to 25D extend planar along the normal direction N, respectively. The length of the side surfaces 25A to 25D may each be 1 mm or more and 10 mm or less. The length of the side surfaces 25A to 25D may be 1 mm or more and 2.5 mm or less, 2.5 mm or more and 5 mm or less, 5 mm or more and 7.5 mm or less, or 7.5 mm or more and 10 mm or less. It is preferable that the length of the side surfaces 25A to 25D is 2 mm or more and 5 mm or less.

[0256] The side surfaces 25A to 25D extend along the nearest neighbor atom direction and the intersection direction of the nearest neighbor atom directions. The intersection direction of the nearest neighbor atom directions is more specifically the orthogonal direction orthogonal to the nearest neighbor atom direction. In this form, the side surfaces 25A to 25D extend along the [11-20] direction and the [1-100] direction.

[0257] The side surface 25A and the side surface 25C are formed along the [11-20] direction. The side surface 25B and the side surface 25D are formed along the [1-100] direction. The side surface 25A and the side surface 25C may be formed along the [1-100] direction, and the side surface 25B and the side surface 25D may be formed along the [11-20] direction.

[0258] The in-plane variation of the side surfaces 25A to 25D is 20 μm or less. The in-plane variation along the [11-20] direction of the side surfaces 25B and 25D extending along the [1-100] direction is 20 μm or less. More specifically, the in-plane variation of the side surfaces 25B and 25D is 10 μm or less.

[0259] The in-plane variation along the [1-100] direction of the side surfaces 25A and 25C extending along the [11-20] direction is 20 μm or less. More specifically, the in-plane variation of the side surfaces 25A and 25C is 10 μm or less.

[0260] The in-plane variation is defined by the maximum value of the distance between a reference virtual line and a measurement virtual line set on one of the side surfaces 25A to 25D selected from the side surfaces 25A to 25D. The reference virtual line is a straight line connecting two corner portions of the SiC semiconductor layer 22 in a plan view and is set on one of the side surfaces 25A to 25D selected. The measurement virtual line is a straight line extending parallel to the reference virtual line in a plan view and is set so as to be in contact with the top or base of a protrusion (meandering) existing on one of the side surfaces 25A to 25D selected.

[0261] For example, the distance between the reference virtual line and the measurement virtual line in contact with the top of the protrusion (meandering), and the distance between the reference virtual line and the measurement virtual line in contact with the base of the protrusion (meandering) are measured. The in-plane variation of one of the side surfaces 25A to 25D selected is defined by the maximum value of the measured distance between the reference virtual line and the measurement virtual line.

[0262] The SiC semiconductor layer 22 has a laminated structure including an n-type SiC semiconductor substrate 31 and an n-type SiC epitaxial layer 32 in this form. The second main surface 24 of the SiC semiconductor layer 22 is formed by the SiC semiconductor substrate 31. The first main surface 23 of the SiC semiconductor layer 22 is formed by the SiC epitaxial layer 32. The side surfaces 25A to 25D of the SiC semiconductor layer 22 are formed by the SiC semiconductor substrate 31 and the SiC epitaxial layer 32. +

[0263] ​The thickness of the SiC semiconductor substrate 31 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 31 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less. It is preferable that the thickness of the SiC semiconductor substrate 31 is 50 μm or more and 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 31, the resistance value can be reduced by shortening the current path.

[0264] The SiC epitaxial layer 32 has a thickness less than that of the SiC semiconductor substrate 31. The thickness of the SiC epitaxial layer 32 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 32 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less. It is preferable that the thickness of the SiC epitaxial layer 32 is 5 μm or more and 20 μm or less.

[0265] The n-type impurity concentration of the SiC epitaxial layer 32 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 31. The n-type impurity concentration of the SiC semiconductor substrate 31 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity concentration of the SiC epitaxial layer 32 may be 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less.

[0266] The SiC semiconductor layer 22 includes an active region 33 and an outer region 34. The active region 33 includes an impurity region 33A having n-type impurities and / or p-type impurities. The active region 33 is a region where a semiconductor functional device is formed by the impurity region 33A. The semiconductor functional device may include a diode. The semiconductor functional device may include a transistor. The semiconductor functional device may include a field effect transistor.

[0267] In plan view, the active region 33 may be set at the center of the SiC semiconductor layer 22 at a distance from the inner region from the side surfaces 25A to 25D. The active region 33 may be set in a rectangular shape having four sides parallel to the side surfaces 25A to 25D in plan view.

[0268] The outer region 34 is a region outside the active region 33. The outer region 34 may be set in a region between the side surfaces 25A to 25D and the periphery of the active region 33. The outer region 34 may be set in an annular shape (for example, endless) surrounding the active region 33 in plan view.

[0269] The SiC semiconductor device 21 includes an insulating layer 35 formed on the first main surface 23. The insulating layer 35 selectively covers the first main surface 23. The insulating layer 35 may include silicon oxide or silicon nitride. The peripheral portion of the insulating layer 35 is continuous with the side surfaces 25A to 25D. An opening 39 for selectively exposing the active region 33 is formed in the insulating layer 35.

[0270] The SiC semiconductor device 21 includes a first electrode layer 36 formed on the first main surface 23. More specifically, the first electrode layer 36 is formed on the insulating layer 35. The first electrode layer 36 may include conductive polysilicon or metal. The first electrode layer 36 enters the opening 39 from above the insulating layer 35. The first electrode layer 36 is electrically connected to the active region 33 within the opening 39.

[0271] The SiC semiconductor device 21 includes a resin layer 37 formed on the first main surface 23. More specifically, the resin layer 37 is formed on the insulating layer 35. The resin layer 37 selectively covers the first electrode layer 36. The peripheral portion 46 of the resin layer 37 described above is formed at a distance from the side surfaces 25A to 25D in the inner region. As a result, the resin layer 37 exposes the peripheral portion of the SiC semiconductor layer 22 in plan view.

[0272] The resin layer 37 may contain a negative-type or positive-type photosensitive resin. In this form, the resin layer 37 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 37 may contain polyimide as an example of a negative-type photosensitive resin. An opening 40 for exposing the first electrode layer 36 is formed in the resin layer 37.

[0273] The SiC semiconductor device 21 includes a second electrode layer 38 formed on the second main surface 24. The second electrode layer 38 covers the second main surface 24. The second electrode layer 38 is electrically connected to the second main surface 24. The second electrode layer 38 may contain conductive polysilicon or metal.

[0274] At the corner connecting the first main surface 23 and the side surfaces 25A to 25D of the SiC semiconductor layer 22, an inclined portion 41 inclined downward from the first main surface 23 toward the side surfaces 25A to 25D is formed. The corner of the SiC semiconductor layer 22 includes a corner connecting the first main surface 23 and the side surfaces 25A and 25C and extending along the [11-20] direction. The corner of the SiC semiconductor layer 22 includes a corner connecting the first main surface 23 and the side surfaces 25B and 25D and extending along the [1-100] direction.

[0275] More specifically, the inclined portion 41 is formed in the SiC epitaxial layer 32. The inclined portion 41 is formed in a region on the first main surface 23 side with respect to the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32. Therefore, the SiC epitaxial layer 32 is exposed from the inclined portion 41.

[0276] The inclined portion 41 is formed by the inner wall of a depression that is recessed from the first main surface 23 toward the second main surface 24. The inclined portion 41 has an upper end portion 41a and a lower end portion 41b. The upper end portion 41a of the inclined portion 41 is located on the first main surface 23 side. The lower end portion 41b of the inclined portion 41 is located on the second main surface 24 side.

[0277] The upper end portion 41a of the inclined portion 41 extends from the SiC epitaxial layer 32 toward the insulating layer 35 and is continuous with the insulating layer 35. That is, the SiC epitaxial layer 32 and the insulating layer 35 are exposed from the inclined portion 41. Further, the peripheral portion of the insulating layer 35 is formed in the inner region of the SiC semiconductor layer 22 with respect to the side surfaces 25A to 25D.

[0278] The upper end portion 41a of the inclined portion 41 is connected to the upper surface of the insulating layer 35. In the inclined portion 41, the upper connection portion 41c that connects the upper end portion 41a of the inclined portion 41 and the upper surface of the insulating layer 35 may be formed in a curved shape that extends outward from the SiC semiconductor layer 22. The lower end portion 41b of the inclined portion 41 is connected to the side surfaces 25A to 25D. The lower end portion 41b of the inclined portion 41 may be formed in a curved shape that extends toward the second main surface 24.

[0279] The width WI of the inclined portion 41 may be equal to or less than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 may be less than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 is the width in a direction orthogonal to the direction in which the inclined portion 41 extends in a plan view.

[0280] The width WI of the inclined portion 41 may be greater than 0 μm and equal to or less than 10 μm. The width WI may be greater than 0 μm and equal to or less than 2 μm, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WI of the inclined portion 41 is preferably greater than 0 μm and equal to or less than 5 μm. More preferably, the width WI of the inclined portion 41 is greater than 0 μm and equal to or less than 2.5 μm.

[0281] The depth D of the inclined portion 41 may be more than 0 μm and 30 μm or less. The depth D of the inclined portion 41 is the distance from the first main surface 23 to the lower end portion of the inclined portion 41 with respect to the normal direction N. The depth D of the inclined portion 41 may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the depth D of the inclined portion 41 is preferably more than 0 μm and 15 μm or less.

[0282] The SiC semiconductor device 21 is formed in a region on the first main surface 23 side on the side surfaces 25A to 25D and includes a modified layer 42 in which SiC is modified to other properties. In this form, the modified layer 42 is formed in the SiC epitaxial layer 32. More specifically, the modified layer 42 is formed in a region on the first main surface 23 side with respect to the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32.

[0283] The modified layer 42 is formed along the corners connecting the first main surface 23 and the side surfaces 25A to 25D. More specifically, the modified layer 42 is formed at the corner connecting the first main surface 23 and the side surfaces 25A and 25C and extending along the [11-20] direction. Further, the modified layer 42 is formed at the corner connecting the first main surface 23 and the side surfaces 25B and 25D and extending along the [1-100] direction.

[0284] The modified layer 42 extends in a strip shape along the side surfaces 25A to 25D in a direction parallel to the first main surface 23. That is, the modified layer 42 extends in a strip shape along the [1-100] direction and the [11-20] direction. The modified layer 42 is formed in an annular shape (for example, endless) surrounding the active region 33 on the side surfaces 25A to 25D.

[0285] The modified layer 42 is formed in a film shape along the inclined portion 41 of the SiC semiconductor layer 22. The thickness of the portion of the modified layer 42 covering the bottom wall of the inclined portion 41 may be greater than the thickness of the portion of the modified layer 42 covering the side wall of the inclined portion 41. The modified layer 42 may be formed with a uniform thickness along the inner wall of the inclined portion 41.

[0286] The modified layer 42 includes an upper covering portion 42a and a lower covering portion 42b. The upper covering portion 42a of the modified layer 42 covers the upper end portion 41a of the inclined portion 41. The upper covering portion 42a of the modified layer 42 covers the SiC epitaxial layer 32. The upper covering portion 42a of the modified layer 42 extends from the SiC epitaxial layer 32 toward the insulating layer 35 and covers the insulating layer 35. The upper covering portion 42a of the modified layer 42 may be formed in a curved shape extending outward from the SiC semiconductor layer 22.

[0287] The lower covering portion 42b of the modified layer 42 covers the lower end portion 41b of the inclined portion 41. The lower covering portion 42b of the modified layer 42 covers the SiC epitaxial layer 32. The lower covering portion 42b of the modified layer 42 includes a connecting portion 42c connected to the side surfaces 25A to 25D. The connecting portion 42c of the modified layer 42 may be a portion where the modified layer 42 is cleaved. The connecting portion 42c of the modified layer 42 may be formed flush with the side surfaces 25A to 25D.

[0288] The modified layer 42 is exposed from the peripheral portion 46 of the resin layer 37. The peripheral portion 46 of the resin layer 37 is a portion where a dicing street was formed when the SiC semiconductor device 21 was cut out from the 4H-SiC crystal structure 1. By exposing the modified layer 42 from the resin layer 37, it becomes unnecessary to physically cut the resin layer 37. Therefore, the SiC semiconductor device 21 can be smoothly cut out from the 4H-SiC crystal structure 1 while appropriately protecting the active region 33 by the resin layer 37.

[0289] The width WM of the modified layer 42 may be equal to or less than the in-plane variation of the side surfaces 25A to 25D. The width WM of the modified layer 42 may be less than the in-plane variation of the side surfaces 25A to 25D. The width WM of the modified layer 42 is the width in a direction orthogonal to the direction in which the modified layer 42 extends in plan view.

[0290] The width WM of the modified layer 42 may be greater than 0 μm and equal to or less than 10 μm. The width WM of the modified layer 42 may be greater than 0 μm and equal to or less than 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WM of the modified layer 42 is preferably greater than 0 μm and equal to or less than 5 μm. More preferably, the width WM of the modified layer 42 is greater than 0 μm and equal to or less than 2.5 μm.

[0291] The thickness T of the modified layer 42 may be greater than 0 μm and equal to or less than 30 μm. The thickness T of the modified layer 42 is the thickness along the normal direction N in the modified layer 42. The thickness T of the modified layer 42 may be greater than 0 μm and equal to or less than 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, greater than or equal to 15 μm and less than or equal to 20 μm, greater than or equal to 20 μm and less than or equal to 25 μm, or greater than or equal to 25 μm and less than or equal to 30 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the thickness T of the modified layer 42 is preferably greater than 0 μm and equal to or less than 15 μm.

[0292] FIG. 21 is an enlarged view of the region XXI shown in FIG. 17. FIG. 22 is a graph showing the configuration of the modified layer 42. FIG. 22 shows the results of examining the components of the SiC semiconductor layer 22 by Raman spectroscopy.

[0293] In FIG. 21, a first region A, a second region B, and a third region C are shown. The first region A shows the surface layer portion of the modified layer 42. The surface layer portion of the modified layer 42 is a region (here, the upper covering portion 42a) located on the first main surface 23 side of the SiC semiconductor layer 22 in the modified layer 42.

[0294] The second region B indicates the bottom of the modified layer 42. The bottom of the modified layer 42 is a region in the modified layer 42 that is located on the second main surface 24 side with respect to the surface layer portion of the modified layer 42 (here, the lower covering portion 42b). The third region C indicates a region outside the modified layer 42 in the SiC semiconductor layer 22 (here, the SiC epitaxial layer 32).

[0295] FIG. 22 shows a first curve LA, a second curve LB, and a third curve LC. The first curve LA indicates the components of the first region A shown in FIG. 21. The second curve LB indicates the components of the second region B shown in FIG. 21. The third curve LC indicates the components of the third region C shown in FIG. 21.

[0296] The first curve LA has a peak value derived from Si (silicon) in the wavelength range of 500 nm or more and 550 nm or less. The second curve LB has a peak value derived from Si (silicon) in the wavelength range of 500 nm or more and 550 nm or less, and has a peak value derived from C (carbon) in the wavelength range of 1300 nm or more and 1700 nm or less.

[0297] The third curve LC has a peak value derived from SiC (silicon carbide) in the wavelength range of 750 nm or more and 800 nm or less. Therefore, in the third region C, the modified layer 42 is not formed, and only the 4H-SiC single crystal exists.

[0298] Referring to the first curve LA, the silicon density of the surface layer portion (the first region A) of the modified layer 42 is higher than the carbon density of the surface layer portion of the modified layer 42. That is, the surface layer portion of the modified layer 42 includes an Si modified layer in which the SiC of the 4H-SiC crystal structure 1 is modified to Si. The Si modified layer may include polycrystalline Si. The Si modified layer may include amorphous Si. The Si modified layer may include polycrystalline Si and amorphous Si. The Si modified layer may mainly include an Si amorphous layer.

[0299] Referring to the second curve LB, the silicon density at the bottom of the modified layer 42 (second region B) is higher than the carbon density at the bottom of the modified layer 42. The bottom of the modified layer 42 includes a Si modified layer in which the SiC of the 4H-SiC crystal structure 1 is modified to Si. The Si modified layer may include polycrystalline Si. The Si modified layer may include amorphous Si. The Si modified layer may include polycrystalline Si and amorphous Si. The Si modified layer may mainly include a Si amorphous layer.

[0300] Referring to the first curve LA and the second curve LB, the modified layer 42 has different components in the surface layer portion (first region A) and the bottom portion (second region B). More specifically, the modified layer 42 has different silicon densities along the thickness direction. The silicon density at the bottom of the modified layer 42 is lower than the silicon density at the surface layer portion of the modified layer 42. Also, the modified layer 42 has different carbon densities along the thickness direction. The carbon density at the bottom of the modified layer 42 is higher than the carbon density at the surface layer portion of the modified layer 42.

[0301] FIG. 23 is a perspective view showing the 4H-SiC crystal structure 1 used in the manufacture of the SiC semiconductor device 21 shown in FIG. 17.

[0302] Referring to FIG. 23, in the manufacturing method of the SiC semiconductor device 21, the 4H-SiC crystal structure 1 having a stacked structure including the SiC semiconductor wafer 51 and the SiC epitaxial layer 52 is used. The SiC semiconductor wafer 51 serves as the base of the SiC semiconductor substrate 31. The SiC epitaxial layer 52 serves as the base of the SiC epitaxial layer 32. The SiC epitaxial layer 52 is formed by epitaxially growing SiC from the SiC semiconductor wafer 51.

[0303] The first main surface 2 of the 4H-SiC crystal structure 1 is formed by the SiC epitaxial layer 52. The second main surface 3 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 51. The side surface 4 of the 4H-SiC crystal structure 1 is formed by the SiC semiconductor wafer 51 and the SiC epitaxial layer 52.

[0304] In the method for manufacturing the SiC semiconductor device 21, a plurality of device regions 53 corresponding to the SiC semiconductor device 21 are set on the first main surface 2 of the 4H-SiC crystal structure 1. The plurality of device regions 53 are set in a matrix array at intervals in the [1-100] direction and the [11-20] direction. The plurality of device regions 53 each have a side along the [1-100] direction and a side along the [11-20] direction.

[0305] The plurality of device regions 53 are partitioned by a lattice-shaped planned cutting line 54 extending along the [1-100] direction and the [11-20] direction. More specifically, the planned cutting line 54 includes a plurality of first planned cutting lines 55 and a plurality of second planned cutting lines 56. The plurality of first planned cutting lines 55 each extend along the [1-100] direction. The plurality of second planned cutting lines 56 each extend along the [11-20] direction.

[0306] After a predetermined structure is formed in the 4H-SiC crystal structure 1, the 4H-SiC crystal structure 1 is cut along the planned cutting line 54, whereby a plurality of SiC semiconductor devices 21 are cut out.

[0307] Figs. 24A to 24L are cross-sectional perspective views for explaining an example of the method for manufacturing the SiC semiconductor device 21 shown in Fig. 17, which are partial regions of the 4H-SiC crystal structure 1 shown in Fig. 23.

[0308] In Figs. 24A to 24L, four device regions 53 are shown as partial regions of the 4H-SiC crystal structure 1. Also, in Figs. 24I to 24K, enlarged end views of a partial region of the device region 53 as seen from the [1-100] direction are shown. In Figs. 24A to 24L, the technical concept described in Figs. 9A to 9D above is incorporated.

[0309] First, referring to Fig. 24A, the 4H-SiC crystal structure 1 shown in Fig. 23 is prepared.

[0310] Next, referring to FIG. 24B, a plurality of active regions 33 are respectively formed in a plurality of device regions 53. The plurality of active regions 33 are respectively formed by introducing p-type impurities and / or n-type impurities into the plurality of device regions 53.

[0311] Next, referring to FIG. 24C, an insulating layer 35 is formed on the first main surface 2 of the 4H-SiC crystal structure 1. The insulating layer 35 contains silicon oxide. The insulating layer 35 may be formed by a CVD method or a thermal oxidation treatment method. In this form, the insulating layer 35 is formed by thermal oxidation treatment on the first main surface 2.

[0312] Next, referring to FIG. 24D, unnecessary portions of the insulating layer 35 are removed. Thereby, a plurality of openings 39 are formed in the insulating layer 35. Each opening 39 exposes the active region 33 of each device region 53. The unnecessary portions of the insulating layer 35 may be removed by an etching method through a mask (not shown).

[0313] Next, referring to FIG. 24E, a first electrode layer 36 is formed on the insulating layer 35. In the formation process of the first electrode layer 36, first, a conductive material is deposited on the insulating layer 35 by a sputtering method or a CVD method. Next, unnecessary portions of the conductive material are removed by an etching method through a mask (not shown). Thereby, each first electrode layer 36 is formed in each device region 53.

[0314] Next, referring to FIG. 24F, a resin is applied on the insulating layer 35, and a resin layer 37 covering the first electrode layer 36 is formed.

[0315] Next, referring to FIG. 24G, after the resin layer 37 is selectively exposed, it is developed. Thereby, a resin layer 37 having an opening 40 exposing each first electrode layer 36 and a peripheral portion 46 exposing a planned cutting line 54 is formed on the insulating layer 35. The peripheral portion 46 of the resin layer 37 demarcates a dicing street.

[0316] Next, referring to FIG. 24H, the second electrode layer 38 is formed on the second main surface 3 of the 4H-SiC crystal structure 1. The second electrode layer 38 is formed by depositing a conductive material on the second main surface 3 by a sputtering method or a CVD method.

[0317] Next, referring to FIG. 24I, the planned cutting line 54 is heated, and a modified layer 42 (first modified layer) in which SiC is modified to other properties is formed. Here, an example is shown in which the first planned cutting line 55 along the [1-100] direction is heated first.

[0318] More specifically, the formation process of the modified layer 42 includes a step of heating the planned cutting line 54 to a temperature at which C atoms are desorbed or sublimated from SiC. Thereby, the modified layer 42 is formed on the first main surface 2 of the 4H-SiC crystal structure 1.

[0319] The heating of the planned cutting line 54 may be performed by an ablation processing method using laser irradiation. In the ablation processing method, an ultraviolet laser may be used. The laser energy, laser pulse duty ratio, and laser irradiation speed are each set to arbitrary values according to the size, shape, thickness, etc. of the modified layer 42 to be formed.

[0320] In the ablation processing method, the first main surface 2 is irradiated with laser light through the insulating layer 35. The insulating layer 35 is melted or sublimated by the irradiation of the laser light. Thereby, the first main surface 2 is exposed from the insulating layer 35. Further, the laser light is continuously irradiated to the portion of the first main surface 2 exposed from the insulating layer 35. Thereby, the modified layer 42 is formed on the first main surface 2.

[0321] Also, in this step, a depression 57 that penetrates the insulating layer 35 and is recessed from the first main surface 2 toward the second main surface 3 is formed. The depression 57 includes a bottom portion and side portions. The depression 57 may be formed in a tapered shape in which the opening width narrows from the first main surface 2 toward the bottom portion. The bottom portion of the depression 57 may be formed in a curved shape toward the second main surface 3.

[0322] The width W of the depression 57 may be more than 0 μm and 10 μm or less. The width W of the depression 57 is the width in the direction orthogonal to the direction in which the depression 57 extends. The width W of the depression 57 may be more than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width W of the depression 57 is preferably more than 0 μm and 5 μm or less.

[0323] The modified layer 42 is formed in a film shape along the inner wall of the depression 57. The thickness of the portion of the modified layer 42 covering the bottom wall of the depression 57 may be larger than the thickness of the portion of the modified layer 42 covering the side wall of the depression 57. The modified layer 42 may be formed with a uniform thickness along the inner wall of the depression 57.

[0324] The modified layer 42 is also formed on the insulating layer 35 within the depression 57. That is, the modified layer 42 is formed so as to cover the insulating layer 35 within the depression 57. The modified layer 42 partitions the recess 58 within the depression 57. The recess 58 is more specifically partitioned by the outer surface of the modified layer 42.

[0325] The recess 58 includes a bottom portion and side portions. The recess 58 may be formed in a tapered shape in which the opening width narrows from the first main surface 2 toward the bottom. The bottom of the recess 58 may be formed in a curved shape toward the second main surface 3. The recess 58 includes an opening-side corner portion and a bottom-side corner portion. The opening-side corner portion of the recess 58 connects the upper surface of the insulating layer 35 and the side portion of the recess 58. The bottom-side corner portion of the recess 58 connects the bottom of the recess 58 and the side portion of the recess 58.

[0326] The width WR of the recess 58 is less than the width W of the depression 57. The width WR of the recess 58 may be more than 0 μm and less than 10 μm. The width WR of the recess 58 may be more than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and less than 10 μm. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the width WR of the recess 58 is preferably more than 0 μm and less than 5 μm.

[0327] The depth DR of the recess 58 is less than the depth D of the depression 57. The depth DR of the recess 58 may be more than 0 μm and less than 30 μm. The depth DR of the recess 58 may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and less than 30 μm. When the thickness of the 4H-SiC crystal structure 1 is 150 μm or less, the depth DR of the recess 58 is preferably more than 0 μm and 15 μm or less.

[0328] Next, referring to FIG. 24J, a second planned cutting line 56 along the [11-20] direction is heated in the same manner as in FIG. 24I. As a result, a modified layer 42 (second modified layer), a depression 57, and a recess 58 are formed in the second planned cutting line 56.

[0329] The modified layer 42, the depression 57, and the recess 58 along the first planned cutting line 55 form a first cleavage line 61 for cleaving the 4H-SiC crystal structure 1 along the [1-100] direction. The modified layer 42, the depression 57, and the recess 58 along the second planned cutting line 56 form a second cleavage line 62 for cleaving the 4H-SiC crystal structure 1 along the [11-20] direction.

[0330] In this step, the step of forming the second cleavage line 62 after forming the first cleavage line 61 has been described. However, the formation order of the first cleavage line 61 and the second cleavage line 62 is arbitrary and not limited to the above order. For example, the first cleavage line 61 may be formed after the second cleavage line 62 is formed. Also, any first planned cutting line 55 and any second planned cutting line 56 may be selected, and the first cleavage line 61 and the second cleavage line 62 may be formed alternately.

[0331] Next, referring to FIG. 24K, after the formation step of the modified layer 42, the corners of the modified layer 42 may be rounded. More specifically, the outer surface of the modified layer 42 may be flattened by removing the irregularities from the outer surface of the modified layer 42. The modified layer 42 may be removed by an etching method. The etching method may be a dry etching method or a wet etching method. The modified layer 42 may be removed by a plasma etching method as an example of the dry etching method.

[0332] The modified layer 42 has a component different from that of the 4H-SiC crystal structure 1. The etching rate (etching selectivity) for the modified layer 42 is different from the etching rate (etching selectivity) for SiC. Also, the modified layer 42 has a component different from that of the insulating layer 35. The etching rate (etching selectivity) for the modified layer 42 is different from the etching rate (etching selectivity) for the insulating layer 35.

[0333] Therefore, a part of the modified layer 42 can be removed while leaving the 4H-SiC crystal structure 1 and the insulating layer 35. As a result, the opening-side corner portion of the recess 58 is rounded in a curved shape toward the inside of the recess 58. Also, the bottom-side corner portion of the recess 58 is rounded in a curved shape toward the outside of the recess 58.

[0334] According to the recess 58 with the rounded opening-side corner portion, stress concentration on the modified layer 42 at the opening-side corner portion can be relaxed. Also, according to the recess 58 with the rounded bottom-side corner portion, stress concentration on the modified layer 42 at the bottom-side corner portion can be relaxed. Thereby, undesired cracks caused by the stress on the modified layer 42 can be suppressed. In the process of FIG. 24K, the technical idea of FIGS. 8A to 8D may be incorporated and all of the modified layer 42 may be removed.

[0335] Next, referring to FIG. 24L, the 4H-SiC crystal structure 1 is cleaved along the first cleavage line 61 ([1-100] direction) and the second cleavage line 62 ([11-20] direction). Hereinafter, the cleavage process of the 4H-SiC crystal structure 1 will be specifically described with reference to FIGS. 25A to 25D.

[0336] Figures 25A to 25D are perspective views showing the 4H-SiC crystal structure 1 shown in FIG. 23, and are perspective views for explaining an example of the cleavage process of FIG. 24L.

[0337] Referring to FIG. 25A, in this process, first, the 4H-SiC crystal structure 1 is cleaved along the intersection direction of the nearest neighbor atom directions. That is, the 4H-SiC crystal structure 1 is cleaved along the first cleavage line 61 ([1-100] direction). More specifically, the 4H-SiC crystal structure 1 is sequentially cleaved along any first cleavage line 61 selected from a plurality of first cleavage lines 61.

[0338] The 4H-SiC crystal structure 1 may be cleaved by applying stress to the first cleavage line 61. In this process, a process of applying thermal stress to the first cleavage line 61 by heating and cooling is performed.

[0339] The heating process of the first cleavage line 61 may be performed by a laser irradiation method. The laser irradiation method may be performed by an infrared laser (for example, a CO2 laser). By the heating process of the first cleavage line 61, a compressive stress starting from the first cleavage line 61 is thermally induced. The laser energy, the laser pulse duty ratio, and the laser irradiation speed are each set to an arbitrary value according to the magnitude of the stress to be applied to the first cleavage line 61.

[0340] The cooling process of the first cleavage line 61 may include a process of supplying a cooling fluid to the first cleavage line 61. The cooling fluid may include water or air, or a mixture of water and air (aerosol). By the cooling process of the first cleavage line 61, a tensile stress starting from the first cleavage line 61 is thermally induced.

[0341] The supply process of the cooling fluid may include an injection process of the cooling fluid by a coolant jet method or a cooling gas supply method. The cooling process of the first cleavage line 61 may be performed after the heating process of the first cleavage line 61. The cooling process of the first cleavage line 61 may be performed simultaneously with the heating process of the first cleavage line 61.

[0342] Due to the compressive stress generated in the heating process of the first cleavage line 61 and the tensile stress generated in the cooling process of the first cleavage line 61, the 4H-SiC crystal structure 1 is cleaved along the first cleavage line 61 ([1-100] direction).

[0343] As a result, as shown in Fig. 25B, the 4H-SiC crystal structure 1 is divided into a plurality of strip-shaped portions extending along the [1-100] direction. The plurality of strip-shaped portions each include a plurality of device regions 53 arranged in a row along the [1-100] direction.

[0344] Next, referring to Fig. 25C, the 4H-SiC crystal structure 1 is cleaved along the nearest neighbor atom direction. That is, the 4H-SiC crystal structure 1 is cleaved along the second cleavage line 62 ([11-20] direction). More specifically, the 4H-SiC crystal structure 1 is sequentially cleaved along an arbitrary second cleavage line 62 selected from a plurality of second cleavage lines 62.

[0345] The 4H-SiC crystal structure 1 may be cleaved by applying stress to the second cleavage line 62. In this process, a process of applying thermal stress to the second cleavage line 62 by heating and cooling is performed.

[0346] The heating process of the second cleavage line 62 may be performed by a laser irradiation method. The laser irradiation method may be performed by an infrared laser (for example, a CO2 laser). By the heating process of the second cleavage line 62, a compressive stress starting from the second cleavage line 62 is thermally induced. The laser energy, the laser pulse duty ratio, and the laser irradiation speed are each set to an arbitrary value according to the magnitude of the stress to be applied to the second cleavage line 62.

[0347] The cooling process of the second cleavage line 62 may include a step of supplying a cooling fluid to the second cleavage line 62. The cooling fluid may include water or air, or a mixture of water and air (aerosol). By the cooling process of the second cleavage line 62, a tensile stress starting from the second cleavage line 62 is thermally induced.

[0348] The supply of the cooling fluid may be performed by injecting (spraying) the cooling fluid by a coolant jet method or a cooling gas supply method. The cooling process of the second cleavage line 62 may be performed after the heating process of the second cleavage line 62. The cooling process of the second cleavage line 62 may be performed simultaneously with the heating process of the second cleavage line 62.

[0349] Due to the compressive stress generated in the heating process of the second cleavage line 62 and the tensile stress generated in the cooling process of the second cleavage line 62, the 4H-SiC crystal structure 1 is cleaved along the second cleavage line 62 ([11-20] direction).

[0350] Thereby, as shown in FIG. 25D, a plurality of SiC semiconductor devices 21 are cut out from a plurality of strip-shaped portions extending along the [1-100] direction. Through the steps including the above, the SiC semiconductor device 21 is manufactured.

[0351] FIG. 26 is a plan view for explaining the planar shape of the SiC semiconductor device 71 separated through the manufacturing method of the SiC semiconductor device 71 according to the reference example. FIG. 27 is a plan view for explaining the planar shape of the SiC semiconductor device 21 shown in FIG. 17 separated through the manufacturing method of FIGS. 25A to 25D.

[0352] In the manufacturing method of the SiC semiconductor device 71 according to the reference example, after the 4H-SiC crystal structure 1 is cleaved (thermally cut) along the second cleavage line 62 ([11-20] direction), the 4H-SiC crystal structure 1 is cleaved (thermally cut) along the first cleavage line 61 ([1-100] direction). That is, in the manufacturing method of the SiC semiconductor device 71 according to the reference example, after the cleavage process in the nearest neighbor atom direction, the cleavage process in the crossing direction of the nearest neighbor atom direction is performed.

[0353] Referring to FIG. 26, in the SiC semiconductor device 71 according to the reference example, the side surfaces 25A and 25C along the [11-20] direction are formed relatively flat. In the cleavage process in the [11-20] direction, the 4H-SiC crystal structure 1 is cleaved along the nearest neighbor atom direction, and at the same time, the stress (thermal stress) generated in the 4H-SiC crystal structure 1 continues continuously. Therefore, the generation of ridges in the cleavage portion is suppressed.

[0354] On the other hand, meanders 72 that bulge relatively large along the [11-20] direction are formed on the side surfaces 25B and 25D along the [1-100] direction. Among the side surfaces 25A to 25D, the in-plane variation of the side surfaces 25B and 25D along the [1-100] direction exceeds 20 μm.

[0355] In the cleavage process in the [1-100] direction, the 4H-SiC crystal structure 1 is cleaved along the crossing direction of the nearest neighbor atom direction. Moreover, since the 4H-SiC crystal structure 1 has already been cleaved along the [11-20] direction, the stress (thermal stress) applied to the 4H-SiC crystal structure 1 cannot be continuously continued.

[0356] As a result, the force that retains the Si atom arrangement ([11-20] direction) acts from the side surfaces 25A and 25C, and meanders 72 that bulge relatively large are formed on the side surfaces 25B and 25D. Such meanders 72 tend to occur especially starting from the connection portion 73 between the side surfaces 25A and 25C formed by the first cleavage process and the side surfaces 25B and 25D formed by the second cleavage process. In the SiC semiconductor device 71 according to the reference example, the in-plane variation of the side surfaces 25B and 25D is deteriorated by these meanders 72.

[0357] The in-plane variation is defined by the maximum value of the distance between a reference virtual line 74 and a measurement virtual line 75 set on one of the side surfaces 25A to 25D selected from the side surfaces 25A to 25D. The reference virtual line 74 is a straight line connecting two corner portions of the SiC semiconductor layer 22 in a plan view, and is set on one of the side surfaces 25A to 25D selected. The measurement virtual line 75 is a straight line extending parallel to the reference virtual line 74 in a plan view, and is set so as to be in contact with the top or the base of a protrusion (meandering 72) existing on one of the side surfaces 25A to 25D.

[0358] For example, the distance between the reference virtual line 74 and the measurement virtual line 75 in contact with the top of the protrusion (meandering 72), and the distance between the reference virtual line 74 and the measurement virtual line 75 in contact with the base of the protrusion (meandering 72) are measured. The in-plane variation of one of the side surfaces 25A to 25D selected is defined by the maximum value of the measured distance between the reference virtual line 74 and the measurement virtual line 75.

[0359] The distance between a plurality of device regions 53 adjacent in the [11-20] direction and the [1-100] direction is set in consideration of the meandering 72 (in-plane variation). Therefore, when a relatively large meandering 72 (in-plane variation) is formed, it is necessary to increase the distance between the plurality of device regions 53 in order to suppress the contact of adjacent SiC semiconductor devices 71. Therefore, the number of SiC semiconductor devices 71 that can be obtained from one 4H-SiC crystal structure 1 is limited by the meandering 72 (in-plane variation).

[0360] On the other hand, referring to FIG. 27, in the method for manufacturing the SiC semiconductor device 21, after the 4H-SiC crystal structure 1 is cleaved (thermally cut) along the first cleavage line 61 ([1-100] direction), the 4H-SiC crystal structure 1 is cleaved (thermally cut) along the second cleavage line 62 ([11-20] direction). That is, in the method for manufacturing the SiC semiconductor device 21, after the cleavage step in the intersecting direction of the nearest neighbor atom direction, the cleavage step in the nearest neighbor atom direction is performed.

[0361] In the cleavage process in the [1-100] direction, the 4H-SiC crystal structure 1 is cleaved in the intersection direction of the nearest neighbor atom direction. However, since the stress (thermal stress) applied to the 4H-SiC crystal structure 1 continues continuously, the generation of ridges at the cleavage part is suppressed.

[0362] On the other hand, in the cleavage process in the [11-20] direction, since the 4H-SiC crystal structure 1 has already been cleaved along the [1-100] direction, the stress (thermal stress) applied to the 4H-SiC crystal structure 1 becomes discontinuous. However, in this process, stress (thermal stress) is applied to the 4H-SiC crystal structure 1 along the nearest neighbor atom direction ([11-20] direction), and the 4H-SiC crystal structure 1 is cleaved along the nearest neighbor atom direction ([11-20] direction). As a result, the generation of ridges at the cleavage part is suppressed.

[0363] In particular, according to this process sequence, the generation of the meandering 72 starting from the connection part 73 connecting the side surfaces 25A, 25C and the side surfaces 25B, 25D is suppressed. As a result, in the side surfaces 25A to 25D, in-plane variations of 20 μm or less, more specifically, 10 μm or less can be achieved. Also, according to this process sequence, in-plane variations of 20 μm or less, more specifically, 10 μm or less can be achieved in the side surfaces 25B, 25D along the [1-100] direction. Therefore, the flatness of all of the side surfaces 25A to 25D can be improved.

[0364] Also, since the meandering 72 can be suppressed, the distance between a plurality of adjacent device regions 53 in the [11-20] direction and the [1-100] direction can be narrowed. As a result, the number of SiC semiconductor devices 21 that can be obtained from one 4H-SiC crystal structure 1 can be increased.

[0365] Referring to FIGS. 26 and 27, it is understood that when the stress (thermal stress) applied to the 4H-SiC crystal structure 1 is continuous, the straightness of cleavage is stable regardless of the crystal direction. On the other hand, when the stress (thermal stress) generated in the 4H-SiC crystal structure 1 is discontinuous, it is understood that the straightness of cleavage in the intersection direction of the nearest neighbor atom direction becomes unstable.

[0366] Such a phenomenon is remarkably observed in semiconductor materials having a relatively high thermal conductivity among various semiconductor materials used in semiconductor devices. In particular, SiC has a relatively high thermal conductivity compared to the thermal conductivity of single-crystalline silicon (Si), the thermal conductivity of sapphire (Al2O3), the thermal conductivity of gallium nitride (GaN), and the like.

[0367] The thermal conductivity of SiC is 4.5 W / cmK or more and 5.5 W / cmK or less (more specifically, about 4.9 W / cmK). The thermal conductivity of Si is about 1.5 W / cmK. The thermal conductivity of sapphire (Al2O3) is about 0.4 W / cmK. The thermal conductivity of gallium nitride (GaN) is about 2.0 W / cmK.

[0368] That is, SiC has a property that the stress (thermal stress) caused by heat dissipation is likely to be discontinuous compared to single-crystalline silicon (Si), sapphire (Al2O3), gallium nitride (GaN), and the like. Therefore, in SiC, the risk of in-plane variation increases in the cleavage process in the direction intersecting the nearest neighbor atom direction when the stress (thermal stress) is discontinuous. Therefore, the order of performing the cleavage process in the nearest neighbor atom direction after the cleavage process in the direction intersecting the nearest neighbor atom direction is particularly effective for SiC having a relatively high thermal conductivity.

[0369] From the comparison between FIGS. 26 and 27, consider the case where the SiC semiconductor layer 22 has side surfaces 25A and 25C forming the short sides of the rectangle and side surfaces 25B and 25D forming the long sides of the rectangle in plan view. In this case, the side surfaces 25B and 25D have an area exceeding the area of the side surfaces 25A and 25C.

[0370] Therefore, when there are side surfaces having a relatively large area, it is preferable to predetermine the orientations of the plurality of device regions 53 with respect to the crystal direction so that stress (thermal stress) is continuously transmitted in the second cutting step. That is, it is preferable that the side surfaces 25A and 25C forming the short sides of the rectangle are formed along the [1-100] direction, and the side surfaces 25B and 25D forming the long sides of the rectangle are formed along the [11-20] direction.

[0371] In this case, first, the 4H-SiC crystal structure 1 is cut along the [1-100] direction to form the side surfaces 25A and 25C that form the short sides of the rectangle. Thereafter, the 4H-SiC crystal structure 1 is cut along the [11-20] direction to form the side surfaces 25B and 25D that form the long sides of the rectangle.

[0372] According to this process sequence, the continuity of stress (thermal stress) can be enhanced in the second cutting step, so that the flatness can be enhanced in the side surfaces 25B and 25D having a relatively large area. Therefore, when cutting the rectangular device region 53, it is preferable to set the short side of the device region 53 in the [1-100] direction and the long side of the device region 53 in the [11-20] direction.

[0373] As described above, according to the present embodiment, a crystal cutting method capable of appropriately cutting the hexagonal 4H-SiC crystal structure 1 from two different directions can be provided. Further, according to the present embodiment, a method for manufacturing a SiC semiconductor device using the crystal cutting method can be provided. Further, a SiC semiconductor device 21 can be manufactured and provided by such a method for manufacturing a SiC semiconductor device.

[0374] FIG. 28 is a cross-sectional view of a region corresponding to FIG. 19, and is a cross-sectional view showing a schematic configuration of a SiC semiconductor device 91 according to the twelfth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 21, the same reference numerals will be given and the description will be omitted.

[0375] Referring to FIG. 28, the SiC semiconductor device 91 is manufactured by a manufacturing method in which the technical ideas described in FIGS. 10A to 10D are incorporated into the steps of FIGS. 24A to 24L described above. More specifically, the SiC semiconductor device 91 does not have a modified layer 42. In the SiC semiconductor device 91, only the inclined portion 41 is formed at the corner of the SiC semiconductor layer 22.

[0376] As described above, even when manufacturing the SiC semiconductor device 91, the same effects as those described in the eleventh embodiment can be achieved.

[0377] FIG. 29 is a cross-sectional view of a region corresponding to FIG. 19, and is a cross-sectional view showing a schematic configuration of the SiC semiconductor device 92 according to the thirteenth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 21, the same reference numerals will be given and the description will be omitted.

[0378] Referring to FIG. 29, the SiC semiconductor device 92 is manufactured by a manufacturing method in which the technical ideas described in FIGS. 11A to 11D are incorporated into the steps of FIGS. 24A to 24L described above. In the steps of FIGS. 24A to 24L, the step of FIG. 24K is not necessarily implemented.

[0379] More specifically, the SiC semiconductor device 92 includes an inclined portion 41 reaching the SiC semiconductor substrate 31 and a modified layer 42. The inclined portion 41 reaches the SiC semiconductor substrate 31 across the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32. From the inclined portion 41, the SiC semiconductor substrate 31, the SiC epitaxial layer 32, and the insulating layer 35 are exposed. The lower end portion 41b of the inclined portion 41 is located within the SiC semiconductor substrate 31. The lower end portion 41b of the inclined portion 41 may be formed in a curved shape toward the second main surface 24.

[0380] The modified layer 42 is formed in a film shape along the inclined portion 41 of the SiC semiconductor layer 22. The modified layer 42 reaches the SiC semiconductor substrate 31 across the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32. The modified layer 42 is in contact with the SiC semiconductor substrate 31, the SiC epitaxial layer 32, and the insulating layer 35.

[0381] The lower covering portion 42b of the modified layer 42 covers the SiC semiconductor substrate 31. The lower covering portion 42b of the modified layer 42 includes a connecting portion 42c connected to the side surfaces 25A to 25D. The connecting portion 42c of the modified layer 42 may be a portion split in the modified layer 42. The connecting portion 42c of the modified layer 42 may be formed flush with the side surfaces 25A to 25D.

[0382] Even when manufacturing the SiC semiconductor device 92 as described above, effects similar to those described in the eleventh embodiment can be achieved.

[0383] FIG. 30 is a cross-sectional view of a region corresponding to FIG. 19, and is a cross-sectional view showing a schematic configuration of an SiC semiconductor device 93 according to the fourteenth embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the SiC semiconductor device 21, the same reference numerals will be given and the description will be omitted.

[0384] Referring to FIG. 30, the SiC semiconductor device 93 is manufactured by a manufacturing method in which the technical idea described in FIGS. 12A to 12D is incorporated into the steps of FIGS. 24A to 24L described above.

[0385] More specifically, the SiC semiconductor device 93 does not have the modified layer 42. In the SiC semiconductor device 93, only the inclined portion 41 is formed at the corner of the SiC semiconductor layer 22. The inclined portion 41 reaches the SiC semiconductor substrate 31 across the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32.

[0386] The lower end portion 41b of the inclined portion 41 is located within the SiC semiconductor substrate 31. The lower end portion 41b of the inclined portion 41 may be formed in a curved shape toward the second main surface 24. From the inclined portion 41, the SiC semiconductor substrate 31, the SiC epitaxial layer 32, and the insulating layer 35 are exposed.

[0387] As described above, even when manufacturing the SiC semiconductor device 93, the same effects as those described in the 11th embodiment can be achieved.

[0388] FIG. 31 is a cross-sectional view of a region corresponding to FIG. 19, and is a cross-sectional view showing a schematic configuration of an SiC semiconductor device 94 according to the 15th embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 21, the same reference numerals will be given and the description will be omitted.

[0389] Referring to FIG. 31, the SiC semiconductor device 94 does not have an inclined portion 41 at the corner of the SiC semiconductor layer 22. The SiC semiconductor device 94 includes a modified layer 42 formed in the middle of the SiC semiconductor layer 22 in the thickness direction on the side surfaces 25A to 25D.

[0390] More specifically, the modified layer 42 is formed in the middle of the SiC epitaxial layer 32 in the thickness direction on the side surfaces 25A to 25D. The modified layer 42 is formed in the SiC epitaxial layer 32 with a space from the first main surface 23 toward the second main surface 24 side. The modified layer 42 is formed in the SiC epitaxial layer 32 with a space from the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32 toward the first main surface 23 side.

[0391] Such a modified layer 42 is formed by adjusting the condensing point of the laser beam in the steps of FIGS. 24J and 24I described above. In this case, the modified layer 42 is heated and cooled from the second main surface 3 side of the 4H-SiC crystal structure 1, and the 4H-SiC crystal structure 1 is cleaved. The step of FIG. 24K does not necessarily have to be performed.

[0392] Even when manufacturing the SiC semiconductor device 94, the same effects as those described in the eleventh embodiment can be achieved.

[0393] FIG. 32 is a cross-sectional view of a region corresponding to FIG. 19, and is a cross-sectional view showing a schematic configuration of an SiC semiconductor device 95 according to the sixteenth embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the SiC semiconductor device 21, the same reference numerals will be given and the description will be omitted.

[0394] Referring to FIG. 32, the SiC semiconductor device 95 does not have an inclined portion 41 at the corner of the SiC semiconductor layer 22. The SiC semiconductor device 95 includes a modified layer 42 formed in the middle portion in the thickness direction of the SiC semiconductor layer 22 on the side surfaces 25A to 25D.

[0395] The modified layer 42 has an upper end portion on the first main surface 23 side and a lower end portion on the second main surface 24 side. The upper end portion of the modified layer 42 is formed in the SiC epitaxial layer 32 at a distance from the first main surface 23 toward the second main surface 24 side. The lower end portion of the modified layer 42 crosses the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32 and is formed in the SiC semiconductor substrate 31.

[0396] Such a modified layer 42 is formed by adjusting the condensing point of the laser beam in the steps of FIGS. 24J and 24I described above. In this case, the modified layer 42 is heated and cooled from the second main surface 3 side of the 4H-SiC crystal structure 1, and the 4H-SiC crystal structure 1 is cleaved. The step of FIG. 24K does not necessarily have to be performed.

[0397] Even when manufacturing the SiC semiconductor device 95, the same effects as those described in the eleventh embodiment can be achieved.

[0398] FIG. 33 is a cross-sectional view of a region corresponding to FIG. 19, and is a cross-sectional view showing a schematic configuration of an SiC semiconductor device 96 according to the seventeenth embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the SiC semiconductor device 21, the same reference numerals will be given and the description will be omitted.

[0399] Referring to FIG. 33, the SiC semiconductor device 96 is manufactured by a manufacturing method incorporating the technical idea described in FIGS. 13A to 13D in the steps of FIGS. 24A to 24L described above. In the steps of FIGS. 24A to 24L, the step of FIG. 24K does not necessarily have to be performed.

[0400] More specifically, the SiC semiconductor device 96 includes inclined portions 41 and modified layers 42 formed in regions on the second main surface 24 side of the SiC semiconductor layer 22 on the side surfaces 25A to 25D.

[0401] The inclined portion 41 is formed at a corner connecting the second main surface 24 and the side surfaces 25A to 25D. The corners of the SiC semiconductor layer 22 include corners connecting the second main surface 24 and the side surfaces 25A and 25C and extending along the [11-20] direction. The corners of the SiC semiconductor layer 22 include corners connecting the second main surface 24 and the side surfaces 25B and 25D and extending along the [1-100] direction. The inclined portion 41 slopes downward from the second main surface 24 toward the side surfaces 25A to 25D.

[0402] The inclined portion 41 is formed by the inner wall of a depression that is recessed from the second main surface 24 toward the first main surface 23 at the corner of the SiC semiconductor layer 22. The inclined portion 41 is formed on the SiC semiconductor substrate 31. More specifically, the inclined portion 41 is formed in a region on the second main surface 24 side with respect to the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32.

[0403] The inclined portion 41 has an upper end portion 41d and a lower end portion 41e. The upper end portion 41d of the inclined portion 41 is located on the first main surface 23 side of the SiC semiconductor layer 22. The upper end portion 41d of the inclined portion 41 is continuous with the side surfaces 25A to 25D. The upper end portion 41d of the inclined portion 41 may be formed in a curved shape toward the first main surface 23. The lower end portion 41e of the inclined portion 41 is located on the second main surface 24 side of the SiC semiconductor layer 22. The lower end portion 41e of the inclined portion 41 is connected to the second main surface 24 of the SiC semiconductor layer 22.

[0404] The width WI of the inclined portion 41 may be equal to or less than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 may be less than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 is the width in a direction orthogonal to the direction in which the inclined portion 41 extends in a plan view.

[0405] The width WI of the inclined portion 41 may be greater than 0 μm and equal to or less than 10 μm. The width WI of the inclined portion 41 may be greater than 0 μm and equal to or less than 2.5 μm, greater than or equal to 2.5 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 7.5 μm, or greater than or equal to 7.5 μm and less than or equal to 10 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WI of the inclined portion 41 is preferably greater than 0 μm and equal to or less than 5 μm. More preferably, the width WI of the inclined portion 41 is greater than 0 μm and equal to or less than 2.5 μm.

[0406] The depth D of the inclined portion 41 may be greater than 0 μm and equal to or less than 30 μm. The depth D of the inclined portion 41 is the distance from the second main surface 24 to the upper end portion of the inclined portion 41 with respect to the normal direction N. The depth D of the inclined portion 41 may be greater than 0 μm and equal to or less than 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, greater than or equal to 15 μm and less than or equal to 20 μm, greater than or equal to 20 μm and less than or equal to 25 μm, or greater than or equal to 25 μm and less than or equal to 30 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the depth D of the inclined portion 41 is preferably greater than 0 μm and equal to or less than 15 μm.

[0407] The modified layer 42 is formed on the SiC semiconductor substrate 31. More specifically, the modified layer 42 is formed in a region on the second main surface 24 side of the SiC semiconductor layer 22 with respect to the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32. The modified layer 42 is formed along the corner portions connecting the second main surface 24 and the side surfaces 25A to 25D. The modified layer 42 is formed at the corner portion connecting the second main surface 24 and the side surfaces 25A and 25C and extending along the [11-20] direction. The modified layer 42 is formed at the corner portion connecting the second main surface 24 and the side surfaces 25B and 25D and extending along the [1-100] direction.

[0408] In this form, the modified layer 42 extends in a strip shape along the side surfaces 25A to 25D in a direction parallel to the second main surface 24. That is, the modified layer 42 extends in a strip shape along the [1-100] direction and the [11-20] direction. The modified layer 42 is formed in an annular (endless) shape surrounding the active region 33 on the side surfaces 25A to 25D.

[0409] The modified layer 42 is formed in a film shape along the inclined portion 41 of the SiC semiconductor layer 22. The thickness of the portion of the modified layer 42 covering the bottom wall of the inclined portion 41 may be greater than the thickness of the portion of the modified layer 42 covering the side wall of the inclined portion 41. The modified layer 42 may be formed with a uniform thickness along the inner wall of the inclined portion 41.

[0410] The modified layer 42 includes an upper covering portion 42d and a lower covering portion 42e. The upper covering portion 42d of the modified layer 42 covers the upper end portion 41d of the inclined portion 41. The lower covering portion 42e of the modified layer 42 covers the lower end portion 41e of the inclined portion 41.

[0411] The upper covering portion 42d of the modified layer 42 includes a connection portion 42f connected to the side surfaces 25A to 25D. The connection portion 42f of the modified layer 42 may be a portion split in the modified layer 42. The connection portion 42f of the modified layer 42 may be formed flush with the side surfaces 25A to 25D.

[0412] The width WM of the modified layer 42 may be equal to or less than the in-plane variation of the side surfaces 25A to 25D. The width WM of the modified layer 42 may be less than the in-plane variation of the side surfaces 25A to 25D. The width WM of the modified layer 42 is the width in a direction orthogonal to the direction in which the modified layer 42 extends in a plan view.

[0413] The width WM of the modified layer 42 may be more than 0 μm and 10 μm or less. The width WM of the modified layer 42 may be more than 0 μm and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WM of the modified layer 42 is preferably more than 0 μm and 5 μm or less. The width WM of the modified layer 42 is more preferably more than 0 μm and 2.5 μm or less.

[0414] The thickness T of the modified layer 42 may be more than 0 μm and 30 μm or less. The thickness T of the modified layer 42 is the thickness along the normal direction N in the modified layer 42. The thickness T of the modified layer 42 may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the thickness T of the modified layer 42 is preferably more than 0 μm and 15 μm or less.

[0415] The second electrode layer 38 exposes the modified layer 42 on the second main surface 24 of the SiC semiconductor layer 22. That is, the peripheral portion of the second electrode layer 38 is formed in the inner region of the SiC semiconductor layer 22 with respect to the side surfaces 25A to 25D. The modified layer 42 may extend from the inclined portion 41 toward the second electrode layer 38 and have a covering portion that covers the second electrode layer 38.

[0416] Even when manufacturing the SiC semiconductor device 96 as described above, the same effects as those described in the eleventh embodiment can be achieved.

[0417] FIG. 34 is a cross-sectional view of a region corresponding to FIG. 19, and is a cross-sectional view showing a schematic configuration of an SiC semiconductor device 97 according to the eighteenth embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the SiC semiconductor device 21, the same reference numerals are given and the description is omitted.

[0418] Referring to FIG. 34, the SiC semiconductor device 97 is manufactured by a manufacturing method in which the technical idea described in FIGS. 14A to 14D is incorporated into the steps of FIGS. 24A to 24L described above.

[0419] More specifically, the SiC semiconductor device 97 does not have a modified layer 42. The SiC semiconductor device 97 includes inclined portions 41 formed in regions on the second main surface 24 side of the SiC semiconductor layer 22 on the side surfaces 25A to 25D.

[0420] The inclined portions 41 are formed at the corners connecting the second main surface 24 and the side surfaces 25A to 25D. The corners of the SiC semiconductor layer 22 include corners connecting the second main surface 24 and the side surfaces 25A and 25C and extending along the [11-20] direction. The corners of the SiC semiconductor layer 22 include corners connecting the second main surface 24 and the side surfaces 25B and 25D and extending along the [1-100] direction.

[0421] The inclined portions 41 are inclined downward from the second main surface 24 toward the side surfaces 25A to 25D. The inclined portions 41 are formed by the inner walls of depressions recessed from the second main surface 24 toward the first main surface 23 at the corners of the SiC semiconductor layer 22.

[0422] The inclined portions 41 are formed on the SiC semiconductor substrate 31. More specifically, the inclined portions 41 are formed in a region on the second main surface 24 side with respect to the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32.

[0423] The inclined portions 41 have upper ends 41d and lower ends 41e. The upper ends 41d of the inclined portions 41 are located on the first main surface 23 side. The lower ends 41e of the inclined portions 41 are located on the second main surface 24 side. The upper ends 41d of the inclined portions 41 are continuous with the side surfaces 25A to 25D. The upper ends 41d of the inclined portions 41 may be formed in a curved shape toward the first main surface 23. The lower ends 41e of the inclined portions 41 are connected to the second main surface 24.

[0424] The width WI of the inclined portion 41 may be equal to or less than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 may be less than the in-plane variation of the side surfaces 25A to 25D. The width WI of the inclined portion 41 is the width in a direction orthogonal to the direction in which the inclined portion 41 extends in a plan view.

[0425] The width WI of the inclined portion 41 may be greater than 0 μm and equal to or less than 10 μm. The width WI of the inclined portion 41 may be greater than 0 μm and equal to or less than 2.5 μm, greater than or equal to 2.5 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 7.5 μm, or greater than or equal to 7.5 μm and less than or equal to 10 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the width WI of the inclined portion 41 is preferably greater than 0 μm and equal to or less than 5 μm. More preferably, the width WI of the inclined portion 41 is greater than 0 μm and equal to or less than 2.5 μm.

[0426] The depth D of the inclined portion 41 may be greater than 0 μm and equal to or less than 30 μm. The depth D of the inclined portion 41 is the distance from the first main surface 23 to the lower end portion of the inclined portion 41 with respect to the normal direction N. The depth D of the inclined portion 41 may be greater than 0 μm and equal to or less than 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, greater than or equal to 15 μm and less than or equal to 20 μm, greater than or equal to 20 μm and less than or equal to 25 μm, or greater than or equal to 25 μm and less than or equal to 30 μm. When the thickness of the SiC semiconductor layer 22 is 150 μm or less, the depth D of the inclined portion 41 is preferably greater than 0 μm and equal to or less than 15 μm.

[0427] The second electrode layer 38 exposes the inclined portion 41 on the second main surface 24. That is, the peripheral edge portion of the second electrode layer 38 is formed in the inner region of the SiC semiconductor layer 22 with respect to the side surfaces 25A to 25D.

[0428] Even when manufacturing the SiC semiconductor device 97, the same effects as those described in the eleventh embodiment can be achieved.

[0429] FIG. 35 is a cross-sectional view of a region corresponding to FIG. 19, and is a cross-sectional view showing a schematic configuration of the SiC semiconductor device 98 according to the 19th embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the SiC semiconductor device 21, the same reference numerals will be given and the description will be omitted.

[0430] Referring to FIG. 35, the SiC semiconductor device 98 does not have the inclined portions 41 at the corners on the first main surface 23 side and the corners on the second main surface 24 side. The SiC semiconductor device 98 includes a modified layer 42 formed in the middle of the SiC semiconductor layer 22 in the thickness direction on the side surfaces 25A to 25D.

[0431] More specifically, the modified layer 42 is formed in the middle of the SiC semiconductor substrate 31 in the thickness direction. The modified layer 42 is formed at a distance from the boundary region between the SiC semiconductor substrate 31 and the SiC epitaxial layer 32 toward the second main surface 24 side. Further, the modified layer 42 is formed at a distance from the second main surface 24 toward the SiC epitaxial layer 32 side.

[0432] Such a modified layer 42 is formed by adjusting the focal point of the laser beam when irradiating the second main surface 24 with the laser beam. In this case, the modified layer 42 is heated and cooled from the second main surface 3 side of the 4H-SiC crystal structure 1, and the 4H-SiC crystal structure 1 is cleaved. The process of FIG. 24K does not necessarily have to be carried out.

[0433] As described above, even when manufacturing the SiC semiconductor device 98, the same effects as those described in the 11th embodiment can be achieved.

[0434] FIG. 36 is a top view showing the SiC semiconductor device 101 according to the 20th embodiment of the present invention. FIG. 37 is a top view showing the SiC semiconductor device 101 shown in FIG. 36, and is a top view with the resin layer 116 removed. The SiC semiconductor device 101 is a device manufactured using the aforementioned 4H-SiC crystal structure 1. The SiC semiconductor device 101 is also an example of a form representing the specific structure of the aforementioned SiC semiconductor device 21.

[0435] Referring to FIGS. 36 and 37, the SiC semiconductor device 101 includes an SiC semiconductor layer 102. The thickness of the SiC semiconductor layer 102 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor layer 102 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0436] The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, 105D connecting the first main surface 103 and the second main surface 104. In this form, the side surfaces 105A to 105D are all cut surfaces. More specifically, the side surfaces 105A to 105D are cleavage surfaces.

[0437] The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular shape in this form) in a plan view (hereinafter simply referred to as "plan view") when viewed from the normal direction N thereof. The side surface 105A faces the side surface 105C. The side surface 105B faces the side surface 105D.

[0438] The SiC semiconductor layer 102 includes a 4H-SiC single crystal. The first main surface 103 and the second main surface 104 face the c-plane of the 4H-SiC single crystal. The first main surface 103 faces the (0001) plane, and the second main surface 104 faces the (000-1) plane.

[0439] The first main surface 103 and the second main surface 104 have an off-angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the (0001) plane. The off-angle θ may be 0° or more and 2° or less, 2° or more and 4° or less, 4° or more and 6° or less, 6° or more and 8° or less, or 8° or more and 10° or less. The off-angle θ is preferably 0° or more and 4° or less.

[0440] When the off-angle θ is 0°, it means that the normal direction N and the c-axis coincide. The off-angle θ may be more than 0° and less than 4°. The off-angle θ is typically set in the range of 2° or 4°, more specifically, in the range of 2° ± 10% or 4° ± 10%.

[0441] The side surfaces 105A to 105D each extend planar along the normal direction N. The length of the side surfaces 105A to 105D may each be 1 mm or more and 10 mm or less. The length of the side surfaces 105A to 105D may be 1 mm or more and 2.5 mm or less, 2.5 mm or more and 5 mm or less, 5 mm or more and 7.5 mm or less, or 7.5 mm or more and 10 mm or less. The length of the side surfaces 105A to 105D is preferably 2 mm or more and 5 mm or less.

[0442] The side surfaces 105A to 105D extend along the nearest neighbor atom direction and the intersection direction of the nearest neighbor atom directions. The intersection direction of the nearest neighbor atom directions is more specifically the orthogonal direction orthogonal to the nearest neighbor atom direction. In this form, the side surfaces 105A to 105D extend along the [11-20] direction and the [1-100] direction.

[0443] The side surfaces 105A and 105C forming the short sides of the rectangle are formed along the intersection direction of the nearest neighbor atom directions (that is, the [1-100] direction). The side surfaces 105B and 105D forming the long sides of the rectangle are formed along the nearest neighbor atom direction (that is, the [11-20] direction). The side surfaces 105A and 105C may be formed along the [11-20] direction, and the side surfaces 105B and 105D may be formed along the [1-100] direction.

[0444] The in-plane variation of the side surfaces 105A to 105D is 20 μm or less. The in-plane variation along the [11-20] direction of the side surfaces 105A and 105C extending along the [1-100] direction is 20 μm or less. The in-plane variation of the side surfaces 105A and 105C is more specifically 10 μm or less.

[0445] The in-plane variation along the [1-100] direction of the side surfaces 105B and 105D extending along the [11-20] direction is 20 μm or less. More specifically, the in-plane variation of the side surfaces 105B and 105D is 10 μm or less.

[0446] The in-plane variation is defined by the maximum value of the distance between a reference virtual line and a measurement virtual line set on one of the side surfaces 105A to 105D selected from the side surfaces 105A to 105D. The reference virtual line is a straight line connecting two corner portions of the SiC semiconductor layer 102 in a plan view and is set on one of the selected side surfaces 105A to 105D. The measurement virtual line is a straight line extending parallel to the reference virtual line in a plan view and is set so as to be in contact with the top or base of a protrusion (meandering) existing on one of the selected side surfaces 105A to 105D.

[0447] For example, the distance between the reference virtual line and the measurement virtual line in contact with the top of the protrusion (meandering), and the distance between the reference virtual line and the measurement virtual line in contact with the base of the protrusion (meandering) are measured. The in-plane variation of one selected side surface 105A to 105D is defined by the maximum value of the measured distance between the reference virtual line and the measurement virtual line.

[0448] The SiC semiconductor layer 102 includes an active region 106 and an outer region 107. The active region 106 is a region where a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) as an example of a field effect transistor is formed. The outer region 107 is a region outside the active region 106.

[0449] The active region 106 may be set at the center of the SiC semiconductor layer 102 at an interval from the inner region in a plan view with respect to the side surfaces 105A to 105D. The active region 106 may be set in a rectangular shape (a rectangular shape in this form) having four sides parallel to the side surfaces 105A to 105D in a plan view.

[0450] The outer region 107 is set in the region between the side surfaces 105A to 105D and the active region 106. The outer region 107 may be set in an annular (for example, endless) shape surrounding the active region 106 in plan view.

[0451] The SiC semiconductor device 101 includes a gate terminal electrode layer 108 and a source terminal electrode layer 109 formed on the first main surface 103. In this form, the gate terminal electrode layer 108 includes a gate pad 110 and gate fingers 111. The gate pad 110 and the gate fingers 111 are arranged in the active region 106.

[0452] The gate pad 110 is formed in a region along the side surface 105A in plan view. The gate pad 110 is formed in a region along the central portion of the side surface 105A in plan view. The gate pad 110 may be formed in a region along a corner connecting any two of the side surfaces 105A to 105D in plan view. The gate pad 110 is formed in a rectangular shape in plan view.

[0453] The gate fingers 111 include outer gate fingers 111A and inner gate fingers 111B. The outer gate fingers 111A are drawn out from the gate pad 110 and extend in a strip shape along the periphery of the active region 106. In this form, the outer gate fingers 111A are formed along three side surfaces 105A, 105B, and 105D, and partition the inner region of the active region 106 from three directions.

[0454] The outer gate fingers 111A have a pair of open ends 112A and 112B. The pair of open ends 112A and 112B of the outer gate fingers 111A are formed in a region facing the gate pad 110 with the inner region of the active region 106 interposed therebetween. In this form, the pair of open ends 112A and 112B of the outer gate fingers 111A are formed in a region along the side surface 105C.

[0455] The inner gate finger 111B is drawn out from the gate pad 110 to the inner region of the active region 106. The inner gate finger 111B extends in a strip shape in the inner region of the active region 106. The inner gate finger 111B extends from the side 105A side toward the side 105C side.

[0456] In this form, the source terminal electrode layer 109 includes a source pad 113, a source routing wiring 114, and a source connection portion 115. The source pad 113 is formed in the active region 106 at a distance from the gate pad 110 and the gate finger 111. The source pad 113 covers a C-shaped (in FIGS. 36 and 37, an inverted C-shaped) region partitioned by the gate pad 110 and the gate finger 111. The source pad 113 is formed in a C shape (in FIGS. 36 and 37, an inverted C shape) in plan view.

[0457] The source routing wiring 114 is formed in the outer region 107. The source routing wiring 114 extends in a strip shape along the active region 106. In this form, the source routing wiring 114 is formed in an annular shape (for example, endless) surrounding the active region 106 in plan view. The source routing wiring 114 is electrically connected to the SiC semiconductor layer 102 in the outer region 107.

[0458] The source connection portion 115 connects the source pad 113 and the source routing wiring 114. The source connection portion 115 is formed in the region between the pair of open end portions 112A and 112B of the outer gate finger 111A. The source connection portion 115 crosses the boundary region between the active region 106 and the outer region 107 from the source pad 113 and is connected to the source routing wiring 114.

[0459] The MISFET formed in the active region 106 includes an npn-type parasitic bipolar transistor due to its structure. When the avalanche current generated in the outer region 107 flows into the active region 106, the parasitic bipolar transistor is turned on. In this case, for example, due to latch-up, the control of the MISFET may become unstable.

[0460] Therefore, in the SiC semiconductor device 101, an avalanche current absorption structure that absorbs the avalanche current generated in the region outside the active region 106 is formed by utilizing the structure of the source terminal electrode layer 109.

[0461] More specifically, the avalanche current generated in the outer region 107 is absorbed by the source routing wiring 114. The avalanche current reaches the source pad 113 through the source connection portion 115. When an external connection conductor (for example, a bonding wire) is connected to the source pad 113, the avalanche current is taken out by this conductor.

[0462] Thereby, it is possible to suppress the parasitic bipolar transistor from being turned on by the unwanted current generated in the outer region 107. Therefore, latch-up can be suppressed, and the stability of the MISFET can be enhanced.

[0463] A gate voltage is applied to the gate pad 110 and the gate fingers 111. The gate voltage may be 10V or more and 50V or less (for example, about 30V). A source voltage is applied to the source pad 113. The source voltage may be a reference voltage (for example, GND voltage).

[0464] The SiC semiconductor device 101 includes a resin layer 116 formed on the first main surface 103 (more specifically, on the interlayer insulating layer 191 described later). In FIG. 36, for clarity, the resin layer 116 is shown by hatching. The resin layer 116 covers the gate pad 110, the gate fingers 111, and the source pad 113.

[0465] The resin layer 116 may contain a negative-type or positive-type photosensitive resin. In this form, the resin layer 116 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 116 may contain polyimide as an example of a negative-type photosensitive resin.

[0466] The resin layer 116 includes a gate pad opening 117 and a source pad opening 118. The gate pad opening 117 exposes the gate pad 110. The source pad opening 118 exposes the source pad 113.

[0467] The peripheral portion 119 of the resin layer 116 is formed at a distance from the side surfaces 105A to 105D in the inner region. Thereby, the resin layer 116 exposes the peripheral portion of the SiC semiconductor layer 102 (more specifically, the interlayer insulating layer 191 described later).

[0468] The peripheral portion 119 of the resin layer 116 is a portion where a dicing street was formed when cutting out the SiC semiconductor device 101 from the 4H-SiC crystal structure 1. By exposing the peripheral portion of the SiC semiconductor layer 102 from the resin layer 116, it becomes unnecessary to physically cut the resin layer 116. Therefore, the SiC semiconductor device 101 can be smoothly cut out from the 4H-SiC crystal structure 1.

[0469] FIG. 38 is an enlarged view of the region XXXVIII shown in FIG. 37 and is a diagram for explaining the structure of the first main surface 103 of the SiC semiconductor layer 102. FIG. 39 is a cross-sectional view taken along the line XXXIX-XXXIX shown in FIG. 38. FIG. 40 is a cross-sectional view taken along the line XL-XL shown in FIG. 38. FIG. 41 is an enlarged view of the region XLI shown in FIG. 39. FIG. 42 is a cross-sectional view taken along the line XLII-XLII shown in FIG. 37. FIG. 43 is an enlarged view of the region XLIII shown in FIG. 42. FIG. 44 is an enlarged view of the region XLIV shown in FIG. 42.

[0470] Referring to FIGS. 38 to 44, in this form, the SiC semiconductor layer 102 is n +It has a laminated structure including a p-type SiC semiconductor substrate 121 and an n-type SiC epitaxial layer 122.

[0471] The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 121. The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 122. The side surfaces 105A to 105D of the SiC semiconductor layer 102 are formed by the SiC semiconductor substrate 121 and the SiC epitaxial layer 122. The second main surface 104 may be a ground surface having grinding marks.

[0472] The thickness of the SiC epitaxial layer 122 is less than the thickness of the SiC semiconductor substrate 121. The thickness of the SiC semiconductor substrate 121 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 121 may be 1 μm or more and 50 μm or less, 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 400 μm or less, 400 μm or more and 600 μm or less, 600 μm or more and 800 μm or less, or 800 μm or more and 1000 μm or less.

[0473] The thickness of the SiC semiconductor substrate 121 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 121, the resistance value can be reduced by shortening the current path.

[0474] The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 is preferably 5 μm or more and 20 μm or less.

[0475] The n-type impurity concentration of the SiC epitaxial layer 122 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 121. The n-type impurity concentration of the SiC semiconductor substrate 121 is 1.0×1018 cm -3 1.0×10 or more above 21 cm -3 It may be below. The n-type impurity concentration of the SiC epitaxial layer 122 is 1.0×10 15 cm -3 1.0×10 or more above 18 cm -3 It may be below.

[0476] In this form, the SiC epitaxial layer 122 has a plurality of regions having different n-type impurity concentrations along the normal direction N. More specifically, the SiC epitaxial layer 122 includes a high-concentration region 122a having a relatively high n-type impurity concentration and a low-concentration region 122b having an n-type impurity concentration lower than that of the high-concentration region 122a.

[0477] The high-concentration region 122a is formed in the region on the first main surface 103 side. The low-concentration region 122b is formed in the region on the second main surface 104 side with respect to the high-concentration region 122a. The n-type impurity concentration of the high-concentration region 122a is 1×10 16 cm -3 1×10 or more above 18 cm -3 It may be below. The n-type impurity concentration of the low-concentration region 122b is 1×10 15 cm -3 1×10 or more above 16 cm -3 It may be below.

[0478] The thickness of the high-concentration region 122a is less than or equal to the thickness of the low-concentration region 122b. More specifically, the thickness of the high-concentration region 122a is less than the thickness of the low-concentration region 122b. That is, the thickness of the high-concentration region 122a is less than half of the total thickness of the SiC epitaxial layer 122.

[0479] The SiC epitaxial layer 122 is formed, for example, by changing the introduction amount (addition amount) of n-type impurities along the growth direction of SiC when epitaxially growing SiC from the SiC semiconductor wafer 51 in the step of preparing the 4H-SiC crystal structure 1 (see FIGS. 23 and 24A).

[0480] The SiC semiconductor device 101 includes a drain pad 123 connected to the second main surface 104 of the SiC semiconductor layer 102. That is, the SiC semiconductor substrate 121 is formed as a drain region 124 of the MISFET. The SiC epitaxial layer 122 is formed as a drift region 125 of the MISFET. The maximum voltage that can be applied between the source pad 113 and the drain pad 123 when off may be 1000 V or more and 10000 V or less.

[0481] The drain pad 123 may include at least one of an Al layer, a Ti layer, a Ni layer, an Au layer, and an Ag layer. The drain pad 123 may have a stacked structure in which at least two of the Al layer, the Ti layer, the Ni layer, the Au layer, and the Ag layer are stacked in any manner. The drain pad 123 may have a single-layer structure composed of an Al layer, a Ti layer, a Ni layer, an Au layer, or an Ag layer. The drain pad 123 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from the second main surface 104.

[0482] The SiC semiconductor device 101 includes a p-type body region 126 formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. The p-type impurity concentration of the body region 126 may be 1×10 17 cm -3 or more and 1×10 20 cm -3 or less. The body region 126 defines the active region 106.

[0483] The SiC semiconductor device 101 includes a plurality of gate trenches 131 in the surface layer portion of the first main surface 103 in the active region 106. The plurality of gate trenches 131 are formed at intervals in an arbitrary first direction X. The plurality of gate trenches 131 are formed in a strip shape extending along a second direction Y intersecting the first direction X. The second direction Y is a direction orthogonal to the first direction X. Thereby, the plurality of gate trenches 131 are formed in a stripe shape extending along the second direction Y as a whole in plan view.

[0484] It is preferable that the first direction X is set in the [11-20] direction and the second direction Y is set in the [1-100] direction. That is, it is preferable that the plurality of gate trenches 131 are formed at intervals in the [11-20] direction and are formed in a strip shape extending along the [1-100] direction.

[0485] The first direction X may be set in the [1-100] direction and the second direction Y may be set in the [11-20] direction. That is, the plurality of gate trenches 131 may be formed at intervals in the [1-100] direction and may be formed in a strip shape extending along the [11-20] direction.

[0486] Each gate trench 131 extends in a strip shape from the peripheral edge portion on one side (side surface 105B side) to the peripheral edge portion on the other side (side surface 105D side) in the active region 106. Each gate trench 131 crosses the intermediate portion between the peripheral edge portion on one side and the peripheral edge portion on the other side in the active region 106. One end portion of each gate trench 131 is located at the peripheral edge portion on one side in the active region 106. The other end portion of each gate trench 131 is located at the peripheral edge portion on the other side in the active region 106.

[0487] Each gate trench 131 has a length on the order of millimeters (a length of 1 mm or more). The length of each gate trench 131 may be 1 mm or more and 10 mm or less. The length of each gate trench 131 may be 1 mm or more and 2 mm or less, 2 mm or more and 4 mm or less, 4 mm or more and 6 mm or less, 6 mm or more and 8 mm or less, or 8 mm or more and 10 mm or less. The length of each gate trench 131 is preferably 2 mm or more and 5 mm or less. Also, the total extension of one or more gate trenches 131 per unit area is 0.5 μm / μm 2 or more and 0.75 μm / μm 2 or less, which is preferable.

[0488] Each gate trench 131 includes an active trench portion 131a and a contact trench portion 131b. The active trench portion 131a is a portion along the channel region of the MISFET in the active region 106. The contact trench portion 131b is a portion mainly for making contact with the gate finger 111 in the gate trench 131.

[0489] The contact trench portion 131b is drawn out from the active trench portion 131a to the peripheral portion of the active region 106. The contact trench portion 131b is formed in the region directly below the gate finger 111. The amount of drawout of the contact trench portion 131b is arbitrary.

[0490] Each gate trench 131 penetrates the body region 126 and reaches the SiC epitaxial layer 122. The bottom wall of each gate trench 131 is located within the SiC epitaxial layer 122.

[0491] More specifically, the bottom wall of each gate trench 131 is located in the high-concentration region 122a of the SiC epitaxial layer 122. The bottom wall of the gate trench 131 may be formed parallel to the first main surface 103. The bottom wall of the gate trench 131 may be formed in a curved shape toward the second main surface 104.

[0492] The side wall of the gate trench 131 may extend along the normal direction N. The side wall of the gate trench 131 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102. The gate trench 131 may be formed in a tapered shape with a bottom area less than the opening area.

[0493] The depth along the normal direction N of the gate trench 131 may be 0.5 μm or more and 3 μm or less. The depth of the gate trench 131 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The depth of the gate trench 131 is preferably 0.5 μm or more and 1.0 μm or less.

[0494] The width along the first direction X of the gate trench 131 may be 0.1 μm or more and 2 μm or less. The width of the gate trench 131 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. The width of the gate trench 131 is preferably 0.1 μm or more and 0.5 μm or less.

[0495] Referring to FIG. 41, the opening edge portion 132 of each gate trench 131 includes an inclined portion 133 that slopes downward from the first main surface 103 toward the gate trench 131. The opening edge portion 132 of the gate trench 131 is a corner connecting the first main surface 103 and the side wall of the gate trench 131.

[0496] In this form, the inclined portion 133 is formed in a curved shape that is recessed toward the SiC semiconductor layer 102. The inclined portion 133 may be formed in a curved shape that protrudes inward of the gate trench 131. The electric field with respect to the opening edge portion 132 is relaxed by the inclined portion 133.

[0497] The SiC semiconductor device 101 includes a gate insulating layer 134 and a gate electrode layer 135 formed in each gate trench 131. In FIG. 38, the gate insulating layer 134 and the gate electrode layer 135 are indicated by hatching.

[0498] The gate insulating layer 134 contains silicon oxide. The gate insulating layer 134 may contain other insulating films such as silicon nitride. The gate insulating layer 134 is formed in a film shape along the inner wall surface of the gate trench 131. The gate insulating layer 134 partitions a recessed space in the gate trench 131.

[0499] The gate insulating layer 134 includes a first region 134a, a second region 134b, and a third region 134c. The first region 134a is formed along the side wall of the gate trench 131. The second region 134b is formed along the bottom wall of the gate trench 131. The third region 134c is drawn out from the first region 134a onto the first main surface 103 and is formed on the first main surface 103.

[0500] The thickness T1 of the first region 134a is less than the thickness T2 of the second region 134b and the thickness T3 of the third region 134c. The ratio T2 / T1 of the thickness T2 of the second region 134b to the thickness T1 of the first region 134a may be 2 or more and 5 or less. The ratio T3 / T1 of the thickness T3 of the third region 134c to the thickness T1 of the first region 134a may be 2 or more and 5 or less.

[0501] The thickness T1 of the first region 134a may be 0.01 μm or more and 0.2 μm or less. The thickness T2 of the second region 134b may be 0.05 μm or more and 0.5 μm or less. The thickness T3 of the third region 134c may be 0.05 μm or more and 0.5 μm or less.

[0502] By thinning the first region 134a, an increase in carriers induced in a region near the side wall of the gate trench 131 in the body region 126 can be suppressed. Thereby, an increase in channel resistance can be suppressed. By thickening the second region 134b, the electric field concentration on the bottom wall of the gate trench 131 can be alleviated.

[0503] By thickening the third region 134c, the breakdown voltage of the gate insulating layer 134 in the vicinity of the opening edge portion 132 can be improved. Further, by thickening the third region 134c, it is possible to suppress the third region 134c from disappearing by an etching method. Thereby, the first region 134a can be protected by the third region 134c.

[0504] For example, it is possible to suppress the first region 134a from being removed by an etching method due to the disappearance of the third region 134c. Thereby, the gate electrode layer 135 can be appropriately opposed to the SiC semiconductor layer 102 (body region 126) with the gate insulating layer 134 interposed therebetween.

[0505] The gate insulating layer 134 further includes a bulging portion 134d that bulges toward the inside of the gate trench 131 at the opening edge portion 132. The bulging portion 134d is formed at a portion connecting the first region 134a and the third region 134c of the gate insulating layer 134. The bulging portion 134d protrudes in a curved shape toward the inside of the gate trench 131. The bulging portion 134d narrows the opening of the gate trench 131 at the opening edge portion 132.

[0506] The breakdown voltage of the gate insulating layer 134 at the opening edge portion 132 is improved by the bulging portion 134d. A gate insulating layer 134 having no bulging portion 134d may be formed. A gate insulating layer 134 having a uniform thickness may be formed.

[0507] The gate electrode layer 135 is embedded in the gate trench 131 with the gate insulating layer 134 interposed therebetween. More specifically, the gate electrode layer 135 is embedded in a recess space partitioned by the gate insulating layer 134. The gate electrode layer 135 is controlled by a gate voltage.

[0508] The gate electrode layer 135 is formed in a wall shape extending along the normal direction N in a cross-sectional view. The gate electrode layer 135 has an upper end portion located on the opening side of the gate trench 131. The upper end portion of the gate electrode layer 135 is formed in a curved shape recessed toward the bottom wall of the gate trench 131. The upper end portion of the gate electrode layer 135 has a constricted portion along the bulging portion 134d of the gate insulating layer 134.

[0509] In a direction (first direction X) orthogonal to the direction in which the gate trench 131 extends, the cross-sectional area of the gate electrode layer 135 is 0.05 μm 2 or more and 0.5 μm 2 or less. The cross-sectional area of the gate electrode layer 135 is defined by the product of the thickness along the normal direction N of the gate electrode layer 135 and the width along the first direction X of the gate electrode layer 135.

[0510] The thickness of the gate electrode layer 135 is the distance from the upper end portion to the lower end portion of the gate electrode layer 135. The width of the gate electrode layer 135 is the width of the gate electrode layer 135 at an intermediate position between the upper end portion and the lower end portion of the gate electrode layer 135. When the upper end portion is a curved surface (in this form, a curved shape recessed downward), the position of the upper end portion of the gate electrode layer 135 is taken as the intermediate position at the upper end portion of the gate electrode layer 135.

[0511] The cross-sectional area of the gate electrode layer 135 is 0.05 μm 2 or more and 0.1 μm 2 or less, 0.1 μm 2 or more and 0.2 μm 2 or less, 0.2 μm 2 or more and 0.3 μm 2 or less, 0.3 μm 2 or more and 0.4 μm 2 or less, or 0.4 μm 2 or more and 0.5 μm 2 or less may also be acceptable.

[0512] The gate electrode layer 135 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy, and copper alloy. In this form, the gate electrode layer 135 contains p-type polysilicon doped with p-type impurities. The p-type impurities in the gate electrode layer 135 may contain at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0513] The p-type impurity concentration of the gate electrode layer 135 is equal to or higher than the p-type impurity concentration of the body region 126. More specifically, the p-type impurity concentration of the gate electrode layer 135 exceeds the p-type impurity concentration of the body region 126. The p-type impurity concentration of the gate electrode layer 135 is 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the gate electrode layer 135 may be 10 Ω / sq or more and 500 Ω / sq or less (about 200 Ω / sq in this form).

[0514] Referring to FIGS. 38 and 40, the SiC semiconductor device 101 further includes a gate wiring layer 136 formed in the active region 106. In FIG. 40, the gate wiring layer 136 is indicated by hatching. The gate wiring layer 136 electrically connects the gate pad 110 (gate finger 111) and the gate electrode layer 135.

[0515] In this form, the gate wiring layer 136 is formed on the first main surface 103. More specifically, the gate wiring layer 136 is formed on the third region 134c of the gate insulating layer 134.

[0516] In this form, the gate wiring layer 136 is formed along the gate finger 111. More specifically, the gate wiring layer 136 is formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102, partitioning the inner region of the active region 106 from three directions.

[0517] The gate wiring layer 136 is connected to the gate electrode layer 135 exposed from the contact trench portion 131b of each gate trench 131. In this form, the gate wiring layer 136 is formed by the lead-out portion of the gate electrode layer 135 drawn out onto the first main surface 103 from each gate trench 131. The upper end portion of the gate wiring layer 136 is connected to the upper end portion of the gate electrode layer 135.

[0518] Referring to FIGS. 38, 39, and 41, the SiC semiconductor device 101 includes a plurality of source trenches 141 formed on the first main surface 103 in the active region 106. Each source trench 141 is formed in a region between two adjacent gate trenches 131.

[0519] Each source trench 141 is formed in a strip shape extending along the second direction Y. The plurality of source trenches 141 are formed in a stripe shape extending along the second direction Y as a whole in plan view. Thereby, the plurality of gate trenches 131 and the plurality of source trenches 141 are alternately formed along the first direction X and are formed in a stripe shape extending along the second direction Y.

[0520] Regarding the first direction X, the pitch between the central portions of two adjacent source trenches 141 may be 1.5 μm or more and 3 μm or less. The pitch of the source trench 141 may be 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0521] Each source trench 141 penetrates the body region 126 and reaches the SiC epitaxial layer 122. The bottom wall of each source trench 141 is located within the SiC epitaxial layer 122. More specifically, the bottom wall of each source trench 141 is located in the high-concentration region 122a.

[0522] Regarding the normal direction N, the depth of the source trench 141 is greater than or equal to the depth of the gate trench 131 in this form. More specifically, the depth of the source trench 141 exceeds the depth of the gate trench 131. The bottom wall of the source trench 141 is located on the side of the second main surface 104 with respect to the bottom wall of the gate trench 131.

[0523] The bottom wall of the source trench 141 is located in the region between the bottom wall of the gate trench 131 and the low-concentration region 122b with respect to the normal direction N. The bottom wall of the source trench 141 may be formed parallel to the first main surface 103. The bottom wall of the source trench 141 may be formed in a curved shape toward the second main surface 104.

[0524] The side wall of the source trench 141 may extend along the normal direction N. The side wall of the source trench 141 may be formed substantially perpendicular to the first main surface 103. The source trench 141 may be formed in a tapered shape with a bottom area less than the opening area.

[0525] The ratio of the depth of the source trench 141 to the depth of the gate trench 131 may be 1.5 or more. The ratio of the depth of the source trench 141 to the depth of the gate trench 131 is preferably 2 or more.

[0526] The depth of the source trench 141 may be 0.5 μm or more and 10 μm or less. The depth of the source trench 141 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The depth of the source trench 141 is preferably 1 μm or more and 6 μm or less.

[0527] The width of the source trench 141 may be 0.1 μm or more and 2 μm or less. The width of the source trench 141 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. The width of the source trench 141 is preferably 0.1 μm or more and 0.5 μm or less. The width of the source trench 141 along the first direction X may be substantially equal to the width of the gate trench 131 along the first direction X. The width of the source trench 141 may be equal to or greater than the width of the gate trench 131.

[0528] The SiC semiconductor device 101 includes a source insulating layer 142 and a source electrode layer 143 formed in each source trench 141. In FIG. 38, the source insulating layer 142 and the source electrode layer 143 are shown by hatching.

[0529] The source insulating layer 142 may contain silicon oxide. The source insulating layer 142 may contain other insulating films such as silicon nitride. The source insulating layer 142 is formed in a film shape along the inner wall surface of the source trench 141 and partitions a recess space in the source trench 141.

[0530] The source insulating layer 142 includes a first region 142a and a second region 142b. The first region 142a is formed along the side wall of the source trench 141. The second region 142b is formed along the bottom wall of the source trench 141. The thickness T11 of the first region 142a is less than the thickness T12 of the second region 142b.

[0531] The ratio T12 / T11 of the thickness T12 of the second region 142b to the thickness T11 of the first region 142a may be 2 or more and 5 or less. The thickness T11 of the first region 142a may be 0.01 μm or more and 0.2 μm or less. The thickness T12 of the second region 142b may be 0.05 μm or more and 0.5 μm or less.

[0532] The thickness T11 of the first region 142a may be substantially equal to the thickness T1 of the first region 134a of the gate insulating layer 134. The thickness T12 of the second region 142b may be substantially equal to the thickness T2 of the second region 134b of the gate insulating layer 134. A source insulating layer 142 having a uniform thickness may be formed.

[0533] The source electrode layer 143 is embedded in the source trench 141 with the source insulating layer 142 interposed therebetween. More specifically, the source electrode layer 143 is embedded in a recessed space partitioned by the source insulating layer 142. The source electrode layer 143 is controlled by a source voltage.

[0534] The source electrode layer 143 has an upper end portion located on the opening side of the source trench 141. The upper end portion of the source electrode layer 143 is formed on the bottom wall side of the source trench 141 with respect to the first main surface 103. The upper end portion of the source electrode layer 143 is formed in a curved shape recessed toward the bottom wall of the source trench 141. The upper end portion of the source electrode layer 143 may be formed parallel to the first main surface 103.

[0535] The upper end portion of the source electrode layer 143 may be located above the first main surface 103. The upper end portion of the source electrode layer 143 may protrude above the upper end portion of the source insulating layer 142. The upper end portion of the source electrode layer 143 may be located below the upper end portion of the source insulating layer 142.

[0536] The thickness along the normal direction N of the source electrode layer 143 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm). The thickness of the source electrode layer 143 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness of the source electrode layer 143 is preferably 1 μm or more and 6 μm or less.

[0537] The source electrode layer 143 preferably contains polysilicon having properties similar to SiC in terms of material. Thereby, the stress generated in the SiC semiconductor layer 102 due to the source electrode layer 143 can be reduced. The source electrode layer 143 may contain the same conductive material type as the gate electrode layer 135.

[0538] The source electrode layer 143 may contain conductive polysilicon. The source electrode layer 143 may contain n-type polysilicon or p-type polysilicon as an example of conductive polysilicon. Instead of conductive polysilicon, the source electrode layer 143 may contain at least one of tungsten, aluminum, copper, aluminum alloy, and copper alloy.

[0539] When the gate electrode layer 135 contains p-type polysilicon doped with p-type impurities, the source electrode layer 143 preferably contains p-type polysilicon doped with p-type impurities. Thereby, the source electrode layer 143 can be formed simultaneously with the gate electrode layer 135.

[0540] In this case, the p-type impurities in the source electrode layer 143 may contain at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga). The p-type impurity concentration of the source electrode layer 143 is equal to or higher than the p-type impurity concentration of the body region 126. More specifically, the p-type impurity concentration of the source electrode layer 143 exceeds the p-type impurity concentration of the body region 126.

[0541] The p-type impurity concentration of the source electrode layer 143 is 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the source electrode layer 143 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form).

[0542] The p-type impurity concentration of the source electrode layer 143 may be approximately equal to the p-type impurity concentration of the gate electrode layer 135. The sheet resistance of the source electrode layer 143 may be approximately equal to the sheet resistance of the gate electrode layer 135.

[0543] As described above, the SiC semiconductor device 101 has a trench gate structure 151 and a trench source structure 152. The trench gate structure 151 includes a gate trench 131, a gate insulating layer 134, and a gate electrode layer 135. The trench source structure 152 includes a source trench 141, a source insulating layer 142, and a source electrode layer 143.

[0544] The SiC semiconductor device 101 includes an n-type source region 153 formed in a region along the sidewall of the gate trench 131 in the surface layer portion of the body region 126. + The n-type impurity concentration of the source region 153 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The source regions 153 are formed in plurality along the sidewalls of the gate trench 131 on one side and the other side with respect to the first direction X.

[0545] The plurality of source regions 153 are each formed in a strip shape extending along the second direction Y. The plurality of source regions 153 are formed in a stripe shape as a whole in a plan view. Each source region 153 is exposed from the sidewalls of the gate trench 131 and the source trench 141.

[0546] The SiC semiconductor device 101 includes a plurality of p-type contact regions 154 formed in the surface layer portion of the first main surface 103. The p-type impurity concentration of the contact region 154 exceeds the p-type impurity concentration of the body region 126. The p-type impurity concentration of the contact region 154 may be 1.0×10 + cm 18 or more and 1.0×10 -3 cm 21 or less. -3

[0547] The plurality of contact regions 154 are respectively formed along the side walls of the plurality of source trenches 141. In this form, a plurality of contact regions 154 are formed for one source trench 141. With respect to one source trench 141, the plurality of contact regions 154 are formed at intervals in the second direction Y along the source trench 141.

[0548] The plurality of contact regions 154 are formed at intervals from the gate trench 131 in the first direction X. Thereby, each contact region 154 faces the gate trench 131 across the source region 153 in a plan view.

[0549] Each contact region 154 covers the side wall and the bottom wall of the source trench 141. The bottom of each contact region 154 may be formed parallel to the bottom wall of the source trench 141. More specifically, each contact region 154 integrally includes a first surface layer region 154a, a second surface layer region 154b, and an inner wall region 154c.

[0550] The first surface layer region 154a is formed along the side wall on one side of the source trench 141 in the surface layer portion of the first main surface 103. The first surface layer region 154a extends from the side wall on one side of the source trench 141 toward the adjacent gate trench 131. The first surface layer region 154a may extend to the intermediate region between the source trench 141 and the gate trench 131.

[0551] The second surface layer region 154b is formed along the side wall on the other side of the source trench 141 in the surface layer portion of the first main surface 103. The second surface layer region 154b extends from the side surface on the other side of the source trench 141 toward the adjacent gate trench 131. The second surface layer region 154b may extend to the intermediate region between the source trench 141 and the gate trench 131.

[0552] The inner wall region 154c is formed in the SiC semiconductor layer 102 in a region along the inner wall of the source trench 141. The inner wall region 154c is formed along the side wall of the source trench 141. The inner wall region 154c covers a corner portion connecting the side wall and the bottom wall of the source trench 141. The inner wall region 154c covers the bottom wall of the source trench 141 from the side wall of the source trench 141 via the corner portion. The bottom of each contact region 154 is formed by the inner wall region 154c.

[0553] The SiC semiconductor device 101 includes a plurality of p-type deep well regions 155 formed in the surface layer portion of the first main surface 103. The deep well region 155 is also referred to as a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the active region 106.

[0554] The plurality of deep well regions 155 are formed in a one-to-one correspondence with the plurality of source trenches 141. Each deep well region 155 covers the inner wall of the corresponding source trench 141 with the contact region 154 interposed therebetween. The deep well region 155 is formed in a strip shape extending along the source trench 141 in a plan view. The deep well region 155 is formed along the side wall of the source trench 141.

[0555] The deep well region 155 covers a corner portion connecting the side wall and the bottom wall of the source trench 141. The deep well region 155 covers the bottom wall of the source trench 141 from the side wall of the source trench 141 via the corner portion. The deep well region 155 is continuous with the body region 126 on the side wall of the source trench 141.

[0556] The deep well region 155 is formed in the high concentration region 122a of the SiC epitaxial layer 122. The deep well region 155 has a bottom portion located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The bottom of the deep well region 155 may be formed parallel to the bottom wall of the source trench 141.

[0557] The p-type impurity concentration in the deep well region 155 may be substantially equal to the p-type impurity concentration in the body region 126. The p-type impurity concentration in the deep well region 155 may exceed the p-type impurity concentration in the body region 126. The p-type impurity concentration in the deep well region 155 may be less than the p-type impurity concentration in the body region 126.

[0558] The p-type impurity concentration in the deep well region 155 may be less than or equal to the p-type impurity concentration in the contact region 154. The p-type impurity concentration in the deep well region 155 may be less than the p-type impurity concentration in the contact region 154. The p-type impurity concentration in the deep well region 155 may be 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0559] The deep well region 155 forms a pn junction with the SiC semiconductor layer 102 (the high-concentration region 122a of the SiC epitaxial layer 122). From this pn junction, a depletion layer spreads toward a plurality of gate trenches 131. The depletion layer spreading from the deep well region 155 extends toward the region on the second main surface 104 side with respect to the bottom wall of the gate trench 131.

[0560] The depletion layer spreading from the deep well region 155 may overlap the bottom wall of the gate trench 131. The depletion layer spreading from the bottom of the deep well region 155 may overlap the bottom wall of the gate trench 131.

[0561] In a SiC semiconductor device including only a pn junction diode, due to the structure without trenches, the problem of electric field concentration in the SiC semiconductor layer 102 is small. The deep well region 155 makes the trench gate type MISFET approach the structure of the pn junction diode.

[0562] As a result, in the trench gate type MISFET, the electric field within the SiC semiconductor layer 102 can be relaxed. Narrowing the pitch between a plurality of adjacent deep well regions 155 is effective in alleviating electric field concentration. According to the deep well region 155 having a bottom on the second main surface 104 side with respect to the bottom wall of the gate trench 131, the depletion layer can appropriately relax the electric field concentration with respect to the gate trench 131.

[0563] Preferably, the bottoms of the plurality of deep well regions 155 are formed at a substantially constant interval from the second main surface 104. Thereby, it is possible to suppress variations in the distance between the bottom of each deep well region 155 and the second main surface 104. In this case, since it is possible to suppress the breakdown voltage (for example, electrostatic breakdown withstand voltage) of the SiC semiconductor layer 102 from being limited by the deep well region 155, it is possible to appropriately improve the breakdown voltage.

[0564] Also, in this form, a high concentration region 122a of the SiC epitaxial layer 122 is interposed in the region between a plurality of adjacent deep well regions 155. Thereby, the JFET (Junction Field Effect Transistor) resistance in the region between the plurality of deep well regions 155 can be reduced.

[0565] Furthermore, in this form, the bottom of the deep well region 155 is located within the high concentration region 122a of the SiC epitaxial layer 122. Thereby, using the high concentration region 122a located directly below the deep well region 155, the current path can be extended in the lateral direction parallel to the first main surface 103. As a result, the current spreading resistance can be reduced. The low concentration region 122b of the SiC epitaxial layer 122 increases the breakdown voltage of the SiC semiconductor layer 102 in such a structure.

[0566] In addition, the deep well region 155 is formed using the source trench 141. That is, the deep well region 155 is conformally formed with respect to the inner wall of the source trench 141. Thereby, variations in the depth of each deep well region 155 can be appropriately suppressed. Further, by using the source trench 141, the deep well region 155 can be appropriately formed in a relatively deep region of the SiC semiconductor layer 102.

[0567] The SiC semiconductor device 101 includes a plurality of source sub-trenches 156 formed in a region along the upper end portion of the source electrode layer 143 on the first main surface 103. The plurality of source sub-trenches 156 communicate with the corresponding source trench 141 and form a part of the side wall of the source trench 141.

[0568] In this form, the source sub-trench 156 is formed in an annular (for example, endless) shape surrounding the upper end portion of the source electrode layer 143 in plan view. That is, the source sub-trench 156 borders the upper end portion of the source electrode layer 143.

[0569] The source sub-trench 156 is formed by digging down a part of the source insulating layer 142. More specifically, the source sub-trench 156 is formed by digging down from the first main surface 103 the upper end portion of the source insulating layer 142 and the upper end portion of the source electrode layer 143.

[0570] The upper end portion of the source electrode layer 143 has a constricted shape with respect to the lower end portion of the source electrode layer 143. The lower end portion of the source electrode layer 143 is the portion of the source electrode layer 143 located on the bottom wall side of the source trench 141. The width of the upper end portion of the source electrode layer 143 along the first direction X may be less than the width of the lower end portion of the source electrode layer 143 along the first direction X.

[0571] The source sub-trench 156 is formed in a tapered shape in which the bottom area is less than the opening area in cross-sectional view. The bottom wall of the source sub-trench 156 may be formed in a curved shape toward the second main surface 104.

[0572] From the inner wall of the source sub-trench 156, the source region 153, the contact region 154, the source insulating layer 142, and the source electrode layer 143 are exposed. From the bottom wall of the source sub-trench 156, at least the first region 142a of the source insulating layer 142 is exposed. In the source insulating layer 142, the upper end of the first region 142a is located below the first main surface 103.

[0573] The opening edge portion 157 of each source trench 141 includes an inclined portion 158 that slopes downward from the first main surface 103 toward the inside of the source trench 141. The opening edge portion 157 of the source trench 141 is a corner connecting the first main surface 103 and the side wall of the source trench 141. The inclined portion 158 of the source trench 141 is formed by the source sub-trench 156.

[0574] In this form, the inclined portion 158 is formed in a curved shape that is recessed toward the SiC semiconductor layer 102. The inclined portion 158 may be formed in a curved shape that protrudes toward the source sub-trench 156. The electric field with respect to the opening edge portion 157 is relaxed by the inclined portion 158.

[0575] The SiC semiconductor device 101 includes a low-resistance electrode layer 159 formed on the gate electrode layer 135. The low-resistance electrode layer 159 covers the upper end portion of the gate electrode layer 135 in the gate trench 131. That is, the trench gate structure 151 includes the low-resistance electrode layer 159.

[0576] The low-resistance electrode layer 159 includes a conductive material having a sheet resistance less than the sheet resistance of the gate electrode layer 135. The sheet resistance of the low-resistance electrode layer 159 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance of the low-resistance electrode layer 159 may be 0.01 Ω / □ or more and 0.1 Ω / □ or less, 0.1 Ω / □ or more and 1 Ω / □ or less, 1 Ω / □ or more and 2 Ω / □ or less, 2 Ω / □ or more and 4 Ω / □ or less, 4 Ω / □ or more and 6 Ω / □ or less, 6 Ω / □ or more and 8 Ω / □ or less, or 8 Ω / □ or more and 10 Ω / □ or less.

[0577] The current supplied into the gate trench 131 flows through the low-resistance electrode layer 159 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 135. As a result, since the entire gate electrode layer 135 can be quickly shifted from the off state to the on state, the delay of the switching response can be suppressed.

[0578] Particularly, in the case of the gate trench 131 having a length on the order of millimeters, although it takes time for the current to be transmitted, according to the low-resistance electrode layer 159, the delay of the switching response can be appropriately suppressed. That is, the low-resistance electrode layer 159 is formed as a current diffusion electrode layer that diffuses the current in the gate trench 131.

[0579] The low-resistance electrode layer 159 is formed in a film shape. The low-resistance electrode layer 159 has a connection portion 159a that contacts the upper end portion of the gate electrode layer 135 and a non-connection portion 159b opposite thereto. The connection portion 159a and the non-connection portion 159b of the low-resistance electrode layer 159 may be formed in a curved shape following the upper end portion of the gate electrode layer 135. The connection portion 159a and the non-connection portion 159b of the low-resistance electrode layer 159 can take various forms.

[0580] The entire connection portion 159a of the low-resistance electrode layer 159 may be located above the first main surface 103. The entire connection portion 159a of the low-resistance electrode layer 159 may be located below the first main surface 103.

[0581] The connection portion 159a of the low-resistance electrode layer 159 may include a portion located above the first main surface 103. The connection portion 159a of the low-resistance electrode layer 159 may include a portion located below the first main surface 103. For example, the central portion of the connection portion 159a of the low-resistance electrode layer 159 may be located below the first main surface 103, and the peripheral portion of the connection portion 159a of the low-resistance electrode layer 159 may be located above the first main surface 103.

[0582] The entire non-connected portion 159b of the low-resistance electrode layer 159 may be located above the first main surface 103. The entire non-connected portion 159b of the low-resistance electrode layer 159 may be located below the first main surface 103.

[0583] The non-connected portion 159b of the low-resistance electrode layer 159 may include a portion located above the first main surface 103. The non-connected portion 159b of the low-resistance electrode layer 159 may include a portion located below the first main surface 103. For example, the central portion of the non-connected portion 159b of the low-resistance electrode layer 159 may be located below the first main surface 103, and the peripheral portion of the non-connected portion 159b of the low-resistance electrode layer 159 may be located above the first main surface 103.

[0584] The low-resistance electrode layer 159 has an edge portion 159c in contact with the gate insulating layer 134. The edge portion 159c of the low-resistance electrode layer 159 is in contact with a corner portion (the bulging portion 134d in this form) that connects the first region 134a and the second region 134b in the gate insulating layer 134.

[0585] The edge portion 159c of the low-resistance electrode layer 159 is formed in a region on the first main surface 103 side with respect to the bottom of the source region 153. That is, the edge portion 159c of the low-resistance electrode layer 159 is formed in a region on the first main surface 103 side of the boundary region between the body region 126 and the source region 153.

[0586] Therefore, the edge portion 159c of the low-resistance electrode layer 159 faces the source region 153 with the gate insulating layer 134 interposed therebetween. The edge portion 159c of the low-resistance electrode layer 159 does not face the body region 126 with the gate insulating layer 134 interposed therebetween. Thereby, the formation of a leakage current path can be suppressed in the region between the low-resistance electrode layer 159 and the body region 126 in the gate insulating layer 134.

[0587] A leakage current path can be formed by undesired diffusion of the electrode material of the low-resistance electrode layer 159 with respect to the gate insulating layer 134. By connecting the edge 159c of the low-resistance electrode layer 159 to a relatively thick third region 134c (bulge 134d) in the gate insulating layer 134, formation of the leakage current path can be appropriately suppressed.

[0588] In the normal direction N, the thickness TR of the low-resistance electrode layer 159 is equal to or less than the thickness TG of the gate electrode layer 135 (TR≦TG). More specifically, the thickness TR of the low-resistance electrode layer 159 is equal to or less than half of the thickness TG of the gate electrode layer 135 (TR≦TG / 2).

[0589] The ratio TR / TG of the thickness TR of the low-resistance electrode layer 159 to the thickness TG of the gate electrode layer 135 may be 0.01 or more and 1 or less. The ratio TR / TG may be 0.01 or more and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and 1 or less.

[0590] The thickness TG of the gate electrode layer 135 may be 0.5 μm or more and 3 μm or less. The thickness TG of the gate electrode layer 135 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0591] The thickness TR of the low-resistance electrode layer 159 may be 0.01 μm or more and 3 μm or less. The thickness TR of the low-resistance electrode layer 159 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0592] In this form, the low-resistance electrode layer 159 also covers the upper end portion of the gate wiring layer 136. The portion of the low-resistance electrode layer 159 that covers the upper end portion of the gate wiring layer 136 is integrally formed with the portion that covers the upper end portion of the gate electrode layer 135. As a result, the low-resistance electrode layer 159 covers the entire area of the gate electrode layer 135 and the entire area of the gate wiring layer 136.

[0593] Therefore, the current supplied from the gate pad 110 (gate finger 111) flows through the low-resistance electrode layer 159 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 135 and the entire gate wiring layer 136. As a result, the entire gate electrode layer 135 can be quickly shifted from the off state to the on state via the gate wiring layer 136, so that the delay of the switching response can be suppressed.

[0594] In particular, in the case of the gate trench 131 having a length on the order of millimeters, the delay of the switching response can be appropriately suppressed by the low-resistance electrode layer 159 that covers the upper end portion of the gate wiring layer 136.

[0595] The low-resistance electrode layer 159 includes a polyside layer. More specifically, the low-resistance electrode layer 159 is composed of a p-type polyside layer containing p-type impurities added to the gate electrode layer 135 (p-type polysilicon). The polyside layer is formed by siliciding the surface layer portion of the gate electrode layer 135 containing p-type polysilicon with a metal material. The silicidation of p-type polysilicon is performed by heat treatment. The heat treatment may be the RTA (Rapid Thermal Annealing) method.

[0596] In this form, the low-resistance electrode layer 159 has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less. The specific resistance of the low-resistance electrode layer 159 may be 10 μΩ·cm or more and 20 μΩ·cm or less, 20 μΩ·cm or more and 40 μΩ·cm or less, 40 μΩ·cm or more and 60 μΩ·cm or less, 60 μΩ·cm or more and 80 μΩ·cm or less, or 80 μΩ·cm or more and 110 μΩ·cm or less.

[0597] The low-resistance electrode layer 159 more specifically contains at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2 as a silicide. Among these types, NiSi, CoSi2, and TiSi2 are suitable as the silicide layer for forming the low-resistance electrode layer 159 because they have relatively small specific resistance values and temperature dependencies.

[0598] The sheet resistance in the gate trench 131 in which the gate electrode layer 135 (p-type polysilicon) and the low-resistance electrode layer 159 (p-type silicide) are embedded is equal to or less than the sheet resistance of the gate electrode layer 135 (p-type polysilicon) alone. The sheet resistance in the gate trench 131 is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities.

[0599] The sheet resistance in the gate trench 131 approximates the sheet resistance of the low-resistance electrode layer 159. That is, the sheet resistance in the gate trench 131 may be 0.01 Ω / sq or more and 10 Ω / sq or less. The sheet resistance in the gate trench 131 may be 0.01 Ω / sq or more and 0.1 Ω / sq or less, 0.1 Ω / sq or more and 1 Ω / sq or less, 1 Ω / sq or more and 2 Ω / sq or less, 2 Ω / sq or more and 4 Ω / sq or less, 4 Ω / sq or more and 6 Ω / sq or less, 6 Ω / sq or more and 8 Ω / sq or less, or 8 Ω / sq or more and 10 Ω / sq or less. The sheet resistance in the gate trench 131 is preferably less than 10 Ω / sq.

[0600] Referring to FIGS. 42 and 43, the active region 106 has an active main surface 161 that forms a part of the first main surface 103. The outer region 107 has an outer main surface 162 that forms a part of the first main surface 103. The outer main surface 162 is connected to the side surfaces 105A to 105D.

[0601] The outer main surface 162 is located on the second main surface 104 side with respect to the active main surface 161. In this form, the outer region 107 is formed by digging down the first main surface 103 toward the second main surface 104 side. Therefore, the outer region 107 is formed in a region that is recessed toward the second main surface 104 side with respect to the active main surface 161.

[0602] The outer main surface 162 may be located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The outer main surface 162 may be formed at a depth position substantially equal to the bottom wall of the source trench 141. That is, the outer main surface 162 may be located substantially on the same plane as the bottom wall of the source trench 141. The distance between the outer main surface 162 and the second main surface 104 may be substantially equal to the distance between the bottom wall of the source trench 141 and the second main surface 104.

[0603] The outer main surface 162 may be located on the second main surface 104 side with respect to the bottom wall of the source trench 141. The outer main surface 162 may be located on the second main surface 104 side with respect to the bottom wall of the source trench 141 in a range exceeding 0 μm and equal to or less than 1 μm.

[0604] The SiC epitaxial layer 122 is exposed from the outer main surface 162. More specifically, the high-concentration region 122a of the SiC epitaxial layer 122 is exposed from the outer main surface 162. The outer main surface 162 faces the low-concentration region 122b of the SiC epitaxial layer 122 with the high-concentration region 122a of the SiC epitaxial layer 122 interposed therebetween.

[0605] In this form, the active region 106 is partitioned into a mesa shape by the outer region 107. That is, the active region 106 is formed as an active mesa 163 that protrudes upward from the outer region 107.

[0606] The active mesa 163 includes an active sidewall 164 that connects the active main surface 161 and the outer main surface 162. The first main surface 103 of the SiC semiconductor layer 102 is formed by the active main surface 161, the outer main surface 162, and the active sidewall 164.

[0607] In this form, the active sidewall 164 extends along a direction substantially perpendicular to the active main surface 161 (outer main surface 162). The active sidewall 164 may slope downward from the active main surface 161 toward the outer main surface 162. The active sidewall 164 demarcates a boundary region between the active region 106 and the outer region 107.

[0608] The SiC epitaxial layer 122 is exposed from the active sidewall 164. More specifically, the high-concentration region 122a of the SiC epitaxial layer 122 is exposed from the active sidewall 164. Thereby, the main structure of the MISFET can be appropriately formed in the high-concentration region 122a partitioned by the active mesa 163.

[0609] At least the body region 126 is exposed from the region on the active main surface 161 side of the active sidewall 164. FIGS. 42 and 43 show exemplary forms in which the body region 126 and the source region 153 are exposed from the active sidewall 164.

[0610] The SiC semiconductor device 101 includes a p + -type diode region 171, a p-type outer deep well region 172, and a p-type field limit structure 173 formed in the surface layer portion of the outer main surface 162 (first main surface 103) in the outer region 107.

[0611] The diode region 171 is formed in the region between the active sidewall 164 and the side surfaces 105A to 105D in the outer region 107. The diode region 171 is formed at a distance from the active sidewall 164 and the side surfaces 105A to 105D.

[0612] The diode region 171 extends in a strip shape along the active region 106 in a plan view. In this form, the diode region 171 is formed in an annular shape (for example, endless) surrounding the active region 106 in a plan view.

[0613] The diode region 171 overlaps with the source routing wiring 114 in a plan view. The diode region 171 is electrically connected to the source routing wiring 114. The diode region 171 forms part of an avalanche current absorption structure.

[0614] The diode region 171 forms a pn junction with the SiC semiconductor layer 102. More specifically, the diode region 171 is located within the SiC epitaxial layer 122. Therefore, the diode region 171 forms a pn junction with the SiC epitaxial layer 122.

[0615] More specifically, the diode region 171 is located within the high-concentration region 122a of the SiC epitaxial layer 122. Therefore, the diode region 171 forms a pn junction with the high-concentration region 122a of the SiC epitaxial layer 122. Thereby, a pn junction diode 174 is formed with the diode region 171 as the anode and the SiC semiconductor layer 102 as the cathode.

[0616] The whole of the diode region 171 is located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The bottom of the diode region 171 is located on the second main surface 104 side with respect to the bottom wall of the source trench 141. The bottom of the diode region 171 may be formed at a depth position substantially equal to the bottom of the contact region 154. That is, the bottom of the diode region 171 may be located on substantially the same plane as the bottom of the contact region 154.

[0617] The distance between the bottom of the diode region 171 and the second main surface 104 may be substantially equal to the distance between the bottom of the contact region 154 and the second main surface 104. The bottom of the diode region 171 may be located closer to the second main surface 104 than the bottom of the contact region 154. The bottom of the diode region 171 may be located closer to the second main surface 104 than the bottom of the contact region 154 by a range greater than 0 μm and less than or equal to 1 μm.

[0618] The p-type impurity concentration of the diode region 171 is substantially equal to the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the diode region 171 exceeds the p-type impurity concentration of the body region 126. The p-type impurity concentration of the diode region 171 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0619] The outer deep well region 172 is formed in a region between the active sidewall 164 and the diode region 171 in a plan view. In this form, the outer deep well region 172 is formed at an interval from the active sidewall 164 toward the diode region 171 side. The outer deep well region 172 is also referred to as a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the outer region 107.

[0620] The outer deep well region 172 extends in a strip shape along the active region 106 in a plan view. In this form, the outer deep well region 172 is formed in an annular shape (for example, endless shape) surrounding the active region 106 in a plan view.

[0621] The bottom of the outer deep well region 172 is located closer to the second main surface 104 than the bottom of the diode region 171. In this form, the outer deep well region 172 covers the diode region 171 from the second main surface 104 side. The outer deep well region 172 may overlap with the source routing wiring 114 in a plan view.

[0622] The outer deep well region 172 is electrically connected to the source routing wire 114 via the diode region 171. The outer deep well region 172 may form part of the pn junction diode 174. The outer deep well region 172 may form part of the avalanche current absorption structure.

[0623] The entire outer deep well region 172 is located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The bottom of the outer deep well region 172 is located on the second main surface 104 side with respect to the bottom wall of the source trench 141.

[0624] The bottom of the outer deep well region 172 may be formed at a depth position substantially equal to the bottom of the deep well region 155. That is, the bottom of the outer deep well region 172 may be located substantially on the same plane as the bottom of the deep well region 155. The distance between the bottom of the outer deep well region 172 and the outer main surface 162 may be substantially equal to the distance between the bottom of the deep well region 155 and the bottom wall of the source trench 141.

[0625] The distance between the bottom of the outer deep well region 172 and the second main surface 104 may be substantially equal to the distance between the bottom of the deep well region 155 and the second main surface 104. Thereby, it is possible to suppress the occurrence of variations between the distance between the bottom of the outer deep well region 172 and the second main surface 104 and the distance between the bottom of the deep well region 155 and the second main surface 104.

[0626] In this case, since it is possible to suppress the breakdown voltage (for example, electrostatic breakdown withstand voltage) of the SiC semiconductor layer 102 from being limited by the outer deep well region 172 and the deep well region 155, it is possible to appropriately improve the breakdown voltage.

[0627] The bottom of the outer deep well region 172 may be located on the second main surface 104 side with respect to the bottom of the deep well region 155. The bottom of the outer deep well region 172 may be located on the second main surface 104 side with respect to the bottom of the deep well region 155 in a range exceeding 0 μm and equal to or less than 1 μm.

[0628] The p-type impurity concentration of the outer deep well region 172 may be equal to or less than the p-type impurity concentration of the diode region 171. The p-type impurity concentration of the outer deep well region 172 may be less than the p-type impurity concentration of the diode region 171.

[0629] The p-type impurity concentration of the outer deep well region 172 may be approximately equal to the p-type impurity concentration of the deep well region 155. The p-type impurity concentration of the outer deep well region 172 may be approximately equal to the p-type impurity concentration of the body region 126.

[0630] The p-type impurity concentration of the outer deep well region 172 may exceed the p-type impurity concentration of the body region 126. The p-type impurity concentration of the outer deep well region 172 may be less than the p-type impurity concentration of the body region 126.

[0631] The p-type impurity concentration of the outer deep well region 172 may be equal to or less than the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the outer deep well region 172 may be less than the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the outer deep well region 172 may be 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0632] The field limit structure 173 is formed in the region between the diode region 171 and the side surfaces 105A to 105D in a plan view. In this form, the field limit structure 173 is formed at an interval from the diode region 171 toward the side surfaces 105A to 105D.

[0633] The field limit structure 173 includes one or a plurality (for example, two or more and twenty or less) of field limit regions. In this form, the field limit structure 173 includes a group of field limit regions having a plurality (five) of field limit regions 175A, 175B, 175C, 175D, and 175E.

[0634] The field limit regions 175A to 175E are formed in this order at intervals in a direction away from the diode region 171. The field limit regions 175A to 175E are each formed in a strip shape extending along the periphery of the active region 106 in a plan view.

[0635] More specifically, the field limit regions 175A to 175E are each formed in an annular shape (for example, endless) surrounding the active region 106 in a plan view. The field limit regions 175A to 175E are each also referred to as an FLR (Field Limiting Ring) region.

[0636] In this form, the bottoms of the field limit regions 175A to 175E are located on the second main surface 104 side with respect to the bottom of the diode region 171. The innermost field limit region 175A of the field limit regions 175A to 175E covers the diode region 171 from the second main surface 104 side in this form.

[0637] The field limit region 175A may overlap with the aforementioned source routing wiring 114 in a plan view. The field limit region 175A may be electrically connected to the source routing wiring 114 via the diode region 171. The field limit region 175A may form a part of the pn junction diode 174. The field limit region 175A may form a part of the avalanche current absorption structure.

[0638] The entirety of the field limit regions 175A to 175E is located on the second main surface 104 side with respect to the bottom wall of the gate trench 131. The bottoms of the field limit regions 175A to 175E are located on the second main surface 104 side with respect to the bottom wall of the source trench 141.

[0639] The field limit regions 175A to 175E may be formed at a depth position substantially equal to that of the deep well region 155 (outer deep well region 172). That is, the bottoms of the field limit regions 175A to 175E may be located on substantially the same plane as the bottom of the deep well region 155 (outer deep well region 172).

[0640] The bottoms of the field limit regions 175A to 175E may be located on the outer main surface 162 side with respect to the bottom of the deep well region 155 (outer deep well region 172). The bottoms of the field limit regions 175A to 175E may be located on the second main surface 104 side with respect to the bottom of the deep well region 155 (outer deep well region 172).

[0641] The widths between the adjacent field limit regions 175A to 175E may be different from each other. The distances between the adjacent field limit regions 175A to 175E may increase in a direction away from the active region 106. The distances between the adjacent field limit regions 175A to 175E may decrease in a direction away from the active region 106.

[0642] The depths of the field limit regions 175A to 175E may be different from each other. The depths of the field limit regions 175A to 175E may decrease in a direction away from the active region 106. The depths of the field limit regions 175A to 175E may increase in a direction away from the active region 106.

[0643] The p-type impurity concentration of the field limit regions 175A to 175E may be less than or equal to the p-type impurity concentration of the diode region 171. The p-type impurity concentration of the field limit regions 175A to 175E may be less than the p-type impurity concentration of the diode region 171.

[0644] The p-type impurity concentration of the field limit regions 175A to 175E may be less than or equal to the p-type impurity concentration of the outer deep well region 172. The p-type impurity concentration of the field limit regions 175A to 175E may be less than the p-type impurity concentration of the outer deep well region 172.

[0645] The p-type impurity concentration of the field limit regions 175A to 175E may be greater than or equal to the p-type impurity concentration of the outer deep well region 172. The p-type impurity concentration of the field limit regions 175A to 175E may be greater than the p-type impurity concentration of the outer deep well region 172.

[0646] The p-type impurity concentration of the field limit regions 175A to 175E may be 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less. It is preferable that the p-type impurity concentration of the field limit regions 175A to 175E < the p-type impurity concentration of the outer deep well region 172 < the p-type impurity concentration of the diode region 171.

[0647] The field limit structure 173 relaxes the electric field concentration in the outer region 107. The number, width, depth, p-type impurity concentration, etc. of the field limit regions can take various values according to the electric field to be relaxed.

[0648] The SiC semiconductor device 101 includes an outer insulating layer 181 formed on the outer main surface 162 (the first main surface 103) in the outer region 107. The outer insulating layer 181 selectively covers the diode region 171, the outer deep well region 172, and the field limit structure 173 in the outer region 107.

[0649] The outer insulating layer 181 is formed in a film shape along the active sidewall 164 and the outer main surface 162. The outer insulating layer 181 is continuous with the gate insulating layer 134 above the active main surface 161. More specifically, the outer insulating layer 181 is continuous with the third region 134c of the gate insulating layer 134.

[0650] The outer insulating layer 181 may contain silicon oxide. The outer insulating layer 181 may contain other insulating films such as silicon nitride. In this form, the outer insulating layer 181 is formed of the same type of insulating material as the gate insulating layer 134.

[0651] The outer insulating layer 181 includes a first region 181a and a second region 181b. The first region 181a of the outer insulating layer 181 covers the active sidewall 164. The second region 181b of the outer insulating layer 181 covers the outer main surface 162.

[0652] The thickness of the second region 181b of the outer insulating layer 181 may be less than or equal to the thickness of the first region 181a of the outer insulating layer 181. The thickness of the second region 181b of the outer insulating layer 181 may be less than the thickness of the first region 181a of the outer insulating layer 181.

[0653] The thickness of the first region 181a of the outer insulating layer 181 may be approximately equal to the thickness of the first region 134a of the gate insulating layer 134. The thickness of the second region 181b of the outer insulating layer 181 may be approximately equal to the thickness of the third region 134c of the gate insulating layer 134. The outer insulating layer 181 having a uniform thickness may be formed.

[0654] Referring to FIGS. 42 and 43, the SiC semiconductor device 101 includes a sidewall 182 that covers the active sidewall 164. The sidewall 182 protects and reinforces the active mesa 163 from the outer region 107 side.

[0655] The sidewall 182 forms a step relaxation structure that relaxes a step 183 formed between the active main surface 161 and the outer main surface 162. When an upper layer structure covering the boundary region between the active region 106 and the outer region 107 is formed, the upper layer structure covers the sidewall 182. The sidewall 182 enhances the flatness of the upper layer structure.

[0656] The sidewall 182 may have an inclined portion 184 that slopes downward from the active main surface 161 toward the outer main surface 162. The step 183 can be appropriately relaxed by the inclined portion 184. The inclined portion 184 may be formed in a curved shape that is recessed toward the SiC semiconductor layer 102 side. The inclined portion 184 may be formed in a curved shape that protrudes outside the SiC semiconductor layer 102.

[0657] The sidewall 182 is formed self-aligned with respect to the active main surface 161. More specifically, the sidewall 182 is formed along the active sidewall 164. In this form, the sidewall 182 is formed in an annular (e.g., endless) shape that surrounds the active region 106 in plan view.

[0658] The sidewall 182 may contain an insulating material. In this case, the sidewall 182 can enhance the insulation of the active region 106 with respect to the outer region 107. The sidewall 182 may contain a conductive material.

[0659] The sidewall 182 may contain the same type of conductive material as the gate electrode layer 135. The sidewall 182 may contain the same type of conductive material as the source electrode layer 143. Thereby, the sidewall 182 can be formed simultaneously with the gate electrode layer 135 and / or the source electrode layer 143.

[0660] The sidewall 182 includes polysilicon in this form. The sidewall 182 may include n-type polysilicon or p-type polysilicon. When the gate electrode layer 135 includes p-type polysilicon doped with p-type impurities, the sidewall 182 preferably includes p-type polysilicon doped with p-type impurities. The p-type impurities in the sidewall 182 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0661] The p-type impurity concentration of the sidewall 182 is equal to or higher than the p-type impurity concentration of the body region 126. More specifically, the p-type impurity concentration of the sidewall 182 exceeds the p-type impurity concentration of the body region 126. The p-type impurity concentration of the sidewall 182 may be approximately equal to the p-type impurity concentration of the gate electrode layer 135. The sheet resistance of the source electrode layer 143 may be approximately equal to the sheet resistance of the gate electrode layer 135.

[0662] The p-type impurity concentration of the sidewall 182 is 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the sidewall 182 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form).

[0663] Referring to FIGS. 39 to 43, the SiC semiconductor device 101 includes an interlayer insulating layer 191 formed on the first main surface 103. The interlayer insulating layer 191 selectively covers the active region 106 and the outer region 107. The interlayer insulating layer 191 is formed in a film shape along the active main surface 161 and the outer main surface 162.

[0664] The interlayer insulating layer 191 selectively covers the trench gate structure 151, the gate wiring layer 136, and the trench source structure 152 in the active region 106. The interlayer insulating layer 191 selectively covers the diode region 171, the outer deep well region 172, and the field limit structure 173 in the outer region 107.

[0665] The interlayer insulating layer 191 is formed along the outer surface (inclined portion 184) of the sidewall 182 in the boundary region between the active region 106 and the outer region 107. The peripheral portion of the interlayer insulating layer 191 may be flush with the side surfaces 105A to 105D.

[0666] The interlayer insulating layer 191 may contain silicon oxide or silicon nitride. The interlayer insulating layer 191 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

[0667] The interlayer insulating layer 191 may have a single-layer structure composed of a PSG layer or a BPSG layer. The interlayer insulating layer 191 may have a laminated structure including a PSG layer or a BPSG layer laminated in this order from the first main surface 103 side. The interlayer insulating layer 191 may have a laminated structure including a BPSG layer or a PSG layer laminated in this order from the first main surface 103 side.

[0668] Gate contact holes 192, source contact holes 193, diode contact holes 194, and anchor holes 195 are formed in the interlayer insulating layer 191. The gate contact holes 192 expose the gate wiring layer 136 in the active region 106. The gate contact holes 192 may be formed in a strip shape along the gate wiring layer 136.

[0669] The opening edge portion of the gate contact hole 192 is formed in a curved shape toward the inside of the gate contact hole 192. The opening edge portion of the gate contact hole 192 may be formed in a curved shape that is recessed toward the interlayer insulating layer 191.

[0670] The source contact hole 193 exposes the source region 153, the contact region 154, and the trench source structure 152 in the active region 106. The source contact hole 193 may be formed in a strip shape along the trench source structure 152 or the like.

[0671] The opening edge portion of the source contact hole 193 is formed in a curved shape toward the inside of the source contact hole 193. The opening edge portion of the source contact hole 193 may be formed in a curved shape that is recessed toward the inside of the interlayer insulating layer 191.

[0672] The diode contact hole 194 exposes the diode region 171 in the outer region 107. The diode contact hole 194 may be formed in a strip shape (more specifically, an endless (annular) shape) extending along the diode region 171.

[0673] The diode contact hole 194 may expose the outer deep well region 172 and / or the field limit structure 173. The opening edge portion of the diode contact hole 194 is formed in a curved shape toward the inside of the diode contact hole 194. The opening edge portion of the diode contact hole 194 may be formed in a curved shape that is recessed toward the inside of the interlayer insulating layer 191.

[0674] The anchor hole 195 is formed by digging down the interlayer insulating layer 191 in the outer region 107. The anchor hole 195 exposes the first main surface 103 (outer main surface 162). The anchor hole 195 is formed in the region between the field limit structure 173 and the side surfaces 105A to 105D in plan view.

[0675] Referring to FIG. 37, the anchor holes 195 extend in a strip along the active region 106 in a plan view. In this form, the anchor holes 195 are formed in an annular (e.g., endless) shape surrounding the active region 106 in a plan view.

[0676] The opening edge portion of the anchor hole 195 is formed in a curved shape toward the inside of the anchor hole 195. The opening edge portion of the anchor hole 195 may be formed in a curved shape recessed toward the inside of the interlayer insulating layer 191.

[0677] Referring to FIGS. 42 and 44, an inclined portion 196 and a modified layer 197 are formed in the outer region 107. The modified layer 197 is formed by modifying SiC into other properties. The inclined portion 196 and the modified layer 197 respectively correspond to the inclined portion 41 and the modified layer 42 related to the aforementioned SiC semiconductor device 21. The description of the components of the modified layer 197 shall be applied mutatis mutandis to the description of the components of the modified layer 42 (see also FIGS. 21 and 22).

[0678] The inclined portion 196 is formed at a corner connecting the outer main surface 162 (the first main surface 103) and the side surfaces 105A to 105D. The corner of the SiC semiconductor layer 102 includes a corner connecting the outer main surface 162 and the side surfaces 105A and 105C and extending along the [1-100] direction. The corner of the SiC semiconductor layer 102 includes a corner connecting the outer main surface 162 and the side surfaces 105B and 105D and extending along the [11-20] direction.

[0679] The inclined portion 196 slopes downward from the outer main surface 162 toward the side surfaces 105A to 105D. The inclined portion 196 is formed by the inner wall of a recess recessed from the outer main surface 162 toward the second main surface 104 at the corner of the SiC semiconductor layer 102.

[0680] In this form, the inclined portion 196 is formed in the SiC epitaxial layer 122. The inclined portion 196 is formed in a region on the outer main surface 162 side with respect to the boundary region between the SiC semiconductor substrate 121 and the SiC epitaxial layer 122. Therefore, the SiC epitaxial layer 122 is exposed from the inclined portion 196.

[0681] More specifically, the inclined portion 196 is formed in a region on the outer main surface 162 side with respect to the boundary region between the high-concentration region 122a and the low-concentration region 122b in the SiC epitaxial layer 122. That is, the high-concentration region 122a is exposed from the inclined portion 196.

[0682] The inclined portion 196 has an upper end portion 196a and a lower end portion 196b. The upper end portion 196a of the inclined portion 196 is located on the outer main surface 162 side. The lower end portion 196b of the inclined portion 196 is located on the second main surface 104 side.

[0683] In this form, the upper end portion 196a of the inclined portion 196 extends toward the insulating laminated structure 198 including the outer insulating layer 181 and the interlayer insulating layer 191 from the SiC epitaxial layer 122 and is continuous with the insulating laminated structure 198. That is, the SiC epitaxial layer 122 and the insulating laminated structure 198 are exposed from the inclined portion 196. The peripheral portion of the insulating laminated structure 198 is formed in the inner region of the SiC semiconductor layer 102 with respect to the side surfaces 105A to 105D. The insulating laminated structure 198 corresponds to the insulating layer 35 of the SiC semiconductor device 21 described above.

[0684] The upper end portion 196a of the inclined portion 196 is connected to the upper surface of the interlayer insulating layer 191. In the inclined portion 196, the upper connection portion 196c that connects the upper end portion 196a of the inclined portion 196 and the upper surface of the insulating laminated structure 198 may be formed in a curved shape extending outward from the SiC semiconductor layer 102.

[0685] The lower end portion 196b of the inclined portion 196 exposes the SiC epitaxial layer 122. More specifically, the lower end portion 196b of the inclined portion 196 exposes the high-concentration region 122a of the SiC epitaxial layer 122. The lower end portion 196b of the inclined portion 196 is connected to the side surfaces 105A to 105D. The lower end portion 196b of the inclined portion 196 may be formed in a curved shape toward the second main surface 104.

[0686] Referring to FIG. 44, the width WI of the inclined portion 196 may be equal to or less than the in-plane variation of the side surfaces 105A to 105D. The width WI of the inclined portion 196 may be less than the in-plane variation of the side surfaces 105A to 105D. The width WI of the inclined portion 196 is the width in a direction orthogonal to the direction in which the inclined portion 196 extends in a plan view.

[0687] The width WI of the inclined portion 196 may be greater than 0 μm and equal to or less than 10 μm. The width WI of the inclined portion 196 may be greater than 0 μm and equal to or less than 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm. When the thickness of the SiC semiconductor layer 102 is 150 μm or less, the width WI of the inclined portion 196 is preferably greater than 0 μm and equal to or less than 5 μm. More preferably, the width WI of the inclined portion 196 is greater than 0 μm and equal to or less than 2.5 μm.

[0688] The depth D of the inclined portion 196 may be greater than 0 μm and equal to or less than 30 μm. The depth D of the inclined portion 196 is the distance from the outer main surface 162 (the first main surface 103) to the lower end portion 196b of the inclined portion 196 with respect to the normal direction N. The depth D of the inclined portion 196 may be greater than 0 μm and equal to or less than 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, greater than or equal to 15 μm and less than or equal to 20 μm, greater than or equal to 20 μm and less than or equal to 25 μm, or greater than or equal to 25 μm and less than or equal to 30 μm. When the thickness of the SiC semiconductor layer 102 is 150 μm or less, the depth D of the inclined portion 196 is preferably greater than 0 μm and equal to or less than 15 μm.

[0689] The modified layer 197 is formed in a region on the first main surface 103 side at the side surfaces 105A to 105D. More specifically, the modified layer 197 is formed along the corners connecting the outer main surface 162 and the side surfaces 105A to 105D. Even more specifically, the modified layer 197 is formed at the corner connecting the outer main surface 162 and the side surfaces 105A and 105C and extending along the [1-100] direction. The modified layer 197 is formed at the corner connecting the outer main surface 162 and the side surfaces 105B and 105D and extending along the [11-20] direction.

[0690] In this form, the modified layer 197 is formed in the SiC epitaxial layer 122. More specifically, the modified layer 197 is formed in a region on the outer main surface 162 side with respect to the boundary region between the SiC semiconductor substrate 121 and the SiC epitaxial layer 122. Even more specifically, the modified layer 197 is formed in the high-concentration region 122a of the SiC epitaxial layer 122. In this form, the modified layer 197 is formed in a region on the outer main surface 162 side with respect to the boundary region between the high-concentration region 122a and the low-concentration region 122b.

[0691] In this for...

Claims

【Claim 1】 A step of preparing a hexagonal crystal structure; A step of cutting the crystal structure in the m-axis direction of the hexagonal crystal to form a first cut portion; A step of cutting the crystal structure in the a-axis direction of the hexagonal crystal to form a second cut portion that crosses the first cut portion, the method for manufacturing a semiconductor device comprising these steps.

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