Laminated ceramic electronic component

Abstract

To provide a laminated ceramic electronic component having high moisture resistance.SOLUTION: A laminated ceramic electronic component is provided, having an element main body I in which dielectric layers and electrode layers are laminated. The dielectric layer contains a main component represented by a general formula ABO3. The dielectric layer contains with respect to 100 mole of a main component, Mn oxide (in terms of MnO) of 0.05 mol or more and 0.25 mol or less, Mg oxide (in terms of MgO) of 1.00 mol or more and 2.50 mol or less, R oxide (R is at least one selected from at least one of Y, Dy, Ho, Yb, Lu, Gd, and Tb) of 0.50 moles or more and 1.50 moles or less of (in terms of R2O3), Zr oxide of 0.05 moles or more and 0.45 moles or less (in terms of ZrO2, and further contains V. In the dielectric layer, the Zr / V ratio is 2.00 or more and 4.00 or less based on atomic number.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component.

Background Art

[0002] Patent Document 1 describes a multilayer ceramic electronic component having a configuration in which a segregation phase containing Mg is formed in at least a part of a portion where no electrode exists. By having such a configuration, even when the dielectric layer is made thin, a multilayer ceramic electronic component having a high relative permittivity, low dielectric loss, and high reliability can be provided.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a multilayer ceramic electronic component having high moisture resistance.

Means for Solving the Problems

[0005] In order to achieve the above object, a multilayer ceramic electronic component according to the present invention is a multilayer ceramic electronic component having an element body in which a dielectric layer and an electrode layer are laminated, wherein the dielectric layer contains a main component represented by the general formula ABO3 (A is Ba alone, or at least one selected from Ba, Ca, and Sr, and B is Ti alone, or at least one selected from Ti, Zr, and Hf). The dielectric layer contains, per 100 moles of the main component, 0.05 to 0.25 moles of an oxide of Mn in terms of MnO, 1.00 to 2.50 moles of an oxide of Mg in terms of MgO, 0.50 to 1.50 moles of an oxide of R (R is at least one selected from Y, Dy, Ho, Yb, Lu, Gd, and Tb) in terms of R2O3, and 0.05 to 0.45 moles of an oxide of Zr in terms of ZrO2, and further contains V. In the dielectric layer, the Zr / V ratio is 2.00 or more and 4.00 or less on an atomic number basis.

[0006] The dielectric layer may contain 0.40 to 0.80 moles of an oxide of Si in terms of SiO2, per 100 moles of the main component.

[0007] Segregation containing Mg and Si may be formed at the interface between the electrode layer and the dielectric layer and in the region composed of the dielectric layer. The coverage rate of the electrode layer may be 80% or more and 100% or less.

Brief Description of Drawings

[0008]

Figure 1

Figure 2

Embodiments for Carrying Out the Invention

[0009] Hereinafter, the present invention will be described based on the embodiments shown in the drawings.

[0010] Multilayer ceramic capacitor 1 As shown in Fig. 1, a multilayer ceramic capacitor 1, which is a type of multilayer ceramic electronic component according to an embodiment of the present invention, has a capacitor element body 10 configured by alternately laminating a dielectric layer 2 and an internal electrode layer 3. The internal electrode layers 3 are laminated such that their respective end faces are alternately exposed on the surfaces of the opposing ends of the capacitor element body 10. A pair of external electrodes 4 are formed at both ends of the capacitor element body 10 and are connected to the exposed end faces of the alternately arranged internal electrode layers 3 to form a capacitor circuit.

[0011] There is no particular limitation on the shape of the capacitor element body 10, but as shown in Fig. 1, it is usually in the shape of a rectangular parallelepiped. Also, there is no particular limitation on its dimensions, and appropriate dimensions may be selected according to the application.

[0012] Dielectric layer 2 The dielectric layer 2 contains a main component represented by the general formula ABO3 (where A is Ba alone, or at least one selected from Ba, Ca, and Sr, and B is Ti alone, or at least one selected from Ti, Zr, and Hf), and further contains an oxide of Mn, an oxide of Mg, an oxide of R, and an oxide of Zr. Further, the dielectric layer 2 contains V. Further, the dielectric layer 2 may contain an oxide of Si.

[0013] In this embodiment, the oxides include complex oxides. For example, the oxide of Mn includes a complex oxide of Mn and other elements. The oxide of Mn, the oxide of Mg, the oxide of R, and the oxide of Si may all be simple oxides (oxides of a single metal element).

[0014] The dielectric layer 2 preferably contains barium titanate as the main component. Barium titanate is represented by the composition formula Ba m TiO 2+m where m satisfies 0.995 ≦ m ≦ 1.010. Hereinafter, the case where the dielectric layer 2 contains barium titanate as the main component will be described.

[0015] The content of the Mn oxide is more than 0 mol and not more than 0.25 mol and not less than 0.05 mol in terms of MnO conversion with respect to 100 mol of the main component. When the content of the Mn oxide in the dielectric layer 2 is too small, segregation containing Mg and Si described later hardly occurs, and the coverage rate described later is likely to decrease. Then, the moisture resistance of the multilayer ceramic capacitor 1 decreases. When the content of the Mn oxide in the dielectric layer 2 is too large, the moisture resistance of the multilayer ceramic capacitor 1 decreases.

[0016] The content of the Mg oxide is not less than 1.00 mol and not more than 2.50 mol in terms of MgO conversion with respect to 100 mol of the main component. It may be not less than 1.50 mol and not more than 2.00 mol. Whether the content of the Mg oxide in the dielectric layer 2 is too small or too large, the moisture resistance of the multilayer ceramic capacitor 1 decreases. In particular, when the content of the Mg oxide is less than 1.50 mol, the sintering stability of the dielectric layer 2 is likely to deteriorate. When the content of the Mg oxide is more than 2.00 mol, the relative permittivity of the dielectric layer 2 is likely to decrease.

[0017] The content of the R oxide is not less than 0.50 mol and not more than 1.50 mol in terms of R2O3 conversion with respect to 100 mol of the main component. It may be not less than 0.60 mol and not more than 1.20 mol. Whether the content of the R oxide is too small or too large, the moisture resistance of the multilayer ceramic capacitor 1 decreases. When the content of the R oxide is less than 0.60 mol, the reliability of the multilayer ceramic capacitor 1 is likely to decrease. When the content of the R oxide is more than 1.20 mol, the insulation resistance of the dielectric layer 2 is likely to decrease.

[0018] R is at least one selected from Y, Gd, Tb, Dy, Ho, Yb, and Lu. It is preferable that R is at least one selected from Y, Dy, and Ho, and it is particularly preferable that R is Y or Dy.

[0019] The content of the oxide of Zr is 0.05 mol or more and 0.45 mol or less in terms of ZrO2 based on 100 mol of the main component. It may be 0.20 mol or more and 0.40 mol or less. Whether the content of the oxide of Zr is too small or too large, the moisture resistance of the multilayer ceramic capacitor 1 decreases. Furthermore, the smaller the content of the oxide of Zr, the less likely segregation containing Mg and Si described later occurs.

[0020] There is no particular limitation on the content of V. For example, it may be 0.004 mol or more and 0.10 mol or less in terms of V2O5 based on 100 mol of the main component. Also, there is no particular limitation on how the dielectric layer 2 contains V. For example, it may be contained as an oxide of V.

[0021] There is no particular limitation on the content of the oxide of Si. For example, it may be contained in an amount of 0.30 mol or more and 1.00 mol or less in terms of SiO2 based on 100 mol of the main component, or it may be contained in an amount of 0.40 mol or more and 0.80 mol or less. In particular, by containing the oxide of Si in an amount of 0.40 mol or more and 0.80 mol or less, the effect of improving the wettability described later is more easily obtained. As a result, the effect of more easily discharging the pores in the dielectric layer 2 to the outside of the dielectric layer 2 during sintering is also enhanced. And the sintering density of the capacitor element body 10 is more likely to be improved. Therefore, the moisture resistance of the multilayer ceramic capacitor 1 is more likely to be further improved.

[0022] The dielectric layer 2 may further contain other components, that is, the above-mentioned main components, oxides of Mn, oxides of Mg, oxides of R, oxides of Zr, oxides of Si, and components other than V, according to desired characteristics. There is no particular limitation on the content of other components, and it may be in a range that does not significantly affect the performance of the multilayer ceramic capacitor 1. For example, it may be 5 wt% or less in total with respect to the dielectric layer 2.

[0023] It is preferable that the dielectric layer 2 does not substantially contain Al. Specifically, it is preferable that the content of Al is 0.1 mol or less (including 0) in terms of Al2O3.

[0024] In the dielectric layer 2, the Zr / V ratio is 2.0 or more and 4.0 or less on an atomic number basis. When the Zr / V ratio is outside the above range, the moisture resistance of the multilayer ceramic capacitor 1 decreases. Further, when the Zr / V ratio is too small, segregation containing Mg and Si described later is less likely to occur in the dielectric layer 2.

[0025] There is no particular limitation on the thickness of the dielectric layer 2. In the present embodiment, when the thickness (layer thickness) of the dielectric layer 2 is t1 [μm], 0.30 ≤ t1 ≤ 2.0 may be satisfied. It is preferably 0.35 ≤ t1 ≤ 1.8, and more preferably 0.40 ≤ t1 ≤ 1.5. When t1 is within the above range, breakdown voltage failure and short circuit failure are less likely to occur in the multilayer ceramic capacitor 1, and the capacitance of the multilayer ceramic capacitor 1 is likely to increase.

[0026] There is no particular limitation on the number of layers of the dielectric layer 2. In the present embodiment, it is preferably 20 or more, more preferably 50 or more, and particularly preferably 100 or more.

[0027] The reason why the moisture resistance of the multilayer ceramic capacitor 1 is improved when the content of each component in the dielectric layer 2 is within the above range will be described. By setting the content of each component in the dielectric layer 2 within the above range, the wettability of various oxides other than the main component with respect to the main component is likely to be improved in the initial stage of firing. As a result, pores in the dielectric layer 2 are easily discharged to the outside of the dielectric layer 2 during sintering, and the sintering density of the capacitor element body 10 is likely to be further improved. Since the sintering density of the capacitor element body 10 is improved, moisture is less likely to penetrate from the outside to the inside of the capacitor element body 10. As a result, it is considered that the moisture resistance is improved, and the electrical characteristics are less likely to deteriorate and structural defects are less likely to occur even when a long-term moisture resistance test is performed.

[0028] Internal electrode layer 3 The conductive material contained in the internal electrode layer 3 is not particularly limited. Since the constituent material of the dielectric layer 2 has reduction resistance, a relatively inexpensive base metal material can be used as the conductive material. The base metal material used as the conductive material is preferably Ni or a Ni alloy. The Ni alloy is preferably an alloy of Ni and one or more elements selected from Mn, Cr, Co, Cu, Sn, and Al. The Ni content in the Ni alloy is preferably 95% by weight or more. Note that various trace components such as P may be contained in the base metal material in an amount of about 0.1% by weight or less each.

[0029] There is no particular limitation on the thickness of the internal electrode layer 3. In this embodiment, when the thickness (layer thickness) of the internal electrode layer 3 is t2 [μm], 0.30 ≤ t2 ≤ 1.0 may be satisfied. It is preferably 0.30 ≤ t2 ≤ 0.80, and more preferably 0.30 ≤ t2 ≤ 0.60. When t2 is within the above range, it becomes easier to reduce the size of the capacitor element body 10, particularly the height dimension. Furthermore, the coverage rate described later is likely to improve, and the capacitance of the multilayer ceramic capacitor 1 is likely to improve.

[0030] When the internal electrode layer 3 is enlarged, as shown in FIG. 2, there may be a portion where the internal electrode is actually not formed (electrode discontinuity portion 3a) in the portion where the internal electrode is to be formed. This electrode discontinuity portion 3a is a region where the distance between adjacent conductive material particles has widened due to the spheroidization of the conductive material particles (mainly Ni particles when Ni or a Ni alloy is used as the conductive material) by grain growth during firing, and the conductive material no longer exists.

[0031] Note that FIG. 2 is a schematic enlarged cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1. Also, there is no particular limitation on the size of the observation range for confirming the coverage rate, the presence or absence of Mg—Si segregation, etc., which will be described later, and it may be set to a size sufficient to confirm the coverage rate, the presence or absence of Mg—Si segregation, etc. For example, 2000 μm 2 may be sufficient. The image obtained by observing the observation range may be a single image with a sufficiently large area, or a plurality of images with a sufficiently large total area.

[0032] In the cross-section shown in FIG. 2, due to the electrode discontinuous portion 3a, the internal electrode layer 3 appears to be discontinuous. However, the electrode discontinuous portions 3a are scattered on the main surface of the internal electrode layer 3. Therefore, even though the internal electrode layer 3 is discontinuous in the cross-section shown in FIG. 2, it is continuous in other cross-sections, and the electrical continuity of the internal electrode layer 3 is ensured.

[0033] In the cross-section shown in FIG. 2, that is, in the cross-section parallel to the X-Y plane of FIG. 2, the sum of the line length of the region where the internal electrode layer 3 is actually formed and the length of the electrode discontinuous portion 3a becomes the line length of the region where the internal electrode layer 3 should be formed. In the present embodiment, the ratio of the line length of the region where the internal electrode layer 3 is actually formed to the line length of the region where the internal electrode layer 3 should be formed is defined as the coverage rate of the electrode layer. The coverage rate of the electrode layer can be said to be the ratio of the internal electrode layer 3 covering the dielectric layer 2. The coverage rate also varies depending on the thickness of the dielectric layer 2 and the thickness of the internal electrode layer 3. When the coverage rate is 100%, there is no electrode discontinuous portion 3a and each internal electrode layer exists as a single line segment.

[0034] In the present embodiment, the coverage rate may be 80% or more and 100% or less. It is preferably 85% or more and 100% or less. More preferably, it is 90% or more and 100% or less. Particularly preferably, it is 95% or more and 100% or less. The higher the coverage rate, the fewer the electrode discontinuous portions 3a. Therefore, in particular, it becomes difficult for water or plating solution to penetrate during the manufacturing process of the multilayer ceramic capacitor 1. As a result, the moisture resistance of the multilayer ceramic capacitor 1 is likely to be improved. When the coverage rate is 100%, there is no electrode discontinuous portion 3a.

[0035] Also, the higher the coverage rate and the fewer the electrode discontinuous portions 3a, the larger the electrode area of the multilayer ceramic capacitor 1 and the larger the capacitance of the multilayer ceramic capacitor 1. From this point as well, a high coverage rate is preferable.

[0036] Segregation phase 5 The segregation phase 5 is a phase having a composition different from that of the dielectric layer 2 and the internal electrode layer 3 mainly composed of barium titanate. The multilayer ceramic capacitor 1 according to the present embodiment may not contain the segregation phase 5, but preferably contains the segregation phase 5 containing Mg and Si as shown in FIG. 2.

[0037] FIG. 2 is a schematic enlarged cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1.

[0038] The segregation phase 5 containing Mg and Si may include the interface between the dielectric layer 2 and the internal electrode layer 3, or may cover the entire outer periphery of the dielectric layer 2. The segregation phase 5 containing Mg and Si may contain elemental components other than Mg and Si. Further, the multilayer ceramic capacitor 1 according to the present embodiment may contain a segregation phase 5 not containing Mg and / or Si. There is no particular limitation on the content of Mg and the content of Si in the segregation phase 5 containing Mg and Si. For example, a segregation phase 5 in which the content of Mg is 10 at% or more and more, and the content of Si is 10 at% or more and more than that of the dielectric layer 2 may be used as the segregation phase 5 containing Mg and Si.

[0039] When the multilayer ceramic capacitor 1 according to the present embodiment contains a segregation phase 5 containing Mg and Si (hereinafter sometimes simply referred to as Mg-Si segregation), it is preferable that Mg-Si segregation is formed in the region including the interface between the internal electrode layer 3 and the dielectric layer 2 and the dielectric layer 2. That is, it is preferable that Mg-Si segregation is formed at the interface between the dielectric layer 2 and / or the internal electrode layer 3 and the dielectric layer 2.

[0040] On the other hand, Mg-Si segregation may or may not be formed in the electrode discontinuous portion 3a. Further, when the coverage rate is 90% or more and 100% or less, it is difficult for Mg-Si segregation to be formed in the electrode discontinuous portion 3a.

[0041] Three internal electrode layers 3 are shown in FIG. 2. Assume that all segregation phases 5 shown in FIG. 2 are Mg-Si segregation. There are two electrode discontinuities 3a in the third internal electrode layer 3 from the top, and Mg-Si segregation is formed in part of each electrode discontinuity 3a.

[0042] In the dielectric layer 2 between the second internal electrode layer 3 from the top and the third internal electrode layer 3 from the top in FIG. 2, there is Mg-Si segregation that is entirely covered by the dielectric layer 2. Such Mg-Si segregation is Mg-Si segregation in the dielectric layer 2.

[0043] Part of the other Mg-Si segregation in FIG. 2 overlaps with the interface between the dielectric layer 2 and the internal electrode layer 3. Such Mg-Si segregation is Mg-Si segregation at the interface between the dielectric layer and the internal electrode layer.

[0044] The multilayer ceramic capacitor 1 in which both Mg-Si segregation is formed in the region consisting of the interface between the internal electrode layer 3 and the dielectric layer 2 and the dielectric layer 2 and the coverage rate is 90% or more and 100% or less has particularly improved moisture resistance. Furthermore, it is more preferable that Mg-Si segregation is formed in both the dielectric layer 2 and the above interface.

[0045] The dielectric layer 2 includes dielectric particles mainly containing the main component and grain boundaries existing between the dielectric particles. Mg and Si tend to exist at the grain boundaries. When forming Mg-Si segregation, Mg and Si move along the grain boundaries. When forming Mg-Si segregation, the pores near the grain boundaries also tend to move at the same time, and the pores are easily discharged outside the dielectric layer 2. As a result, the sintering density of the capacitor element body 10 is improved. Furthermore, when the coverage rate is 90% or more and 100% or less, there are few defective parts in the internal electrode layer 3. Therefore, the diffusion of moisture into the internal electrode layer 3 is suppressed, and the degradation of electrical characteristics and the generation of structural defects are also easily suppressed.

[0046] In addition, Mg and Si tend to exist at grain boundaries. When Mg and Si exist at grain boundaries, the sintering start temperature during sintering is suitably controlled, and a dense sintered body is likely to be obtained. However, when a large amount of Mg and Si exists at grain boundaries, the amount of the paraelectric region in the dielectric layer 2 increases and the relative permittivity tends to decrease. Therefore, by forming Mg and Si as Mg-Si segregation in the region composed of the interface between the internal electrode layer 3 and the dielectric layer 2 and the dielectric layer 2, the amount of the paraelectric region in the dielectric layer 2 is reduced. Note that it is preferable that Mg-Si segregation is not formed at the electrode discontinuous portion 3a.

[0047] From the above, the multilayer ceramic capacitor 1 in which both Mg-Si segregation is formed in the region composed of the interface between the internal electrode layer 3 and the dielectric layer 2 and the dielectric layer 2, and the coverage rate is 90% or more and 100% or less can improve the moisture resistance while suitably maintaining the magnetic properties, particularly the relative permittivity of the dielectric layer 2.

[0048] External electrode 4 There is no particular limitation on the conductive material contained in the external electrode 4. For example, well-known Ni, Cu, Ni alloy, or Cu alloy can be used as the conductive material contained in the external electrode 4. There is no particular limitation on the thickness of the external electrode 4, and it may be appropriately determined according to the application and the like. The thickness of the external electrode 4 is usually preferably about 5 to 50 μm.

[0049] Method for manufacturing multilayer ceramic capacitor 1 The multilayer ceramic capacitor 1 of the present embodiment is manufactured by the same method as the conventional multilayer ceramic capacitor. Specifically, first, a green chip is produced by a method using a paste, for example, an ordinary method such as a printing method or a sheet method. Next, the green chip is fired. Then, it is manufactured by printing or transferring an external electrode to the fired green chip and then firing the external electrode. Hereinafter, the manufacturing method will be specifically described.

[0050] First, prepare a dielectric raw material for forming the dielectric layer 2. The prepared dielectric raw material is made into a paint to prepare a paste for the dielectric layer. The paste for the dielectric layer may be an organic-based paint or an aqueous-based paint.

[0051] As the dielectric raw material, prepare a raw material of barium titanate, a raw material of an oxide of Mn, a raw material of an oxide of Mg, a raw material of an oxide of R, a raw material of an oxide of Zr, and a raw material of an oxide of V. When including an oxide of Si in the dielectric layer 2, also prepare a raw material of the oxide of Si. As these raw materials, for example, simple oxides of each element, composite oxides of each element, or mixtures thereof can be used. Also, various compounds that become the above simple oxides or composite oxides by firing, for example, carbonates, oxalates, nitrates, hydroxides, organometallic compounds, etc. of each element can be appropriately selected and mixed for use.

[0052] Note that as the raw material of barium titanate, those produced by various methods such as various liquid phase methods (for example, oxalate method, hydrothermal synthesis method, alkoxide method, sol-gel method, etc.) in addition to the so-called solid phase method can be used.

[0053] In this embodiment, the BET specific surface area of the raw material of barium titanate is preferably 6.0 m 2 / g or more in order to meet the requirement of thinning the dielectric layer 2.

[0054] When thinning the dielectric layer 2, in order to ensure sufficient reliability, it is necessary to arrange a plurality of dielectric particles between the layers of the internal electrode layer 3. In order to arrange a plurality of dielectric particles between the layers of the internal electrode layer 3, it is required to reduce the average particle size of the dielectric particles. In order to reduce the average particle size of the dielectric particles, it is conceivable to reduce the average particle size of the raw material of barium titanate. The average particle size of the raw material of barium titanate is in an inverse proportional relationship with the specific surface area of the raw material of barium titanate. Therefore, it is preferable that the BET specific surface area of the raw material of barium titanate is 6.0 m 2 / g or more.

[0055] When the dielectric layer 2 contains components other than the above components, raw materials for the components are prepared. As raw materials for the components, similar to the above components, simple oxides of the components, composite oxides of the components, or mixtures thereof can be used. In addition, various compounds that become the above simple oxides or composite oxides by firing can also be used.

[0056] The content of each compound in the dielectric raw material may be determined so that the composition of the dielectric layer 2 described above is obtained after firing. In the state before being made into a paint, the average particle size of the dielectric raw material is usually about 0.05 to 1 μm.

[0057] When the paste for the dielectric layer is an organic-based paint, the dielectric raw material and the organic vehicle are kneaded to produce an organic-based paint. The organic vehicle is a binder dissolved in an organic solvent. There is no particular limitation on the type of binder. For example, it may be appropriately selected from various binders commonly used in this technical field, such as ethyl cellulose and polyvinyl butyral. There is no particular limitation on the type of organic solvent. For example, it may be appropriately selected from various organic solvents such as terpineol, butyl carbitol, acetone, and toluene according to the method for manufacturing the green chip.

[0058] When the paste for the dielectric layer is an aqueous-based paint, the dielectric raw material and the aqueous vehicle are kneaded to produce an aqueous-based paint. The aqueous vehicle is a water-soluble binder, a dispersant, etc. dissolved in water. There is no particular limitation on the type of water-soluble binder. For example, it may be appropriately selected from various water-soluble binders commonly used in this technical field, such as polyvinyl alcohol, cellulose, and water-soluble acrylic resin.

[0059] Hereinafter, the case where the paste for the dielectric layer is an organic-based paint will be described.

[0060] The paste for the internal electrode layer is prepared by kneading the above-described various conductive materials, or various oxides, organometallic compounds, resinates, etc. that become the above-described various conductive materials after firing, and the above-described organic vehicle. Further, the paste for the internal electrode layer may contain a co-material. There is no particular limitation on the type of the co-material. It is preferable that the composition of the co-material is the same as the composition of the main component.

[0061] The paste for the external electrode may be prepared in the same manner as the method for preparing the paste for the internal electrode layer described above.

[0062] There is no particular limitation on the content of the organic vehicle in each of the above-described pastes. It may be the normal content in this technical field. For example, the content of the binder in each paste may be about 1 to 5% by weight, and the content of the solvent may be about 10 to 50% by weight. Further, each paste may contain additives selected from various dispersants, plasticizers, dielectrics, insulators, etc. as required. The total content of these additives in each paste is preferably 10% by weight or less.

[0063] When the printing method is used for manufacturing the green chip, the paste for the dielectric layer and the paste for the internal electrode layer are printed and laminated on a substrate such as PET, cut into a predetermined shape, and then peeled off from the substrate to obtain a green chip.

[0064] When the sheet method is used for manufacturing the green chip, first, a green sheet is formed using the paste for the dielectric layer, and the paste for the internal electrode layer is printed on the green sheet. Next, the green sheets printed with the paste for the internal electrode layer are laminated and cut into a predetermined shape to obtain a green chip.

[0065] Before firing described later, a debinding treatment is performed on the green chip. There is no particular limitation on the debinding conditions. The heating rate is preferably 5 to 300 °C / hour, the holding temperature is preferably 180 to 400 °C, and the temperature holding time is preferably 0.5 to 24 hours. Further, the atmosphere during debinding is preferably air or a reducing atmosphere.

[0066] The atmosphere during the firing of the green chip is preferably a reducing atmosphere. As the atmosphere gas for creating a reducing atmosphere, for example, a mixed gas of N2 and H2 can be humidified and used. The oxygen partial pressure during firing can be appropriately determined according to the type of conductive material in the paste for the internal electrode layer. When using a base metal such as Ni or Ni alloy as the conductive material in the paste for the internal electrode layer, the oxygen partial pressure is preferably 10 -11 ~10 -8 MPa, and the heating rate is preferably 600 - 8000 °C / hour, more preferably 800 - 8000 °C / hour.

[0067] The other conditions are preferably as follows. The holding temperature during firing is preferably 1300 °C or lower, more preferably 1000 - 1300 °C. The temperature holding time during firing is preferably 0.2 - 8 hours, more preferably 0.2 - 3 hours. In particular, when the holding temperature during firing is within the above range, it becomes easier to sufficiently promote the densification of the dielectric layer 2 while preventing electrode disconnection due to abnormal sintering of the internal electrode layer 3 and deterioration of dielectric characteristics due to excessive grain growth of dielectric particles. The cooling rate after firing is preferably 50 - 8000 °C / hour.

[0068] After firing in a reducing atmosphere, it is preferable to anneal the capacitor element body 10. Annealing is a process for re - oxidizing the dielectric layer 2. By annealing, the high - temperature load life of the multilayer ceramic capacitor 1 can be significantly extended.

[0069] The oxygen partial pressure in the atmosphere during annealing is preferably 10 -9 ~10 -5 MPa. When the oxygen partial pressure is within the above range, it becomes easier to sufficiently promote the re - oxidation of the dielectric layer 2 while preventing the oxidation of the internal electrode layer 3.

[0070] The holding temperature during annealing is preferably 1100°C or lower, more preferably 900 - 1100°C. When the holding temperature during annealing is within the above range, it becomes easier to sufficiently promote the re-oxidation of the dielectric layer 2 while preventing the oxidation of the internal electrode layer 3. As a result, it becomes easier to optimize the insulation resistance (IR), high-temperature load life, and capacitance of the multilayer ceramic capacitor 1.

[0071] Note that usually, annealing consists of a heating process, a temperature holding process, and a cooling process, but annealing may also be composed only of the heating process and the cooling process. That is, the temperature holding time may be 0. In this case, the holding temperature is synonymous with the maximum temperature.

[0072] The conditions other than the holding temperature in annealing are shown below. The temperature holding time in annealing is preferably 0 - 30 hours, more preferably 1 - 25 hours. The cooling rate in annealing is preferably 50 - 500°C / hour, more preferably 100 - 300°C / hour. Also, as the annealing atmosphere gas, preferably humidified N2 gas or the like is used.

[0073] There is no particular limitation on the method of humidifying N2 gas, mixed gas, etc. in the above-mentioned debinding treatment, firing, and annealing. For example, it may be humidified using a wetter or the like. When using a wetter or the like, the water temperature is preferably about 5 - 75°C.

[0074] The debinding treatment, firing, and annealing may be performed continuously or independently.

[0075] The end faces of the capacitor element body 10 obtained as described above are polished, and an external electrode paste is applied and fired to form the external electrodes 4. There is no particular limitation on the method of end face polishing. For example, methods such as barrel polishing and sandblasting can be mentioned. Furthermore, if necessary, a coating layer may be formed on the surface of the external electrodes 4 by plating or the like.

[0076] The multilayer ceramic capacitor 1 of the present embodiment manufactured in this way is mounted on a printed circuit board or the like by soldering or the like, and is used in various electronic devices or the like. In particular, it is suitably used for in-vehicle electronic devices or the like that are required to be small, have high performance, high reliability, and high moisture resistance.

[0077] As described above, the embodiments of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.

[0078] In the above-described embodiment, the multilayer ceramic capacitor 1 has been exemplified as the multilayer ceramic electronic component according to the present invention. However, the multilayer ceramic electronic component according to the present invention is not limited to the multilayer ceramic capacitor 1, and any electronic component having the above configuration may be used.

Example

[0079] Hereinafter, the present invention will be described based on more detailed examples, but the present invention is not limited to these examples.

[0080] (Experimental Example 1) As the raw material of the main component, barium titanate powder (BaTiO3 powder) having a BET specific surface area of 8.0 m 2 / g was prepared, and as the raw materials of the sub-components, MnO powder, MgO powder, Dy2O3 powder, ZrO2 powder, V2O5 powder, and SiO2 powder were prepared respectively. In this example, R is Dy.

[0081] Next, the BaTiO3 powder prepared above and the raw materials of the sub-components were wet pulverized in a ball mill for 15 hours and dried to obtain a dielectric raw material. The addition amount of each sub-component was adjusted so that the content of the sub-component in the fired dielectric layer was the amount shown in Table 1 with respect to 100 moles of BaTiO3 as the main component.

[0082] Next, 100 parts by weight of the obtained dielectric raw material, 10 parts by weight of polyvinyl butyral resin, 5 parts by weight of dioctyl phthalate (DOP) as a plasticizer, and 100 parts by weight of alcohol as a solvent were mixed in a ball mill to form a paste, and a paste for a dielectric layer was obtained.

[0083] Separately from the paste for the dielectric layer, 44.6 parts by weight of Ni powder, 52 parts by weight of terpineol, 3 parts by weight of ethyl cellulose, and 0.4 parts by weight of benzotriazole were kneaded with a three-roll mill and slurried to prepare a paste for an internal electrode layer.

[0084] Then, using the paste for the dielectric layer prepared by the above method, a green sheet was formed on a PET film. Next, using the paste for the internal electrode layer on the green sheet, an electrode layer that would ultimately become the internal electrode layer was printed in a predetermined pattern. After printing the electrode layer, the green sheet was peeled off from the PET film to produce a green sheet having the electrode layer. Next, a plurality of green sheets having the electrode layer were laminated and pressure-bonded to produce a green laminate. Further, the green laminate was cut into a predetermined size to produce a green chip.

[0085] Next, the obtained green chip was subjected to a debinding treatment, firing, and annealing under the following conditions to obtain a capacitor element body as a sintered body.

[0086] The debinding treatment conditions were a heating rate of 25°C / hour, a holding temperature of 260°C, a temperature holding time of 8 hours, and an atmosphere of air.

[0087] The firing conditions were a heating rate of 800°C / hour, a holding temperature of 1100 - 1300°C, a temperature holding time of 1 hour, a cooling rate of 800°C / hour, and an atmosphere gas of a humidified N2 + H2 mixed gas (oxygen partial pressure: 10 -10 MPa).

[0088] The annealing conditions were as follows: heating rate: 200 °C / hour, holding temperature: 1000 °C, temperature holding time: 2 hours, cooling rate: 200 °C / hour, and ambient gas: humidified N2 gas (oxygen partial pressure: 10 -7 MPa).

[0089] A wetter was used for humidifying the ambient gas during firing and annealing.

[0090] Next, after polishing the end face of the obtained capacitor element body by sandblasting, Cu was applied as an external electrode to obtain a sample of the multilayer ceramic capacitor shown in FIG. 1. The size of the obtained capacitor sample was 3.2 mm × 1.6 mm × 0.6 mm, and the thickness t1 of the dielectric layer and the thickness t2 of the internal electrode layer were both 0.50 μm. Also, the number of dielectric layers sandwiched between the internal electrode layers was 10.

[0091] For the obtained capacitor samples, observation of segregation phases, coverage ratio, relative permittivity, dielectric loss (tan δ), and measurement of high-temperature load life were performed by the methods shown below, respectively.

[0092] Observation of segregation phase First, the capacitor samples were cut along a plane perpendicular to the dielectric layer. Next, SEM observation and STEM-EDX analysis were performed on this cut surface, and from the results of elemental mapping of Mg element and elemental mapping of Si element, the presence or absence of Mg-Si segregation was confirmed at each of the dielectric layer, the interface between the dielectric layer and the internal electrode layer, and the electrode discontinuity. Specifically, when there was Mg-Si segregation where the entire surrounding was covered by the dielectric layer, it was considered that there was Mg-Si segregation in the dielectric layer. When there was Mg-Si segregation where a part overlapped with the interface between the dielectric layer and the internal electrode layer, it was considered that there was Mg-Si segregation at the interface between the dielectric layer and the internal electrode layer. When there was Mg-Si segregation where a part or all overlapped with the electrode discontinuity, it was considered that there was Mg-Si segregation at the electrode discontinuity. The results are shown in Table 1. In the capacitor samples where no Mg-Si segregation was included in any of the dielectric layer, the interface between the dielectric layer and the internal electrode layer, and the electrode discontinuity, no Mg-Si segregation was also included in other locations.

[0093] Coverage rate Regarding the above-mentioned cross-section, SEM observation was carried out, and the coverage rate was calculated from the obtained SEM photographs. Specifically, assuming that there is no electrode discontinuity in the internal electrode layer, the ratio of the line length of the region where the electrode layer is actually formed to the line length of the region where the electrode layer should be formed was calculated, and this was taken as the coverage rate. The case where the coverage rate is 80% or more and 100% or less was regarded as good, and the case where it is 90% or more and 100% or less was regarded as even better. The results are shown in Table 1.

[0094] Moisture resistance test First, 300 capacitor samples were prepared and divided into three groups of 100 each. Then, a DC voltage of 20 V / μm was applied to each capacitor sample at a temperature of 85% and a relative humidity of 85%.

[0095] A DC current was applied to the capacitor samples in the first group for 2000 hours, the capacitor samples in the second group for 3000 hours, and the capacitor samples in the third group for 4000 hours. After applying the DC current, the insulation resistance was measured after setting the temperature of each capacitor sample to room temperature (25°C). Capacitor samples with an insulation resistance exceeding 1 MΩ were regarded as good products, and capacitor samples with an insulation resistance of 1 MΩ or less were regarded as defective products. Table 1 shows the number of defective products in each group.

[0096] For the first group, the case where the number of defective products is 0 was regarded as good. That is, the case where the ratio of defective products is less than 1% was regarded as good. For the second group, the case where the number of defective products is less than 20 was regarded as good, the case where it is less than 9 was regarded as better, and the case where it is less than 5 was regarded as particularly good. That is, the case where the ratio of defective products is less than 20% was regarded as good, the case where it is less than 9% was regarded as better, and the case where it is less than 5% was regarded as particularly good. For the third group, the case where the number of defective products is less than 30 was regarded as good, the case where it is less than 17 was regarded as better, and the case where it is less than 10 was regarded as particularly good. That is, the case where the ratio of defective products is less than 30% was regarded as good, the case where it is less than 17% was regarded as better, and the case where it is less than 10% was regarded as particularly good.

[0097]

Table 1

[0098] From Table 1, when the content of all secondary components, such as containing 0.05 mol or more and 0.25 mol or less of Mn oxide in terms of MnO, is within a predetermined range and the Zr / V ratio is also within a predetermined range, Mg-Si segregation occurs, the coating rate is high, and the result of the moisture resistance test is good. On the contrary, no Mg-Si segregation occurred in Sample No. 1 where the content of Mn oxide was too small. And the result of the moisture resistance test was inferior to that of each example. Sample No. 8 where the content of Mn oxide was too large had a result of the moisture resistance test inferior to that of each example.

[0099] (Experimental Example 2) For Sample No. 3 in Experimental Example 1, it was carried out under the same conditions except that the content of Mg oxide was changed. The results are shown in Table 2.

[0100]

Table 2

[0101] As shown in Table 2, when the content of all sub-components, such as containing 1.00 mol or more and 2.50 mol or less of the oxide of Mg in terms of MgO, is within a predetermined range and the Zr / V ratio is also within a predetermined range, Mg-Si segregation occurs, the coating rate is high, and the result of the moisture resistance test is good. On the other hand, for sample No. 9 with too little content of the oxide of Mg and sample No. 16 with too much content of the oxide of Mg, the results of the moisture resistance test were both inferior to those of each example.

[0102] (Experimental Example 3) For sample No. 3 in Experimental Example 1, it was carried out under the same conditions except for changing the content of the oxide of R(Dy). The results are shown in Table 3.

[0103]

Table 3

[0104] As shown in Table 3, when the content of all sub-components, such as containing 0.50 mol or more and 1.50 mol or less of the oxide of R(Dy) in terms of R2O3, is within a predetermined range and the Zr / V ratio is also within a predetermined range, Mg-Si segregation occurs, the coating rate is high, and the result of the moisture resistance test is good. On the other hand, for sample No. 17 with too little content of the oxide of R and sample No. 22 with too much content of the oxide of R, the results of the moisture resistance test were both inferior to those of each example.

[0105] (Experimental Example 4) For sample No. 3 in Experimental Example 1, capacitor samples numbered 23 to 28 were prepared under the same conditions except for changing the content of the oxide of Zr and the content of the oxide of V. Note that the Zr / V ratio was made the same for all samples. The results are shown in Table 4.

[0106]

Table 4

[0107] From Table 4, for sample numbers 24 to 27 where the contents of all secondary components were within a predetermined range and the Zr / V ratio was also within a predetermined range, Mg-Si segregation occurred, the coating rate was high, and the results of the moisture resistance test were good. In contrast, for sample number 23 where the content of the oxide of Zr was too small, Mg-Si segregation did not occur, and the results of the moisture resistance test were inferior to those of each example. For sample number 28 where the content of the oxide of Zr was too large, the results of the moisture resistance test were inferior to those of each example.

[0108] (Experimental Example 5) Regarding sample number 3 of Experimental Example 1, capacitor samples numbered 29 to 35 were prepared under the same conditions except that the content of the oxide of Zr was changed as shown in Table 5. The results are shown in Table 5.

[0109]

Table 5

[0110] From Table 5, for sample numbers 30 to 34 where the contents of all secondary components were within a predetermined range and the Zr / V ratio was also within a predetermined range, Mg-Si segregation occurred, the coating rate was high, and the results of the moisture resistance test were good. In contrast, for sample number 29 where the contents of all secondary components were within a predetermined range but the Zr / V ratio was too small, Si segregation did not occur, and the results of the moisture resistance test were inferior to those of each example. For sample number 35 where the contents of all secondary components were within a predetermined range but the Zr / V ratio was too large, the results of the moisture resistance test were inferior to those of each example.

[0111] (Experimental Example 6) Regarding sample number 3 of Experimental Example 1, capacitor samples numbered 36 to 40 were prepared under the same conditions except that the content of the oxide of Si was changed as shown in Table 6. The results are shown in Table 6.

[0112]

Table 6

[0113] From Table 6, for sample numbers 36 to 40 where the contents of all sub-components were within a predetermined range and the Zr / V ratio was also within a predetermined range, Mg-Si segregation occurred, the coating rate was high, and the results of the moisture resistance test were good. Furthermore, for sample numbers 37 to 40 where the content of the oxide of Si was 0.40 mol or more and 0.80 mol or less in terms of SiO2 conversion, the results of the moisture resistance test were further improved compared to sample numbers 3 and 36 which were under the same conditions except that the content of the oxide of Si was less than 0.40 mol or exceeded 0.80 mol.

[0114] (Experimental Example 7) For sample number 39 in Experimental Example 6, sample numbers 39a to 39c and 41 to 45 were prepared under the same conditions except that the coating rate was changed by changing the electrode printing thickness to change the thickness t2 of the internal electrode layer. The results are shown in Table 7.

[0115]

Table 7

[0116] From Table 7, for sample numbers 39, 39c, and 41 to 45 where the coating rate was 85% or more and 100% or less, the results of the moisture resistance test were improved compared to sample numbers 39a and 39b where the coating rate was 80% or more and less than 85%. Furthermore, for sample numbers 41 to 45 where the coating rate was 90% or more and 100% or less and Mg-Si segregation was not formed at the electrode discontinuous part, the results of the moisture resistance test were further improved compared to sample numbers 39 and 39a to 39c where the coating rate was 80% or more and less than 90%.

Explanation of Reference Signs

[0117] 1… Multilayer ceramic capacitor 2… Dielectric layer 3… Internal electrode layer 3a… Electrode discontinuous part 4… External electrode 5… Segregation phase 10… Capacitor element body

Claims

1. A multilayer ceramic electronic component having an element body in which a dielectric layer and an electrode layer are laminated, The dielectric layer has a general formula ABO 3 where A is Ba alone or at least one selected from Ba, Ca, and Sr, and B is Ti alone or at least one selected from Ti, Zr, and Hf), and contains a main component represented by The dielectric layer contains, per 100 moles of the main component, 0.05 mol or more and 0.25 mol or less of an oxide of Mn in terms of MnO, 1.00 mol or more and 2.50 mol or less of an oxide of Mg in terms of MgO, 0.50 mol or more and 1.50 mol or less of an oxide of R (R is at least one selected from Y, Dy, Ho, Yb, Lu, Gd, and Tb) in terms of R 2 O 3 in terms of 0.50 mol or more and 1.50 mol or less, and 0.05 mol or more and 0.45 mol or less of an oxide of Zr in terms of ZrO 2 and further contains V The multilayer ceramic electronic component in which the Zr / V ratio in the dielectric layer is 2.00 or more and 4.00 or less on an atomic number basis.

2. The dielectric layer contains 0.40 mol or more and 0.80 mol or less of an oxide of Si in terms of SiO with respect to 100 mol of the main component. 2 The multilayer ceramic electronic component according to claim 1.

3. Segregation containing Mg and Si is formed in a region including the interface between the electrode layer and the dielectric layer and the dielectric layer, The multilayer ceramic electronic component according to claim 1 or 2, wherein the coverage rate of the electrode layer is 80% or more and 100% or less.

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