Display device

Abstract

To provide a semiconductor device which has high reliability, and with which it is possible to realize a narrowed frame.SOLUTION: A drive circuit includes a first transistor having a first gate and a second gate electrically connected via a semiconductor film that is held therebetween, and a second transistor of which one of the source and the drain is electrically connected to one of the source and the drain of the first transistor. A pixel unit includes a third transistor, a liquid crystal element, and a capacitive element, and the liquid crystal element has a light-transmissive first conductive film electrically connected to one of the source and the drain of the third transistor, a second conductive film, a liquid crystal layer to which an electrical field generated between the first and the second conductive films is applied. The capacitive element includes a first conductive film, a light-transmissive third conductive film, and a nitride insulating film located between the first and the third conductive films, the nitride insulting film being located between the semiconductor film and the second gate of the first transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. In particular, the present invention relates to a sequential circuit using transistors of the same conductivity type. The present invention relates to a semiconductor device, such as a semiconductor display device, using the sequential circuit. [Background technology]

[0002] Semiconductor display devices such as liquid crystal display devices and EL display devices used in portable electronic devices Therefore, there is a demand to narrow the area other than the pixel area (to narrow the frame). Or a system-on-panel in which all the components are fabricated on the same substrate as the pixel section meets the above requirements. In the case of a system-on-panel, the driver circuit is unipolar, just like the pixel section. It is desirable to use transistors with a larger number of transistors because this reduces the cost of manufacturing the panel. The following Patent Documents 1 and 2 disclose a semiconductor display device using a driving circuit. A technology that uses unipolar transistors to construct various circuits such as inverters and shift registers. The following has been disclosed: [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-325798 A [Patent Document 2] JP 2010-277652 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a liquid crystal display device, which is one of the semiconductor devices, in the case of a transmission type, a region through which light passes Increasing the ratio occupied by the pixels, i.e., the so-called aperture ratio, enables effective utilization of the light emitted from the backlight, thus reducing power consumption. However, if the layout of the pixels is determined with priority given to improving the aperture ratio, the sizes of semiconductor elements such as transistors and capacitor elements constituting the pixels must also be reduced. When the capacitance value of the capacitor element becomes small, it becomes difficult to control the orientation of the liquid crystal molecules without reducing the drive frequency, and problems such as a short period for holding the electric potential of the image

[0005] signal occur, resulting in a deterioration of the displayed image quality. In addition, further reduction of the bezel width is required for semiconductor display devices. Moreover, in the drive circuit of a semiconductor display device having unipolar transistors, electrical property degradation such as a shift in the threshold voltage may be

[0006] observed in the transistors in the sequential circuit that outputs a signal having a pulse, and ensuring the reliability of the semiconductor display device is also required. Based on the technical background described above, one aspect of the present invention aims to provide a semiconductor device that can suppress deterioration of image quality while

[0007] lowering power consumption. Alternatively, one aspect of the present invention aims to provide a semiconductor device that has high reliability and can achieve bezel width reduction. This is the case. In the above configuration, the capacitive element will have translucency with respect to visible light. Therefore, While securing the capacitance value necessary to obtain high image quality, the aperture ratio of the pixel can be increased, so the Light loss within the panel can be suppressed to a small level, and the power consumption of the semiconductor device can be reduced in this way.

[0008] Note that in the case of using the metal oxide film and the pixel electrode as a pair of electrodes for the capacitive element as described above, in order to increase the capacitance value of the capacitive element, it is desirable not to provide a resin film such as acrylic between the metal oxide film and the pixel electrode. However, when the resin film is not provided, the distance between the region near the surface of the semiconductor film (back channel region) on the side far from the gate electrode and the surface of the element substrate on which the transistor is formed becomes closer than when the resin film is provided. Therefore, when moisture in the air adheres to the surface of the element substrate, positive fixed charges are generated near the surface, and negative charges are likely to be generated in the back channel region due to the fixed charges. Therefore, it has been empirically found that the threshold voltage is more likely to shift in the negative direction for transistors in which the period during which the potential of the gate electrode is lower than that of the source electrode or drain electrode is longer. However, it has been found that when there is no resin film, the shift of the threshold voltage in the negative direction is particularly likely to be large compared to the case where a resin film is provided.

[0009] Therefore, in one aspect of the present invention, among the transistors included in the sequential circuit, buffer, etc. included in the drive circuit, transistors whose threshold voltage is likely to shift in the negative direction have a gate electrode not only on the normal gate electrode but also on the back channel region side of the semiconductor film. And the gate electrode on the back channel region side is electrically connected to the normal gate electrode.​​​​​​​​​​​ It is assumed that there is.

[0010] By providing a gate electrode on the back channel region side, a negative potential is applied to the back channel region. This prevents the transistor threshold voltage from shifting in the negative direction. In addition, instead of applying a constant potential to the gate electrode on the back channel region side, The gate electrode is electrically connected to a normal gate electrode, and the pair of gate electrodes are provided with the same potential. By applying this, the channel formation region can be increased, and the drain current can be increased. Therefore, it is possible to reduce the size of the transistor while suppressing the decrease in on-state current. This makes it possible to keep the area of ​​the drive circuit small. Effect of the Invention

[0011] According to one embodiment of the present invention, a semiconductor device capable of suppressing deterioration in image quality and reducing power consumption Alternatively, according to one embodiment of the present invention, a highly reliable and narrow frame device can be provided. It is possible to provide a semiconductor device having such a structure. [Brief description of the drawings]

[0012]

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Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0014] Note that the present invention includes all semiconductor devices using transistors, such as integrated circuits, RF tags, and semiconductor display devices. Note that integrated circuits include microprocessors, image processing circuits, DSP (Digital Signal Processor), microcontrollers including LSIs (Large Scale Integrated Circuits) including microcontrollers, FPGAs (Field Programmable Gate Arrays), and C PLDs (Complex PLDs) and other programmable logic circuits (PLDs: Programmable Logic Devices) are included in the scope. Also, semiconductor displays PLD (Complex PLD) and other programmable logic circuits (PLD: Programmable Logic Device) are included in the scope. Also, semiconductor displays are included in the scope. Also, semiconductor displays The display device includes a liquid crystal display device, a light-emitting device having a light-emitting element typified by an organic light-emitting element in each pixel, a device, an electronic paper, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), an FED (Field Emi ssion Display), etc., and a semiconductor display device having a circuit element using a semiconductor film in a drive circuit is included in the scope thereof.

[0015] In the present specification, the semiconductor display device includes a panel in which display elements such as liquid crystal elements and light-emitting elements are formed in each pixel, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, the semiconductor display device according to one aspect of the present invention includes an element substrate corresponding to a form before the display element is completed in the process of manufacturing the semiconductor display device, and the element substrate includes a transistor, an electrode such as a pixel electrode or a common electrode used for the display element, and a capacitor element in a plurality of each pixel.

[0016] In addition, the semiconductor display device according to one aspect of the present invention may include a touch panel, which is a position input device capable of detecting a position pointed by a finger or a stylus and generating a signal including the position information, as a component.

[0017] In the present specification, "connection" means electrical connection, which corresponds to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily mean a directly connected state, but current, voltage, or potential can be supplied or transmitted through circuit elements such as wiring, resistors, diodes, and transistors. ​​​​​​​​​​A state where it is indirectly connected is also included in that scope. Also, even when constituent elements that are independent on the circuit diagram are connected to each other, actually, for example, when a part of the wiring functions as an electrode, there may be a case where one conductive film has the functions of a plurality of constituent elements. In this specification, connection includes such a case where one conductive film has the functions of a plurality of constituent elements within that scope. Even when constituent elements that are independent on the circuit diagram are connected to each other, actually, for example, when a part of the wiring functions as an electrode, there may be a case where one conductive film has the functions of a plurality of constituent elements. In this specification, connection includes such a case where one conductive film has the functions of a plurality of constituent elements. Even in such a case, it is included in that scope.

[0018] Also, the source of a transistor means a source region that is a part of a semiconductor film functioning as an active layer, or a source electrode connected to the above semiconductor film. Similarly, the drain of a transistor means a drain region that is a part of the above semiconductor film, or a drain electrode connected to the above semiconductor film. Also, the gate means a gate electrode. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship.

[0019] The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship. The source and drain that a transistor has change their names depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but actually, the names of the source and drain are interchanged according to the above potential relationship.

[0020] <Example 1 of the Configuration of a Sequential Circuit> FIG. 1(A) shows, as an example, the configuration of a sequential circuit according to one aspect of the present invention. In FIG. 1(A), The sequential circuit 10 shown has a circuit 11, a transistor 12, and a transistor 13. The circuit 11 has a function of controlling the potentials of the gate of the transistor 12 and the gate of the transistor 13 according to the potentials of the signal LIN and the signal RIN.

[0021] The transistor 12 has a function of controlling the electrical connection between the wiring to which the signal Sig or the high-level potential VDD is applied and the output terminal OUT. Further, the transistor 13 has a function of controlling the electrical connection between the wiring to which the low-level potential VSS is applied and the output terminal OUT. Specifically, one of the source and drain of the transistor 12 is connected to the wiring to which the signal Sig or the high-level potential VDD is applied, and one of the source and drain of the transistor 13 is connected to the wiring to which the low-level potential VSS is applied. For the signal Sig, a signal with a duty ratio of about 0.5, which is the ratio of the pulse width to the pulse period such as a clock signal, can be used. Also, the other of the source and drain of the transistor 12 and the other of the source and drain of the transistor 13 are connected to the output terminal OUT.

[0022] By controlling the potential of the gate of the transistor 12 and the potential of the gate of the transistor 13 by the circuit 11, conduction or non-conduction of the transistor 12 is selected, and conduction or non-conduction of the transistor 13 is selected. And when the transistor 12 is in the conductive state and the transistor 13 is in the non-conductive state, the wiring to which the signal Sig or the potential VDD is applied is connected to the output terminal OUT. Also, when the transistor 12 is in the non-conductive state and the transistor 13 is in the non-conductive state, ​​​​​​​​​​​​​When the transistor 13 is in a conductive state, the wiring to which the potential VSS is applied is connected to the output terminal OUT. can be.

[0023] The output signal including the potential of the output terminal OUT of the sequential circuit 10 is connected to a plurality of pixels. When supplying the signal to a wiring called a bus line, for example a scanning line, the duty of the output signal is In this case, the transistor 12 outputs Since transistor 12 is continuously in a non-conducting state during periods other than the pulse of the signal, The period of time that transistor 13 is in the conductive state is significantly longer than the period of time that transistor 13 is in the non-conductive state. A signal Sig or a potential VD Since D is given, transistor 12 has a gate for either the source or the drain. The period during which the potential of the gate is in a low state is longer than that of the transistor 13, and the threshold voltage is negative. It can be seen that the shift is more likely to occur in the direction of the arrow.

[0024] Therefore, in one embodiment of the present invention, the transistor 12 is electrically connected and is a semiconductor The gate electrodes are electrically connected to each other. By providing a pair of gate electrodes in the transistor 12, a positive Even if fixed charges are generated, the fixed charges generate negative charges near the surface of the semiconductor film. This prevents the threshold voltage of the transistor 12 from shifting in the negative direction. This improves the reliability of the sequential circuit 10 and, in turn, the reliability of a semiconductor device using the sequential circuit 10. It is possible.

[0025] In addition, by electrically connecting a pair of gate electrodes, a single gate electrode is formed on only one of the pair of gate electrodes. Unlike the case where a fixed potential is applied, the same potential is applied to a pair of gate electrodes, so the number of channel formation regions increases, and an increase in the drain current of transistor 12 can be realized. Therefore, while suppressing a decrease in the on-current, the size of transistor 12 can be suppressed to be small, so that the area of the sequential circuit 10, and thus the driving circuit using the sequential circuit 10, can be suppressed to be small. In particular, since a larger current supply capacity is required for transistor 12 provided on the output side of sequential circuit 10 than for the transistors used in circuit 11, by transistor 12 having a pair of gate electrodes as described above, the area of the sequential circuit or the driving circuit can be suppressed to be smaller compared to the case where the same configuration is applied to other transistors in sequential circuit 10. It can be said that the effect is significant.

[0026] Also, by providing a pair of electrically connected gate electrodes, the depletion layer in the semiconductor film is less likely to be formed, so that the S value (subthreshold value) of transistor 12 can be improved.

[0027] Next, FIG. 1(B) shows a more detailed configuration example of the sequential circuit 10 shown in FIG. 1(A). The sequential circuit 10 shown in FIG. 1(B) has the same circuit 11, transistor 12, and transistor 13 as the sequential circuit 10 shown in FIG. 1(A). And in FIG. 1(B), the case where circuit 1 1 has transistors 14 to 17 is illustrated.

[0028] Transistor 14 is selected to be conductive or non-conductive according to the potential of signal LIN. When transistor 14 is in the conductive state, the wiring to which potential VDD is applied and the gate of transistor 12 are electrically connected. Transistor 15 is conductive according to the potential of signal RIN ​ Or non-conduction is selected. When transistor 15 is in the conductive state, the wiring to which the potential VDD is applied is electrically connected to the gate of transistor 13. Transistor 16 is selected to conduct or not conduct according to the potential of signal RIN. When transistor 16 is in the conductive state the wiring to which the potential VSS is applied is electrically connected to the gate of transistor 12 Transistor 17 is selected to conduct or not conduct according to the potential of signal LIN When transistor 17 is in the conductive state, the wiring to which the potential VSS is applied and the transistor The gate of 13 is electrically connected.

[0029] Regarding the operation example of the sequential circuit 10 shown in FIG. 1(B), an example where one of the source and drain of transistor 12 is connected to the wiring to which signal Sig is applied will be described. Also, FIG. 3 illustrates the timing chart of the sequential circuit 10 shown in FIG. 1(B). However In FIG. 3, the timing chart when all of transistors 12 to 17 are n-channel type is illustrated. Also, in FIG. 3, the gate of transistor 12 is shown as node α. As shown in FIG. 3, in period T1, the potential of signal Sig is at a low level, the potential of signal LIN is

[0030] at a high level, and the potential of signal RIN is at a low level. Therefore, in period T1, transistors 14 and 17 are in the conductive state, and transistors 15 and 16 are in the non-conductive state. Therefore, at node α, a potential that has dropped by the threshold voltage of transistor 14 from potential VDD is applied. Also, since potential VSS is applied to the gate of transistor 13 transistor 13 is in the non-conductive state. is applied, so transistor 13 is in the non-conductive state. is applied, so transistor 13 is in the non-conductive state.

[0031] Next, as shown in FIG. 3, in period T2, the potential of signal Sig is at a high level, signal LIN has a low potential, and signal RIN has a low potential. Therefore, in period T2, transistors 14 to 17 are in a non-conducting state, so node α is in a floating state. Thus, in an ideal state where the parasitic capacitance added to node α is significantly smaller than the capacitance formed between the source and gate of transistor 12, the potential of node α rises by the amount of the change in the potential of signal Sig that occurs from period T1 to period T2, that is, by the potential difference between the low-level potential and the high-level potential of signal Sig. Then, when the potential of node α rises, the gate voltage of transistor 12 becomes sufficiently higher than its threshold voltage, so the high-level potential of signal Sig is applied to output terminal OUT. Note that the rising amplitude of the potential of node α varies depending on the capacitance ratio between the parasitic capacitance added to node α and the capacitance C formed between the source and gate of transistor 14. That is, the smaller the parasitic capacitance added to node α compared to capacitance C, the larger the rising amplitude of the potential of node α, and the larger the parasitic capacitance added to node α compared to capacitance C, the smaller the rising amplitude of the potential of node α. Therefore, it is desirable to make the capacitance C formed between the source and gate of transistor 14 larger than the parasitic capacitance added to node α so that the potential of node α rises to such an extent that the gate voltage of transistor 12 becomes sufficiently higher than its threshold voltage.

[0032] Incidentally, the rising width of the potential of node α varies depending on the capacitance ratio between the parasitic capacitance added to node α and the capacitance C formed between the source and gate of transistor 14. That is, the smaller the parasitic capacitance added to node α compared to capacitance C, the larger the rising width of the potential of node α, and the larger the parasitic capacitance added to node α compared to capacitance C, the smaller the rising width of the potential of node α. Thus, it is desirable to make the capacitance C formed between the source and gate of transistor 14 larger than the parasitic capacitance added to node α so that the potential of node α rises to such an extent that the gate voltage of transistor 12 becomes sufficiently higher than its threshold voltage. That is, the smaller the parasitic capacitance added to node α compared to capacitance C, the larger the rising width of the potential of node α, and the larger the parasitic capacitance added to node α compared to capacitance C, the smaller the rising width of the potential of node α. Therefore, it is desirable to make the capacitance C formed between the source and gate of transistor 14 larger than the parasitic capacitance added to node α so that the potential of node α rises to such an extent that the gate voltage of transistor 12 becomes sufficiently higher than its threshold voltage. Next, as shown in FIG. 3, in period T3, the potential of signal Sig is at a low level, signal LIN

[0033] Next, as shown in FIG. 3, in period T3, the potential of signal Sig is at a low level, signal LIN ​​​​​The potential of is at a low level, and the potential of signal RIN is at a high level. Therefore, in period T3, Transistors 14 and 17 are in a non-conducting state, and transistors 15 and transistor 16 are in a conducting state. Thus, since the potential VSS is applied to node α, transistor 12 becomes non-conducting. Also, since the potential VDD is applied to the gate of transistor 13, transistor 13 becomes conducting. Therefore, the potential VSS is applied to the output terminal OUT.

[0034] Next, as shown in FIG. 3, in period T4, the potential of signal Sig is at a high level, the potential of signal LIN is at a low level, and the potential of signal RIN is at a low level. Therefore, in period T4, transistors 14 to 17 are in a non-conducting state. Thus, transistor 12 maintains a non-conducting state, and transistor 13 maintains a conducting state. Therefore, the potential VSS is applied to the output terminal OUT.

[0035] By the operations in the above periods T1 to T4, an output signal having a pulse is output from the output terminal OUT of the sequential circuit 10. Note that an output signal including the potential of the output terminal OUT of the sequential circuit 10 is supplied to a wiring called a bus line connected to a plurality of pixels, for example, a scanning line. In this case, similar to transistor 12, transistors 14 to 17 have a period in which the potential of the gate is lower than one of the source or drain for a longer time than transistor 13, and it can be seen that the threshold voltage is likely to shift in the negative direction. Therefore, in one aspect of the present invention, at least one of transistors 14 to 17 has a period in which the potential of the gate is lower than one of the source or drain for a longer time than transistor 13, and it can be seen that the threshold voltage is likely to shift in the negative direction. Thus, it can be understood that the threshold voltage is likely to shift in the negative direction.

[0036] Therefore, in one aspect of the present invention, at least one of transistors 14 to 17 ​​is a pair of gate electrodes that are electrically connected and overlap with a semiconductor film sandwiched therebetween may have. In FIG. 1(B), the case where the transistors 14 to 17 have a pair of gate electrodes that are electrically connected is illustrated. By providing a pair of gate electrodes that are electrically connected to the transistors 14 to 17, it is possible to suppress the threshold voltage of the transistors 1 4 to 17 from shifting in the negative direction . Therefore, the reliability of the sequential circuit 10, and thus the semiconductor device using the sequential circuit 10, can be improved .

[0037] Also, since the size of the transistors 14 to 17 can be reduced while suppressing a decrease in the on-current, the area of the sequential circuit 10, and thus the drive circuit using the sequential circuit 10, can be reduced .

[0038] Further, by providing a pair of gate electrodes that are electrically connected, a depletion layer is less likely to be formed in the semiconductor film, so the S value of the transistors 14 to 17 can be improved .

[0039] <Example configuration of transistor> Next, a specific configuration example of the transistor 20 having a pair of gate electrodes that are electrically connected and can be used as the transistors 12, 14 to 17 shown in FIG. 1 is shown in FIG. 2 . In FIG. 2(A), a top view of the transistor 20 is shown. Note . In FIG. 2(A), various insulating films such as the gate insulating film are omitted in order to clarify the layout of the transistor 20 . Also, a cross-sectional view taken along the broken line A1-A 2 in the top view shown in FIG. 2(A) is shown in FIG. 2(B), and a cross-sectional view taken along the broken line A3-A4 is shown in FIG. 2(C) . ​​​

[0040] As shown in FIG. 2, the transistor 20 includes a gate electrode on a substrate 31 having an insulating surface and a conductive film 21 having a function as, and an insulating film 22 having a function as a gate insulating film and located on the conductive film 2 1, and an oxide semiconductor film 23 overlapping the conductive film 21 on the insulating film 22 electrically connected to the oxide semiconductor film 23 and having a function as a source electrode or a drain electrode and conductive films 24 and 25.

[0041] Also, in FIG. 2, an insulating film 26 and an insulating film 27 are provided so as to be laminated in order on the oxide semiconductor film 23, the conductive film 24, and the conductive film 25. The transistor 20 may include the insulating film 26 and the insulating film 27 as its components. In FIG. 2, the insulating film 26 and the insulating film 27 laminated in order are illustrated, but instead of the insulating film 26 and the insulating film 27, a single-layer insulating film may be used, or a laminated insulating film of three or more layers may be used. .

[0042] Also, a nitride insulating film 28 and an insulating film 29 are provided so as to be laminated in order on the insulating film 26 and the insulating film 27. The insulating film 29 is not necessarily provided. However, the insulating film 2 9 has a function as a dielectric film of a pixel capacitor element to be described later together with the nitride insulating film 28. The nitride insulating film 28 has a higher relative permittivity and a greater internal stress tendency than an oxide insulating film such as silicon oxide. Therefore, when only the nitride insulating film 28 is used without using the insulating film 29 as the dielectric film of the capacitor element, if the film thickness of the nitride insulating film 28 is small, the capacitance value of the capacitor element becomes too large, and the writing speed of the image signal to the pixel is increased at low power consumption . will be too high, and This becomes difficult. Conversely, when the film thickness of the nitride insulating film 28 is large, the internal stress becomes too large, and there is a risk that the characteristics of semiconductor elements formed using the semiconductor film deteriorate, such as a shift in the threshold voltage of the transistor. Also, when the internal stress of the nitride insulating film 28 becomes too large, the nitride insulating film 28 is likely to peel off from the substrate 31, hindering the improvement of the yield. However, by using an insulating film 29 made of an insulator such as silicon oxide having a relative permittivity lower than that of the nitride insulating film 28, together with the nitride insulating film 28, as the dielectric film of the pixel capacitor element, the permittivity of the dielectric film can be adjusted to a desired value without increasing the film thickness of the nitride insulating film 28.

[0043] The insulating film 22, the insulating film 26, the insulating film 27, the nitride insulating film 28, and the insulating film 29 have an opening 3 2. The opening 32 is provided in a region different from the oxide semiconductor film 23, the conductive film 24, and the conductive film 25, and still overlaps with the conductive film 21.

[0044] Further, the transistor 20 has a conductive film 30 having a function as a gate electrode on the insulating film 29, or on the nitride insulating film 28 when the insulating film 29 is not provided. The conductive film 30 is provided at a position overlapping with the conductive film 21 and the oxide semiconductor film 23. Therefore, the transistor 20 has a pair of gate electrodes that are electrically connected and overlap with each other with the oxide semiconductor film 23, which is a semiconductor film, in between. Also, the conductive film 30 is electrically connected to the conductive film 21 at the opening 32. The conductive film 30 has translucency with respect to visible light.

[0045] In FIG. 2(C), after forming openings in the insulating film 26 and the insulating film 27, the nitride insulating film 28, and an insulating film 29 are formed, and then, the insulating film 22 and the nitride are formed so as to overlap the opening. The case where the opening 32 is formed in the insulating film 28 and the insulating film 29 is exemplified. However , in one aspect of the present invention, the insulating film 22, the insulating film 26, the insulating film 27, the nitride insulating film 28, and the insulating film 29 may be formed with the opening 32 by etching or the like using a single mask. However , in the pixel, when the pixel electrode is provided on the insulating film 29 or when the insulating film 29 is not provided but on the nitride insulating film 28, and the pixel electrode is electrically connected at the opening formed in the conductive film located between the insulating film 22 and the insulating films 26 and 27, the insulating films 26, 27, the nitride insulating film 28, and the insulating film 29, there will be a difference in the film thickness of the insulating film to be removed by etching between the opening for the pixel electrode and the opening 32. Therefore, when forming both the opening for the pixel electrode and the opening 32 with a single mask, there is a risk that the conductive film located between the insulating film 22 and the insulating films 26 and 27 will be partially over-etched at the opening for the pixel electrode, or that the conductive film 21 will not be exposed at the opening 3 2. However, as shown in FIG. 2( C), when forming the opening in the insulating films 26 and 27 and then forming the opening 32 in the insulating film 22, the nitride insulating film 28, and the insulating film 29, even if both the above opening and the opening 32 are formed with a single mask, a difference in the film thickness of the insulating film to be removed by etching between the opening and the opening 32 is less likely to occur. Therefore, the above-mentioned problems are less likely to occur, and the yield can be increased. 2. However, as shown in FIG. 2( C), when forming the opening in the insulating films 26 and 27 and then forming the opening 32 in the insulating film 22, the nitride insulating film 28, and the insulating film 29, even if both the above opening and the opening 32 are formed with a single mask, a difference in the film thickness of the insulating film to be removed by etching between the opening and the opening 32 is less likely to occur. Therefore, the above-mentioned problems are less likely to occur, and the yield can be increased. 2, etc. However, as shown in the cross-sectional view of FIG. 2( C), when forming the opening in the insulating films 26 and 27 and then forming the opening 32 in the insulating film 22, the nitride insulating film 28, and the insulating film 29, even if both the above opening and the opening 32 are formed with a single mask, a difference in the film thickness of the insulating film to be removed by etching between the opening and the opening 32 is less likely to occur. Therefore, the above-mentioned problems are less likely to occur, and the yield can be increased. After forming the opening in the insulating films 26 and 27, when forming the opening 32 in the insulating film 22, the nitride insulating film 28, and the insulating film 29, even if both the above opening and the opening 32 are formed with a single mask, a difference in the film thickness of the insulating film to be removed by etching between the opening and the opening 32 is less likely to occur. Therefore, the above-mentioned problems are less likely to occur, and the yield can be increased. a single mask, even if both the above opening and the opening 32 are formed with a single mask, a difference in the film thickness of the insulating film to be removed by etching between the opening and the opening 32 is less likely to occur. Therefore, the above-mentioned problems are less likely to occur, and the yield can be increased. a single mask, even if both the above opening and the opening 32 are formed with a single mask, a difference in the film thickness of the insulating film to be removed by etching between the opening and the opening 32 is less likely to occur. Therefore, the above-mentioned problems are less likely to occur, and the yield can be increased. a single mask, even if both the above opening and the opening 32 are formed with a single mask, a difference in the film thickness of the insulating film to be removed by etching between the opening and the opening 32 is less likely to occur. Therefore, the above-mentioned problems are less likely to occur, and the yield can be increased.

[0046] In addition, the transistor 20 shown in FIG. 2 has a configuration in which the end portions of the oxide semiconductor film 23 that do not overlap with the conductive film 24 and the conductive film 25, in other words, the end portions located in a region different from the region where the conductive film 24 and the conductive film 25 are located, overlap with the conductive film 21 and the conductive film 30. When the end portion of the oxide semiconductor film 23 is exposed to plasma during etching for forming the end portion, chlorine radicals, fluorine radicals, etc. generated from the etching gas are likely to bind to the metal elements constituting the oxide semiconductor. Therefore, at the end portion of the oxide semiconductor film, oxygen that was bound to the metal element is likely to desorb, so oxygen deficiency is formed and it is considered that n-type formation is likely. However, in the transistor 20 shown in FIG. 2, since the end portion of the oxide semiconductor film 23 that does not overlap with the conductive film 24 and the conductive film 25 overlaps with the conductive film 21 and the conductive film 30, by controlling the potentials of the conductive film 21 and the conductive film 30, the electric field applied to the end portion can be controlled. Thus, the current flowing between the conductive film 24 and the conductive film 25 through the end portion of the oxide semiconductor film 23 can be controlled by the potentials applied to the conductive film 21 and the conductive film 30. Specifically, when potentials are applied to the conductive film 21 and the conductive film 30 such that the transistor 20 is in a non-conductive state, the off-current flowing between the conductive film 24 and the conductive film 25 through the end portion can be reduced. Therefore, in the transistor 20, in order to obtain a large on-current, the channel length is shortened. As a result, even if the length between the conductive film 24 and the conductive film 25 at the end portion of the oxide semiconductor film 23 becomes short, the off-current of the transistor 20 can be reduced. Thus, the transistor 20 can obtain a large on-current when in a conductive state by shortening the channel length. When the end portion of the oxide semiconductor film 23 that does not overlap with the conductive film 24 and the conductive film 25 overlaps with the conductive film 21 and the conductive film 30, the electric field applied to the end portion can be controlled by controlling the potentials of the conductive film 21 and the conductive film 30. Thus, the current flowing between the conductive film 24 and the conductive film 25 through the end portion of the oxide semiconductor film 23 can be controlled by the potentials applied to the conductive film 21 and the conductive film 30. Specifically, when potentials are applied to the conductive film 21 and the conductive film 30 such that the transistor 20 is in a non-conductive state, the off-current flowing between the conductive film 24 and the conductive film 25 through the end portion can be reduced. Therefore, in the transistor 20, in order to obtain a large on-current, the channel length is shortened. As a result, even if the length between the conductive film 24 and the conductive film 25 at the end portion of the oxide semiconductor film 23 becomes short, the off-current of the transistor 20 can be reduced. Thus, the transistor 20 can obtain a large on-current when in a conductive state by shortening the channel length.

[0047] Specifically, when potentials are applied to the conductive film 21 and the conductive film 30 such that the transistor 20 is in a non-conductive state, the off-current flowing between the conductive film 24 and the conductive film 25 through the end portion can be reduced. Therefore, in the transistor 20, in order to obtain a large on-current, the channel length is shortened. As a result, even if the length between the conductive film 24 and the conductive film 25 at the end portion of the oxide semiconductor film 23 becomes short, the off-current of the transistor 20 can be reduced. Thus, the transistor 20 can obtain a large on-current when in a conductive state by shortening the channel length. As a result, even if the length between the conductive film 24 and the conductive film 25 at the end portion of the oxide semiconductor film 23 becomes short, the off-current of the transistor 20 can be reduced. Therefore, the transistor 20 can obtain a large on-current when in a conductive state by shortening the channel length. Thus, the transistor 20 can obtain a large on-current when in a conductive state by shortening the channel length. A turn-on current can be obtained, and the off current can be suppressed to a small value when in the non-conducting state. To obtain a large turn-on current, the channel length is preferably 0.5 μm or more and 4.5 μm or less, more preferably 1 μm or more and 4 μm or less, even more preferably 1 μm or more and 3.5 μm or less, even more preferably 1 μm or more and 2.5 μm or less, and most preferably 2 μm.

[0048] Fig. 25 shows an example of a cross-sectional view of the transistor 20 at the end of the oxide semiconductor film 23. In Fig. 25, in the channel width direction corresponding to the broken line A3 - A4 in Fig. 2(A), the case where the end of the oxide semiconductor film 23 is positioned so as to overlap the conductive film 21 is exemplified. Also, in Fig. 25, the insulating film 26, the insulating film 27, the nitride insulating film 28, and the insulating film 29 are shown as single-layer insulating films.

[0049] As shown in Fig. 25, the distance between the end of the oxide semiconductor film 23 and the end of the conductive film 30 is defined as Tov, and the distance between the conductive film 21 and the conductive film 30 is defined as Tge. In one aspect of the present invention, it is preferable that Tov is 1.0 times or more of Tge because the current flowing between the conductive film 24 and the conductive film 25 can be controlled through the end of the oxide semiconductor film 23. Also, it is preferable that Tov is 7.5 times or less of Tge because the effect of controlling the above current can be obtained, and the size of the transistor 20 can be suppressed to be smaller.

[0050] Specifically, when a potential that causes the transistor 20 to be in the conducting state is applied to the conductive film 21 and the conductive film 30, the current flowing between the conductive film 24 and the conductive film 25 can be increased through the end. The current is related to the field-effect mobility and the increase in the on-current of the transistor 20 ​ In addition, the end portion of the oxide semiconductor film 23 overlaps with the conductive film 21 and the conductive film 30. As a result, in the oxide semiconductor film 23, carriers are transported to the insulating film 22 and the insulating film 26 and the oxide Since the oxide semiconductor film 23 flows not only at the interface with the semiconductor film 23 but also over a wide area of ​​the oxide semiconductor film 23, The amount of carrier movement in the transistor 20 increases. As a result, As the on-current increases, the field effect mobility also increases. Typically, the field effect mobility is 1 0cm 2 / V·s or more, even 20 cm 2 / V·s or more. Note that the electric field effect The actual mobility is not an approximation of the mobility as a physical property value of the oxide semiconductor film, but This is the field effect mobility in the saturation region.

[0051] In addition, the transistor 20 shown in FIG. 2 has an etched portion for forming the conductive film 24 and the conductive film 25. During the etching, an insulating film (protective insulating film) for protecting the surface of the oxide semiconductor film 23 is formed. Unlike the structure (channel protection structure) in which the protective insulating film is provided, It has a channel etch structure.

[0052] In the case of a transistor having a channel protection structure, the purpose is to protect the surface of the oxide semiconductor film 23. In order to achieve this object, the ends of the conductive film 24 and the ends of the conductive film 25 are respectively disposed on the protective insulating film. Therefore, the conductive film 24 and the conductive film 25 are formed by etching. The alignment of the mask used to fabricate the transistor with the channel protection structure is This requires higher precision than a transistor with a channel etch structure. In the case of a transistor having a protective structure, the ends of the conductive film 24 and the ends of the conductive film 25 are more securely In order to be positioned on the protective insulating film, it is desirable to shorten the distance between the end of the conductive film 24 and the end of the conductive film 2 5 in the channel length direction in order to suppress a decrease in yield. However, if the distance between the end of the conductive film 24 and the end of the conductive film 25 is shortened, the region where the conductive film 24 and the conductive film 25 overlap with the oxide semiconductor film 23 becomes wider, so that the electric field that should be applied to the oxide semiconductor film 23 from the conductive film 3 0 is likely to be shielded by the conductive film 24 and the conductive film 25. Note that the channel length direction corresponds to the direction in which carriers move between the conductive film 24 and the conductive film 25 at the shortest distance. On the other hand, in the case of the transistor 20 having a channel etch structure, higher accuracy is not required for the alignment of the mask used when forming the conductive film 24 and the conductive film 25 by etching. Therefore, in the transistor 20 having a channel etch structure, even if the distance between the end of the conductive film 24 and the end of the conductive film 25 is made longer than that of the transistor having a channel protection structure, a decrease in yield can be suppressed. Thus, since the region where the conductive film 24 and the conductive film 25 overlap with the oxide semiconductor film 23 can be narrowed, the electric field that should be applied to the oxide semiconductor film 23 from the conductive film 30 is less likely to be shielded by the conductive film 24 and the conductive film 25. Therefore, the transistor 20 having a channel etch structure is more likely to obtain a larger on-current than the transistor having a channel protection structure, and even if the channel length is shortened, the off-current flowing through the end of the oxide semiconductor film 23 can be suppressed to be small.

[0053] Also, the protective insulating film is exposed to plasma during the etching when forming the conductive film 24 and the conductive film 25. When forming the conductive film 24 and the conductive film 25 by etching, the alignment of the mask used is not required to have higher accuracy than that of the transistor having a channel protection structure. Therefore, in the transistor 20 having a channel etch structure, even if the distance between the end of the conductive film 24 and the end of the conductive film 25 is made longer than that of the transistor having a channel protection structure, a decrease in yield can be suppressed. Thus, since the region where the conductive film 24 and the conductive film 25 overlap with the oxide semiconductor film 23 can be narrowed, the electric field that should be applied to the oxide semiconductor film 23 from the conductive film 30 is less likely to be shielded by the conductive film 24 and the conductive film 25. Therefore, the transistor 20 having a channel etch structure is more likely to obtain a larger on-current than the transistor having a channel protection structure, and even if the channel length is shortened, the off-current flowing through the end of the oxide semiconductor film 23 can be suppressed to be small. Also, the protective insulating film is exposed to plasma during the etching when forming the conductive film 24 and the conductive film 25. Moreover, the protective insulating film is exposed to plasma during the etching when forming the conductive film 24 and the conductive film 25.

[0054] In addition, the protective insulating film is exposed to plasma during the etching when forming the conductive film 24 and the conductive film 25. ​​​​​​Since it is exposed, it is considered that oxygen is likely to desorb and oxygen deficiency is likely to be formed. . Therefore, it can be said that the protective insulating film has poor ability to supply an amount of oxygen sufficient to reduce the oxygen deficiency in the oxide semiconductor film 23 in contact with the protective insulating film. On the other hand, in the transistor 20 with a channel etch structure, among the oxide semiconductor films 23, the portion that does not overlap with the conductive films 24 and 25 is exposed to plasma by the etching when forming the conductive films 24 and 25. However, after forming the conductive films 24 and 25, by forming the insulating films 26 and 27 having the ability to supply a sufficient amount of oxygen to the oxide semiconductor film 23, the oxygen deficiency in the oxide semiconductor film 23 can be reduced. Therefore, the transistor 20 with a channel etch structure can obtain higher reliability than the transistor with a channel protection structure. 3. Among the oxide semiconductor films 23, the portion that does not overlap with the conductive films 24 and 25 is exposed to plasma by the etching when forming the conductive films 24 and 25. However, after forming the conductive films 24 and 25, by forming the insulating films 26 and 27 having the ability to supply a sufficient amount of oxygen to the oxide semiconductor film 23, the oxygen deficiency in the oxide semiconductor film 23 can be reduced. Therefore, the transistor 20 with a channel etch structure can obtain higher reliability than the transistor with a channel protection structure. However, after forming the conductive films 24 and 25, by forming the insulating films 26 and 27 having the ability to supply a sufficient amount of oxygen to the oxide semiconductor film 23, the oxygen deficiency in the oxide semiconductor film 23 can be reduced. Therefore, the transistor 20 with a channel etch structure can obtain higher reliability than the transistor with a channel protection structure. However, after forming the conductive films 24 and 25, by forming the insulating films 26 and 27 having the ability to supply a sufficient amount of oxygen to the oxide semiconductor film 23, the oxygen deficiency in the oxide semiconductor film 23 can be reduced. Therefore, the transistor 20 with a channel etch structure can obtain higher reliability than the transistor with a channel protection structure. However, after forming the conductive films 24 and 25, by forming the insulating films 26 and 27 having the ability to supply a sufficient amount of oxygen to the oxide semiconductor film 23, the oxygen deficiency in the oxide semiconductor film 23 can be reduced. Therefore, the transistor 20 with a channel etch structure can obtain higher reliability than the transistor with a channel protection structure. However, after forming the conductive films 24 and 25, by forming the insulating films 26 and 27 having the ability to supply a sufficient amount of oxygen to the oxide semiconductor film 23, the oxygen deficiency in the oxide semiconductor film 23 can be reduced. Therefore, the transistor 20 with a channel etch structure can obtain higher reliability than the transistor with a channel protection structure. However, after forming the conductive films 24 and 25, by forming the insulating films 26 and 27 having the ability to supply a sufficient amount of oxygen to the oxide semiconductor film 23, the oxygen deficiency in the oxide semiconductor film 23 can be reduced. Therefore, the transistor 20 with a channel etch structure can obtain higher reliability than the transistor with a channel protection structure.

[0055] -OS (C Axis Aligned Crystalline Oxide Semiconductor) film is used, compared with the case where an amorphous oxide semiconductor film or a microcrystalline oxide semiconductor film is used for the oxide semiconductor film 23, the region of the oxide semiconductor film 23 that does not overlap with the conductive films 24 and 25 is difficult to be removed by the etching when forming the conductive films 24 and 25. Therefore, the transistor 20 using the CAAC-OS film for the oxide semiconductor film 23 can obtain higher reliability. Details of the CAAC-OS film, the amorphous oxide semiconductor film, and the microcrystalline oxide semiconductor film will be described later. -OS (C Axis Aligned Crystalline Oxide Semiconductor) film is used, compared with the case where an amorphous oxide semiconductor film or a microcrystalline oxide semiconductor film is used for the oxide semiconductor film 23, the region of the oxide semiconductor film 23 that does not overlap with the conductive films 24 and 25 is difficult to be removed by the etching when forming the conductive films 24 and 25. Therefore, the transistor 20 using the CAAC-OS film for the oxide semiconductor film 23 can obtain higher reliability. Details of the CAAC-OS film, the amorphous oxide semiconductor film, and the microcrystalline oxide semiconductor film will be described later. -OS (C Axis Aligned Crystalline Oxide Semiconductor) film is used, compared with the case where an amorphous oxide semiconductor film or a microcrystalline oxide semiconductor film is used for the oxide semiconductor film 23, the region of the oxide semiconductor film 23 that does not overlap with the conductive films 24 and 25 is difficult to be removed by the etching when forming the conductive films 24 and 25. Therefore, the transistor 20 using the CAAC-OS film for the oxide semiconductor film 23 can obtain higher reliability. Details of the CAAC-OS film, the amorphous oxide semiconductor film, and the microcrystalline oxide semiconductor film will be described later. -OS (C Axis Aligned Crystalline Oxide Semiconductor) film is used, compared with the case where an amorphous oxide semiconductor film or a microcrystalline oxide semiconductor film is used for the oxide semiconductor film 23, the region of the oxide semiconductor film 23 that does not overlap with the conductive films 24 and 25 is difficult to be removed by the etching when forming the conductive films 24 and 25. Therefore, the transistor 20 using the CAAC-OS film for the oxide semiconductor film 23 can obtain higher reliability. Details of the CAAC-OS film, the amorphous oxide semiconductor film, and the microcrystalline oxide semiconductor film will be described later. -OS (C Axis Aligned Crystalline Oxide Semiconductor) film is used, compared with the case where an amorphous oxide semiconductor film or a microcrystalline oxide semiconductor film is used for the oxide semiconductor film 23, the region of the oxide semiconductor film 23 that does not overlap with the conductive films 24 and 25 is difficult to be removed by the etching when forming the conductive films 24 and 25. Therefore, the transistor 20 using the CAAC-OS film for the oxide semiconductor film 23 can obtain higher reliability. Details of the CAAC-OS film, the amorphous oxide semiconductor film, and the microcrystalline oxide semiconductor film will be described later. -OS (C Axis Aligned Crystalline Oxide Semiconductor) film is used, compared with the case where an amorphous oxide semiconductor film or a microcrystalline oxide semiconductor film is used for the oxide semiconductor film 23, the region of the oxide semiconductor film 23 that does not overlap with the conductive films 24 and 25 is difficult to be removed by the etching when forming the conductive films 24 and 25. Therefore, the transistor 20 using the CAAC-OS film for the oxide semiconductor film 23 can obtain higher reliability. Details of the CAAC-OS film, the amorphous oxide semiconductor film, and the microcrystalline oxide semiconductor film will be described later. -OS (C Axis Aligned Crystalline Oxide Semiconductor) film is used, compared with the case where an amorphous oxide semiconductor film or a microcrystalline oxide semiconductor film is used for the oxide semiconductor film 23, the region of the oxide semiconductor film 23 that does not overlap with the conductive films 24 and 25 is difficult to be removed by the etching when forming the conductive films 24 and 25. Therefore, the transistor 20 using the CAAC-OS film for the oxide semiconductor film 23 can obtain higher reliability. Details of the CAAC-OS film, the amorphous oxide semiconductor film, and the microcrystalline oxide semiconductor film will be described later.

[0056] Note that a transistor having an oxide semiconductor film is an accumulation-type transistor. Here, Regarding the flow of carriers in the off state and on state of a transistor having an oxide semiconductor film, it will be described with reference to the schematic diagrams shown in FIG. 36. FIGS. 36(A) and 36(B) are cross-sectional views in the channel length direction, and FIG. 36(C) is a cross-sectional view in the channel width direction.

[0057] In FIG. 36, a transistor having an oxide semiconductor film includes a gate electrode GE_1, a gate insulating film GI_1 on the gate electrode GE_1, an oxide semiconductor film OS on the gate insulating film GI_1, electrodes S and D on the oxide semiconductor film OS, and a gate insulating film GI_2 on the oxide semiconductor film OS and the electrodes S and D, and a gate electrode GE_2 on the gate insulating film GI_2. The oxide semiconductor film OS has a channel region i and a low-resistance region n + in contact with the electrodes S and D. The gate electrode GE_1 and the gate electrode GE_2 are connected as shown in FIG. 36(C).

[0058] When the transistor is in the off state, as shown in FIG. 36(A), when a negative voltage is applied to the gate electrodes GE_1 and GE _2, electrons are repelled from the channel region i of the oxide semiconductor film OS, and the channel region i is completely depleted. As a result, the off-current of the transistor becomes extremely small.

[0059] On the other hand, in the on state, as shown in FIG. 36(B), electrons are accumulated from the low-resistance region n + in contact with the electrode S to the low-resistance region n + in contact with the electrode D, and a current path is formed as indicated by the arrow. As shown in FIG. 36(C), the gate electrodes GE_1 and GE_2 are the same. As a potential, and since the side surface of the oxide semiconductor film OS faces the gate electrode GE_2, further more, in the channel width direction, the gate electrodes GE_1 and GE_2 surround the oxide semiconductor film OS via the gate insulating films GI_1 and GI_2. As shown in FIG. 36(B), carriers flow not only at the interfaces between the gate insulating films GI_ 1, GI_2 and the oxide semiconductor film OS, but also in a wide range within the oxide semiconductor film OS. As a result, the amount of carrier movement in the transistor increases. As a result, the on-current of the transistor increases, and the field-effect mobility increases. Typically, the field-effect mobility is 10 cm / V·s or more, and further 20 cm / V·s or more. Note that 2 here, the field-effect mobility is not an approximate value of the mobility as a physical property value of the oxide semiconductor film, but 2 is the field-effect mobility in the saturation region of the transistor. Note that the channel length L of the transistor is 0.5 μm or more and 6.5 μm or less, preferably greater than 1 μm and less than 6 μm, more preferably greater than 1 μm and 4 μm or less, more preferably greater than 1 μm and 3.5 μm or less, and even more preferably greater than 1 μm and 2.5 μm or less. By setting it in this way, the increase in the field-effect mobility is remarkable. Also, since the channel length is as small as 0.5 μm or more and 6.5 μm or less, it is possible to make the channel width small as well. Therefore, as shown in FIG. 36(C), even if a region for forming the connection part of the gate electrodes GE_1 and GE_2 is provided, it is possible to reduce the area of the transistor. Next, the specific structure of the transistor 20 having a pair of electrically connected gate electrodes is as follows. Since it becomes the connection part of the gate electrodes GE_1 and GE_2, it is possible to reduce the area of the transistor.

[0060] Next, the specific structure of the transistor 20 having a pair of electrically connected gate electrodes A conventional example is shown in FIG. 19. FIG. 19(A) shows a top view of the transistor 20. Note that in FIG. 19(A), in order to clarify the layout of the transistor 20, various insulating films such as the gate insulating film other than the insulating film 26 and the insulating film 27 are omitted. Also, FIG. 19(B) shows a cross-sectional view taken along the broken line A1 - A2 of the top view shown in FIG. 19(A), and FIG. 19(C) shows a cross-sectional view taken along the broken line A3 - A4.

[0061] The transistor 20 shown in FIG. 19 has a different structure from the transistor 20 shown in FIG. 2 in that the insulating film 26 and the insulating film 27 are partially removed around the transistor 20. Specifically, in FIG. 19, among the ends of the oxide semiconductor film 23, the ends that do not overlap with the conductive film 24 and the conductive film 25 are at least covered by the insulating film 26 and the insulating film 27, so that the insulating film 26 and the insulating film 27 are partially removed. In the transistor 20 shown in FIG. 19, with the above configuration, the conductive film 30 that functions as a gate can be brought closer to the end of the oxide semiconductor film 23 at the ends of the insulating film 26 and the insulating film 27. As described above, the ends of the oxide semiconductor film 23 are likely to be n-type, but by bringing the conductive film 30 closer to the above ends of the oxide semiconductor film 23, the electric field applied from the conductive film 30 to the ends can be made stronger. Therefore, the current flowing between the conductive film 24 and the conductive film 25 through the ends of the oxide semiconductor film 23 can be more reliably controlled by the potential applied to the conductive film 30. As a result, even if the channel length of the transistor 20 is shortened, the off-current of the transistor 20 can be more effectively suppressed, and at the same time, a larger on-current can be ensured.

[0062] ​​​​​​​​​​​​​​In the transistor 20 shown in FIGS. 2 and 19, in the channel length direction, the end of the conductive film 30 is provided at a position overlapping with the oxide semiconductor film 23, but the end of the oxide semiconductor film 23 may be provided at a position overlapping with the conductive film 30.

[0063] In addition, a specific configuration example of the transistor 20 having a pair of electrically connected gate electrodes is shown in FIG. 20. FIG. 20(A) shows a top view of the transistor 20. Note that in FIG. 20 (A), various insulating films such as a gate insulating film are omitted in order to clarify the layout of the transistor 20. Also, a cross-sectional view taken along the broken line A1 - A2 of the top view shown in FIG. 20(A) is shown in FIG. 20(B), and a cross-sectional view taken along the broken line A3 - A4 is shown in FIG. 20(C). (A), various insulating films such as a gate insulating film are omitted in order to clarify the layout of the transistor 20. Also, a cross-sectional view taken along the broken line A1 - A2 of the top view shown in FIG. 20(A) is shown in FIG. 20(B), and a cross-sectional view taken along the broken line A3 - A4 is shown in FIG. 20(C). In the transistor 20 shown in FIG. 20, in the region where the oxide semiconductor film 23 is located, the conductive film 3 0 does not overlap with the conductive film 24 and the conductive film 25. In other words, in the region where the oxide semiconductor film 23 is located, the structure is different from that of the transistor 20 shown in FIG. 2 in that the conductive film 30 is located in a region different from the region where the conductive film 24 and the conductive film 25 are located.

[0064] In the transistor 20 shown in FIG. 20, in the region where the oxide semiconductor film 23 is located, the conductive film 3 0 does not overlap with the conductive film 24 and the conductive film 25. In other words, in the region where the oxide semiconductor film 23 is located, the structure is different from that of the transistor 20 shown in FIG. 2 in that the conductive film 30 is located in a region different from the region where the conductive film 24 and the conductive film 25 are located. film 23 is located, the structure is different from that of the transistor 20 shown in FIG. 2 in that the conductive film 30 is located in a region different from the region where the conductive film 24 and the conductive film 25 are located.

[0065] In addition, a specific configuration example of the transistor 20 having a pair of electrically connected gate electrodes is shown in FIG. 21. FIG. 21(A) shows a top view of the transistor 20. Note that in FIG. 21 (A), various insulating films such as a gate insulating film are omitted in order to clarify the layout of the transistor 20. Also, a cross-sectional view taken along the broken line A1 - A2 of the top view shown in FIG. 21(A) is shown in FIG. 21(B), and a cross-sectional view taken along the broken line A3 - A4 is shown in FIG. 21(C). (A), various insulating films such as a gate insulating film are omitted in order to clarify the layout of the transistor 20. Also, a cross-sectional view taken along the broken line A1 - A2 of the top view shown in FIG. 21(A) is shown in FIG. 21(B), and a cross-sectional view taken along the broken line A3 - A4 is shown in FIG. 21(C). In the transistor 20 shown in FIG. 21, in the region where the oxide semiconductor film 23 is located, the conductive film 3 0 does not overlap with the conductive film 24 and the conductive film 25. In other words, in the region where the oxide semiconductor film 23 is located, the structure is different from that of the transistor 20 shown in FIG. 2 in that the conductive film 30 is located in a region different from the region where the conductive film 24 and the conductive film 25 are located.

[0066] In the region where the oxide semiconductor film 23 is located, the transistor 20 shown in FIG. 21 has a conductive film 3 0 overlapping the conductive film 24 and not overlapping the conductive film 25, and has a different structure from the transistor 20 shown in FIG. 2. In other words, in the region where the oxide semiconductor film 23 is located, a part of the region where the conductive film 24 is located has the conductive film 30 located therein, and further, in the region where the oxide semiconductor film 23 is located, the conductive film 30 is located in a region different from the region where the conductive film 25 is located, and thus has a different structure from the transistor 20 shown in FIG. 2.

[0067] In addition, a specific configuration example of the transistor 20 having a pair of electrically connected gate electrodes is shown in FIG. 24. FIG. 24(A) shows a top view of the transistor 20. Note that in FIG. 24 (A), various insulating films such as a gate insulating film are omitted in order to clarify the layout of the transistor 20. Further, a cross-sectional view taken along the broken line A1 - A2 of the top view shown in FIG. 24(A) is shown in FIG. 24(B), and a cross-sectional view taken along the broken line A3 - A4 is shown in FIG. 24(C). (A), various insulating films such as a gate insulating film are omitted in order to clarify the layout of the transistor 20. Further, a cross-sectional view taken along the broken line A1 - A2 of the top view shown in FIG. 24(A) is shown in FIG. 24(B), and a cross-sectional view taken along the broken line A3 - A4 is shown in FIG. 24(C). In addition, a cross-sectional view taken along the broken line A1 - A2 of the top view shown in FIG. 24(A) is shown in FIG. 24(B), and a cross-sectional view taken along the broken line A3 - A4 is shown in FIG. 24(C). The transistor 20 shown in FIG. 24 has a different structure from the transistor 20 shown in FIG. 2 in that the conductive film 21 and the conductive film 30 are electrically connected via the conductive film 34. Specifically,

[0068] the conductive film 34 is formed on the insulating film 22 and is in contact with the conductive film 21 at the opening 32a formed in the insulating film 22. Further, the conductive film 30 is in contact with the conductive film 34 at the opening 32b formed in the insulating films 26 to 29. The transistor 20 shown in FIG. 24 has a different structure from the transistor 20 shown in FIG. 2 in that the conductive film 21 and the conductive film 30 are electrically connected via the conductive film 34. Specifically, the conductive film 34 is formed on the insulating film 22 and is in contact with the conductive film 21 at the opening 32a formed in the insulating film 22. Further, the conductive film 30 is in contact with the conductive film 34 at the opening 32b formed in the insulating films 26 to 29. the conductive film 34 is formed on the insulating film 22 and is in contact with the conductive film 21 at the opening 32a formed in the insulating film 22. Further, the conductive film 30 is in contact with the conductive film 34 at the opening 32b formed in the insulating films 26 to 29.

[0069] The transistor 20 shown in FIGS. 20, 21, and 24 is also the same as the transistor shown in FIG. 19 ​​​Similarly, the insulating film 26 and the insulating film 27 may be partially removed.

[0070] In addition, in the transistor 20 illustrated in FIGS. 2, 19, 20, and 21, an oxide semiconductor film 23 is not necessarily composed of a single oxide semiconductor film, but is composed of a stack of multiple oxide semiconductors. In FIG. 23A, the oxide semiconductor film 23 is a three-layer stack. 23A shows an example in which the insulating film is formed of an oxide semiconductor film having a thickness of 100 nm to 150 nm. In the transistor 20 shown in FIG. 1, the oxide semiconductor film 23 includes oxide semiconductor films 23a to 23b. The compound semiconductor film 23c is laminated in order from the insulating film 22 side.

[0071] The oxide semiconductor film 23a and the oxide semiconductor film 23c constitute the oxide semiconductor film 23b. The element contains at least one metal element that forms an oxide. The energy of the conduction band minimum is The difference is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.05 eV or more, more preferably 0.07 eV or more, more preferably 0.1 eV or more, more preferably ... .15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, true The oxide semiconductor film 23b is an oxide film close to a vacant level. It is preferable for the compound to contain the compound to have a high carrier mobility.

[0072] Note that the oxide semiconductor film 23c is formed by arranging the conductive film 24 and the conductive film 25 as shown in FIG. It may be configured so as to overlap the insulating film 22 at the upper layer.

[0073] Next, a transistor having a pair of gate electrodes overlapping with a semiconductor film sandwiched therebetween is The circuit symbol is shown in FIG. 22(A). In the circuit symbol shown in FIG. 22(A), a pair of gate electrodes are F The gate electrodes are indicated by G and BG, the source electrode is indicated by S, and the drain electrode is indicated by D. In the circuit symbol, there is no limitation on the positional relationship between the conductive film 30 that functions as a gate electrode and the conductive films 24 and 25 that function as a source electrode or a drain electrode.

[0074] Fig. 22(B1) shows the circuit symbol of the transistor 20 in which the conductive films 24 and 25 that function as a source electrode or a drain electrode partially overlap with the conductive film 30 that functions as a gate electrode on the oxide semiconductor film 23. The circuit symbol shown in Fig. 22(B1) shows, similar to the circuit symbol shown in Fig. 22(A), a pair of gate electrodes as FG and BG, and a source electrode as S and a drain electrode as D.

[0075] Fig. 22(B2) shows a cross-sectional view of the transistor 20 corresponding to the circuit symbol shown in Fig. 22(B1) as an example. In the transistor 20 shown in Fig. 22(B2), in the channel length direction, the distance Wsd between the end of the conductive film 24 and the end of the conductive film 25 is shorter than the distance Wbg between the ends of the conductive film 30. And in the cross-sectional view in the channel length direction, a pair of ends of the conductive film 30 overlap with the conductive films 24 and 25.

[0076] Also, Fig. 22(C1) shows the circuit symbol of the transistor 20 in which the conductive films 24 and 25 that function as a source electrode or a drain electrode do not overlap with the conductive film 30 that functions as a gate electrode on the oxide semiconductor film 23. The circuit symbol shown in Fig. 22(C1) shows, similar to the circuit symbol shown in Fig. 22(A), a pair of gate electrodes as FG and BG, and a source electrode as S and a drain electrode as D.

[0077] Fig. 22(C2) shows a cross-sectional view of the transistor 20 corresponding to the circuit symbol shown in Fig. 22(C1). A figure is shown as an example. The transistor 20 shown in Fig. 22(C2) has, in the channel length direction, a distance Wsd between the end of the conductive film 24 and the end of the conductive film 25 that is longer than the distance W bg between the ends of the conductive film 30. And in a cross-sectional view in the channel length direction, a pair of ends of the conductive film 30 do not overlap with the conductive film 24 and the conductive film 25.

[0078] In the drawings attached to this specification, the circuit symbol shown in Fig. 22(A) includes the transistor 20 having the structure represented by the circuit symbol in Fig. 22(B1) and the transistor 20 having the structure represented by the circuit symbol in Fig. 22(C1).

[0079] <Measurement of Electrical Characteristics of Transistor> Next, the results of measuring the electrical characteristics of a transistor having a channel formation region in an oxide semiconductor film when irradiated with light are described.

[0080] First, the structure of the transistor used for the measurement is described. For the measurement, a first transistor having one gate electrode and a second transistor having a pair of gate electrodes that overlap with each other with a semiconductor film interposed therebetween were used.

[0081] The first transistor had a gate electrode using a tungsten film with a thickness of 200 nm on an insulating surface, and on the gate electrode, a gate insulating film in which a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm were laminated in this order. Further, the first transistor had an In-Ga-Zn oxide semiconductor film with a thickness of 35 nm at a position overlapping the gate electrode on the gate insulating film. Also, the first transistor had, on the oxide semiconductor film, a film thickness A tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and an aluminum film with a thickness of 200 nm The source electrode and the drain electrode were laminated in this order with a titanium film of 1000 nm. A silicon oxynitride film having a thickness of 50 nm is formed on the semiconductor film and the source and drain electrodes. A silicon oxynitride film having a thickness of 400 nm and a silicon nitride film having a thickness of 100 nm are laminated in this order. It was set up so that

[0082] The second transistor is a 100 nm thick indium oxide doped silicon nitride film. The second transistor has the same structure as the first transistor only in that it further has a gate electrode using a silicon tin oxide film. The second transistor had a gate electrode made of tungsten. The gate electrode made of an indium tin oxide film containing silicon oxide is electrically connected to the It was being done.

[0083] In the first and second transistors, an In-Ga-Zn oxide semiconductor is used. The film was made by using a target with a composition (atomic ratio) of In, Ga, and Zn of 1:1:1. The first transistor and the second transistor are formed by a sputtering method. The silicon oxynitride film with a thickness of 50 nm was formed by silane with a flow rate of 20 sccm and 3000 s. The source gas was nitrous oxide (N2O) at 1.0 ccm, the pressure in the processing chamber was 200 Pa, and the substrate temperature was 350° C. A 27.12MHz high-frequency power source was used to generate 150W (power density 2.5×10 -2 W / cm 2 The film was formed by plasma CVD, in which high-frequency power of 1000 Hz was supplied to parallel plate electrodes. In the first and second transistors, a silicon oxynitride film having a thickness of 400 nm is used. The plain film was formed by plasma CVD using silane with a flow rate of 160 sccm and nitrous oxide with a flow rate of 4000 sccm as source gases, setting the pressure in the processing chamber at 200 Pa, the substrate temperature at 220 °C, and applying 1500 W (power density: 2.5×10 W / cm ) of high-frequency power to a parallel-plate electrode using a 27.12 MHz high-frequency power supply. Also, in the first transistor and the second transistor, the silicon nitride film with a thickness of 100 nm was formed by plasma CVD using silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm as source gases, setting the pressure in the processing chamber at 100 Pa, the substrate temperature at 350 °C, and applying 1000 W (power density: 1.6×10 -1 W / cm 2 ) of high-frequency power to a parallel-plate electrode using a 27.12 MHz high-frequency power supply. Moreover, the first transistor and the second transistor had a channel length L of 6 μm and a channel width W of 50 μm. And the measurement of the electrical characteristics of the first transistor and the second transistor was performed in the order of measuring the drain current before the stress application process (Measurement 1) and measuring the drain current after the stress application process (Measurement 2). In the stress application process, the substrate temperature was maintained at 60 °C and the gate voltage Vg was maintained at -30 V for 1 hour in an environment where no light was irradiated in a dark room. Specifically, the measurement of the drain current in Measurement 1 and Measurement 2 was performed at a substrate temperature of 60 °C in an environment where no light was irradiated in a dark room. Also, during the measurement, the gate voltage Vg was changed by 0.25 V between -1 5 V and 30 V, and the voltage between the source electrode and the drain electrode was set to 0.1 V. -1 W / cm 2 ) of high-frequency power to a parallel-plate electrode using a 27.12 MHz high-frequency power supply. was set to 0.1 V.

[0084] Moreover, the first transistor and the second transistor had a channel length L of 6 μm and a channel width W of 50 μm. was 50 μm.

[0085] And the measurement of the electrical characteristics of the first transistor and the second transistor was performed in the order of measuring the drain current before the stress application process (Measurement 1) and measuring the drain current after the stress application process (Measurement 2). In the stress application process, the substrate temperature was maintained at 60 °C and the gate voltage Vg was maintained at -30 V for 1 hour in an environment where no light was irradiated in a dark room. Specifically, the measurement of the drain current in Measurement 1 and Measurement 2 was performed at a substrate temperature of 60 °C in an environment where no light was irradiated in a dark room. Also, during the measurement, the gate voltage Vg was changed by 0.25 V between -1 5 V and 30 V, and the voltage between the source electrode and the drain electrode was maintained at 60 °C and the gate voltage Vg was maintained at -30 V for 1 hour in an environment where no light was irradiated in a dark room. Specifically, the measurement of the drain current in Measurement 1 and Measurement 2 was performed at a substrate temperature of 60 °C in an environment where no light was irradiated in a dark room. Also, during the measurement, the gate voltage Vg was changed by 0.25 V between -1 5 V and 30 V, and the voltage between the source electrode and the drain electrode was maintained at 60 °C and the gate voltage Vg was maintained at -30 V for 1 hour in an environment where no light was irradiated in a dark room. Specifically, the measurement of the drain current in Measurement 1 and Measurement 2 was performed at a substrate temperature of 60 °C in an environment where no light was irradiated in a dark room. Also, during the measurement, the gate voltage Vg was changed by 0.25 V between -1 5 V and 30 V, and the voltage between the source electrode and the drain electrode Vds was set to 0.1 V or 10 V.

[0086] Figure 17(A) shows the relationship between the gate voltage Vg and the drain current Id of the first transistor obtained by measurement. Further, when the voltage Vds is 10 V, the field-effect mobility μFE obtained by calculation is also shown. In addition, Figure 17(B) shows the relationship between the gate voltage Vg and the drain current Id of the second transistor obtained by measurement. Further, when the voltage Vds is 10 V, the field-effect mobility μFE obtained by calculation is also shown. From Figures 17(A) and 17(B), it was found that the second transistor has a larger drain current Id and field-effect mobility μFE than the first transistor. Furthermore, when the voltage Vds is 10 V, the field-effect mobility μFE obtained by calculation is also shown. In addition, Figure 17(B) shows the relationship between the gate voltage Vg and the drain current Id of the second transistor obtained by measurement. Furthermore, when the voltage Vds is 10 V, the field-effect mobility μFE obtained by calculation is also shown. From Figures 17(A) and 17(B), it was found that the second transistor has a larger drain current Id and field-effect mobility μFE than the first transistor. And Table 1 below shows the threshold voltage (Vth) and the shift value (Shift) of the first transistor (Single Gate) and the second transistor (Dual Gate) obtained by measurement. Note that the shift value is defined as the value of the gate voltage when the drain current rises. Specifically, in a semi-logarithmic graph showing the relationship between the logarithmic scale of the drain current and the linear scale of the gate voltage, it is defined as the voltage at the intersection of the tangent line where the change in the slope of the drain current is the steepest and the scale line corresponding to a drain current of 1e-12 [A]. The shift value used was the value when the voltage Vds was 10 V. As shown in Table 1, in the first transistor, due to the stress application process, the threshold voltage is -4.

[0087] And Table 1 below shows the threshold voltage (Vth) and the shift value (Shift) of the first transistor (Single Gate) and the second transistor (Dual Gate) obtained by measurement. Note that the shift value is defined as the value of the gate voltage when the drain current rises. Specifically, in a semi-logarithmic graph showing the relationship between the logarithmic scale of the drain current and the linear scale of the gate voltage, it is defined as the voltage at the intersection of the tangent line where the change in the slope of the drain current is the steepest and the scale line corresponding to a drain current of 1e-12 [A]. The shift value used was the value when the voltage Vds was 10 V. And Table 1 below shows the threshold voltage (Vth) and the shift value (Shift) of the first transistor (Single Gate) and the second transistor (Dual Gate) obtained by measurement. Note that the shift value is defined as the value of the gate voltage when the drain current rises. Specifically, in a semi-logarithmic graph showing the relationship between the logarithmic scale of the drain current and the linear scale of the gate voltage, it is defined as the voltage at the intersection of the tangent line where the change in the slope of the drain current is the steepest and the scale line corresponding to a drain current of 1e-12 [A]. The shift value used was the value when the voltage Vds was 10 V. Shift) of the first transistor (Single Gate) and the second transistor (Dual Gate) obtained by measurement. Note that the shift value is defined as the value of the gate voltage when the drain current rises. Specifically, in a semi-logarithmic graph showing the relationship between the logarithmic scale of the drain current and the linear scale of the gate voltage, it is defined as the voltage at the intersection of the tangent line where the change in the slope of the drain current is the steepest and the scale line corresponding to a drain current of 1e-12 [A]. The shift value used was the value when the voltage Vds was 10 V. As shown in Table 1, in the first transistor, due to the stress application process, the threshold voltage is -4. And Table 1 below shows the threshold voltage (Vth) and the shift value (Shift) of the first transistor (Single Gate) and the second transistor (Dual Gate) obtained by measurement. Note that the shift value is defined as the value of the gate voltage when the drain current rises. Specifically, in a semi-logarithmic graph showing the relationship between the logarithmic scale of the drain current and the linear scale of the gate voltage, it is defined as the voltage at the intersection of the tangent line where the change in the slope of the drain current is the steepest and the scale line corresponding to a drain current of 1e-12 [A]. The shift value used was the value when the voltage Vds was 10 V.

[0088]

Table 1

[0089] As shown in Table 1, in the first transistor, due to the stress application process, the threshold voltage is -4. It was found that the shift value of the 48V was -6.80V. Also, in the second transistor due to the stress application process, the threshold voltage was 0.27V and the shift value was 0.25V shifted. Therefore, it was found that the negative shift of the threshold voltage and the shift value of the second transistor were suppressed more than those of the first transistor.

[0090] Therefore, from the above measurement, it was found that by providing a pair of gate electrodes positioned with a semiconductor film interposed therebetween, the negative shift of the threshold voltage of the transistor can be suppressed. Also, by applying the same potential to the pair of gate electrodes, it was found that an increase in the drain current can be realized.

[0091] 〈Comparison of Channel Etch-Type Transistors and Channel Protection-Type Transistors in Dual Gate Drive〉 Here, the field-effect mobility and on-current of the channel etch-type transistor and the channel protection-type transistor are compared. Here, the field-effect mobility (μ ), and the on-current (Ion) of the dual gate drive transistor in which the gate electrodes facing each other with an oxide semiconductor film interposed therebetween are connected and have the same potential are compared. FE

[0092] The electrical characteristics of the channel etch-type transistor and the channel protection-type transistor were calculated. FIG. 29(A) shows the structure of the channel protection-type transistor used in the calculation. Note that device simulation software Atlas (manufactured by Silvaco) was used for the calculation.

[0093] For the channel protection-type transistor, a gate insulating film GI_1 is formed on the gate electrode GE_1 Then, an oxide semiconductor film OS is formed over the gate insulating film GI_1. The gate insulating film GI_ 1 and the oxide semiconductor film OS are provided with a source electrode S and a drain electrode D formed thereon. Note that a channel protection film CS is formed between the ends of the source electrode S and the drain electrode D and the oxide semiconductor film OS. A gate insulating film GI_2 is formed over the oxide semiconductor film OS, the source electrode S, the drain electrode D, and the channel protection film CS. A gate electrode GE_2 is formed over the gate insulating film GI_2. The gate electrodes GE_1 and GE_2 are connected to each other through openings (not shown) formed in the gate insulating film GI_1 and the gate insulating film GI_2. protection film CS. A gate insulating film GI_2 is formed over the oxide semiconductor film OS, the source electrode S, the drain electrode D, and the channel protection film CS. A gate electrode GE_2 is formed over the gate insulating film GI_2. The gate electrodes GE_1 and GE_2 are connected to each other through openings (not shown) formed in the gate insulating film GI_1 and the gate insulating film GI_2. protection film CS. A gate insulating film GI_2 is formed over the oxide semiconductor film OS, the source electrode S, the drain electrode D, and the channel protection film CS. A gate electrode GE_2 is formed over the gate insulating film GI_2. The gate electrodes GE_1 and GE_2 are connected to each other through openings (not shown) formed in the gate insulating film GI_1 and the gate insulating film GI_2.

[0094] In a channel etch type transistor, the channel protection film CS is not provided, and the ends of the source electrode S and the drain electrode D are in contact with the oxide semiconductor film OS. In a channel etch type transistor, the channel protection film CS is not provided, and the ends of the source electrode S and the drain electrode D are in contact with the oxide semiconductor film OS.

[0095] The conditions used in the calculation are shown in Table 2.

[0096] [Table 2]

[0097] FIG. 29(A) shows a transistor with dual gate driving. As a comparative example, calculations similar to those for the transistor with dual gate driving were also performed for a transistor with single gate driving that does not have the gate electrode GE_2. FIG. 29(A) shows a transistor with dual gate driving. As a comparative example, calculations similar to those for the transistor with dual gate driving were also performed for a transistor with single gate driving that does not have the gate electrode GE_2. FIG. 29(A) shows a transistor with dual gate driving. As a comparative example, calculations similar to those for the transistor with dual gate driving were also performed for a transistor with single gate driving that does not have the gate electrode GE_2.

[0098] In the channel protection type transistor, the length of the region where the oxide semiconductor film OS and the source electrode S or the drain electrode D overlap with each other through the channel protection film CS is defined as Sov. Also, In the channel protection type transistor, the length of the region where the oxide semiconductor film OS and the source electrode S or the drain electrode D overlap with each other through the channel protection film CS is defined as Sov. Also, , in the source electrode S and the drain electrode D, a region overlapping with the oxide semiconductor film OS through the channel protective film CS is defined as the Sov region. The relationship between Sov and the field-effect mobility was calculated, and the results are shown in Fig. 29(B). The relationship between Sov and the on-current was calculated, and the results are shown in Fig. 29(C). Also, in the case of a channel-etched transistor, with Sov set to 0 μm, the field-effect mobility and the on-current were calculated. The calculation results are shown in Fig. 29(B) and Fig. 29(C) respectively. Fig. 29(B) shows the results when the drain voltage Vd is 1V. Fig. 29(C) shows the results when the drain voltage Vd is 1V and the gate voltage Vg is 10V. As shown in Fig. 29(B), in the channel-etched transistor (Sov = 0 μm), the field-effect mobility of the Dual Gate-driven transistor is approximately twice that of the Single Gate-driven transistor. On the other hand, in the channel-protected transistor, the field-effect mobility of the Dual Gate-driven transistor decreases as the length of Sov increases.

[0099] Also, as shown in Fig. 29(C), in the channel-etched transistor (Sov = 0 μm), the on-current of the Dual Gate-driven transistor is approximately twice that of the Single Gate-driven transistor. On the other hand, in the channel-protected transistor, the on-current of the Dual Gate-driven transistor decreases as the length of Sov increases. Note that Fig. 29(B) shows the results when the drain voltage Vd is 1V. Fig. 29(C) shows the results when the drain voltage Vd is 1V and the gate voltage Vg is 10V. As shown in Fig. 29(B), in the channel-etched transistor (Sov = 0 μm), the field-effect mobility of the Dual Gate-driven transistor is approximately twice that of the Single Gate-driven transistor. On the other hand, in the channel-protected transistor, the field-effect mobility of the Dual Gate-driven transistor decreases as the length of Sov increases.

[0100] Note that Fig. 29(B) shows the results when the drain voltage Vd is 1V. Fig. 29(C) shows the results when the drain voltage Vd is 1V and the gate voltage Vg is 10V. As shown in Fig. 29(C), in the channel-etched transistor (Sov = 0 μm), the on-current of the Dual Gate-driven transistor is approximately twice that of the Single Gate-driven transistor. On the other hand, in the channel-protected transistor, the on-current of the Dual Gate-driven transistor decreases as the length of Sov increases.

[0101] As shown in Fig. 29(B), in the channel-etched transistor (Sov = 0 μm), the field-effect mobility of the Dual Gate-driven transistor is approximately twice that of the Single Gate-driven transistor. On the other hand, in the channel-protected transistor, the field-effect mobility of the Dual Gate-driven transistor decreases as the length of Sov increases. In the channel-etched transistor (Sov = 0 μm), compared with the Single Gate-driven transistor, the field-effect mobility of the Dual Gate-driven transistor is about twice as large. On the other hand, in the channel-protected transistor, the field-effect mobility of the Dual Gate-driven transistor decreases as the length of Sov increases. In the channel-etched transistor (Sov = 0 μm), compared with the Single Gate-driven transistor, the on-current of the Dual Gate-driven transistor is about twice as large. On the other hand, in the channel-protected transistor, the on-current of the Dual Gate-driven transistor decreases as the length of Sov increases. In the channel-protected transistor, the field-effect mobility of the Dual Gate-driven transistor decreases as the length of Sov increases. In the channel-protected transistor, the on-current of the Dual Gate-driven transistor decreases as the length of Sov increases.

[0102] In the channel-etched transistor (Sov = 0 μm), compared with the Single Gate-driven transistor, the on-current of the Dual Gate-driven transistor is about twice as large. On the other hand, in the channel-protected transistor, the on-current of the Dual Gate-driven transistor decreases as the length of Sov increases. In the channel-etched transistor (Sov = 0 μm), compared with the Single Gate-driven transistor, the on-current of the Dual Gate-driven transistor is about twice as large. On the other hand, in the channel-protected transistor, the on-current of the Dual Gate-driven transistor decreases as the length of Sov increases. In the channel-protected transistor, the on-current of the Dual Gate-driven transistor decreases as the length of Sov increases. In the channel-protected transistor, the on-current of the Dual Gate-driven transistor decreases as the length of Sov increases. In the channel-protected transistor, the on-current of the Dual Gate-driven transistor decreases as the length of Sov increases.

[0103] In a channel protection type transistor, the Sov regions at the source electrode S and the drain electrode D shield the electric field of the gate electrode GE_2. Therefore, in the oxide semiconductor film OS, a region where the carrier density cannot be controlled by the voltage of the gate electrode GE_2 expands. As a result, as the length of Sov increases, the field-effect mobility decreases and the on-current is considered to decrease. From the above, compared with the channel protection type transistor, the channel etch type transistor is more effective in increasing the field-effect mobility and current amplification effect in Dual Gate driving. In a channel protection type transistor, the Sov regions at the source electrode S and the drain electrode D shield the electric field of the gate electrode GE_2. Therefore, in the oxide semiconductor film OS, a region where the carrier density cannot be controlled by the voltage of the gate electrode GE_2 expands. As a result, as the length of Sov increases, the field-effect mobility decreases and the on-current is considered to decrease. From the above, compared with the channel protection type transistor, the channel etch type transistor is more effective in increasing the field-effect mobility and current amplification effect in Dual Gate driving. In a channel protection type transistor, the Sov regions at the source electrode S and the drain electrode D shield the electric field of the gate electrode GE_2. Therefore, in the oxide semiconductor film OS, a region where the carrier density cannot be controlled by the voltage of the gate electrode GE_2 expands. As a result, as the length of Sov increases, the field-effect mobility decreases and the on-current is considered to decrease. From the above, compared with the channel protection type transistor, the channel etch type transistor is more effective in increasing the field-effect mobility and current amplification effect in Dual Gate driving. In a channel protection type transistor, the Sov regions at the source electrode S and the drain electrode D shield the electric field of the gate electrode GE_2. Therefore, in the oxide semiconductor film OS, a region where the carrier density cannot be controlled by the voltage of the gate electrode GE_2 expands. As a result, as the length of Sov increases, the field-effect mobility decreases and the on-current is considered to decrease. From the above, compared with the channel protection type transistor, the channel etch type transistor is more effective in increasing the field-effect mobility and current amplification effect in Dual Gate driving. In a channel protection type transistor, the Sov regions at the source electrode S and the drain electrode D shield the electric field of the gate electrode GE_2. Therefore, in the oxide semiconductor film OS, a region where the carrier density cannot be controlled by the voltage of the gate electrode GE_2 expands. As a result, as the length of Sov increases, the field-effect mobility decreases and the on-current is considered to decrease. From the above, compared with the channel protection type transistor, the channel etch type transistor is more effective in increasing the field-effect mobility and current amplification effect in Dual Gate driving. In a channel protection type transistor, the Sov regions at the source electrode S and the drain electrode D shield the electric field of the gate electrode GE_2. Therefore, in the oxide semiconductor film OS, a region where the carrier density cannot be controlled by the voltage of the gate electrode GE_2 expands. As a result, as the length of Sov increases, the field-effect mobility decreases and the on-current is considered to decrease. From the above, compared with the channel protection type transistor, the channel etch type transistor is more effective in increasing the field-effect mobility and current amplification effect in Dual Gate driving. In a channel protection type transistor, the Sov regions at the source electrode S and the drain electrode D shield the electric field of the gate electrode GE_2. Therefore, in the oxide semiconductor film OS, a region where the carrier density cannot be controlled by the voltage of the gate electrode GE_2 expands. As a result, as the length of Sov increases, the field-effect mobility decreases and the on-current is considered to decrease. From the above, compared with the channel protection type transistor, the channel etch type transistor is more effective in increasing the field-effect mobility and current amplification effect in Dual Gate driving.

[0104] 〈Regarding the improvement of current driving force by Dual Gate driving〉 In a transistor with Dual Gate driving where gate electrodes facing each other across an oxide semiconductor film are connected and have the same potential, the improvement of the current driving force by reducing the channel length L will be explained. In a transistor with Dual Gate driving where gate electrodes facing each other across an oxide semiconductor film are connected and have the same potential, the improvement of the current driving force by reducing the channel length L will be explained. In a transistor with Dual Gate driving where gate electrodes facing each other across an oxide semiconductor film are connected and have the same potential, the improvement of the current driving force by reducing the channel length L will be explained.

[0105] 〈〈Regarding the saturation mobility in an ideal model〉〉 First, a simulation was performed on an ideal model that does not consider effects such as interface levels and interface scattering. Fig. 30 shows the model of the transistor used in the calculation. Note that device simulation software Atlas (manufactured by Silvaco) was used for the calculation. First, a simulation was performed on an ideal model that does not consider effects such as interface levels and interface scattering. Fig. 30 shows the model of the transistor used in the calculation. Note that device simulation software Atlas (manufactured by Silvaco) was used for the calculation. First, a simulation was performed on an ideal model that does not consider effects such as interface levels and interface scattering. Fig. 30 shows the model of the transistor used in the calculation. Note that device simulation software Atlas (manufactured by Silvaco) was used for the calculation. First, a simulation was performed on an ideal model that does not consider effects such as interface levels and interface scattering. Fig. 30 shows the model of the transistor used in the calculation. Note that device simulation software Atlas (manufactured by Silvaco) was used for the calculation.

[0106] In the transistor shown in Fig. 30, a gate insulating film GI_1 is formed on the gate electrode GE_1, and an oxide semiconductor film OS is formed on the gate insulating film GI_1. Source electrode S and drain electrode D are formed on the gate insulating film GI_1 and the oxide semiconductor film OS. The oxide semiconductor In the transistor shown in Fig. 30, a gate insulating film GI_1 is formed on the gate electrode GE_1, and an oxide semiconductor film OS is formed on the gate insulating film GI_1. Source electrode S and drain electrode D are formed on the gate insulating film GI_1 and the oxide semiconductor film OS. The oxide semiconductor In the transistor shown in Fig. 30, a gate insulating film GI_1 is formed on the gate electrode GE_1, and an oxide semiconductor film OS is formed on the gate insulating film GI_1. Source electrode S and drain electrode D are formed on the gate insulating film GI_1 and the oxide semiconductor film OS. The oxide semiconductor A gate insulating film GI_2 is formed on the film OS, the source electrode S, and the drain electrode D. The gate electrode GE_2 is formed on the gate insulating film GI_2. Also, the gate electrode GE_1 and the gate electrode GE_2 are connected at an opening (not shown) formed in the gate insulating film GI_1 and the gate insulating film GI_2.

[0107] The conditions used in the calculation are shown in Table 3.

[0108]

Table 3

[0109] Since the gate electrode GE_1 and the gate electrode GE_2 are connected, they are always at the same potential. Also, since the model uses two-dimensional simulation, the effect in the channel width direction is not considered. Further, the saturation mobility μ is calculated by substituting the value of the Vg-Id characteristic when the drain voltage (Vd) is 10 V into Equation 1. Here, the field-effect mobility in the saturation region is described as the saturation mobility. The maximum value of the saturation mobility obtained by calculation is an index of the current driving force in the saturation region (gate voltage (Vg) < drain voltage (Vd) + threshold voltage (Vth FE )) and is different from the approximate value of the mobility as a physical property value of the oxide semiconductor film.

[0110]

Equation

[0111] In Equation 1, W is the channel width of the transistor, and C Bottom is the capacitance value per unit area between the gate electrode GE_1 and the oxide semiconductor film OS. Dual ​​​​​​In the case of a gate-driven transistor, a gate electrode GE_2 and an oxide semiconductor film OS Although capacitance is also formed between the saturation mobility and the current driving capability, Therefore, the capacitance of the gate electrode GE_2 side of the dual gate drive transistor is omitted. Dual Gate drive transistors are also single gate drive transistors. The same formula 1 is used.

[0112] The calculation results for the dual gate driven transistor are shown in FIG. The calculation results for a single-gate driven transistor without E_2 are shown in Figure 31(B). As shown in.

[0113] As shown in Figure 31, the dual gate drive transistor and the single gate drive transistor In each of the transistors, a sharp peak in saturation mobility was obtained. The shorter the length, the higher the peak value of the saturated mobility.

[0114] Here, as the channel length L becomes shorter, the saturation mobility improves. The following explains how this corresponds to an improvement in the current driving force of the capacitor.

[0115] In the results obtained from the simulation of the ideal model, the gate voltage Vg=Vt The on-current is plotted against the L length at h+5 and Vg=Vth+10. The graph is shown in FIG. 32. The upper part of FIG. 32 shows the on-current, and the lower part of FIG. 32 shows the on-current. × channel length. In FIG. 32, the left column shows the results when the drain voltage (Vd) is 1V. The right column shows the calculation results when the drain voltage (Vd) is 10V.

[0116] The on-current shown in FIG. 32 is inversely proportional to the channel length (L). This is because the on-current is inversely proportional to the channel length (L). This is because the on-current is inversely proportional to the channel length (L).

[0117] If the on-current is exactly inversely proportional to the channel length, the value of on-current × channel length will be a constant value independent of the channel length. In FIG. 32, when the drain voltage (Vd) is 1 V, the value of on-current × channel length is a constant value with respect to the channel length (L). On the other hand, when the drain voltage (Vd) is 10 V, as the channel length (L) becomes shorter, the value of on-current × channel length increases. This indicates that when the drain voltage (Vd) is 10 V, the effective channel length (described later) is shorter than the channel length defined in FIG. 30 (the distance between the source electrode S and the drain electrode D). In FIG. 32, when the drain voltage (Vd) is 1 V, the value of on-current × channel length is a constant value with respect to the channel length (L). On the other hand, when the drain voltage (Vd) is 10 V, as the channel length (L) becomes shorter, the value of on-current × channel length increases. This indicates that when the drain voltage (Vd) is 10 V, the effective channel length (described later) is shorter than the channel length defined in FIG. 30 (the distance between the source electrode S and the drain electrode D). In FIG. 32, when the drain voltage (Vd) is 1 V, the value of on-current × channel length is a constant value with respect to the channel length (L). On the other hand, when the drain voltage (Vd) is 10 V, as the channel length (L) becomes shorter, the value of on-current × channel length increases. This indicates that when the drain voltage (Vd) is 10 V, the effective channel length (described later) is shorter than the channel length defined in FIG. 30 (the distance between the source electrode S and the drain electrode D). In FIG. 32, when the drain voltage (Vd) is 10 V, as the channel length (L) becomes shorter, the value of on-current × channel length increases. This indicates that when the drain voltage (Vd) is 10 V, the effective channel length (described later) is shorter than the channel length defined in FIG. 30 (the distance between the source electrode S and the drain electrode D). In FIG. 32, when the drain voltage (Vd) is 10 V, as the channel length (L) becomes shorter, the value of on-current × channel length increases. This indicates that when the drain voltage (Vd) is 10 V, the effective channel length (described later) is shorter than the channel length defined in FIG. 30 (the distance between the source electrode S and the drain electrode D). In FIG. 32, when the drain voltage (Vd) is 10 V, as the channel length (L) becomes shorter, the value of on-current × channel length increases. This indicates that when the drain voltage (Vd) is 10 V, the effective channel length (described later) is shorter than the channel length defined in FIG. 30 (the distance between the source electrode S and the drain electrode D). In FIG. 32, when the drain voltage (Vd) is 10 V, as the channel length (L) becomes shorter, the value of on-current × channel length increases. This indicates that when the drain voltage (Vd) is 10 V, the effective channel length (described later) is shorter than the channel length defined in FIG. 30 (the distance between the source electrode S and the drain electrode D).

[0118] 〈〈Theory of Bulk Current〉〉 Hereinafter, the reason for the peak occurring at a low gate voltage in the saturation mobility of an ideal model transistor will be explained. Hereinafter, the reason for the peak occurring at a low gate voltage in the saturation mobility of an ideal model transistor will be explained.

[0119] In the transistor shown in FIG. 30, it is assumed that the electron density contained in the oxide semiconductor film OS is represented by a constant value n0(y) in the film thickness direction of the oxide semiconductor film OS. y represents an arbitrary position in the channel length direction within the oxide semiconductor film OS. The potential φ in the film thickness direction of the oxide semiconductor film OS is shown in Equation 2 and is constant. However, it is assumed that the gate voltage Vg_1 of the gate electrode GE_1 and the gate voltage Vg_2 of the gate electrode GE_2 are at the same potential, and the flat band voltages on both the gate electrode GE_1 side and the gate electrode GE_2 side are both the flat band voltage V In the transistor shown in FIG. 30, it is assumed that the electron density contained in the oxide semiconductor film OS is represented by a constant value n0(y) in the film thickness direction of the oxide semiconductor film OS. y represents an arbitrary position in the channel length direction within the oxide semiconductor film OS. The potential φ in the film thickness direction of the oxide semiconductor film OS is shown in Equation 2 and is constant. However, it is assumed that the gate voltage Vg_1 of the gate electrode GE_1 and the gate voltage Vg_2 of the gate electrode GE_2 are at the same potential, and the flat band voltages on both the gate electrode GE_1 side and the gate electrode GE_2 side are both the flat band voltage V In the transistor shown in FIG. 30, it is assumed that the electron density contained in the oxide semiconductor film OS is represented by a constant value n0(y) in the film thickness direction of the oxide semiconductor film OS. y represents an arbitrary position in the channel length direction within the oxide semiconductor film OS. The potential φ in the film thickness direction of the oxide semiconductor film OS is shown in Equation 2 and is constant. However, it is assumed that the gate voltage Vg_1 of the gate electrode GE_1 and the gate voltage Vg_2 of the gate electrode GE_2 are at the same potential, and the flat band voltages on both the gate electrode GE_1 side and the gate electrode GE_2 side are both the flat band voltage V In the transistor shown in FIG. 30, it is assumed that the electron density contained in the oxide semiconductor film OS is represented by a constant value n0(y) in the film thickness direction of the oxide semiconductor film OS. y represents an arbitrary position in the channel length direction within the oxide semiconductor film OS. The potential φ in the film thickness direction of the oxide semiconductor film OS is shown in Equation 2 and is constant. However, it is assumed that the gate voltage Vg_1 of the gate electrode GE_1 and the gate voltage Vg_2 of the gate electrode GE_2 are at the same potential, and the flat band voltages on both the gate electrode GE_1 side and the gate electrode GE_2 side are both the flat band voltage V In the transistor shown in FIG. 30, it is assumed that the electron density contained in the oxide semiconductor film OS is represented by a constant value n0(y) in the film thickness direction of the oxide semiconductor film OS. y represents an arbitrary position in the channel length direction within the oxide semiconductor film OS. The potential φ in the film thickness direction of the oxide semiconductor film OS is shown in Equation 2 and is constant. However, it is assumed that the gate voltage Vg_1 of the gate electrode GE_1 and the gate voltage Vg_2 of the gate electrode GE_2 are at the same potential, and the flat band voltages on both the gate electrode GE_1 side and the gate electrode GE_2 side are both the flat band voltage V In the transistor shown in FIG. 30, it is assumed that the electron density contained in the oxide semiconductor film OS is represented by a constant value n0(y) in the film thickness direction of the oxide semiconductor film OS. y represents an arbitrary position in the channel length direction within the oxide semiconductor film OS. The potential φ in the film thickness direction of the oxide semiconductor film OS is shown in Equation 2 and is constant. However, it is assumed that the gate voltage Vg_1 of the gate electrode GE_1 and the gate voltage Vg_2 of the gate electrode GE_2 are at the same potential, and the flat band voltages on both the gate electrode GE_1 side and the gate electrode GE_2 side are both the flat band voltage V In the transistor shown in FIG. 30, it is assumed that the electron density contained in the oxide semiconductor film OS is represented by a constant value n0(y) in the film thickness direction of the oxide semiconductor film OS. y represents an arbitrary position in the channel length direction within the oxide semiconductor film OS. The potential φ in the film thickness direction of the oxide semiconductor film OS is shown in Equation 2 and is constant. However, it is assumed that the gate voltage Vg_1 of the gate electrode GE_1 and the gate voltage Vg_2 of the gate electrode GE_2 are at the same potential, and the flat band voltages on both the gate electrode GE_1 side and the gate electrode GE_2 side are both the flat band voltage V FB and assume that they are the same.

[0120]

Number

[0121] At this time, in a transistor having an oxide semiconductor film that is an accumulation type, the drain current I d is approximately given only by the bulk current I bulk alone.

[0122]

Number

[0123] In Equation 3, t is the film thickness of the oxide semiconductor film, μ is the electron mobility of the oxide semiconductor film, k B is the Boltzmann constant, T is the absolute temperature, L eff is the effective channel length. Here,[[]] the channel length is the distance between the source electrode and the drain electrode, and the effective channel length is , in the oxide semiconductor film, it represents the distance between the n-region spreading from under the source electrode and the n-region spreading from under the drain electrode. In particular, when the channel length is short or the drain voltage is high case, the effective channel length becomes shorter than the channel length.

[0124] Note that n0(0) is the electron density at the source electrode side end of the region defined by the above-mentioned effective channel length, and is expressed by Equation 4. Also, n0(L ) is the electron density at the drain electrode side end of the region defined by the above-mentioned effective channel length eff and is expressed by Equation 5. In addition, in Equations 4 and 5, N is the donor density in the channel region of the oxide semiconductor film and q is the elementary charge. D

[0125]

Number

[0126] [Number]

[0127] In the saturation region where Vd > Vg - Vth and Vg > Vth, the drain voltage Vd is replaced by Vg - V th, so Equation 3 becomes Equation 6.

[0128] [Number]

[0129] For the drain current Id obtained from Equation 6, calculating the saturation mobility μ FE sat results in Equation 7.

[0130] [Number]

[0131] In Equation 7, when Vg is set to Vth, the denominator becomes 0, and the saturation mobility μ FE sat diverges to infinity. This property is the cause of the peak at low gate voltage Vg in the saturation mobility as shown in Figure 31. That is, the more the bulk current flowing inside the oxide semiconductor film OS is the main factor of the drain current, the clearer the peak, such as the saturation mobility when the channel length in Figure 31 is 2 μm, appears.

[0132] Also, as one of the other factors for increasing the saturation mobility, it is conceivable that the effective channel length L eff is shorter than the channel length L. For example, in the oxide semiconductor film OS, the source In the vicinity of the region in contact with the source electrode S and the drain electrode D, when the n-region spreads, the effective channel length L becomes shorter than the channel length L. This effect is also evident from the proportional relationship with respect to L / L eff of the saturation mobility μ shown in Equation 7. of the saturation mobility μ FE sat of L / L eff as shown in Equation 7.

[0133] <<Current density in the oxide semiconductor film OS>> That the bulk current affects the saturation mobility is a phenomenon peculiar to transistors having an oxide semiconductor film, which is an accumulation-type device, and there is little influence of the bulk current in an inversion-type device such as a transistor having a silicon film as the semiconductor film. That the bulk current affects the saturation mobility is a phenomenon peculiar to transistors having an oxide semiconductor film, which is an accumulation-type device, and there is little influence of the bulk current in an inversion-type device such as a transistor having a silicon film as the semiconductor film. That the bulk current affects the saturation mobility is a phenomenon peculiar to transistors having an oxide semiconductor film, which is an accumulation-type device, and there is little influence of the bulk current in an inversion-type device such as a transistor having a silicon film as the semiconductor film.

[0134] Next, a graph plotting the current density distribution obtained by device simulation is shown in FIG. 33. FIG. 33(A) shows the Vg-Id characteristics obtained by calculation with a drain voltage of 10 V, and FIGS. 33(B) and 33(C) show the current density distribution in the cross-sectional direction of A1-A2 of the oxide semiconductor film. FIG. 33(B) shows the saturation region (Vg = 0.5 V), and FIG. 33(C) shows the current density distribution in the linear region (Vg = 15 V). Note that the channel length L / channel width W of the transistor used in the calculation is 2 μm / 50 μm, and the drain voltage Vd is 10 V. Next, a graph plotting the current density distribution obtained by device simulation is shown in FIG. 33. FIG. 33(A) shows the Vg-Id characteristics obtained by calculation with a drain voltage of 10 V, and FIGS. 33(B) and 33(C) show the current density distribution in the cross-sectional direction of A1-A2 of the oxide semiconductor film. FIG. 33(B) shows the saturation region (Vg = 0.5 V), and FIG. 33(C) shows the current density distribution in the linear region (Vg = 15 V). Note that the channel length L / channel width W of the transistor used in the calculation is 2 μm / 50 μm, and the drain voltage Vd is 10 V. Next, a graph plotting the current density distribution obtained by device simulation is shown in FIG. 33. FIG. 33(A) shows the Vg-Id characteristics obtained by calculation with a drain voltage of 10 V, and FIGS. 33(B) and 33(C) show the current density distribution in the cross-sectional direction of A1-A2 of the oxide semiconductor film. FIG. 33(B) shows the saturation region (Vg = 0.5 V), and FIG. 33(C) shows the current density distribution in the linear region (Vg = 15 V). Note that the channel length L / channel width W of the transistor used in the calculation is 2 μm / 50 μm, and the drain voltage Vd is 10 V. Next, a graph plotting the current density distribution obtained by device simulation is shown in FIG. 33. FIG. 33(A) shows the Vg-Id characteristics obtained by calculation with a drain voltage of 10 V, and FIGS. 33(B) and 33(C) show the current density distribution in the cross-sectional direction of A1-A2 of the oxide semiconductor film. FIG. 33(B) shows the saturation region (Vg = 0.5 V), and FIG. 33(C) shows the current density distribution in the linear region (Vg = 15 V). Note that the channel length L / channel width W of the transistor used in the calculation is 2 μm / 50 μm, and the drain voltage Vd is 10 V. Next, a graph plotting the current density distribution obtained by device simulation is shown in FIG. 33. FIG. 33(A) shows the Vg-Id characteristics obtained by calculation with a drain voltage of 10 V, and FIGS. 33(B) and 33(C) show the current density distribution in the cross-sectional direction of A1-A2 of the oxide semiconductor film. FIG. 33(B) shows the saturation region (Vg = 0.5 V), and FIG. 33(C) shows the current density distribution in the linear region (Vg = 15 V). Note that the channel length L / channel width W of the transistor used in the calculation is 2 μm / 50 μm, and the drain voltage Vd is 10 V. Next, a graph plotting the current density distribution obtained by device simulation is shown in FIG. 33. FIG. 33(A) shows the Vg-Id characteristics obtained by calculation with a drain voltage of 10 V, and FIGS. 33(B) and 33(C) show the current density distribution in the cross-sectional direction of A1-A2 of the oxide semiconductor film. FIG. 33(B) shows the saturation region (Vg = 0.5 V), and FIG. 33(C) shows the current density distribution in the linear region (Vg = 15 V). Note that the channel length L / channel width W of the transistor used in the calculation is 2 μm / 50 μm, and the drain voltage Vd is 10 V. Next, a graph plotting the current density distribution obtained by device simulation is shown in FIG. 33. FIG. 33(A) shows the Vg-Id characteristics obtained by calculation with a drain voltage of 10 V, and FIGS. 33(B) and 33(C) show the current density distribution in the cross-sectional direction of A1-A2 of the oxide semiconductor film. FIG. 33(B) shows the saturation region (Vg = 0.5 V), and FIG. 33(C) shows the current density distribution in the linear region (Vg = 15 V). Note that the channel length L / channel width W of the transistor used in the calculation is 2 μm / 50 μm, and the drain voltage Vd is 10 V.

[0135] From FIG. 33(B), in the saturation region (low gate voltage Vg), the current density is almost uniformly distributed in the oxide semiconductor film OS. On the other hand, as shown in FIG. 33(C), in the linear region (high gate voltage Vg), the current flowing near the surface of the oxide semiconductor film OS is dominant. As shown in FIG. 33(B), in the saturation region, the current density is almost From FIG. 33(B), in the saturation region (low gate voltage Vg), the current density is almost uniformly distributed in the oxide semiconductor film OS. On the other hand, as shown in FIG. 33(C), in the linear region (high gate voltage Vg), the current flowing near the surface of the oxide semiconductor film OS is dominant. As shown in FIG. 33(B), in the saturation region, the current density is almost From FIG. 33(B), in the saturation region (low gate voltage Vg), the current density is almost uniformly distributed in the oxide semiconductor film OS. On the other hand, as shown in FIG. 33(C), in the linear region (high gate voltage Vg), the current flowing near the surface of the oxide semiconductor film OS is dominant. As shown in FIG. 33(B), in the saturation region, the current density is almost From FIG. 33(B), in the saturation region (low gate voltage Vg), the current density is almost uniformly distributed in the oxide semiconductor film OS. On the other hand, as shown in FIG. 33(C), in the linear region (high gate voltage Vg), the current flowing near the surface of the oxide semiconductor film OS is dominant. As shown in FIG. 33(B), in the saturation region, the current density is almost Since it is uniformly distributed, it can be seen that one of the reasons for the peak in the saturation mobility is the bulk current.

[0136] On the other hand, the current density distribution of the semiconductor film of the inversion-type device obtained by device simulation is shown in Fig. 34. Fig. 34 shows the calculation results when the oxide semiconductor film OS of the transistor shown in Fig. 30 is replaced with a semiconductor film (silicon) including an n -p-n junction. In the channel region of the semiconductor film, acceptor-type impurities with a density of 1×17 / cm were assumed. 3

[0137] Fig. 34(A) shows the Vg-Id characteristics obtained by calculation with a drain voltage of 10V, and Figs. 34(B) and 34(C) show the current density distribution in the cross-sectional direction of A1-A2 of the semiconductor film shown in Fig. 30. Fig. 34(B) shows the current density distribution in the saturation region (Vg = 0.5V), and Fig. 34(C) shows the current density distribution in the linear region ( Vg = 15V). Note that the channel length L / channel width W of the transistor used in the calculation was 2μm / 50μm, and the drain voltage Vd was 10V.

[0138] Unlike a transistor having an oxide semiconductor film which is an accumulation-type device, a transistor having a semiconductor film which is an inversion-type device has, as shown in Fig. 34(B), a large current flowing on the surface of the semiconductor film even near the threshold voltage, and the contribution of the bulk current is small compared with that of the accumulation-type device.

[0139] From the above, in a transistor having an oxide semiconductor film which is an accumulation-type device, in an ideal model, it can be seen that a sharp peak occurs in the saturation mobility due to the bulk current.

[0140] Note that as the channel length L becomes shorter, the peak value of the saturation mobility caused by the bulk current increases. As a cause, in the oxide semiconductor film OS, in the vicinity of the region in contact with the source electrode S and the drain electrode D, as the n region spreads, it is considered that the effective channel length L eff becomes shorter than the channel length L. Further, when the channel length L is small, due to the influence of the source electrode S and the drain electrode D, the energy (Ec) at the lower end of the conduction band of the oxide semiconductor film OS becomes low and the phenomenon (CBL effect (Conduction band lowering effect)) in which the energy at the lower end of the conduction band and the Fermi energy approach each other causes the effective channel length L to be considered shorter than the channel length L. The saturation mobility is as shown in Equation 7, eff and as the effective channel length L becomes smaller, it increases in proportion to L / L eff . Since this effect occurs more prominently as the channel length L is smaller, it is considered that the saturation mobility improves as the channel length L is smaller. eff and becomes larger . Since this effect occurs more prominently as the channel length L is smaller, it is considered that the saturation mobility improves as the channel length L is smaller. The smaller the channel length L, the higher the saturation mobility is considered to be.

[0141] 〈〈Model assuming shallow electron trap levels〉〉 Next, in order to approximate the saturation mobility of an actual transistor, in an ideal model transistor, at the interface between the gate insulating film GI_1 and the oxide semiconductor film OS, a calculation was performed assuming an acceptor-type level that traps electrons and becomes negatively charged, that is, a shallow electron trap level, and the results are shown in FIG. 35. FIG. 35(A) shows the DOS (density of state) of the electron trap levels assumed at the interface between the gate insulating film GI_1 and the oxide semiconductor film OS. The results are shown in FIG. 35.

[0142] FIG. 35(A) shows the DOS (density of state) of the electron trap levels assumed at the interface between the gate insulating film GI_1 and the oxide semiconductor film OS. is shown.

[0143] Next, the saturation mobilities of the transistors with dual - gate driving and the transistors with single - gate driving were calculated respectively. The calculation results of the transistors with dual - gate driving are shown in FIG. 35(B), and the calculation results of the transistors with single - gate driving are shown in FIG. 35(C).

[0144] From FIGS. 35(B) and 35(C), sharp peaks as obtained in the ideal model did not appear in the saturation mobilities of the transistors with dual - gate driving and the transistors with single - gate driving. Also, from FIG. 35(C), in the transistors with single - gate driving, the saturation mobility peak value was not much dependent on the channel length L and was approximately around 5. On the other hand, in the transistors with dual - gate driving, the shorter the channel length L, the higher the saturation mobility peak value, and the value became from 15 to less than 20. This result is the same tendency as the result of the embodiment described later.

[0145] From this, it can be seen that in the transistors with dual - gate driving, the shorter the channel length L, the higher the saturation mobility.

[0146] <Configuration Example of Semiconductor Display Device> Next, a configuration example of the semiconductor display device according to one aspect of the present invention will be described.

[0147] In the semiconductor display device 70 shown in FIG. 6(A), in the pixel portion 71, there are a plurality of pixels 55, wirings GL indicated by wirings GL1 to GLy (y is a natural number) for selecting the pixels 55 for each row, and wirings SL indicated by wirings SL1 to SLx (x is a natural number) for supplying an image signal to the selected pixels 55. ​​​​​​​​A wiring SL represented by a natural number) is provided. The input of a signal to the wiring GL is controlled by a drive circuit 72. The input of an image signal to the wiring SL is controlled by a drive circuit 73. A plurality of pixels 55 are respectively connected to at least one of the wirings GL and at least one of the wirings SL. The input of a signal to the wiring GL is controlled by a drive circuit 72. The input of an image signal to the wiring SL is controlled by a drive circuit 73. A plurality of pixels 55 are respectively connected to at least one of the wirings GL and at least one of the wirings SL. A wiring SL represented by a natural number) is provided. The input of a signal to the wiring GL is controlled by a drive circuit 72. The input of an image signal to the wiring SL is controlled by a drive circuit 73. A plurality of pixels 55 are respectively connected to at least one of the wirings GL and at least one of the wirings SL. A wiring SL represented by a natural number) is provided. The input of a signal to the wiring GL is controlled by a drive circuit 72. The input of an image signal to the wiring SL is controlled by a drive circuit 73. A plurality of pixels 55 are respectively connected to at least one of the wirings GL and at least one of the wirings SL.

[0148] Note that the type and number of wirings provided in the pixel portion 71 can be determined according to the configuration, number, and arrangement of the pixels 55. Specifically, in the case of the pixel portion 71 shown in FIG. 6(A), pixels 55 of x columns × y rows are arranged in a matrix, and wirings SL1 to SLx and wirings GL1 to GLy are arranged within the pixel portion 71 as an example. Note that the type and number of wirings provided in the pixel portion 71 can be determined according to the configuration, number, and arrangement of the pixels 55. Specifically, in the case of the pixel portion 71 shown in FIG. 6(A), pixels 55 of x columns × y rows are arranged in a matrix, and wirings SL1 to SLx and wirings GL1 to GLy are arranged within the pixel portion 71 as an example. Note that the type and number of wirings provided in the pixel portion 71 can be determined according to the configuration, number, and arrangement of the pixels 55. Specifically, in the case of the pixel portion 71 shown in FIG. 6(A), pixels 55 of x columns × y rows are arranged in a matrix, and wirings SL1 to SLx and wirings GL1 to GLy are arranged within the pixel portion 71 as an example. Note that the type and number of wirings provided in the pixel portion 71 can be determined according to the configuration, number, and arrangement of the pixels 55. Specifically, in the case of the pixel portion 71 shown in FIG. 6(A), pixels 55 of x columns × y rows are arranged in a matrix, and wirings SL1 to SLx and wirings GL1 to GLy are arranged within the pixel portion 71 as an example.

[0149] Note that in FIG. 6(A), an example is shown where the drive circuit 72 and the drive circuit 73 are formed on the same substrate as the pixel portion 71, but the drive circuit 72 and the drive circuit 73 may be formed on a substrate different from the pixel portion 71. Note that in FIG. 6(A), an example is shown where the drive circuit 72 and the drive circuit 73 are formed on the same substrate as the pixel portion 71, but the drive circuit 72 and the drive circuit 73 may be formed on a substrate different from the pixel portion 71. Note that in FIG. 6(A), an example is shown where the drive circuit 72 and the drive circuit 73 are formed on the same substrate as the pixel portion 71, but the drive circuit 72 and the drive circuit 73 may be formed on a substrate different from the pixel portion 71.

[0150] Also, FIG. 6(B) shows an example of the configuration of the pixel 55. Each pixel 55 includes a liquid crystal element 60, a transistor 56 that controls the supply of an image signal to the liquid crystal element 60, and a capacitor element 57 that holds the voltage between the pixel electrode and the common electrode of the liquid crystal element 60. The liquid crystal element 60 includes a liquid crystal layer containing a liquid crystal material to which a voltage between the pixel electrode, the common electrode, and the pixel electrode and the common electrode is applied. Also, FIG. 6(B) shows an example of the configuration of the pixel 55. Each pixel 55 includes a liquid crystal element 60, a transistor 56 that controls the supply of an image signal to the liquid crystal element 60, and a capacitor element 57 that holds the voltage between the pixel electrode and the common electrode of the liquid crystal element 60. The liquid crystal element 60 includes a liquid crystal layer containing a liquid crystal material to which a voltage between the pixel electrode, the common electrode, and the pixel electrode and the common electrode is applied. Also, FIG. 6(B) shows an example of the configuration of the pixel 55. Each pixel 55 includes a liquid crystal element 60, a transistor 56 that controls the supply of an image signal to the liquid crystal element 60, and a capacitor element 57 that holds the voltage between the pixel electrode and the common electrode of the liquid crystal element 60. The liquid crystal element 60 includes a liquid crystal layer containing a liquid crystal material to which a voltage between the pixel electrode, the common electrode, and the pixel electrode and the common electrode is applied. Also, FIG. 6(B) shows an example of the configuration of the pixel 55. Each pixel 55 includes a liquid crystal element 60, a transistor 56 that controls the supply of an image signal to the liquid crystal element 60, and a capacitor element 57 that holds the voltage between the pixel electrode and the common electrode of the liquid crystal element 60. The liquid crystal element 60 includes a liquid crystal layer containing a liquid crystal material to which a voltage between the pixel electrode, the common electrode, and the pixel electrode and the common electrode is applied. Also, FIG. 6(B) shows an example of the configuration of the pixel 55. Each pixel 55 includes a liquid crystal element 60, a transistor 56 that controls the supply of an image signal to the liquid crystal element 60, and a capacitor element 57 that holds the voltage between the pixel electrode and the common electrode of the liquid crystal element 60. The liquid crystal element 60 includes a liquid crystal layer containing a liquid crystal material to which a voltage between the pixel electrode, the common electrode, and the pixel electrode and the common electrode is applied.

[0151] The transistor 56 controls whether to apply the potential of the wiring SL to the pixel electrode of the liquid crystal element 60. A predetermined potential is applied to the common electrode of the liquid crystal element 60. The transistor 56 controls whether to apply the potential of the wiring SL to the pixel electrode of the liquid crystal element 60. A predetermined potential is applied to the common electrode of the liquid crystal element 60.

[0152] The specific connection configuration between the transistor 56 and the liquid crystal element 60 will be described below. ) the gate of the transistor 56 is connected to one of the wirings GL1 to GLy. One of the source and drain of the transistor 56 is connected to the wiring SL1. x, and the other of the source and drain of the transistor 56 is connected to the liquid crystal element The pixel electrode of the pixel 60 is connected to the pixel electrode of the pixel 60.

[0153] In the liquid crystal element 60, the voltage applied between the pixel electrode and the common electrode changes depending on the voltage contained in the liquid crystal layer. The orientation of the liquid crystal molecules contained in the liquid crystal element 60 changes, and the transmittance changes. The transmittance of the pixel is controlled by the potential of the image signal applied to the pixel, thereby displaying gray scales. In each of the pixels 55 in the pixel section 71, a liquid crystal element The gray scale of the pixel 60 is adjusted in accordance with an image signal having image information, so that an image is displayed on the pixel section 71. is displayed.

[0154] In FIG. 6B, a pixel 55 has a switch for controlling the input of an image signal to the pixel 55. As an example, a single transistor 56 is used as a switch. A number of functional transistors may be used in pixel 55 .

[0155] In one embodiment of the present invention, a transistor 56 having an extremely low off-state current is used as a It is preferable to use the transistor 56 as a switch to control the input to the A small value prevents charge from leaking through transistor 56. The potential of the image signal applied to the liquid crystal element 60 and the capacitance element 57 can be more reliably held. Therefore, the transmittance of the liquid crystal element 60 changes due to leakage of electric charges within one frame period. This prevents the display of images from being blurred, thereby improving the quality of the images displayed. When the off-current of the transistor 56 is small, the charge leakage through the transistor 56 is prevented. Therefore, during the period when a still image is displayed, the driving circuits 72 and 73 With the above configuration, the supply of the image signal to the pixel section 71 may be stopped. This reduces the number of times the signal is written, thereby reducing the power consumption of the semiconductor display device.

[0156] For example, a transistor including an oxide semiconductor in a semiconductor film has an extremely small off-state current. This is suitable for use as transistor 56.

[0157] In FIG. 6B, the transistor 56 is a pair of transistors overlapping each other with a semiconductor film sandwiched therebetween. The pair of gate electrodes are electrically connected to each other. In one embodiment of the present invention, the above structure increases the on-state current of the transistor 56. Moreover, the reliability of the transistor 56 can be improved.

[0158] 6C shows another example of the pixel 55. The pixel 55 is a pixel having an image signal a transistor 95 for controlling the input of the light emitting element 98; A transistor 96 for controlling the current value supplied to the Element 97.

[0159] The light emitting element 98 is a light emitting diode (LED) or an organic light emitting diode (OLED). current or voltage, such as a photovoltaic (Pb) or photovoltaic (Pb) light emitting diode (Pb) Therefore, it includes an element whose luminance is controlled within that range. For example, an OLED has at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or a plurality of layers provided between the anode and the cathode, and among these layers, it includes at least a light-emitting layer containing a light-emitting substance.

[0160] Note that when the potential difference between the cathode and the anode of the EL layer becomes equal to or higher than the threshold voltage of the light-emitting element 98, electroluminescence is obtained by the current supplied. Electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state.

[0161] Either the anode or the cathode of the light-emitting element 98 has its potential controlled by the image signal input to the pixel 55. Among the anode and the cathode, the electrode whose potential is controlled according to the image signal is defined as the pixel electrode, and the other electrode is defined as the common electrode. A predetermined potential is applied to the common electrode of the light-emitting element 98, and the luminance of the light-emitting element 98 is determined by the potential difference between the pixel electrode and the common electrode. Therefore, the light-emitting element 98 can display gradations by controlling its luminance according to the potential of the image signal. Then, in each of the plurality of pixels 55 of the pixel portion, the gradation of the light-emitting element 98 is adjusted according to the image signal having image information, and an image is displayed on the pixel portion 71.

[0162] Next, the connection configuration of the transistor 95, the transistor 96, the capacitor element 97, and the light-emitting element 98 included in the pixel 55 will be described.

[0163] One of the source or drain of the transistor 95 is connected to the wiring SL, and the other of the source or drain is connected to the gate of the transistor 96. The gate of the transistor 95 is connected to the wiring GL. One of the source or drain of the transistor 96 is connected to the power supply line VL, and the other of the source or drain is connected to the light emitting element 98. Specifically, the other of the source or drain of the transistor 96 is connected to either the anode or the cathode of the light emitting element 98. A predetermined potential is applied to the other of the anode and the cathode of the light emitting element 98.

[0164] In FIG. 6(C), a case where the transistor 96 has a pair of gate electrodes overlapping with each other with a semiconductor film interposed therebetween is illustrated. The pair of gate electrodes are electrically connected. In one aspect of the present invention, with the above configuration, the on-current of the transistor 96 can be increased, and the reliability of the transistor 96 can still be improved.

[0165] <Pixel Configuration> Next, taking a liquid crystal display device, which is one of the semiconductor display devices 70 shown in FIG. 6(A), as an example, a configuration example of the pixel 55 will be described. FIG. 4 shows a top view of the pixel 55 formed on the substrate 31 together with the transistor 20 shown in FIG. 2, as an example. In FIG. 4, various insulating films are omitted for clarity of the layout of the pixel 55. Further, a cross-sectional view of the liquid crystal display device formed using the element substrate having the pixel 55 shown in FIG. 4 is shown in FIG. 5. Among the liquid crystal display devices shown in FIG. 5, the element substrate including the substrate 31 corresponds to the cross-sectional view taken along the broken line B1 - B2 in FIG. 4.

[0166] The pixel 55 shown in FIGS. 4 and 5 has a transistor 56 and a capacitor element 57. Further the pixel 55 shown in FIG. 5 has a liquid crystal element 60.

[0167] The transistor 56 has, on a substrate 31 having an insulating surface, a conductive film 40 that functions as a gate electrode, an insulating film 22 that functions as a gate insulating film and is located on the conductive film 40, an oxide semiconductor film 41 that overlaps the conductive film 40 on the insulating film 22, and conductive films 43 and 44 that are electrically connected to the oxide semiconductor film 41 and function as a source electrode or a drain electrode. The conductive film 40 functions as a wiring GL shown in FIG. 6(B).

[0168] Also, the pixel 55 has a metal oxide film 42 on the insulating film 22. The metal oxide film 42 is a conductive film having translucency with respect to visible light. And on the metal oxide film 42, a conductive film 61 electrically connected to the metal oxide film 42 is provided. The conductive film 61 functions as a wiring for supplying a predetermined

[0169] potential to the metal oxide film 42. Also, in FIG. 5, insulating films 26 and 27 are provided so as to be laminated in order on the oxide semiconductor film 41, the conductive films 43 and 44, the metal oxide film 42, and the conductive film 61. The transistor 56 may include the insulating films 26 and 27 as its components. Note that in FIG. 5, the insulating films 26 and 27 laminated in order are illustrated, but a single insulating film may be used instead of the insulating films

[0170] The insulating film 26 and the insulating film 27 have an opening 58 at a position overlapping with the metal oxide film 42. The opening 58 is in a region different from the oxide semiconductor film 41, the conductive film 43, and the conductive film 44, and is provided in a region overlapping with the metal oxide film 42.

[0171] Also, in FIG. 5, a nitride insulating film 28 and an insulating film 29 are provided so as to be laminated in this order on the insulating film 26 and the insulating film 27 and on the metal oxide film 42 in the opening 58.

[0172] Note that by forming an oxide semiconductor film on the insulating film 22 and forming a nitride insulating film 28 in contact with the oxide semiconductor film, the conductivity of the oxide semiconductor film can be increased. Then, the oxide semiconductor film with increased conductivity can be used as the metal oxide film 42. It is considered that the conductivity of the oxide semiconductor film increases because oxygen vacancies are formed in the oxide semiconductor film during the formation of the opening 58 or during the formation of the nitride insulating film 28, and hydrogen diffusing from the nitride insulating film 28 binds to the oxygen vacancies to generate donors. Specifically, the resistivity of the metal oxide film 42 is typically 1×10 Ωcm or more and less than 1×10 Ωcm, and more preferably, the resistivity is 1×10 Ωcm or more and less than 1×10 Ωcm. -3 Ωcm 4 -3 Ωcm -1

[0173] The metal oxide film 42 preferably has a higher hydrogen concentration than the oxide semiconductor film 41. In the metal oxide film 42, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 8×10 atom 19 s / cm 3 Above, preferably 1×10 20 atoms / cm 3 Above, more preferably 5× 10 20 atoms / cm 3 or more. In the oxide semiconductor film 41, the hydrogen concentration obtained by secondary ion mass analysis method is 5×10 19 atoms / cm 3 Less than, preferably 5 ×10 18 atoms / cm 3 Less than, preferably 1×10 18 atoms / cm 3 or less, More preferably 5×10 17 atoms / cm 3 or less, even more preferably 1×10 16 a toms / cm 3 or less.

[0174] As the nitride insulating film 28, for example, silicon nitride, silicon oxynitride, aluminum nitride , aluminum oxynitride, etc. can be used. The nitride insulating film 28 made of the above-described materials can prevent impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the oxide semiconductor film 41.

[0175] Further, the nitride insulating film 28 and the insulating film 29 are provided with an opening 62 at a position overlapping the conductive film 44. And on the nitride insulating film 28 and the insulating film 29, a conductive film 45 having light transmittance to visible light and having a function as a pixel electrode is provided. The conductive film 45 is electrically connected to the conductive film 44 at the opening It overlaps with the metal oxide film 42 at 58. The overlapping portion where the conductive film 45 and the metal oxide film 42 sandwich the nitride insulating film 28 and the insulating film 29 functions as the capacitor element 57. The overlapping portion where the conductive film 45 and the metal oxide film 42 sandwich the nitride insulating film 28 and the insulating film 29 functions as the capacitor element 57. .

[0176] The capacitor element 57 has the metal oxide film 42 and the conductive film 45 that function as a pair of electrodes, and the nitride insulating film 28 and the insulating film 29 that function as dielectric films, and are transparent to visible light. Therefore, the capacitor element 57 has transparency to visible light, and the aperture ratio of the pixel 55 can be increased compared to a pixel with low transparency of the capacitor element to visible light. Therefore, while securing the capacitance value necessary for obtaining high image quality, the light loss in the panel can be greatly suppressed, and the power consumption of the semiconductor device can be reduced. As described above, the insulating film 29 does not necessarily have to be provided, but by using the insulating film 29 made of an insulator having a lower relative dielectric constant than the nitride insulating film 28 as a dielectric film together with the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitor element 57 can be adjusted to a desired value without increasing the film thickness of the nitride insulating film 28. As described above, the insulating film 29 does not necessarily have to be provided, but by using the insulating film 29 made of an insulator having a lower relative dielectric constant than the nitride insulating film 28 as a dielectric film together with the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitor element 57 can be adjusted to a desired value without increasing the film thickness of the nitride insulating film 28. Therefore, while securing the capacitance value necessary for obtaining high image quality, the light loss in the panel can be greatly suppressed, and the power consumption of the semiconductor device can be reduced. Therefore, while securing the capacitance value necessary for obtaining high image quality, the light loss in the panel can be greatly suppressed, and the power consumption of the semiconductor device can be reduced.

[0177] As described above, the insulating film 29 does not necessarily have to be provided, but by using the insulating film 29 made of an insulator having a lower relative dielectric constant than the nitride insulating film 28 as a dielectric film together with the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitor element 57 can be adjusted to a desired value without increasing the film thickness of the nitride insulating film 28. As described above, the insulating film 29 does not necessarily have to be provided, but by using the insulating film 29 made of an insulator having a lower relative dielectric constant than the nitride insulating film 28 as a dielectric film together with the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitor element 57 can be adjusted to a desired value without increasing the film thickness of the nitride insulating film 28. As described above, the insulating film 29 does not necessarily have to be provided, but by using the insulating film 29 made of an insulator having a lower relative dielectric constant than the nitride insulating film 28 as a dielectric film together with the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitor element 57 can be adjusted to a desired value without increasing the film thickness of the nitride insulating film 28. As described above, the insulating film 29 does not necessarily have to be provided, but by using the insulating film 29 made of an insulator having a lower relative dielectric constant than the nitride insulating film 28 as a dielectric film together with the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitor element 57 can be adjusted to a desired value without increasing the film thickness of the nitride insulating film 28.

[0178] An alignment film 52 is provided on the conductive film 45.

[0179] Also, a substrate 46 is provided so as to face the substrate 31. On the substrate 46, a shielding film 47 having a function of blocking visible light and a coloring layer 48 that transmits visible light in a specific wavelength range are provided. A resin film 50 is provided on the shielding film 47 and the coloring layer 48, and a conductive film 59 having a function as a common electrode is provided on the resin film 50. Also, an alignment film 51 is provided on the conductive film 59. Also, a substrate 46 is provided so as to face the substrate 31. On the substrate 46, a shielding film 47 having a function of blocking visible light and a coloring layer 48 that transmits visible light in a specific wavelength range are provided. A resin film 50 is provided on the shielding film 47 and the coloring layer 48, and a conductive film 59 having a function as a common electrode is provided on the resin film 50. Also, an alignment film 51 is provided on the conductive film 59. Also, a substrate 46 is provided so as to face the substrate 31. On the substrate 46, a shielding film 47 having a function of blocking visible light and a coloring layer 48 that transmits visible light in a specific wavelength range are provided. A resin film 50 is provided on the shielding film 47 and the coloring layer 48, and a conductive film 59 having a function as a common electrode is provided on the resin film 50. Also, an alignment film 51 is provided on the conductive film 59. Also, a substrate 46 is provided so as to face the substrate 31. On the substrate 46, a shielding film 47 having a function of blocking visible light and a coloring layer 48 that transmits visible light in a specific wavelength range are provided. A resin film 50 is provided on the shielding film 47 and the coloring layer 48, and a conductive film 59 having a function as a common electrode is provided on the resin film 50. Also, an alignment film 51 is provided on the conductive film 59. Also, a substrate 46 is provided so as to face the substrate 31. On the substrate 46, a shielding film 47 having a function of blocking visible light and a coloring layer 48 that transmits visible light in a specific wavelength range are provided. A resin film 50 is provided on the shielding film 47 and the coloring layer 48, and a conductive film 59 having a function as a common electrode is provided on the resin film 50. Also, an alignment film 51 is provided on the conductive film 59.

[0180] Between the substrate 31 and the substrate 46, a liquid crystal layer is disposed so as to be sandwiched between the alignment film 52 and the alignment film 51. The liquid crystal element 60 includes a conductive film 45, a conductive film 59, and a liquid crystal layer 53 including a conductive film 59. and a liquid crystal layer 53 .

[0181] In addition, in FIG. 4 and FIG. 5, the liquid crystal driving method is TN (Twisted Nematic ) mode is used as an example of driving the liquid crystal, Field Switching) mode, STN (Super Twisted Ne matic) mode, VA (Vertical Alignment) mode, MVA ( Multi-domain Vertical Alignment mode, IPS ( In-Plane Switching mode, OCB (Optically Com pensated birefringence mode, blue phase mode, TBA(T transverse bend alignment mode, VA-IPS mode, E CB(Electrically Controlled Birefringence) ) mode, FLC (Ferroelectric Liquid Crystal) mode AFLC (AntiFerroelectric Liquid Crystal) Mode, PDLC (Polymer Dispersed Liquid Crystal l) mode, PNLC (Polymer Network Liquid Crystal l) mode, guest host mode, ASV (Advanced Super View) It is also possible to apply a mode.

[0182] Also, in the liquid crystal display device according to one aspect of the present invention, for example, a thermotropic liquid crystal material classified as a liquid crystal or a lyotropic liquid crystal can be used in the liquid crystal layer. Or in the liquid crystal layer, for example, a nematic liquid crystal, a smectic liquid crystal, a cholesteric liquid crystal, or a liquid crystal material classified as a discotic liquid crystal can be used. Or, in the liquid crystal layer for example, a liquid crystal material classified as a ferroelectric liquid crystal or an antiferroelectric liquid crystal can be used. Or, in the liquid crystal layer, for example, a main-chain type polymer liquid crystal, a side-chain type polymer liquid crystal, or a liquid crystal material classified as a composite type polymer liquid crystal or a low-molecular liquid crystal can be used. Or, in the liquid crystal layer, for example, a liquid crystal material classified as a polymer dispersed liquid crystal (PDLC) can be used.

[0183] Also, a liquid crystal showing a blue phase without using an alignment film may be used in the liquid crystal layer. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a chiral agent or an ultraviolet curable resin is added to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less and is optically isotropic, so alignment treatment is unnecessary and the viewing angle dependence is small, which is preferable.

[0184] Also, in FIG. 5, a liquid crystal display device that displays a color image by using a color filter is illustrated, but the liquid crystal display device according to one aspect of the present invention may have a configuration that displays a color image by sequentially lighting a plurality of light sources that emit light of different hues.

[0185] ​​<Example Configuration 2 of Sequential Circuit> Next, a configuration example different from that of FIG. 1 of the sequential circuit according to one aspect of the present invention will be described.

[0186] FIG. 7(A) shows a configuration example of a sequential circuit 10 according to one aspect of the present invention. As shown in FIG. 7(A), the sequential circuit 10 includes transistors 80 to 86. Further, in the sequential circuit 10, a signal RES, a signal LIN, a signal RIN, a signal CK1, and a signal CK2 are input. In addition, a high-level potential VDD and a low-level potential VSS are supplied to the sequential circuit 10. Then, according to the potentials of the above signals, conduction or non-conduction of transistors 80 to 8 6 is respectively selected, and signals including the potential VSS or the potential VDD are output from the output terminal A and the output terminal B included in the sequential circuit 10.

[0187] Specifically, the gate of transistor 80 is connected to the wiring to which the signal LIN is input. One of the source and drain of transistor 80 is connected to the output terminal A, and the other is connected to the wiring to which the potential VDD is applied. The gate of transistor 81 is connected to the output terminal B. One of the source and drain of transistor 81 is connected to the wiring to which the potential VSS is applied, and the other is connected to the output terminal A. The gate of transistor 82 is connected to the wiring to which the signal CK2 is input. The source and drain of transistor 82 are, on the one hand, connected to the other of the source and drain of transistor 83, and, on the other hand, connected to the wiring to which the potential VDD is applied. The gate of transistor 83 is connected to the wiring to which the signal CK1 is input. The transistor One of the source and drain of 83 is connected to output terminal B, and the other is connected to one of the source and drain of transistor 82. The gate of transistor 84 is connected to the wiring to which signal RIN is input. One of the source and drain of transistor 84 is connected to output terminal B, and the other is connected to the wiring to which potential VDD is applied. The gate of transistor 85 is connected to the wiring to which signal LIN is input. One of the source and drain of transistor 85 is connected to the wiring to which potential VSS is applied, and the other is connected to output terminal B. The gate of transistor 86 is connected to the wiring to which signal RES is input. One of the source and drain of transistor 86 is connected to output terminal B, and the other is connected to the wiring to which potential VDD is applied.

[0188] Output terminal A of the sequential circuit 10 shown in Fig. 7(A) corresponds to output terminal OUT shown in Fig. 1(A). Transistor 80 has the function of transistor 12 in Fig. 1(A), and transistor 81 has the function of transistor 13 in Fig. 1(A). And transistors 82 to 86 have the function of circuit 11 in Fig. 1(A).

[0189] In one aspect of the present invention, at least one of transistor 80, transistor 82, transistor 83, transistor 84, transistor 85, and transistor 86 is electrically connected and overlaps with a pair of gate electrodes with a semiconductor film sandwiched therebetween. In Fig. 7(A), transistor 80, transistor 82, and transistor ​​​​​​​​​​​​​All of the resistor 83, the transistor 84, the transistor 85, and the transistor 86 are the above illustrate the case of having the pair of gate electrodes described above. By providing a pair of electrically connected gate electrodes to one or all of the plurality of transistors, even if a positive fixed charge is generated near the surface of the element substrate, it is possible to prevent a negative charge from being generated near the surface of the semiconductor film due to the fixed charge, and suppress the shift of the threshold voltage of the transistor in the negative direction. Therefore, the reliability of the sequential circuit 10, and thus the semiconductor device using the sequential circuit 10, can

[0190] be improved. Also, by electrically connecting a pair of gate electrodes, unlike the case where a certain potential is applied to only one of the pair of gate electrodes, the same potential is applied to the pair of gate electrodes, so that the channel formation region increases, and an increase in the drain current of the transistor can be realized. Therefore, it is possible to suppress a decrease in the on-current while suppressing the size of the transistor, and thus suppress the area of the sequential

[0191] circuit 10, and thus the drive circuit using the sequential circuit 10. Also, by providing a pair of electrically connected gate electrodes, the depletion layer in the semiconductor film becomes less likely to form, so that the S value (subthreshold value) of the

[0192] transistor can be improved. FIG. 8 shows, as an example, a shift register configured by connecting a plurality of stages of the

[0193] sequential circuit 10 shown in FIG. 7(A). The shift register shown in FIG. 8 has sequential The sequential circuits 10_1 to 10_y are the same as the sequential circuit 10 shown in FIG. However, in the sequential circuits 10_1 to 10_y shown in FIG. As the signal K1 and the signal CK2, any two of the signals CLK1 to CLK8 are The shift register shown in FIG. The buffer BUF has a number of buffers BUF indicated by BUF_y. The output signals from the sequential circuits 10_1 to 10_y are input to the BUF_y. Furthermore, the shift register shown in FIG. 8 is a sequential circuit 10_D used as a dummy. The output signal from the sequential circuit 10_DUM is The data is input to the buffer BUF_DUM.

[0194] Specifically, in the sequential circuit 10_8m+1, the signal CLK is used as the signal CK1 and the signal CK2. In the sequential circuit 10_8m+2, the signal CK1 As the signal CK2, the signal CLK3 and the signal CLK4 are used, respectively. In the path 10_8m+3, the signals CLK8 and CLK In the sequential circuit 10_8m+4, the signals CK1 and CK2 are used. The signals CLK5 and CLK6 are used for the sequential circuit 10_8m+5. In this example, the signals CLK2 and CLK3 are used as the signals CK1 and CK2, respectively. In the sequential circuit 10_8m+6, the signal CLK is used as the signal CK1 and the signal CK2. In the sequential circuit 10_8m+7, the signal CK1 As the signal CK1, the signal CLK4 and the signal CLK5 are used, respectively. On the 10_8m path, signals CLK1 and CLK2 are used as signals CK1 and CK2 respectively. Here, 8m to 8m + 7 are arbitrary natural numbers that satisfy the condition that the total number of sequential circuits 10 is y.

[0195] Also, in the sequential circuit 10_DUM, the signals used as signals CK1 and CK2 differ depending on the number of stages of the previous sequential circuit 10. For example, if there is a sequential circuit 10_8m + 1 in the previous stage, in the sequential circuit 10_DUM, signals CLK3 and CLK4 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 2 in the previous stage, in the sequential circuit 10_DUM, signals CLK8 and CLK1 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 3 in the previous stage, in the sequential circuit 10_DUM, signals CLK5 and CLK6 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 4 in the previous stage, in the sequential circuit 10_D UM, signals CLK2 and CLK3 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 5 in the previous stage, in the sequential circuit 10_DUM signals CLK7 and CLK8 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 6 in the previous stage, in the sequential circuit 10_DUM, signals C K1 and CK2, signals CLK4 and CLK5 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 7 in the previous stage, in the sequential circuit 10_DUM, signals CK1 and signals CK2, signals CLK1 and CLK2 are used as signals CK1 and CK2 respectively. If there is a sequential circuit in the previous stage 10_8m + 8, in the sequential circuit 10_DUM, signals CLK6 and CLK7 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 9 in the previous stage, in the sequential circuit 10_DUM signals CLK3 and CLK4 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 10 in the previous stage, in the sequential circuit 10_DUM signals CLK8 and CLK1 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 11 in the previous stage, in the sequential circuit 10_DUM signals CLK5 and CLK6 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 12 in the previous stage, in the sequential circuit 10_DUM signals CLK2 and CLK3 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 13 in the previous stage, in the sequential circuit 10_DUM signals CLK7 and CLK8 are used as signals CK1 and CK2 respectively. If there is a sequential circuit 10_8m + 14 in the previous stage, in the sequential circuit 10_DUM signals CK1 and signals CK2, signals CLK4 and CLK5 are used as signals CK1 and CK2 respectively. If there is a sequential circuit in the previous stage When there is a path 10_8m, in the sequential circuit 10_DUM, signals CK1 and CK2 are used, and signals CLK6 and CLK7 are respectively used.

[0196] Also, in the shift register shown in FIG. 8, the positions of the respective wirings connected to the sequential circuit 10_j (where j is a natural number less than or equal to y) are schematically shown in FIG. 7(B). As can be understood from FIGS. 8 and 7(B), in the sequential circuit 10_j, as the signal LIN, the output signal from the output terminal GOUT5(j - 2)+5 of the buffer BUF connected to the output terminal A and the output terminal B of the previous sequential circuit 10_j - 1 is used. However, in the first-stage sequential circuit 10_1, the signal SP is used as the signal LIN.

[0197] Also, in the sequential circuit 10_j, as the signal RIN, the output signal from the output terminal GOUT5j+2 of the buffer BUF connected to the output terminal A and the output terminal B of the subsequent sequential circuit 10_j + 1 is used. However, in the y-th stage sequential circuit 10_y, the output signal from the output terminal OUT2 of the buffer BUF_DUM connected to the output terminal A and the output terminal B of the sequential circuit 10_DUM is used.

[0198] Also, in the shift register shown in FIG. 8, the positions of the respective wirings connected to the buffer BUF are schematically shown in FIG. 9(A). As shown in FIG. 9(A), in addition to the output signals from the output terminal A and the output terminal B of the sequential circuit 10, signals CK1 to CK5 are input to the buffer BUF. In the buffer BUF, any five of the signals CLK1 to CLK8 are respectively used as the signals CK1 to CK5.

[0199] ​​​​​​​​​​​​​​Specifically, in buffer BUF_8m+1, signals CLK1 to CLK5 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+2, signals CLK6 to CLK8, signal CLK1, and signal CLK2 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+3, signals CLK3 to CLK7 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+4, signal CLK8, and signals CLK1 to CLK4 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+5, signals CLK5 to CLK8 and signal CLK1 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+6, signals CLK2 to CLK6 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+7, signals CLK7 and CLK8, and signals CLK1 to CLK3 are used as signals CK1 to CK5, respectively. In buffer BUF_8m, signals CLK4 to CLK8 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+1, signals CLK1 to CLK5 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+2, signals CLK6 to CLK8, signal CLK1, and signal CLK2 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+3, signals CLK3 to CLK7 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+4, signal CLK8, and signals CLK1 to CLK4 are used as signals CK1 to CK5, respectively. In buffer BUF_8m+5, signals CLK5 to CLK8 and signal CLK1 are used as signals CK1 to CK5, respectively.

[0200] Also, in the shift register shown in FIG. 8, the positions of the respective lines connected to buffer BUF_DUM are schematically shown in FIG. 9(B). As shown in FIG. 9(B), in buffer BUF_DUM, in addition to the output signals from output terminal A and output terminal B of sequential circuit 10, signals CK1 and CK2 are input. In buffer BUF_DUM, any two of signals CLK1 to CLK8 are used as signals CK1 and CK2, respectively. As shown in FIG. 9(B), in buffer BUF_DUM, in addition to the output signals from output terminal A and output terminal B of sequential circuit 10, signals CK1 and CK2 are input. In buffer BUF_DUM, any two of signals CLK1 to CLK8 are used as signals CK1 and CK2, respectively. UM, in addition to the output signals from output terminal A and output terminal B of sequential circuit 10, signals CK1 and CK2 are input. In buffer BUF_DUM, any two of signals CLK1 to CLK8 are used as signals CK1 and CK2, respectively. In buffer BUF_DUM, signals CK1 and CK2 are input. In buffer BUF_DUM, any two of signals CLK1 to CLK8 are used as signals CK1 and CK2, respectively. In buffer BUF_DUM, signals CK1 and CK2 are input. In buffer BUF_DUM, any two of signals CLK1 to CLK8 are used as signals CK1 and CK2, respectively. In buffer BUF_DUM, signals CK1 and CK2 are input. In buffer BUF_DUM, any two of signals CLK1 to CLK8 are used as signals CK1 and CK2, respectively.

[0201] In buffer BUF_DUM, the signals used as signal CK1 and signal CK2 are different depending on the number of stages of the previous buffer BUF. For example, if there is a buffer BUF_8m+1 in the previous stage, in buffer BUF_DUM, as signal CK1 and signal CK2, signal CLK6 and signal CLK7 are respectively used. If there is a buffer BUF_8m+2 in the previous stage, in buffer BUF_DUM, as signal CK1 and signal CK2, signal CLK3 and signal CLK4 are respectively used. If there is a buffer BUF_8m+3 in the previous stage, in buffer BUF_DUM, as signal CK1 and signal CK2, signal CLK8 and signal CLK1 are respectively used. If there is a buffer BUF_8m+4 in the previous stage, in buffer BUF_DUM, as signal CK1 and signal CK2, signal CLK5 and signal CL K6 are respectively used. If there is a buffer BUF_8m+5 in the previous stage, in buffer BUF_DUM, as signal CK1 and signal CK2, signal CLK2 and signal CLK3 are respectively used. If there is a buffer BUF_8m+6 in the previous stage, in buffer BUF_DUM, as signal CK1 and signal CK2, signal CLK7 and signal CLK8 are respectively used. If there is a buffer BUF_8m+7 in the previous stage, in buffer BUF_DUM, as signal CK1 and signal CK2, signal CLK4 and signal CLK5 are respectively used. If there is a buffer BUF_8m in the previous stage, in buffer BUF_DUM, as signal CK1 and signal CK2, signal CLK1 and signal CLK2 are respectively used.

[0202] Also, buffers BUF_1 to BUF_y respectively have output terminals OUT1 to OUT It has a power terminal OUT5. All the output signals GOUT1 to GOUTy are respectively output from the power terminals OUT1 to OUT5. The buffer BUF_DUM has output terminals DUMOUT1 and DUMOUT2.

[0203] FIG. 9(C) shows an example of a more specific configuration of the buffer BUF. The buffer BUF shown in FIG. 9(C) has five buffers 90. In each buffer 90, in addition to the output signals from the output terminals A and B of the sequential circuit 10, any one of the signals CK1 to CK5 is respectively input. And the output terminals of the five buffers 90 respectively correspond to the output terminals OUT1 to OUT5 of the buffer BUF.

[0204] Note that in FIGS. 8, 9(A), and 9(C), the case where the buffer BUF has five buffers 90 is illustrated, but the number of buffers 90 that the buffer BUF has may be a plural number other than five or a single number. The larger the number of buffers 90 that the buffer BUF has, the smaller the number of sequential circuits 10 in the shift register can be suppressed, so the area of the drive circuit having the shift register can be reduced, and the narrow bezel of the semiconductor display device can be realized.

[0205] Also, FIG. 9(D) shows an example of a more specific configuration of the buffer BUF_DUM. The buffer BUF_DUM shown in FIG. 9(D) has two buffers 90. In each buffer 90, in addition to the output signals from the output terminals A and B of the sequential circuit 10_DUM, the signal C Either one of K1 and signal CK2 is input respectively. And each output terminal of the two buffers 90 corresponds to the output terminal OUT1 and the output terminal OUT 2 of the buffer BUF_DUM respectively. In FIGS. 8, 9(B) and 9(D), the buffer BUF _DUM illustrates the case of having two buffers 90, but the number of buffers 90 that the buffer BUF_DU M has may be a plurality other than two, or may be a single number.

[0206] FIG. 10 shows a more specific configuration example of the buffer 90. The buffer 90 shown in FIG. 10 has transistors 91 to 93. The gate of the transistor 91 is connected to the wiring to which the potential V DD is applied. Also, one of the source and drain of the transistor 91 is connected to the output terminal B of the sequential circuit 10_DUM, and the other of the source and drain is connected to the gate of the transistor 92. One of the source and drain of the transistor 92 is connected to any one of the output terminals OUT1 to OUT5 of the buffer 90 (shown as the output terminal OUT in FIG. 10), and the other of the source and drain is connected to the wiring to which any one of the signals CK1 to CK5 (shown as the signal CK in FIG. 10) is input. The gate of the transistor 93 is connected to the output terminal A of the sequential circuit 10_DU M. Also, one of the source and drain of the transistor 93 is connected to the wiring to which the potential VSS is applied, and the other of the source and drain is connected to any one of the output terminals OUT1 to OUT5 of the output terminal (shown as the output terminal OUT in FIG. 10). connected. is connected to the wiring to which the potential VSS is applied, and the other of the source and drain is the output terminal OUT1 to any one of the output terminals OUT5 (shown as the output terminal OUT in FIG. 10) is connected.

[0207] And, in one aspect of the present invention, a signal CK is applied to the other of the source and the drain of the transistor 92, which has a pair of gate electrodes that are electrically connected and overlap with each other with a semiconductor film interposed therebetween. By providing the pair of electrically connected gate electrodes in the transistor 9 2, even if positive fixed charges are generated near the surface of the element substrate, it is possible to prevent negative charges from being generated near the surface of the semiconductor film due to the fixed charges, and to suppress the threshold voltage of the transistor 92 from shifting in the negative direction. Therefore, the reliability of the buffer BUF, and by extension, the semiconductor device using the buffer BUF, can be improved. Moreover, by electrically connecting the pair of gate electrodes, the same potential is applied to the pair of gate electrodes, unlike the case where a certain potential is applied to only one of the pair of gate electrodes. As a result, the channel formation region increases, and an increase in the drain current of the transistor 92 can be realized. Therefore, it is possible to suppress a decrease in the on-current while keeping the size of the transistor 92 small,

[0208] and thus suppress the area of the buffer BUF, and by extension, the drive circuit using the buffer BUF. In particular, for the transistor 92 provided on the output side of the buffer BUF, since a larger current supply capacity is required than for the transistor 91, by having the pair of gate electrodes as described above for the transistor 92, it can be said that the effect of suppressing the area of the buffer BUF or the drive circuit is greater compared to the case where the same configuration is applied to the transistor 91. Also, by providing the pair of electrically connected gate electrodes, the depletion layer in the semiconductor film is reduced, so that the S value (subthreshold value) of the transistor 92 can be improved. .

[0209] Also, by providing the pair of electrically connected gate electrodes, the depletion layer in the semiconductor film is reduced, so that the S value (subthreshold value) of the transistor 92 can be improved. It is.

[0210] 〈Regarding the semiconductor film〉 In addition, impurities such as moisture or hydrogen serving as an electron donor (donor) are reduced, and furthermore, an oxide semiconductor (purified Oxi de Semiconductor) is highly purified by reducing oxygen vacancies. Since it has few carrier generation sources, it can be of the i-type (intrinsic semiconductor) or extremely close to the i-type. Therefore, a transistor having a channel formation region in the highly purified oxide semiconductor film has an extremely small off-current and high reliability. And a transistor in which a channel formation region is formed in the oxide semiconductor film tends to have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. Specifically, the fact that the off-current of a transistor having a channel formation region in a highly purified oxide semiconductor film is small can be proven by various experiments. For example, even in an element with a channel width of 1 × 1 μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current can be below the measurement limit of a semiconductor parameter analyzer, that is, 1 × 10 . In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit is used in which a capacitor element and a transistor are connected and the charge flowing into or out of the capacitor element is controlled by the transistor to measure the off-current.

[0211] In the measurement, a highly purified oxide semiconductor film is used as the channel of the above transistor. The small off-current of the transistor having a channel formation region in the highly purified oxide semiconductor film can be proven by various experiments. For example, even in an element with a channel width of 1 × 1 0 6 μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current can be below the measurement limit of a semiconductor parameter analyzer, that is, 1 × 10 (drain voltage) is in the range of 1 V to 10 V, the off-current can be below the measurement limit of a semiconductor parameter analyzer, that is, 1 × 10 A or less. -13 That is, characteristics of 1 × 10 A or less can be obtained. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit is used in which a capacitor element and a transistor are connected and the charge flowing into or out of the capacitor element is controlled by the transistor to measure the off-current. In the measurement, a highly purified oxide semiconductor film is used as the channel of the above transistor. And a circuit is used in which a capacitor element and a transistor are connected and the charge flowing into or out of the capacitor element is controlled by the transistor to measure the off-current. In the measurement, a highly purified oxide semiconductor film is used as the channel of the above transistor. It is used for the formation region, and the off current of the transistor is measured from the change in the amount of charge per unit time of the capacitive element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor was 3V, an even smaller off current of several tens of yA / μm could be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for the channel formation region has a significantly smaller off current than a transistor using crystalline silicon. When an oxide semiconductor film is used as the semiconductor film, the oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In addition, it preferably has gallium (Ga) as a stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide semiconductor.

[0212] It is also preferable to have tin (Sn) as a stabilizer. It is also preferable to have hafnium (Hf) as a stabilizer. It is also preferable to have aluminum (Al) as a stabilizer. It is also preferable to contain zirconium (Zr) as a stabilizer. Among oxide semiconductors, In-Ga-Zn-based oxides, In-Sn-Zn-based oxides, etc. are different from silicon carbide, gallium nitride, or gallium oxide. Transistors with excellent electrical characteristics can be fabricated by sputtering or wet methods, and they have advantages such as excellent mass productivity. Also, different from silicon carbide, gallium nitride, or gallium oxide, the above In-Ga-Zn-based oxide can be used to fabricate transistors with excellent electrical characteristics on a glass substrate.

[0213] It is also possible to support the enlargement of the substrate size. ​​​​

[0214] Also, as other stabilizers, any one or more of lanthanoids including lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol mium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lut etium (Lu) may be included.

[0215] For example, as the oxide semiconductor, indium oxide, gallium oxide, tin oxide, zinc oxide, I n-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, S n-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also denoted as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, I n-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Pr-Zn-based oxide, In -Nd-Zn-based oxide, In-Ce-Zn-based oxide, In-Sm-Zn-based oxide, In- Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-D y-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm -Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn- Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf- Al-Zn-based oxide can be used.

[0216] Note that, for example, an In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Further, it may contain metal elements other than In, Ga, and Zn. The In-Ga-Zn-based oxide has a sufficiently high resistance in the absence of an electric field, can sufficiently reduce the off-current, and also has a high mobility. For example, a relatively high mobility can be easily obtained in an In-Sn-Zn-based oxide. However, even in an In-Ga-Zn-based oxide, the mobility can be increased by reducing the density of defects in the bulk. Hereinafter, the structure of the oxide semiconductor film will be described. The oxide semiconductor film is roughly classified into a single-crystalline oxide semiconductor film and a non-single-crystalline oxide semiconductor film. The non-single-crystalline oxide semiconductor film refers to an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a CAAC-OS film, and the like.

[0217] An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal component. It is typical of an oxide semiconductor film that has no crystal part even in a minute region and the whole film has a complete amorphous structure. A microcrystalline oxide semiconductor film contains, for example, microcrystals (also referred to as nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film is characterized by having a lower density of defect levels than the amorphous oxide semiconductor film.

[0218]

[0219]

[0220]

[0221]

[0222] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts have a size that fits within a cube with a side length of less than 100 nm. Therefore, the crystal parts included in the CAAC-O S film also include cases where the size fits within a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. The CAAC-OS film is characterized by having a lower density of defect levels than the microcrystalline oxide semiconductor film. When the CAAC-OS film is observed by a transmission electron microscope (TEM: Transmission Electron Microscope), a clear boundary between the crystal parts, that is, a grain boundary (also referred to as a grain boundary), cannot be confirmed. Therefore, it can be said that the CAAC-OS film is less likely to cause a decrease in electron mobility due to grain boundaries. When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation ), it can be confirmed that the metal atoms are arranged in layers in the crystal parts. Each layer of the metal atoms has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film. In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular"

[0223] means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included. On the other hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TE M observation

[0224] ), it can be confirmed that the metal atoms are arranged in layers in the crystal parts. Each layer of the metal atoms has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film. In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore,

[0225] cases of 85° or more and 95° or less are also included. When observed, in the crystal part, it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystal parts. None.

[0226] From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has orientation. It can be understood that it exists.

[0227] When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) device, for example, in the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. In the analysis by the out-of-plane method of the CAAC-OS film having InGaZnO4 crystals, a peak may appear near a diffraction angle (2θ) of 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. It can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface.

[0228] On the other hand, in the in-plane method analysis in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. If it is a single crystal oxide semiconductor film of InGaZnO4, when analyzing (φ scan) while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, even when performing φ scan with 2θ fixed near 56°, no distinct peak appears. If it is a single crystal oxide semiconductor film of InGaZnO4, when analyzing (φ scan) while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, even when performing φ scan with 2θ fixed near 56°, no distinct peak appears. Even when performing φ scan with 2θ fixed near 56°, no distinct peak appears.

[0229] From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has c-axis orientation, and it can be seen that the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-described cross-sectional TEM observation is a plane parallel to the ab-plane of the crystal. Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. In addition, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak with 2θ near 31°, a peak may also appear with 2θ near 36°. The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. The CAAC-OS film has a peak with 2θ near 31°.

[0230] Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. In addition, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak with 2θ near 31°, a peak may also appear with 2θ near 36°. The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. The CAAC-OS film has a peak with 2θ near 31°. Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. In addition, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially.

[0231] In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak with 2θ near 31°, a peak may also appear with 2θ near 36°. The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. The CAAC-OS film has a peak with 2θ near 31°. Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. In addition, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak with 2θ near 31°, a peak may also appear with 2θ near 36°. The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. The CAAC-OS film has a peak with 2θ near 31°. Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film.

[0232] In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak with 2θ near 31°, a peak may also appear with 2θ near 36°. The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. The CAAC-OS film has a peak with 2θ near 31°. In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak with 2θ near 31°, a peak may also appear with 2θ near 36°. The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. The CAAC-OS film has a peak with 2θ near 31°. In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak with 2θ near 31°, a peak may also appear with 2θ near 36°. The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. The CAAC-OS film has a peak with 2θ near 31°. In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak with 2θ near 31°, a peak may also appear with 2θ near 36°. The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. The CAAC-OS film has a peak with 2θ near 31°. It is preferable to show a peak and not to show a peak in the vicinity of 2θ = 36°.

[0233] The transistor using the CAAC-OS film has little change in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0234] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. Further, in order to form the CAAC-OS film, it is preferable to apply the following conditions.

[0235] Further, in order to form the CAAC-OS film, it is preferable to apply the following conditions.

[0236] By reducing the inclusion of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the processing chamber may be reduced. Further, the impurity concentration in the film-forming gas may be reduced. Specifically, a film-forming gas having a dew point of -80°C or lower, preferably -100°C or lower is used. By reducing the inclusion of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the processing chamber may be reduced. Further, the impurity concentration in the film-forming gas may be reduced. Specifically, a film-forming gas having a dew point of -80°C or lower, preferably -100°C or lower is used.

[0237] Further, by increasing the substrate heating temperature during film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower for film formation. By increasing the substrate heating temperature during film formation, when plate-shaped or pellet-shaped sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower for film formation. By increasing the substrate heating temperature during film formation, when plate-shaped or pellet-shaped sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate.

[0238] Further, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film-forming gas and optimizing the power. The oxygen ratio in the film-forming gas is 30% by volume or more, preferably 100% by volume. Let it be the product %.

[0239] As an example of the target, an In-Ga-Zn-based oxide target is shown below.

[0240] InO X powder, GaO Y powder and ZnO Z Mix the powders in a predetermined molar ratio, and after pressure treatment , heat-treat at a temperature of 1000 °C or higher and 1500 °C or lower to obtain a polycrystalline In-Ga -Zn-based oxide target. Here, X, Y, and Z are arbitrary positive numbers. Here, the predetermined molar ratio is, for example, InO X powder, GaO Y powder and ZnO Z powder are 2:1: 3, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 There is. Note that the type of powder and the molar ratio for mixing may be appropriately changed according to the target to be produced.

[0241] Note that since alkali metals are not elements constituting the oxide semiconductor, they are impurities. Alkali earth metals also become impurities when they are not elements constituting the oxide semiconductor. In particular , among alkali metals, Na diffuses into the insulating film in the case where the insulating film in contact with the oxide semiconductor film is an oxide, and becomes Na . Further, Na breaks or interrupts the bond between the metal and oxygen constituting the oxide semiconductor in the oxide semiconductor film. As a result + . For example, abnormal ionization occurs due to the threshold voltage shifting in the negative direction, and the mobility decreases . As a result, deterioration of the electrical characteristics of the transistor, such as a decrease in mobility, occurs, and in addition, variations in characteristics also occur. Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5×10 16 ​ / cm 3 hereinafter 、 preferably 1×10 16 / cm 3 or less, more preferably 1×10 15 / cm 3 or less. Similarly, the measured value of the Li concentration is 5×10 / cm 15 or less, preferably 1×1 3 0 / cm 15 or less. Similarly, the measured value of the K concentration is 5×10 3 / cm 15 or less, preferably 1×10 3 / cm or less. 15 / cm 3 It is preferable to be as follows.

[0242] In addition, when a metal oxide containing indium is used, silicon or carbon having a binding energy with oxygen greater than that of indium may break the bond between indium and oxygen and form oxygen vacancies. Therefore, if silicon or carbon is mixed in the oxide semiconductor film, the electrical characteristics of the transistor are likely to deteriorate, similar to the case of alkali metals and alkaline earth metals. Therefore, it is desirable that the concentration of silicon or carbon in the oxide semiconductor film is low. Specifically, the measured value of the C concentration or the Si concentration by secondary ion mass spectrometry is preferably 1×10 / cm or less. With the above configuration, deterioration of the electrical characteristics of the transistor can be prevented, and the reliability of the semiconductor device can be improved.

[0243] 18 / cm 3 or less.

[0243] In addition, depending on the conductive material used for the source electrode and the drain electrode, the metal in the source electrode and the drain electrode may extract oxygen from the oxide semiconductor film. In this case, the acid Among the oxide semiconductor films, the regions in contact with the source electrode and the drain electrode are n-type formed by the formation of oxygen vacancies. The n-type formed regions function as source regions or drain regions, so the contact resistance between the oxide semiconductor film and the source electrode and the drain electrode can be reduced.

[0244] Since the n-type formed regions function as source regions or drain regions, the contact resistance between the oxide semiconductor film and the source electrode and the drain electrode can be reduced. Thus, by forming the n-type formed regions, the mobility and on-current of the transistor can be increased, thereby enabling the high-speed operation of the semiconductor device using the transistor. Therefore, by forming the n-type formed regions, the mobility and on-current of the transistor can be increased, thereby enabling the high-speed operation of the semiconductor device using the transistor. Thus, by forming the n-type formed regions, the mobility and on-current of the transistor can be increased, thereby enabling the high-speed operation of the semiconductor device using the transistor. This can be achieved.

[0245] Note that the extraction of oxygen by the metal in the source electrode and the drain electrode may occur when the source electrode and the drain electrode are formed by a sputtering method or the like, or may also occur by a heat treatment performed after the source electrode and the drain electrode are formed. Note that the extraction of oxygen by the metal in the source electrode and the drain electrode may occur when the source electrode and the drain electrode are formed by a sputtering method or the like, or may also occur by a heat treatment performed after the source electrode and the drain electrode are formed. This can also occur by a heat treatment performed after the source electrode and the drain electrode are formed.

[0246] In addition, the regions to be n-type formed are more easily formed by using a conductive material that easily binds to oxygen for the source electrode and the drain electrode. Examples of the conductive material include Al, Cr, Cu, Ta, Ti, Mo, W, and the like. In addition, the regions to be n-type formed are more easily formed by using a conductive material that easily binds to oxygen for the source electrode and the drain electrode. Examples of the conductive material include Al, Cr, Cu, Ta, Ti, Mo, W, and the like. Examples of the conductive material include Al, Cr, Cu, Ta, Ti, Mo, W, and the like.

[0247] In addition, the oxide semiconductor film is not necessarily composed of a single metal oxide film, and may be composed of a plurality of stacked metal oxide films. For example, in the case of a semiconductor film in which the first to third metal oxide films are stacked in sequence, the first metal oxide film and the third metal oxide film contain at least one of the metal elements constituting the second metal oxide film in their components, and the energy at the bottom of the conduction band is 0.05 eV or more, 0.07 eV or more, 0. In addition, the oxide semiconductor film is not necessarily composed of a single metal oxide film, and may be composed of a plurality of stacked metal oxide films. For example, in the case of a semiconductor film in which the first to third metal oxide films are stacked in sequence, the first metal oxide film and the third metal oxide film contain at least one of the metal elements constituting the second metal oxide film in their components, and the energy at the bottom of the conduction band is 0.05 eV or more, 0.07 eV or more, 0. In the case of a semiconductor film in which the first to third metal oxide films are stacked in sequence, the first metal oxide film and the third metal oxide film contain at least one of the metal elements constituting the second metal oxide film in their components, and the energy at the bottom of the conduction band is 0.05 eV or more, 0.07 eV or more, 0. In the case of a semiconductor film in which the first to third metal oxide films are stacked in sequence, the first metal oxide film and the third metal oxide film contain at least one of the metal elements constituting the second metal oxide film in their components, and the energy at the bottom of the conduction band is 0.05 eV or more, 0.07 eV or more, 0. The energy at the bottom of the conduction band is 0.05 eV or more, 0.07 eV or more, 0. An oxide film that is above 1 eV or above 0.15 eV, and below 2 eV, 1 eV, 0.5 eV or further below 0.4 eV, and is close to the vacuum level. Furthermore, it is preferable that the second metal oxide film contains at least indium because the carrier mobility increases.

[0248] When the transistor has a semiconductor film with the above configuration, by applying a voltage to the gate electrode, when an electric field is applied to the semiconductor film, a channel region is formed in the second metal oxide film where the energy at the lower end of the conduction band is small. That is, due to the presence of the third metal oxide film between the second metal oxide film and the gate insulating film, a channel region can be formed in the second metal oxide film that is separated from the gate insulating film. Furthermore, since the third metal oxide film contains at least one of the metal elements constituting the second metal oxide film as its components, interface scattering is less likely to occur at the interface between the second metal oxide film and the third metal oxide film. Therefore, the movement of carriers is less likely to be inhibited at this interface, and the field-effect mobility of the transistor increases.

[0249] Also, when interface levels are formed at the interface between the second metal oxide film and the first metal oxide film, channel regions are also formed in the regions near the interface, causing fluctuations in the threshold voltage of the transistor. However, since the first metal oxide film contains at least one of the metal elements constituting the second metal oxide film as its components, interface levels are less likely to be formed at the interface between the second metal oxide film and the first metal oxide film. Therefore, with the above configuration, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

[0250]

[0251] ​​​​​​​​​In addition, in order to prevent the formation of interface levels that inhibit the flow of carriers at the interface of each film due to the presence of impurities between the metal oxide films, it is desirable to stack a plurality of oxide semiconductor films. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and carriers are trapped or disappear due to recombination in the vicinity of the interface. By reducing the impurities between the films, it is easier to form a continuous junction (in particular, a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the films) than simply stacking a plurality of metal oxide films having at least one common metal as the main component. To form a continuous junction, it is necessary to continuously stack each film without exposing it to the atmosphere using a multi-chamber film-forming apparatus (sputtering apparatus) equipped with a load lock chamber. Each chamber in the sputtering apparatus is preferably evacuated to a high vacuum (up to about 5×10 Pa to 1×10 Pa) using an adsorption-type vacuum exhaust pump such as a cryopump to remove water and other substances that become impurities for the oxide semiconductor as much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas from flowing back into the chamber from the exhaust system. In order to obtain a high-purity intrinsic oxide semiconductor, it is important not only to evacuate each chamber to a high vacuum, but also to purify the gas used for sputtering to a high purity. The dew point of the oxygen gas or argon gas used as the above gas should be -40°C or lower, preferably -80°C or lower, more preferably - To form a continuous junction, it is necessary to continuously stack each film without exposing it to the atmosphere using a multi-chamber film-forming apparatus (sputtering apparatus) equipped with a load lock chamber. Each chamber in the sputtering apparatus is preferably evacuated to a high vacuum (up to about 5×10 Pa to 1×10 Pa) using an adsorption-type vacuum exhaust pump such as a cryopump to remove water and other substances that become impurities for the oxide semiconductor as much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas from flowing back into the chamber from the exhaust system.

[0252] In order to obtain a high-purity intrinsic oxide semiconductor, it is important not only to evacuate each chamber to a high vacuum, but also to purify the gas used for sputtering to a high purity. The dew point of the oxygen gas or argon gas used as the above gas should be -40°C or lower, preferably -80°C or lower, more preferably - (sputtering apparatus) to stack them continuously without exposing them to the atmosphere. Each chamber in the sputtering apparatus should be evacuated to a high vacuum (up to about 5×10 Pa to 1×10 Pa) using an adsorption-type vacuum exhaust pump such as a cryopump to remove water and other substances that become impurities for the oxide semiconductor as much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas from flowing back into the chamber from the exhaust system. In addition, in order to prevent the formation of interface levels that inhibit the flow of carriers at the interface of each film due to the presence of impurities between the metal oxide films, it is desirable to stack a plurality of oxide semiconductor films. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and carriers are trapped or disappear due to recombination in the vicinity of the interface. By reducing the impurities between the films, it is easier to form a continuous junction (in particular, a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the films) than simply stacking a plurality of metal oxide films having at least one common metal as the main component. -7 Pa to 1×10 -4 Pa) using an adsorption-type vacuum exhaust pump such as a cryopump to remove water and other substances that become impurities for the oxide semiconductor as much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas from flowing back into the chamber from the exhaust system. In addition, in order to prevent the formation of interface levels that inhibit the flow of carriers at the interface of each film due to the presence of impurities between the metal oxide films, it is desirable to stack a plurality of oxide semiconductor films. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and carriers are trapped or disappear due to recombination in the vicinity of the interface. By reducing the impurities between the films, it is easier to form a continuous junction (in particular, a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the films) than simply stacking a plurality of metal oxide films having at least one common metal as the main component. To form a continuous junction, it is necessary to continuously stack each film without exposing it to the atmosphere using a multi-chamber film-forming apparatus (sputtering apparatus) equipped with a load lock chamber. Each chamber in the sputtering apparatus is preferably evacuated to a high vacuum (up to about 5×10

[0253] In addition, in order to prevent the formation of interface levels that inhibit the flow of carriers at the interface of each film due to the presence of impurities between the metal oxide films, it is desirable to stack a plurality of oxide semiconductor films. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and carriers are trapped or disappear due to recombination in the vicinity of the interface. By reducing the impurities between the films, it is easier to form a continuous junction (in particular, a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the films) than simply stacking a plurality of metal oxide films having at least one common metal as the main component. In addition, in order to prevent the formation of interface levels that inhibit the flow of carriers at the interface of each film due to the presence of impurities between the metal oxide films, it is desirable to stack a plurality of oxide semiconductor films. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and carriers are trapped or disappear due to recombination in the vicinity of the interface. By reducing the impurities between the films, it is easier to form a continuous junction (in particular, a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the films) than simply stacking a plurality of metal oxide films having at least one common metal as the main component. 100°C or lower. Set it to 100 °C or lower and purify the gas used to prevent moisture and the like from being incorporated into the oxide semiconductor film as much as possible. Specifically, when the second metal oxide film is In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), in the target used to form the second metal oxide film, if the atomic ratio of the metal elements is In:M:Zn = x1:y1:z1 then x1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, and z1 / y1 is preferably 1 / 3 or more and 6 or less, further 1 or more and 6 or less. By setting z1 / y1 to 1 or more and 6 or less, a CAAC-OS film is likely to be formed as the second metal oxide film. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3 、 :1:2, etc. Specifically, when the first metal oxide film and the third metal oxide film are In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), in the target used to form the first metal oxide film and the third metal oxide film, if the atomic ratio of the metal elements is In:M:Zn = x2:y2:z2 then x2 / y2 < x1 / y1, and z2 / y2 is preferably 1 / 3 or more and 6 or less, further 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less, a CAAC-OS film is likely to be formed as the first metal oxide film and the third metal oxide film. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, In:M :Zn = 1:3:8, etc.

[0254] Specifically, when the first metal oxide film and the third metal oxide film are In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), in the target used to form the first metal oxide film and the third metal oxide film, if the atomic ratio of the metal elements is In:M:Zn = x2:y2:z2 then x2 / y2 < x1 / y1, and z2 / y2 is preferably 1 / 3 or more and 6 or less, further 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less, a CAAC-OS film is likely to be formed as the first metal oxide film and the third metal oxide film. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, In:M 、 :Zn = 1:3:8, etc. or more and 6 or less, further 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less, a CAAC-OS film is likely to be formed as the first metal oxide film and the third metal oxide film. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, In:M :Zn = 1:3:8, etc. By setting z2 / y2 to 1 or more and 6 or less, a CAAC-OS film is likely to be formed as the first metal oxide film and the third metal oxide film. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, In:M :Zn = 1:3:8, etc. ​

[0255] Note that the thickness of the first metal oxide film and the third metal oxide film is 3 nm or more and 100 nm or less , preferably 3 nm or more and 50 nm or less. Also, the thickness of the second metal oxide film is 3 n m or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0256] In the three-layer semiconductor film, the first to third metal oxide films can take both amorphous and crystalline forms. However, since the second metal oxide film in which the channel region is formed being crystalline can impart stable electrical characteristics to the transistor, it is preferable that the second metal oxide film be crystalline.

[0257] Note that the channel formation region means the region of the semiconductor film of the transistor that overlaps with the gate electrode and is sandwiched between the source electrode and the drain electrode. Also, the channel region means the region where current mainly flows in the channel formation region.

[0258] For example, when using an In-Ga-Zn-based oxide film formed by sputtering as the first and third metal oxide films, a target of In-Ga-Zn-based oxide (In:Ga:Zn = 1:3:2 [atomic number ratio]) can be used for forming the first and third metal oxide films. The film formation conditions may be, for example, using argon gas at 30 sccm and oxygen gas at 15 sccm as the film formation gas, setting the pressure at 0.4 Pa, the substrate temperature at 200 °C, and the DC power at 0.5 kW.

[0259] When the second metal oxide film is a CAAC-OS film, in the formation of the second metal oxide film is an In-Ga-Zn-based oxide (In:Ga:Zn = 1:1:1 [atomic ratio]), it is preferable to use a target containing polycrystalline In-Ga-Zn-based oxide. The film formation conditions are, for example, using 30 sccm of argon gas and 15 sccm of oxygen gas as the film formation gas , setting the pressure to 0.4 Pa, the temperature of the substrate to 300 °C, and the DC power to 0.5 kW, which is possible.

[0260] Note that the transistor may have a structure in which the end of the semiconductor film is inclined, or may have a structure in which the end of the semiconductor film is rounded.

[0261] Also, when using a semiconductor film having a plurality of stacked metal oxide films for a transistor, the region in contact with the source electrode and the drain electrode may be n-type. With the above structure , the mobility and on-current of the transistor can be increased, and high-speed operation of a semiconductor device using the transistor can be realized. Further, when using a semiconductor film having a plurality of stacked metal oxide films for a transistor, the region to be n-type reaching the second metal oxide film that becomes the channel region is more preferable for increasing the mobility and on-current of the transistor and realizing further high-speed operation of the semiconductor device.

[0262] <Manufacturing method> Next, taking a liquid crystal display device as an example, an example of a method for manufacturing a semiconductor display device according to one aspect of the present invention will be described with reference to FIGS. 11 to 14. In FIGS. 11 to 14, the transistor 56 included in the pixel 55 shown in FIG. 5 and the transistor included in the drive circuit shown in FIG. 2 ​A method for manufacturing an element substrate having a resistor 20 will be described.

[0263] As shown in FIG. 11(A), a conductive film is formed on a substrate 31, and then the conductive film is etched. The conductive film 21 and the conductive film 40 are formed by processing (patterning) the shape by the above-mentioned methods. .

[0264] The substrate 31 is preferably a substrate having a heat resistance sufficient to withstand the subsequent manufacturing steps. For example, a glass substrate, a quartz substrate, a ceramic substrate, a sapphire substrate, etc. may be used.

[0265] The conductive film 21 and the conductive film 40 may be made of aluminum, titanium, chromium, cobalt, nickel, etc. Ru, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum and tantalum It is preferable to use a film made of a conductive material containing one or more types of tin. For example, the conductive film 21 and the conductive film 40 may be formed by laminating a copper film on a tungsten nitride film. A conductive film or a single-layer tungsten film can be used. In this embodiment, the conductive film 21 The conductive film 40 is a tungsten film having a thickness of 200 nm.

[0266] Next, as shown in FIG. 11B, an insulating film 2 is formed so as to cover the conductive film 21 and the conductive film 40. After forming the insulating film 22, the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide The semiconductor film 42a is formed. Note that the oxide semiconductor film 23 is formed in a position overlapping with the conductive film 21. The oxide semiconductor film 41 is formed at a position overlapping with the conductive film 40 .

[0267] The insulating film 22 may be made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, Silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide may be used singly or in combination as a laminate. One or more types of the above oxides may be used. The insulating film may be used either as a single layer or as a laminate.

[0268] In this specification, oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and nitroxide refers to a material having a higher nitrogen content than oxygen in its composition. refers to.

[0269] For example, when the insulating film 22 has a two-layer structure, a multilayer film having a first layer made of a silicon nitride film and a second layer made of a silicon oxide film may be used. The second silicon oxide film may be a silicon oxynitride film. Further, the first silicon nitride film may be a silicon oxynitride film. In this embodiment, a silicon nitride film having a thickness of 400 nm and a silicon oxynitride film having a thickness of 50 nm are sequentially laminated and used as the insulating film 22. The second silicon oxide film can be a silicon oxynitride film. Also, the first silicon nitride film can be a silicon oxynitride film. In this embodiment, a silicon nitride film having a thickness of 400 nm and a silicon oxynitride film having a thickness of 50 nm are sequentially laminated and used as the insulating film 22. It is preferable to use a silicon oxide film having a low defect density. Specifically, a silicon oxide film having a spin density of spins derived from a signal having a g value of 2.001 in electron spin resonance (ESR) of 3 × 10 spins / cm

[0270] or less, preferably 5 × 10 spins / cm 17 or less is used. It is preferable to use a silicon oxide film having an excessive amount of oxygen. For the silicon nitride film, a silicon nitride film having a small amount of hydrogen and ammonia release is used. The release amounts of hydrogen and ammonia are analyzed by TDS (Thermal Desorption Spectroscopy). 3 or less is used. It is preferable to use a silicon oxide film having an excessive amount of oxygen. For the silicon nitride film, a silicon nitride film having a small amount of hydrogen and ammonia release is used. The release amounts of hydrogen and ammonia are analyzed by TDS (Thermal Desorption Spectroscopy). or less is used. 16 spins / cm 3 or less is used. The silicon oxide film It is preferable to use a silicon oxide film having an excessive amount of oxygen. For the silicon nitride film, a silicon nitride film having a small amount of hydrogen and ammonia release is used. The release amounts of hydrogen and ammonia are analyzed by TDS (Thermal Desorption Spectroscopy). released is small. The release amounts of hydrogen and ammonia are determined by TDS (Thermal Desorption Spectroscopy) analysis. : Temperature-programmed desorption gas spectrometry) analysis ​It suffices to perform the measurement.

[0271] As the oxide semiconductor films 23, 41, and 42a, an oxide semiconductor film can be used. When a large amount of hydrogen is contained in the oxide semiconductor film used as the oxide semiconductor films 23 and 41, by combining with the oxide semiconductor, a part of the hydrogen becomes a donor and generates electrons as carriers. As a result, the threshold voltages of the transistors 20 and 56 shift in the negative direction. Therefore, after forming the oxide semiconductor film, it is preferable to perform a dehydration treatment (dehydrogenation treatment) to remove hydrogen or moisture from the oxide semiconductor film so that impurities are not contained as much as possible.

[0272] In this embodiment, an In—Ga—Zn-based oxide semiconductor film having a film thickness of 35 nm formed using a target composed of a metal oxide with an atomic ratio of metal elements of In:Ga:Zn = 3:1:2 is used as the oxide semiconductor films 23, 41, and 42a.

[0273] The thicknesses of the oxide semiconductor films 23, 41, and 42a are preferably 1 nm or more and 100 nm or less, more preferably 1 nm or more and 50 nm or less, still more preferably 1 nm or more and 30 nm or less, and still more preferably 3 nm or more and 20 nm or less.

[0274] Note that, due to the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, oxygen in the oxide semiconductor film may decrease. Therefore, it is preferable to perform a process of adding oxygen to the oxide semiconductor film in order to compensate for the oxygen deficiency increased by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. ​

[0275] Thus, in the oxide semiconductor film, by dehydration treatment (dehydrogenation treatment), hydrogen or moisture is removed, and by oxygen addition treatment to compensate for oxygen deficiency, it is possible to obtain an oxide semiconductor film that is i-type (intrinsic) or substantially i-type (intrinsic) approaching the i-type limitlessly.

[0276] Next, after forming a conductive film on the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a and the insulating film 22, by processing the shape of the conductive film by etching or the like, a conductive film 24 and a conductive film 25 in contact with the oxide semiconductor film 23 and a conductive film 43 and a conductive film 44 in contact with the oxide semiconductor film 41 are formed (see FIG. 12(A)). The conductive film 24 and the conductive film 25, and the conductive film 43 and the conductive film 44 can be formed of the same conductive material as the conductive films 21 and 40.

[0277] In this embodiment, a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 200 nm are sequentially laminated and used as the conductive films 24 and 25 and the conductive films 43 and 44.

[0278] Next, an oxide film or an insulating film is formed so as to cover the substrate 31. In FIG. 12(B), the case of forming the insulating films 26 and 27 sequentially laminated is illustrated.

[0279] It is preferable that the insulating film 27 is continuously formed without exposure to the atmosphere after forming the insulating film 26. After forming the insulating film 26, without opening to the atmosphere, by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas, and continuously forming the insulating film 27, the insulating film 26, and The impurity concentration at the interface between the insulating film 27 and the silicon oxide film 21 can be reduced. The oxygen contained in the oxide semiconductor film 23 can be transferred to the oxide semiconductor film 41. In this way, the amount of oxygen vacancies in the oxide semiconductor film 23 and the oxide semiconductor film 41 can be reduced.

[0280] The substrate placed in the evacuated processing chamber of the plasma CVD device is heated to 180°C or higher (up to 400°C). The temperature is preferably kept at 200° C. or higher and 370° C. or lower, and the raw material gas is introduced into the processing chamber. The pressure in the processing chamber is set to 30 Pa or more and 250 Pa or less, and more preferably 40 Pa or more. The pressure is set to 200 Pa or less, and the insulation is achieved by supplying high-frequency power to the electrodes installed in the treatment chamber. As the insulating film 26, a silicon oxide film or a silicon oxynitride film is formed.

[0281] As the source gas for the insulating film 26, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and fluorinated silane. Nitrogen, etc.

[0282] By using the above conditions, an oxide insulating film that transmits oxygen can be formed as the insulating film 26. In addition, by providing the insulating film 26, in the process of forming the insulating film 27 to be formed later, As a result, damage to the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a may be reduced. Reduction is possible.

[0283] In addition, by increasing the amount of oxidizing gas to 100 times the amount of deposition gas containing silicon, It is possible to reduce the hydrogen content in the insulating film 26 and to prevent the hydrogen content in the insulating film 26 from being increased. Dangling bonds can be reduced. Oxygen moving from the insulating film 27 may be trapped by the dangling bonds contained in the insulating film 26. Therefore, the oxygen contained in the insulating film 27 can be efficiently transferred to the oxide semiconductor film 23 and the oxide semiconductor film 41 to fill the oxygen deficiencies contained in the oxide semiconductor film 23 and the oxide semiconductor film 41. As a result, the amount of hydrogen mixed into the oxide semiconductor film 23 and the oxide semiconductor film 41 can be reduced, and at the same time, the oxygen deficiencies contained in the oxide semiconductor film 23 and the oxide semiconductor film 41 can be reduced. Therefore, the negative shift of the threshold voltages of the transistor 20 and the transistor 56 can be suppressed, and the off-currents of the transistor 20 and the transistor 56 can be reduced, and the electrical characteristics of the transistor can be improved.

[0284] In this embodiment, as the insulating film 26, silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm are used as source gases, the pressure in the processing chamber is 200 Pa, the substrate temperature is 350 °C, and 100 W of high-frequency power is supplied to the parallel plate electrode using a 27.12 MHz high-frequency power supply. Then, a silicon oxynitride film with a thickness of 50 nm is formed by plasma CVD. The plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 . When the supplied power is converted to the power per unit area (power density), it is 1.6 × 10 W / -2 cm 2 . Under these conditions, a silicon oxynitride film that permeates oxygen can be formed.

[0285] The insulating film 27 is formed by placing a substrate placed in the evacuated processing chamber of the plasma CVD apparatus at 180 Maintain at 260 °C or less and more preferably 180 °C or more and 230 °C or less. Introduce the raw material gas into the processing chamber and set the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less. Supply high-frequency power of 0.17 W / cm or more and 0.5 W / cm or less, more preferably 0.25 W / cm or more and 0.35 W / cm or less to the electrodes provided in the processing chamber. Under the condition of forming a silicon oxide film or a silicon oxynitride film. Introduce the raw material gas into the processing chamber and set the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less. Supply high-frequency power of 0.17 W / cm 2 or more and 0.5 W / cm 2 or less, more preferably 0.25 W / cm 2 or more and 0.35 W / c m 2 or less to the electrodes provided in the processing chamber to form a silicon oxide film or a silicon oxynitride film.

[0286] As the film formation conditions of the insulating film 27, by supplying the high-frequency power of the above power density in the reaction chamber of the above pressure, the decomposition efficiency of the raw material gas in the plasma increases, the oxygen radicals increase, and the oxidation of the raw material gas proceeds. Therefore, the oxygen content in the insulating film 27 becomes more than the stoichiometric composition. However, when the substrate temperature is the above temperature, the binding force between silicon and oxygen is weak, so a part of oxygen desorbs by heating. As a result, an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and having a part of oxygen desorbed by heating can be formed. Also, since the insulating film 26 is provided on the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a, in the formation process of the insulating film 27, the insulating film 26 has a function of protecting the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a. As a result, while reducing the damage to the oxide semiconductor film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a, the insulating film 27 can be formed using high-frequency power with a high power density.

[0287] ​​​​​​​​​​​In this embodiment, as the insulating film 27, silane with a flow rate of 160 sccm is used as the source gas, and the reaction chamber pressure is 200 Pa, the substrate temperature is 220 °C, and a high-frequency power supply of 27.12 MHz is used to supply 1500 W of high-frequency power to the parallel plate electrode. By the plasma CVD method, an oxynitride silicon film with a thickness of 400 nm is formed. The plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 2 cm . When the supplied power is converted to the power per unit area (power density), it is 2.5×10 -1 W / cm 2 .

[0288] Next, after forming at least the insulating film 27, a heat treatment is performed to move the oxygen contained in the insulating film 26 or the insulating film 27 to the oxide semiconductor film 23 and the oxide semiconductor film 41, and it is preferable to compensate for the oxygen deficiency in the oxide semiconductor film 23 and the oxide semiconductor film 41. The heat treatment may be performed as a heat treatment for dehydrogenating or dehydrating the oxide semiconductor film 23 and the oxide semiconductor film 41. Specifically, in this embodiment, a heat treatment is performed at 350 °C for 1 hour in a nitrogen and oxygen atmosphere.

[0289] Through the above series of steps, the transistor 20 and the transistor 56 are formed.

[0290] Next, as shown in FIG. 13(A), the insulating film 26 and the insulating film 27 are partially etched to form an opening 58. In the opening 58, a part or all of the oxide semiconductor film 42a is exposed.

[0291] Next, a nitride insulating film 28 is formed on the insulating film 26 and the insulating film 27 so as to cover They are formed so as to be laminated in order on the nitride insulating film 28 and the insulating film 29. The nitride insulating film 28 is in contact with the oxide semiconductor film 42a at the opening 58. It is in contact with the oxide semiconductor film 42a.

[0292] As the nitride insulating film 28, for example, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. formed by using a CVD method or the like can be used. The nitride insulating film 28 using the above-described materials can prevent impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the oxide semiconductor film 23 and the oxide semiconductor film 41. Further, by forming the nitride insulating film 28 so as to be in contact with the oxide semiconductor film 42a at the opening 58, the conductivity of the oxide semiconductor film 42a can be enhanced. The oxide semiconductor film 42a with enhanced conductivity is shown as the metal oxide film 42 in FIG. 13(B). In the present embodiment, as the nitride insulating film 28, silane with a flow rate of 50 sccm, nitrogen with a flow rate of 500 sccm, and ammonia with a flow rate of 100 sccm are used as source gases, the pressure in the processing chamber is 100 Pa, the substrate temperature is 350 ° C, and a high-frequency power of 1000 W (the power density is 1.6×10 W / cm ) is supplied to the parallel plate electrode by a plasma CVD method to form a silicon nitride film with a thickness of 100 nm. It is desirable to use an insulating film having a lower relative dielectric constant and a smaller internal stress than the nitride insulating film 28 as the insulating film 29. Specifically, as the insulating film 29, for example, a silicon oxide film, a silicon oxynitride film, aluminum oxide, etc. can be used. Compared with oxide insulating films such as silicon oxide and aluminum oxide, it is possible to prevent impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the oxide semiconductor film 23 and the oxide semiconductor film 41. Also, by forming the nitride insulating film 28 so as to be in contact with the oxide semiconductor film 42a at the opening 58, the conductivity of the oxide semiconductor film 42a can be enhanced. The oxide semiconductor film 42a with enhanced conductivity is shown as the metal oxide film 42 in FIG. 13(B). It is possible to prevent impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the oxide semiconductor film 23 and the oxide semiconductor film 41. Also, by forming the nitride insulating film 28 so as to be in contact with the oxide semiconductor film 42a at the opening 58, the conductivity of the oxide semiconductor film 42a can be enhanced. The oxide semiconductor film 42a with enhanced conductivity is shown as the metal oxide film 42 in FIG. 13(B). By forming the nitride insulating film 28 so as to be in contact with the oxide semiconductor film 42a at the opening 58, the conductivity of the oxide semiconductor film 42a can be enhanced. The oxide semiconductor film 42a with enhanced conductivity is shown as the metal oxide film 42 in FIG. 13(B). The conductivity of the oxide semiconductor film 42a can be enhanced. The oxide semiconductor film 42a with enhanced conductivity is shown as the metal oxide film 42 in FIG. 13(B). The oxide semiconductor film 42a with enhanced conductivity is shown as the metal oxide film 42 in FIG. 13(B).

[0293] In the present embodiment, as the nitride insulating film 28, silane with a flow rate of 50 sccm, nitrogen with a flow rate of 500 sccm, and ammonia with a flow rate of 100 sccm are used as source gases, the pressure in the processing chamber is 100 Pa, the substrate temperature is 350 ° C, and a high-frequency power of 1000 W (the power density is 1.6×10 W / cm ) is supplied to the parallel plate electrode by a plasma CVD method to form a silicon nitride film with a thickness of 100 nm. It is desirable to use an insulating film having a lower relative dielectric constant and a smaller internal stress than the nitride insulating film 28 as the insulating film 29. Specifically, as the insulating film 29, for example, a silicon oxide film, a silicon oxynitride film, aluminum oxide, etc. can be used. It is desirable to use an insulating film having a lower relative dielectric constant and a smaller internal stress than the nitride insulating film 28 as the insulating film 29. Specifically, as the insulating film 29, for example, a silicon oxide film, a silicon oxynitride film, aluminum oxide, etc. can be used. 0 W (as the power density is 1.6×10 -1 W / cm 2 ) is supplied to the parallel plate electrode by a plasma CVD method to form a silicon nitride film with a thickness of 100 nm. It is desirable to use an insulating film having a lower relative dielectric constant and a smaller internal stress than the nitride insulating film 28 as the insulating film 29. Specifically, as the insulating film 29, for example, a silicon oxide film, a silicon oxynitride film, aluminum oxide, etc. can be used.

[0294] It is desirable to use an insulating film having a lower relative dielectric constant and a smaller internal stress than the nitride insulating film 28 as the insulating film 29. Specifically, as the insulating film 29, for example, a silicon oxide film, a silicon oxynitride film, aluminum oxide, etc. can be used. Specifically, as the insulating film 29, for example, a silicon oxide film, a silicon oxynitride film, aluminum oxide, etc. can be used. Specifically, as the insulating film 29, for example, a silicon oxide film, a silicon oxynitride film, aluminum oxide, etc. can be used.

[0295] For example, as the insulating film 29, a silicon oxide film formed by a CVD method using an organic silane gas can be used. As the organic silane gas, ethyl silicate (TEOS: chemical formula Si( OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetrame thylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (O MCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC 2H5)3), tris(dimethylamino)silane (SiH(N(CH3)2)3), etc. can be used.

[0296] In this embodiment, as the insulating film 29, a silicon oxide film with a film thickness of 200 nm formed by a CVD method using ethyl silicate is used.

[0297] Next, as shown in FIG. 14(A), the nitride insulating film 28 and the insulating film 29 are partially etched to form an opening 62. In the opening 62, at least a part of the conductive film 44 is exposed.

[0298] Next, as shown in FIG. 14(B), a transparent conductive film is formed on the insulating film 29, and the shape of the transparent conductive film is processed by etching or the like to form the conductive film 30 and the conductive film 45. The conductive film 30 is provided at a position overlapping the conductive film 21 with the oxide semiconductor film 23 interposed therebetween. Also, the conductive film 45 is connected to the conductive film 44 at the opening 62.

[0299] Note that, as the transparent conductive film used to form the conductive film 21 and the conductive film 45, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, aci d ​​​​Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide added with gallium, indium tin oxide added with silicon oxide, etc. can be used as the conductive film.

[0300] In this embodiment, a conductive film having a thickness of 100 nm and containing indium tin oxide added with silicon oxide, etc. is used to form the conductive film 21 and the conductive film 45. After forming the conductive film 21 and the conductive film 45, heat treatment may be performed. The heat treatment may be performed, for example,

[0301] in a nitrogen atmosphere at 250 °C for 1 hour. Then, by forming an alignment film 52 on the conductive film 45 as shown in FIG. 5, the element substrate can be formed.

[0302] The alignment film 52 can be formed using an organic resin such as polyimide or polyvinyl alcohol, and on its surface, an alignment treatment for arranging liquid crystal molecules in a certain direction, such as rubbing, is performed. Rubbing can be performed by rotating a roller wrapped with a cloth such as nylon so as to be in contact with the alignment film 52 and rubbing the surface of the alignment film 52 in a certain direction. It should be noted that it is also possible to directly form an alignment film 52 having alignment characteristics by vapor deposition using an inorganic material such as silicon oxide without performing an alignment treatment. After forming the element substrate and the counter substrate, as shown in FIG. 5, by enclosing a liquid crystal layer 53 between the substrate 31 and the substrate 46, the panel of the liquid crystal display device can be formed. For injecting the liquid crystal performed to form the liquid crystal layer 53, a dispenser type (dropping type) may be used, or dipping

[0303] can also be used.

[0304] ​​​​​​​​The pumping type (formula) may be used.

[0305] <Top view and cross-sectional view of a semiconductor display device> Next, taking a liquid crystal display device as an example, the appearance of the semiconductor display device according to one aspect of the present invention will be described with reference to FIG. 15. FIG. 15 is a top view of a liquid crystal display device in which a substrate 4001 and a substrate 4006 are adhered by a sealing material 40 05. Further, FIG. 16 corresponds to a cross-sectional view taken along the broken line C 1-C2 in FIG. 15.

[0306] A sealing material 4005 is provided so as to surround a pixel portion 4002 provided on the substrate 4001 and a pair of drive circuits 4004. Further, a substrate 4006 is provided on the pixel portion 4002 and the drive circuit 4004. Therefore, the pixel portion 4002 and the drive circuit 4004 are sealed by the substrate 4001, the sealing material 4005, and the substrate 4006.

[0307] In addition, a drive circuit 4003 is mounted in a region different from the region surrounded by the sealing material 4005 on the substrate 4001.

[0308] The pixel portion 4002 and the drive circuit 4004 provided on the substrate 4001 have a plurality of transistors. In FIG. 16, a transistor 4010 included in the pixel portion 4002 is exemplified

[0309] An insulating film 4020 composed of various insulating films including a nitride insulating film is provided on the transistor 4010, and the transistor 4010 is provided in an opening provided in the insulating film 4020 and is connected to a pixel electrode 4021 on the insulating film 4020.

[0309] In addition, a resin film 4059 is provided on the substrate 4006, and a common The electrode 4060 is provided. And between the substrate 4001 and the substrate 4006, a liquid crystal layer 4028 is provided so as to be sandwiched between the pixel electrode 4021 and the common electrode 4060. The liquid crystal element 4023 has a pixel electrode 4021, a common electrode 4060, and a liquid crystal layer 4028.

[0310] In the liquid crystal element 4023, according to the value of the voltage applied between the pixel electrode 4021 and the common electrode 4060, the alignment of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. Thus, the liquid crystal element 4023 can display gradations by controlling its transmittance according to the potential of the image signal applied to the pixel electrode 4021.

[0311] Also, as shown in FIG. 16, in one aspect of the present invention, the insulating film 4020 is removed at the end of the panel. And in the region where the insulating film 4020 is removed, a conductive film 4050 is formed. The conductive film 4050 and the conductive film that functions as the source or drain of the transistor 4010 can be formed by etching one conductive film.

[0312] And between the substrate 4001 and the substrate 4006, a resin film 4062 in which conductive particles 4061 having conductivity are dispersed is provided. The conductive film 4050 is electrically connected to the common electrode 4060 via the conductive particles 4061. That is, the common electrode 4060 and the conductive film 4050 are electrically connected via the conductive particles 4061 at the end of the panel. For the resin film 4062, a thermosetting resin or an ultraviolet curable resin can be used. Also, for the conductive particles 4061, for example, spherical organic resins such as Au, Ni, and Co can be used. Particles coated with a thin film of metal such as can be used.

[0313] Although the alignment film is not shown in FIG. 16, when the alignment film is provided on the pixel electrode 4021 and the common electrode 4 060, in order to electrically connect the common electrode 4060, the conductive particles 4061, and the conductive film 4050 a part of the alignment film may be removed at the portion overlapping the common electrode 4060 and a part of the alignment film may be removed at the portion overlapping the conductive film 4050.

[0314] Note that in the liquid crystal display device according to one aspect of the present invention, a color image may be displayed by using a color filter, or a color image may be displayed by sequentially lighting a plurality of light sources that emit light of different hues.

[0315] Also, the image signal from the drive circuit 4003, various control signals and potentials from the FPC 4018 are supplied to the drive circuit 4004 or the pixel portion 400 2 via the routing wirings 4030 and 4031.

[0316] <Configuration Example of Electronic Device Using Semiconductor Device> A semiconductor device according to one aspect of the present invention can be used in a display device, a personal computer, an image playback device equipped with a recording medium (typically a device having a display capable of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying the image). In addition, electronic devices that can use the semiconductor device according to one aspect of the present invention include mobile phones, game machines including portable types, portable information terminals, electronic books, video cameras, digital still cameras such as digital cameras, goggle-type displays (head-mounted displays ), navigation systems, audio playback devices (car audio, digital audio players ). ears, etc., copiers, facsimiles, printers, all-in-one printers, automated teller machines (ATMs), vending machines, etc. Examples of these electronic devices are shown in Fig. 18.

[0317] Fig. 18(A) shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, a display unit 5004, a microphone 5005, a speaker 5006, operation keys 5007, a sticker 5008, etc. The semiconductor device according to one aspect of the present invention can be used for the display unit 5003 or the display unit 5004, or other integrated circuits. Note that the portable game machine shown in Fig. 18(A) has two display units 5003 and 5004, but the number of display units of the portable game machine is not limited to this.

[0318] Fig. 18(B) shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit 5603, a second display unit 5604, a connection unit 5605, operation keys 5606, etc. The first display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. And the first housing 5601 and the second housing 5602 are connected by the connection unit 5605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection unit 5605. It is also possible to configure the video on the first display unit 5603 to be switched according to the angle between the first housing 5601 and the second housing 5602 at the connection unit 5605. The semiconductor device according to one aspect of the present invention can be used for the first display unit 5603 or the second display unit 5604, or other integrated circuits.

[0319] ​​​​​​​FIG. 18(C) is a notebook personal computer, which includes a housing 5401, a display unit 5402 , a keyboard 5403, a pointing device 5404, etc. The semiconductor device according to an aspect of the present invention can be used for the display unit 5402 and other integrated circuits.

[0320] FIG. 18(D) is a wristwatch, which includes a housing 5201, a display unit 5202, an operation button 5203, a band 5204, etc. The semiconductor device according to an aspect of the present invention can be used for the display unit 5202 and other integrated circuits.

[0321] FIG. 18(E) is a video camera, which includes a first housing 5801, a second housing 5802, a display unit 58 03, operation keys 5804, a lens 5805, a connection part 5806, etc. The operation keys 580 4 and the lens 5805 are provided on the first housing 5801, and the display unit 5803 is provided on the second housing 5802. The first housing 5801 and the second housing 5802 are connected by the connection part 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection part 5806. The switching of the video on the display unit 5803 may be performed according to the angle between the first housing 5801 and the second housing 5802 at the connection part 5806. The semiconductor device according to an aspect of the present invention can be used for the display unit 5803 and other integrated circuits.

[0322] FIG. 18(F) is a mobile phone, on which a housing 5901 is provided with a display unit 5902, a microphone 5907, a speaker 5904, a camera 5903, an external connection part 5906, and operation buttons 5905. The semiconductor device according to an aspect of the present invention can be used for the display unit 5902 and other integrated circuits. It can be used. Further, when the semiconductor device according to one aspect of the present invention is formed on a flexible substrate it is possible to apply the semiconductor device to a display portion 5902 having a curved surface as shown in FIG. 18(F).

Example

[0323] In this example, transistors were fabricated, and the results of evaluating their Vg-Id characteristics and reliability will be described.

[0324] [Fabrication of Samples] In this example, Samples 1 and 2, which are one aspect of the present invention, and Comparative Sample 3 were fabricated respectively. More specifically, as Sample 1, which is one aspect of the present invention, a transistor corresponding to the configuration shown in FIG. 2 was fabricated. Also, as Sample 2, which is one aspect of the present invention, a transistor corresponding to the configuration shown in FIG. 19 was fabricated. As Comparative Sample 3, a transistor corresponding to a configuration without the conductive film 30 in the configuration shown in FIG. 2 was fabricated.

[0325] [Sample 1] First, a glass substrate was used as the substrate, and a gate electrode was formed on the substrate.

[0326] As the gate electrode, a tungsten film with a thickness of 200 nm was formed by sputtering, a mask was formed on the tungsten film by a photolithography process, and a part of the tungsten film was etched using the mask to form it.

[0327] Next, a gate insulating film was formed on the gate electrode.

[0328] As the gate insulating film, a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm were laminated and formed.

[0329] ​​​​​ The silicon nitride film had a three-layer laminated structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film.

[0330] As the first silicon nitride film, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm were used as source gases and supplied to the processing chamber of a plasma CVD apparatus. The pressure in the processing chamber was controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz was used to supply 2000 W of power to form a film with a thickness of 50 nm. As the second silicon nitride film, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 2000 sccm were used as source gases and supplied to the processing chamber of the plasma CVD apparatus. The pressure in the processing chamber was controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz was used to supply 200 0 W of power to form a film with a thickness of 300 nm. As the third silicon nitride film, silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm were used as source gases and supplied to the processing chamber of the plasma CVD apparatus. The pressure in the processing chamber was controlled to 100 Pa, and a high-frequency power supply of 27.1 2 MHz was used to supply 2000 W of power to form a film with a thickness of 50 nm. The substrate temperature during the formation of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film was set to 350 °C. During the formation of the silicon oxynitride film, silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm were used as source gases and supplied to the processing chamber of the plasma CVD apparatus. The pressure in the processing chamber was controlled to 40 Pa and a high-frequency power supply of 27.12 MHz was used to supply 100 W of power to form the silicon oxynitride film. The substrate temperature during the formation of the silicon oxynitride film was set to 350 °C.

[0331] ​​

[0332] Next, an oxide semiconductor film overlapping the gate electrode was formed through a gate insulating film.

[0333] In this example, an oxide semiconductor film with a thickness of 35 nm was formed on the gate insulating film by a sputtering method. formed.

[0334] The oxide semiconductor film used a sputtering target with an In:Ga:Zn = 1:1:1 (atomic ratio), and oxygen with a flow rate of 100 sccm was used as the sputtering gas and supplied into the processing chamber of the sputtering apparatus. The pressure in the processing chamber was controlled to 0.6 Pa, and a DC power of 5 kW was supplied to form it. Note that the substrate temperature when forming the oxide semiconductor film was set to 170°C. ratio) target, and oxygen with a flow rate of 100 sccm was used as the sputtering gas and sputtered into the processing chamber of the sputtering apparatus. The pressure in the processing chamber was controlled to 0.6 Pa, and a DC power of 5 kW was supplied to form it. Note that the substrate temperature when forming the oxide semiconductor film was set to 170°C. ring apparatus, and the pressure in the processing chamber was controlled to 0.6 Pa, and a DC power of 5 kW was supplied to form it. Note that the substrate temperature when forming the oxide semiconductor film was set to 170°C. power was supplied to form it. The substrate temperature when forming the oxide semiconductor film was 170°C. .

[0335] Next, a source electrode and a drain electrode in contact with the oxide semiconductor film were formed.

[0336] First, a conductive film was formed on the gate insulating film and the oxide semiconductor film. As the conductive film, a 400 - nm - thick aluminum film was formed on a 50 - nm - thick tungsten film, and a 200 - nm - thick titanium film was formed on the aluminum film. Next, a mask was formed on the conductive film through a photolithography process, and a part of the conductive film was etched using the mask to form the source electrode and the drain electrode. 50 nm tungsten film, and a 400 nm aluminum film was formed on the tungsten film, and a 200 nm titanium film was formed on the aluminum film. Next, a mask was formed on the conductive film through a photolithography process, and a part of the conductive film was etched using the mask to form the source electrode and the drain electrode. um film, and a 200 nm titanium film was formed on the aluminum film. Next, a mask was formed on the conductive film through a photolithography process, and a part of the conductive film was etched using the mask to form the source electrode and the drain electrode. conductive film, and a mask was formed on the conductive film using photolithography. A part of the conductive film was etched using the mask to form the source electrode and the drain electrode. electrode and the drain electrode were formed.

[0337] Next, the substrate was moved into the depressurized processing chamber, heated at 350°C, and then 150 W of high - frequency power was supplied to the upper electrode provided in the processing chamber using a 27.12 - MHz high - frequency power source, and the oxide semiconductor film was exposed to the oxygen plasma generated in a dinitrogen monoxide atmosphere. Next, the substrate was moved into the depressurized processing chamber, heated at 350°C, and then 150 W of high - frequency power was supplied to the upper electrode provided in the processing chamber using a 27.12 - MHz high - frequency power source, and the oxide semiconductor film was exposed to the oxygen plasma generated in a dinitrogen monoxide atmosphere. Next, the substrate was moved into the depressurized processing chamber, heated at 350°C, and then 150 W of high - frequency power was supplied to the upper electrode provided in the processing chamber using a 27.12 - MHz high - frequency power source, and the oxide semiconductor film was exposed to the oxygen plasma generated in a dinitrogen monoxide atmosphere.

[0338] Next, a protective film was formed on the oxide semiconductor film, the source electrode, and the drain electrode. In this example, a three-layer structure of a first oxide insulating film, a second oxide insulating film, and a nitride insulating film was used as the protective film.

[0339] The first oxide insulating film was formed by plasma CVD using silane with a flow rate of 20 sccm and dinitrogen with a flow rate of 3000 sccm as source gases, setting the pressure in the processing chamber to 200 Pa, the substrate temperature to 350 °C, and supplying 100 W of high-frequency power to the parallel plate electrode.

[0340] The second oxide insulating film was formed by plasma CVD using silane with a flow rate of 160 sccm and dinitrogen with a flow rate of 4000 sccm as source gases, setting the pressure in the processing chamber to 200 Pa, the substrate temperature to 220 °C, and supplying 1500 W of high-frequency power to the parallel plate electrode. Under these conditions, a silicon oxynitride film containing more oxygen than the stoichiometric composition can be formed, and part of the oxygen is desorbed by heating.

[0341] Next, a heat treatment was performed to desorb water, nitrogen, hydrogen, etc. from the first oxide insulating film and the second oxide insulating film, and part of the oxygen contained in the second oxide insulating film was supplied to the oxide semiconductor film. In this example, a heat treatment was performed at 350 °C for 1 hour in a nitrogen and oxygen atmosphere.

[0342] Next, a nitride insulating film with a thickness of 100 nm was formed on the second oxide insulating film. The nitride insulating film was formed by plasma CVD using silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 scc m as source gases, setting the pressure in the processing chamber to 100 Pa, the substrate temperature to 350 °C, and supplying 1000 W of high-frequency power to the parallel plate electrode. ​​​​​​​​​ .

[0343] Next, in a region where the oxide semiconductor film, source electrode, and drain electrode are not provided, an opening reaching the gate electrode was formed in a part of the gate insulating film and the protective film. The opening was , a mask was formed on the protective film by a photolithography process, and a part of the gate insulating film and the protective film was etched using the mask.

[0344] Next, a gate electrode was formed on the protective film. The gate electrode is electrically connected to a gate electrode located under the oxide semiconductor film through an opening provided in a part of the gate insulating film and the protective film. Hereinafter, the gate electrode on the protective film is referred to as a back gate electrode.

[0345] In this example, as the back gate electrode, a conductive film of indium oxide - tin oxide compound containing 100 nm thick silicon oxide (ITO - SiO2) was formed by sputtering. The composition of the target used for the conductive film was In2O3:SnO2:SiO2 = 85:1 0:5 [wt%]. After that, heat treatment was performed at 250 °C for 1 hour in a nitrogen atmosphere. .

[0346] Sample 1 of this example was obtained through the above steps.

[0347] 〔Sample 2〕 Sample 2 differs from Sample 1 in the structure of the protective film and the back gate electrode. More specifically, , in the channel width direction of the transistor, the side surfaces of the first oxide insulating film and the second oxide insulating film are covered by the back gate electrode.

[0348] Sample 2 was fabricated by, in the fabrication process of Sample 1 described above, the first oxide insulating film, the second oxide A physical insulating film was formed, and after heat treatment, a mask was formed on the second oxide insulating film by a photolithography process. Subsequently, using the mask, a part of the first oxide insulating film and the second oxide insulating film was etched. The other processes are the same as those of Sample 1 described above, so the description of Sample 1 can be incorporated by reference.

[0349] 〔Sample 3〕 Sample 3 for comparison was configured to be different from Sample 1 in that it does not have a back gate electrode.

[0350] Sample 3 was fabricated by omitting the step of forming the back gate electrode in the fabrication process of Sample 1 described above. The other processes are the same as those of Sample 1 described above, so the description of Sample 1 can be incorporated by reference.

[0351] Note that Samples 1 to 3 described above each contained three types of transistors with a channel length (L) of 2 μm, 3 μm, or 6 μm. And all the transistors contained in Samples 1 to 3 had a channel width (W) of 50 μm.

[0352] [Vg-Id Characteristics] Next, as the initial characteristics of the transistors of Samples 1 to 3, the Vg-Id characteristics were measured. In this example, with the substrate temperature at 25°C, the potential difference between the source and drain (hereinafter also referred to as the drain voltage, Vd) was set to 1 V and 10 V, and the potential difference between the source and back gate electrodes (hereinafter also referred to as the gate voltage, Vg) was changed from -15 V to 15 V, and the change characteristics of the current flowing between the source and drain (hereinafter also referred to as the drain current, Id), that is, the Vg-Id characteristics, were measured.

[0353] ​​​​​​​​​​​​ Here, in Sample 1 and Sample 2, a driving method was used in which a gate voltage was applied with the gate electrode and the back gate electrode being electrically short-circuited. In Dual Gate driving, the gate voltages of the gate electrode and the back gate electrode are always equal.

[0354] Fig. 26 shows the Vg-Id characteristics of Sample 3. Figs. 26(A), (B), and (C) are the results for transistors with channel lengths (L) of 2 μm, 3 μm, and 6 μm, respectively. Similarly, Fig. 27 shows the Vg-Id characteristics of Sample 1, and Fig. 28 shows the Vg-Id characteristics of Sample 2.

[0355] Also, in each of Figs. 26, 27, and 28, the horizontal axis represents the gate voltage Vg, the first vertical axis represents the drain current Id, and the second vertical axis represents the field-effect mobility. Here, the field-effect mobility is the field-effect mobility calculated at Vd = 10 V in order to show the value in the saturation region.

[0356] In Sample 3 for comparison shown in Fig. 26, it was found that the value of the field-effect mobility hardly changes regardless of the channel length (L). Also, it was shown that the threshold voltage shifts in the negative direction as the channel length (L) is smaller and the drain voltage Vd is larger.

[0357] On the other hand, in Sample 1 of one aspect of the present invention shown in Fig. 27, it was confirmed that the field-effect mobility is improved compared to the above-mentioned Sample 3 under all conditions of the channel length (L). Furthermore, it was found that the field-effect mobility improves as the channel length (L) is smaller. Also, even under the condition where the channel length (L) is the smallest (L = 2 μm), the threshold for the drain voltage Vd It was found that the change in the threshold voltage is extremely small compared to Sample 3.

[0358] Also in Sample 2 of one aspect of the present invention shown in FIG. 28, under all conditions of channel length (L), it was confirmed that the field-effect mobility was improved compared to the above Sample 3. Furthermore, it was found that the smaller the channel length (L), the more the field-effect mobility is improved. Also, even under the condition where the channel length (L) is the smallest (L = 2 μm), the change in the threshold voltage with respect to the drain voltage Vd was found to be extremely small compared to Sample 3. It was found that the change in the threshold voltage is extremely small compared to Sample 3.

[0359] In Samples 1 and 2, by Dual Gate driving, it becomes possible to apply an electric field more effectively to the oxide semiconductor in which a channel is formed compared to Sample 3, and as a result, even when the channel length (L) is small, it can be seen that the change in the threshold voltage with respect to the drain voltage Vd can be reduced. Also for the same reason, in Samples 1 and 2, by Dual Gate driving, they are less affected by the drain voltage Vd, and the saturation in the saturation region can also be improved. From the above results, in the semiconductor device according to one aspect of the present invention, it was confirmed that the smaller the channel length (L ) of the transistor, the more the field-effect mobility is improved, and further, even when the channel length (L) is small, the threshold voltage can be set to a good value. By using such a transistor, it is possible to realize a narrow border of the semiconductor display device.

[0360] From the above results, in the semiconductor device according to one aspect of the present invention, it was confirmed that the smaller the channel length (L ) of the transistor, the more the field-effect mobility is improved, and further, even when the channel length (L) is small, the threshold voltage can be set to a good value. By using such a transistor, it is possible to realize a narrow border of the semiconductor display device. transistor, it is possible to realize a narrow border of the semiconductor display device. .

Explanation of Signs

[0361] 10 Sequential circuit 10_DUM Sequential circuit 10_j sequential circuit 10_j-1 sequential circuit 10_y sequential circuit 10_1 sequential circuit 10_8m sequential circuit 11 circuit 12 transistors 13 transistors 14 transistors 15 transistors 16 transistors 17 transistors 20 transistors 21 conductive film 22 insulating film 23 oxide semiconductor film 23a oxide semiconductor film 23b oxide semiconductor film 23c oxide semiconductor film 24 conductive film 25 conductive film 26 insulating film 27 insulating film 28 nitride insulating film 29 insulating film 30 conductive film 31 substrate 32 opening 32a opening 32b opening 34 conductive film 40 conductive film 41 oxide semiconductor film 42 metal oxide film 42a oxide semiconductor film 43 conductive film 44 conductive film 45 conductive film 46 substrate 47 masking film 48 coloring layer 50 resin film 51 alignment film 52 alignment film 53 liquid crystal layer 55 pixel 56 transistors 57 capacitor element 58 Opening 59 Conductive film 60 Liquid crystal element 61 Conductive film 62 Opening 70 Semiconductor display device 71 Pixel section 72 Driving circuit 73 Driving circuit 80 Transistor 81 Transistor 82 Transistor 83 Transistor 84 Transistor 85 Transistor 86 Transistor 90 Buffer 91 Transistor 92 Transistor 93 Transistor 95 Transistor 96 Transistor 97 Capacitor element 98 Light emitting element 4001 Substrate 4002 Pixel section 4003 Driving circuit 4004 Driving circuit 4005 Sealing material 4006 Substrate 4010 Transistor 4018 FPC 4020 Insulating film 4021 Pixel electrode 4023 Liquid crystal element 4028 Liquid crystal layer 4030 Wiring 4050 Conductive film 4059 Resin film 4060 Common electrode 4061 Conductive particles 4062 Resin film 5001 Housing 5002 Housing 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation Key 5008 Stylus 5201 Housing 5202 Display Unit 5203 Operation Button 5204 Band 5401 Housing 5402 Display Unit 5403 Keyboard 5404 Pointing Device 5601 Housing 5602 Housing 5603 Display Unit 5604 Display Unit 5605 Connection Part 5606 Operation Key 5801 Housing 5802 Housing 5803 Display Unit 5804 Operation Key 5805 Lens 5806 Connection Part 5901 Housing 5902 Display Unit 5903 Camera 5904 Speaker 5905 Button 5906 External Connection Part 5907 Microphone

Claims

1. A pixel includes a transistor, a capacitive element, and a display element, wherein one of the source or drain of the transistor is electrically connected to a first electrode of the display element, and one of the source or drain of the transistor is electrically connected to one electrode of the capacitive element, and the display device is a first conductive film having a function as a gate electrode of the transistor, a first insulating film having a region disposed above the first conductive film and having a function as a gate insulating film of the transistor, an oxide semiconductor film having a region disposed above the first insulating film and having a channel region of the transistor, a metal oxide film having a region disposed above the first insulating film and having a function as the other electrode of the capacitive element, a third conductive film electrically connected to the oxide semiconductor film and electrically connected to a second conductive film having a function as the first electrode, a fourth conductive film electrically connected to the oxide semiconductor film, having a function as a first wiring electrically connected to the other of the source or drain of the transistor, and having a region extending in a first direction across pixels adjacent to the pixel, a fifth conductive film electrically connected to the metal oxide film, having a function as a second wiring for supplying a potential to the metal oxide film, and having a region extending in the first direction across pixels adjacent to the pixel, a second insulating film having a region disposed above the oxide semiconductor film and having a region disposed above the metal oxide film, a third insulating film having a region disposed above the second insulating film and having a region disposed above the metal oxide film, and a sixth conductive film having a region disposed above the second conductive film and having a function as a second electrode of the display element, wherein the second conductive film has a region disposed above the third insulating film, and the metal oxide film has a region that does not overlap with the second insulating film and has an overlap with the second conductive film through the third insulating film in the region, a display device.

2. A pixel includes a transistor, a capacitive element, and a display element, wherein one of the source or drain of the transistor is electrically connected to a first electrode of the display element, One of the source or drain of the transistor is a display device electrically connected to one electrode of the capacitive element, a first conductive film having a function as a gate electrode of the transistor, a first insulating film having a region disposed above the first conductive film and having a function as a gate insulating film of the transistor, an oxide semiconductor film having a region disposed above the first insulating film and having a channel region of the transistor, a metal oxide film having a region disposed above the first insulating film and having a function as the other electrode of the capacitive element, a third conductive film electrically connected to the oxide semiconductor film and electrically connected to a second conductive film having a function as the first electrode, a fourth conductive film electrically connected to the oxide semiconductor film, having a function as a first wiring electrically connected to the other of the source or drain of the transistor, and having a region extending in a first direction across pixels adjacent to the pixel, a fifth conductive film electrically connected to the metal oxide film, having a function as a second wiring for supplying a potential to the metal oxide film, and having a region extending in the first direction across pixels adjacent to the pixel, a second insulating film having a region disposed above the oxide semiconductor film and having a region disposed above the metal oxide film, a third insulating film having a region disposed above the second insulating film and having a region disposed above the metal oxide film, a sixth conductive film having a region disposed above the second conductive film and having a function as a second electrode of the display element, the second conductive film has a region disposed above the third insulating film, the metal oxide film has a region that does not overlap with the second insulating film and has an overlap with the second conductive film through the third insulating film in the region, the fifth conductive film does not have an overlap with the fourth conductive film, A display device.

3. A pixel includes a transistor, a capacitive element, and a display element, One of the source or drain of the transistor is electrically connected to the first electrode of the display element, One of the source or drain of the transistor is a display device electrically connected to one electrode of the capacitive element, a first conductive film having a function as a gate electrode of the transistor, It has a region disposed above the first conductive film and has a first insulating film that functions as a gate insulating film of the transistor. It has a region disposed above the first insulating film and has an oxide semiconductor film having a channel region of the transistor. It has a region disposed above the first insulating film and has a metal oxide film that functions as the other electrode of the capacitor element. A third conductive film that is electrically connected to the oxide semiconductor film and is electrically connected to a second conductive film that functions as the first electrode. It is electrically connected to the oxide semiconductor film, has a function as a first wiring electrically connected to the other of the source or drain of the transistor, and has a region extending in a first direction across pixels adjacent to the pixel. A fourth conductive film. It is electrically connected to the metal oxide film, has a function as a second wiring for supplying a potential to the metal oxide film, and has a region extending in the first direction across pixels adjacent to the pixel. A fifth conductive film. It has a region disposed above the oxide semiconductor film and has a second insulating film having a region disposed above the metal oxide film. It has a region disposed above the second insulating film and has a third insulating film having a region disposed above the metal oxide film. It has a region disposed above the second conductive film and has a sixth conductive film that functions as the second electrode of the display element. The second conductive film has a region disposed above the third insulating film. The metal oxide film has a region that does not overlap with the second insulating film, and in this region, it has an overlap with the second conductive film via the third insulating film. The metal oxide film does not have an overlap with the third conductive film. A display device.

4. A pixel has a transistor, a capacitor element, and a display element. One of the source or drain of the transistor is electrically connected to the first electrode of the display element. A display device in which one of the source or drain of the transistor is electrically connected to one electrode of the capacitor element. A first conductive film that functions as a gate electrode of the transistor. It has a region disposed above the first conductive film and has a first insulating film that functions as a gate insulating film of the transistor. An oxide semiconductor film having a region disposed above the first insulating film and having a channel region of the transistor, A metal oxide film having a region disposed above the first insulating film and having a function as the other electrode of the capacitor element, A third conductive film electrically connected to the oxide semiconductor film and electrically connected to a second conductive film having a function as the first electrode, A fourth conductive film that is electrically connected to the oxide semiconductor film, has a function as a first wiring electrically connected to the other of the source or drain of the transistor, and has a region extending in a first direction across pixels adjacent to the pixel, A fifth conductive film that is electrically connected to the metal oxide film, has a function as a second wiring that supplies a potential to the metal oxide film, and has a region extending in the first direction across pixels adjacent to the pixel, A second insulating film having a region disposed above the oxide semiconductor film and having a region disposed above the metal oxide film, A third insulating film having a region disposed above the second insulating film and having a region disposed above the metal oxide film, A sixth conductive film having a region disposed above the second conductive film and having a function as a second electrode of the display element, The second conductive film has a region disposed above the third insulating film, The metal oxide film has a region that does not overlap with the second insulating film, and has an overlap with the second conductive film through the third insulating film in the region, The metal oxide film does not have an overlap with the fourth conductive film, A display device.

5. In any one of Claims 1 to 4, The oxide semiconductor film contains In, Ga, and Zn, A display device.

6. In any one of Claims 1 to 4, The oxide semiconductor contained in the oxide semiconductor film is indium oxide, A display device.

Images