Photoresist development with organic vapor

Abstract

SOLUTION: To provide developing a resist which is useful, for example, to form a patterning mask in the context of high resolution patterning, in which development can be accomplished using an organic vapor, such as a carboxylic acid, and in some embodiments, the organic vapor is trifluoroacetic acid, and in some embodiments, the organic vapor is hexafluoroacetylacetone, and metal-containing resist films, such as EUV-sensitive organometallic oxides, can be deposited on semiconductor substrates using dry or wet deposition techniques, and metal-containing resist films on semiconductor substrates can be developed using organic vapors, or residues of metal-containing resist materials formed on surfaces of a process chamber can be removed using organic vapors.SELECTED DRAWING: Figure 6B

Description

Technical Field

[0001] Incorporation by Reference As part of this application, a PCT application form is filed simultaneously with this specification. Each application specified in the simultaneously filed PCT application form, for which this application claims benefit or priority, is hereby incorporated by reference in its entirety for all purposes into this specification.

Background Art

[0002] The fabrication of semiconductor devices such as integrated circuits is a multi-step process involving photolithography. Generally, this process includes depositing materials onto a wafer and patterning the materials using lithographic techniques to form the structural features of the semiconductor device (e.g., transistors and circuits). Steps in a typical photolithography process known in the art include preparing a substrate to which a photoresist is applied, such as by spin coating, exposing the photoresist to light in a desired pattern to render the exposed regions of the photoresist somewhat soluble in a developer, developing by applying the developer to remove either the exposed or unexposed regions of the photoresist, and performing subsequent processing to form features on the regions of the substrate from which the photoresist has been removed, such as by etching or material deposition.

[0003] The evolution of semiconductor design has created a need for, and has been driven by, the ability to form ever smaller features on semiconductor substrate materials. This technological advancement is characterized in "Moore's Law" as the doubling of the transistor density in high-density integrated circuits every two years. In fact, chip design and manufacturing have advanced to the point where the latest microprocessors can include billions of transistors and other circuit features on a single chip. Individual features on such chips can be on the order of 22 nanometers (nm) or less, and in some cases less than 10 nm.

[0004] One challenge in manufacturing devices with such small features is the ability to reliably and reproducibly form a photolithography mask with sufficient resolution. Current photolithography processes typically use 193 nm ultraviolet (UV) light to expose photoresist. The fact that the light has a wavelength significantly longer than the desired size of the features fabricated on the semiconductor substrate causes inherent problems. To achieve feature sizes smaller than the wavelength of the light, the use of complex resolution enhancement techniques such as multipatterning is necessary. Therefore, there is great interest and research effort being directed towards the development of photolithography techniques that use short-wavelength light such as extreme ultraviolet (EUV) light having a wavelength of 10 nm to 15 nm, for example, 13.5 nm.

[0005] However, EUV photolithography processes may have issues such as reduced output and light loss during patterning. Conventional chemically amplified resists (CARs) similar to those used in 193 nm UV lithography have potential drawbacks when used in EUV lithography because they have a low absorption coefficient, especially in the EUV region, and the diffusion of photoactivated species can cause blurring or line edge roughness. Additionally, small features patterned with conventional CAR materials can result in high aspect ratios that pose a risk of pattern collapse in order to provide the etching resistance necessary to pattern the underlying device layer. Therefore, there remains a need for improved EUV photoresist materials having properties such as reduced thickness, greater absorbance, and greater etching resistance.

[0006] The description of the background provided herein is for the purpose of generally presenting the context of the present technology. Within the scope of what is described in this background section, the research by the inventors named at the present time, as well as aspects of the description that cannot be separately regarded as prior art as of the time of filing the application, are not admitted as prior art against the present technology, whether explicitly or implicitly. SUMMARY OF THE INVENTION

[0007] A method of developing a photo-patterned metal-containing resist is provided herein. The method includes providing a photo-patterned metal-containing resist on a surface of a semiconductor substrate within a process chamber and dry-developing the resist by selectively removing a portion of the photo-patterned metal-containing resist by exposing it to a developing chemical including an organic vapor to form a resist mask.

[0008] In some embodiments, the organic vapor includes a carboxylic acid. In some embodiments, the organic vapor includes trifluoroacetic acid. In some embodiments, the organic vapor includes trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, chlorodifluoroacetic acid, thioacetic acid, or thioglycolic acid. In some embodiments, the organic vapor includes hexafluoroacetylacetone. In some embodiments, the developing chemical includes a gas-phase mixture of a halogenated carboxylic acid and a hydrogen halide. In some embodiments, dry-developing the photo-patterned metal-containing resist includes reacting the organic vapor with the photo-patterned metal-containing resist to form volatile compounds at a temperature of less than about 200°C. In some embodiments, dry-developing the photo-patterned metal-containing resist includes exposing it to at least the organic vapor in a plasma-free thermal process. In some embodiments, the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist, and the photo-patterned metal-containing EUV resist is an organometallic oxide or an organometallic-containing film. In some embodiments, dry-developing the photo-patterned metal-containing resist includes selectively removing the EUV non-exposed portion of the resist relative to the EUV-exposed portion of the resist using the developing chemical to form a resist mask.

[0009] A method for removing residues from one or more surfaces of a process chamber is also provided. The method includes depositing a metal-containing resist material on a surface of a semiconductor substrate within the process chamber, wherein a portion of the metal-containing resist material forms residues on one or more surfaces of the process chamber, and introducing a dry etchant containing an organic vapor into the process chamber, wherein the dry etchant at least partially removes the residues on one or more surfaces of the process chamber.

[0010] In some embodiments, the organic vapor includes a carboxylic acid. In some embodiments, the organic vapor includes trifluoroacetic acid. In some embodiments, the organic vapor includes trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, chlorodifluoroacetic acid, thioacetic acid, or thioglycolic acid. In some embodiments, the organic vapor includes hexafluoroacetylacetone. In some embodiments, the dry etchant includes a gas-phase mixture of a halogenated carboxylic acid and a hydrogen halide. In some embodiments, at least partial removal of the residues includes reacting the organic vapor with the metal-containing resist material to form volatile compounds at a temperature of less than about 200°C. In some embodiments, at least partial removal of the residues includes exposing at least to the organic vapor in a plasma-free thermal process. In some embodiments, the metal-containing resist material is an organometallic oxide or an organometallic-containing film. In some embodiments, the method further includes purging the process chamber after introducing the dry etchant to remove residual dry etchant from the process chamber, and conditioning one or more surfaces of the process chamber by forming a protective coating of the metal-containing resist material on one or more surfaces of the process chamber. BRIEF DESCRIPTION OF THE DRAWINGS

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[0024] The present disclosure generally relates to the field of semiconductor processing. In certain aspects, the present disclosure is directed to processes and apparatuses for developing a photoresist (e.g., an EUV-sensitive metal and / or metal oxide-containing photoresist) using an organic vapor, such as an organic acid, to form a patterning mask in, for example, EUV patterning or other wavelength patterning scenarios. Although the following description focuses on EUV photoresists, it will be apparent that the photoresists described herein may also be suitable for use with radiation of other wavelengths, and the techniques and apparatuses described herein are not limited to the manufacture of EUV photoresists only.

[0025] Reference will now be made in detail to specific embodiments of the present disclosure. Examples of specific embodiments are shown in the accompanying drawings. While the present disclosure will be described in conjunction with these specific embodiments, it will be understood that the present disclosure is not intended to be limited to such specific embodiments. On the contrary, the present disclosure is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0026] Introduction Patterning of thin films in semiconductor processing is often an important step in semiconductor manufacturing. Patterning involves lithography. In conventional photolithography, such as 193 nm photolithography, a pattern is printed by emitting photons from a photon source onto a mask and printing that pattern onto a photosensitive photoresist, thereby causing a chemical reaction within the photoresist and, after development, removing certain portions of the photoresist to form the pattern.

[0027] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include 22 nm, 16 nm, and subsequent nodes. For example, at the 16 nm node, the width of a typical via or line in a damascene structure is typically about 30 nm or less. Scaling of features on advanced semiconductor integrated circuits (ICs) and other devices drives lithography to improve resolution.

[0028] Extreme ultraviolet (EUV) lithography can extend lithography technology by shifting to an imaging source wavelength shorter than what is achievable with conventional photolithography methods. An EUV light source with a wavelength of about 10 - 20 nm, or 11 - 14 nm, such as a wavelength of 13.5 nm, can be used in state-of-the-art lithography tools, also called scanners. Since EUV radiation is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor, it operates in a vacuum.

[0029] EUV lithography utilizes EUV resist that is patterned to form a mask for use in etching the underlying layer. The EUV resist may be a polymer-based chemically amplified resist (CAR) obtained by a liquid-based spin-on technique. Alternatives to CAR are available from Inpria of Corvallis, Oregon, and are, for example, metal oxide-containing films that are directly photopatternable, such as those described in U.S. Patent Application Publication No. 2017 / 0102612, U.S. Patent Application Publication No. 2016 / 021660, and U.S. Patent Application Publication No. 2016 / 0116839, the disclosures of which are incorporated herein by reference at least with respect to the disclosure of photopatternable metal oxide-containing films. Such films can be provided by spin-on techniques or dry vapor deposition. The metal oxide-containing films are, for example, described in U.S. Patent No. 9,996,004, issued June 12, 2018, entitled EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS, and / or International Patent Application No. PCT / US2019 / 31618, filed May 9, 2019, entitled METHODS FOR MAKING EUV PATTERNABLE HARD MASKS, and can be patterned directly (i.e., without using a separate photoresist) by EUV exposure in a vacuum atmosphere that provides a patterning resolution of less than 30 nm, and the disclosures of the above relating at least to the composition, deposition, and patterning of a directly photopatternable metal oxide film for forming an EUV resist mask are incorporated herein by reference. Generally, patterning involves exposing the EUV resist with EUV radiation to form a photopattern in the resist, followed by development to remove a portion of the resist according to the photopattern to form the mask.

[0030] This disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, but it should also be understood that it is applicable to other next-generation lithography techniques. In addition to EUV with the standard 13.5 nm EUV wavelength currently in use and being developed, the radiation sources most relevant to such lithography generally refer to DUV (deep UV), which refers to the use of an excimer laser source of 248 nm or 193 nm, X-rays including EUV in the lower energy range of the X-ray spectrum, and e-beams that can cover a wide energy range. The particular method may depend on the particular materials and applications used in the semiconductor substrate and the final semiconductor device. Accordingly, the methods described in this application are merely illustrative of methods and materials that may be used in this technology.

[0031] EUV resists that are directly photo-patternable can be composed of, or contain, metals and / or metal oxides mixed within an organic component. The metal / metal oxides are very promising in that they can enhance the absorption of EUV photons, generate secondary electrons, and / or exhibit high etch selectivity with respect to the underlying film stack and device layers. To date, these resists have been developed using wet (solvent) techniques, which require the wafer to be transferred to a track where the wafer is exposed to a developing solvent, dried, and baked. Wet development not only limits productivity but can also cause line collapse due to surface tension effects and / or delamination between layers.

[0032] To overcome these problems by eliminating substrate peeling and interfacial defects, dry development techniques have been proposed. Dry development can improve performance at narrower line widths (e.g., prevent line collapse and delamination due to surface tension seen in wet development) and has the potential to improve throughput (e.g., by avoiding the need for wet development tracks). Other advantages can include elimination of the use of organic solvent developers, reduced sensitivity to underlying adhesion, and elimination of solubility-based limitations. Dry development provides further tunability and is also capable of performing critical dimension (CD) control and scum removal.

[0033] Dry development has unique challenges, including the etching selectivity between unexposed resist material and EUV-exposed resist material, and the dose for effective resist exposure may be higher compared to wet development when considering size requirements. Suboptimal selectivity can also round the PR corner due to a decrease in contrast at the feature edge, which may increase the variation in line CD in the next transfer etching step.

[0034] Dry Removal of Metal-Containing Resist According to various aspects of the present disclosure, a photopatterned metal-containing photoresist is developed by exposure to the vapor of an organic acid or other vapor-phase precursor. An EUV-sensitive metal or metal oxide-containing film, such as an organotin oxide, is disposed on a semiconductor substrate. The EUV-sensitive metal or metal oxide-containing film is directly patterned by EUV exposure in a vacuum atmosphere. Next, a developer chemical is used to develop the pattern and form a resist mask. In some embodiments, the developer chemical is a dry developer chemical. In some embodiments, the dry developer chemical includes an organic vapor such as trifluoroacetic acid. Such dry development techniques can be performed while flowing an organic vapor and using either a gentle plasma (high pressure, low power) or a non-plasma thermal process. Additionally or alternatively, the present disclosure provides for dry chamber cleaning of EUV resist material or metal-containing resist material from the inner surface of a process chamber by exposure to an organic acid or other vapor-phase precursor. In some embodiments, the organic vapor is trifluoroacetic acid. The dry cleaning may be a non-plasma thermal-based cleaning operation. The dry chamber cleaning can be performed in any process chamber used for deposition, bevel edge, and / or backside cleaning, baking, development, or etching operations.

[0035] Various embodiments of the present disclosure can include combinations of all dry operations by vapor deposition, EUV lithographic patterning, and dry development. Various other embodiments include combinations of wet processing operations and dry processing operations. For example, a spin-on EUV photoresist (wet process) can be combined with dry development or other wet or dry processes as described herein. Also described are various post-deposition (or post-application) processes such as bevel and backside cleaning, chamber cleaning, descumming, planarization, curing to modify and enhance film characteristics, and photoresist rework processes.

[0036] FIG. 1 shows a flow diagram of an exemplary method for depositing and developing a photoresist according to some embodiments. The operations of process 100 may be performed in a different order and / or with a different, fewer, or additional number of operations. Aspects of process 100 may be described with reference to FIGS. 2, 3A-3C, 4A-4B, 5, and 6A-6D. One or more operations of process 100 may be performed using the apparatus described in any one of FIGS. 7-11B. In some embodiments, the operations of process 100 may be implemented, at least in part, in accordance with software stored on one or more non-transitory computer-readable media. In some embodiments, dry chamber cleaning may be performed after deposition, backside cleaning and bevel edge cleaning, post-application bake, post-exposure bake, or dry development.

[0037] In block 102 of process 100, a layer of photoresist is deposited. This can be either a dry deposition process such as a vapor deposition process or a wet process such as a spin-on deposition process.

[0038] The photoresist may be a metal-containing EUV resist. An EUV-sensitive metal or metal oxide-containing film may be deposited on the semiconductor substrate by any suitable technique including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, the described process has been demonstrated for an EUV photoresist composition based on organotin oxide and is applicable to both commercially available spin-coatable formulations (e.g., formulations available from Inpria Corp, Corvallis, Oregon) and formulations applied using the dry vacuum deposition techniques further described below.

[0039] The semiconductor substrate can include any material structure suitable for photolithography processing, particularly for the production of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer having features with irregular surface topography ("underlying features") formed thereon. As referred to herein, "surface" is the surface on which the films of the present disclosure are deposited or the surface that is exposed to EUV during processing. The underlying features can include regions where material has been removed (e.g., by etching) or regions where material has been added (e.g., by deposition) during processing prior to performing the methods of the present disclosure. Such preprocessing can include the methods of the present disclosure or other processing methods in an iterative process in which two or more layers of features are formed on the substrate.

[0040] An EUV-sensitive thin film can be deposited on the semiconductor substrate, and such a film can operate as a resist for subsequent EUV lithography and processing. Such an EUV-sensitive thin film undergoes changes such as the loss of bulky pendant substituents bonded to metal atoms in a low-density M-OH-enriched material when exposed to EUV, and includes materials that enable crosslinking to a higher-density M-O-M-bonded metal oxide material. Through EUV patterning, regions of the film are formed that have changed physical or chemical properties compared to the non-exposed regions. These properties can be utilized in subsequent processing, such as to dissolve either the non-exposed or exposed regions, or to selectively deposit material on either the exposed or non-exposed regions. In some embodiments, the non-exposed film has a more hydrophobic surface than the exposed film under the conditions under which such subsequent processing is performed. For example, the removal of material may be performed by taking advantage of differences in the chemical composition, density, and crosslinking of the film. The removal can be performed by wet or dry processing, as further described below.

[0041] The thin film, in various embodiments, is an organometallic material, such as an organotin material containing tin oxide, or other metal oxide materials / parts. The organometallic compound can be made by the gas-phase reaction of an organometallic precursor and a counter-reagent. In various embodiments, the organometallic compound is formed by mixing a specific combination of organometallic precursors having bulky alkyl groups or fluoroalkyl groups with a counter-reagent and polymerizing the mixture in the gas phase, generating a low-density EUV-sensitive material that deposits on a semiconductor substrate.

[0042] In various embodiments, the organometallic precursor contains at least one alkyl group on each metal atom that can withstand the gas-phase reaction, but other ligands or ions coordinated to the metal atom can be replaced by the counter-reagent. The organometallic precursor includes organometallic precursors of the following formula: M a R b L c (Formula 1)

[0043] wherein M is an element having a high patterning radiation absorption cross-section, R is an alkyl such as C n H 2n+1 etc., preferably n = 1 to 6, L is a ligand, ion, or other moiety that reacts with the counter-reagent, and a ≧ 1, b ≧ 1, and c ≧ 1. In various embodiments, M has an atomic absorption cross-section of 1×10 7 cm 2 / mol or more. M can be selected from the group consisting of, for example, tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, M is tin. R is, for example, of the formula C n F x H (2n+1)It may be fluorinated to have. In various embodiments, R has at least one beta hydrogen or beta fluorine. For example, R can be selected from the group consisting of methyl, ethyl, i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec-butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L can be any moiety that is easily substituted by a reverse reactant to produce an M-OH moiety, such as a moiety selected from the group consisting of amines (dialkylamino, monoalkylamino, etc.), alkoxy, carboxylate, halogen, and mixtures thereof.

[0044] The organometallic precursor can be any of a wide variety of candidate organometallic precursors. For example, when M is tin, such precursors include t-butyltris(dimethylamino)tin, i-butyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, i-propyl(tris)dimethylaminotin, n-propyltris(dimethylamino)tin, ethyltris(dimethylamino)tin, and similar alkyl(tris)(t-butoxy)tin compounds, such as t-butyltris(t-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0045] The reverse reactant has the ability to substitute a reactive moiety, ligand, or ion (e.g., L in Formula 1 above) to link at least two metal atoms via a chemical bond. Reverse reactants can include water, peroxides (e.g., hydrogen peroxide), dihydroxy or polyhydroxy alcohols, fluorinated dihydroxy or polyhydroxy alcohols, fluorinated glycols, and other sources of hydroxyl moieties. In various embodiments, the reverse reactant reacts with the organometallic precursor by forming an oxygen bridge between adjacent metal atoms. Other potential reverse reactants include hydrogen sulfide and hydrogen disulfide, which can bridge metal atoms via sulfur bridges.

[0046] The film may include optional materials in addition to the organometallic precursor and the counter-reactant, and can modify the chemical or physical properties of the film, such as modifying the sensitivity of the film to EUV or enhancing the etching resistance. Such optional materials may be introduced, for example, by doping during vapor phase formation before deposition onto the semiconductor substrate, after deposition of the thin film, or both. In some embodiments, some Sn-L bonds can be replaced with Sn-H by introducing a gentle remote H2 plasma, thereby enhancing the reactivity of the resist under EUV.

[0047] In various embodiments, the EUV-patternable film is fabricated using vapor deposition equipment and processes known in the art and deposited on a semiconductor substrate. In such processes, the polymeric organometallic material is formed in the vapor phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD using CVD components, such as a discontinuous ALD-like process in which the metal precursor and the counter-reactant are separated either in time or in space.

[0048] Generally, the method includes mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant to form a polymeric organometallic material and depositing the organometallic material on the surface of a semiconductor substrate. In some embodiments, a plurality of organometallic precursors are included in the vapor stream. In some embodiments, a plurality of counter-reactants are included in the vapor stream. As will be understood by those skilled in the art, the mixing and deposition aspects of the process can be carried out simultaneously in a substantially continuous process.

[0049] In an exemplary continuous CVD process, in separate inlet paths, two or more gas streams of organometallic precursors and reverse reactants are introduced into the deposition chamber of the CVD apparatus, where they mix and react in the gas phase to form an aggregated polymer material (e.g., via metal-oxygen-metal bond formation). The gas streams can be introduced, for example, using separate injection inlets or a dual-plenum showerhead. The apparatus is configured such that the organometallic precursor and reverse reactant streams are mixed within the chamber, whereby the organometallic precursor and reverse reactant can react to form a polymerized organometallic material. Without limiting the mechanism, function, or utility of the present technology, it is believed that the product from such a gas-phase reaction becomes heavier in molecular weight as metal atoms are crosslinked by the reverse reactant and then either condenses or, in some cases, deposits on a semiconductor substrate. In various embodiments, the steric hindrance of bulky alkyl groups prevents the formation of a densely packed network and generates a smooth, amorphous, low-density film.

[0050] The CVD process is generally carried out at a reduced pressure, such as 10 millitorr to 10 torr. In some embodiments, the process is carried out at 0.5 to 2 torr. In some embodiments, the temperature of the semiconductor substrate is below the temperature of the reactant stream. For example, the substrate temperature can be from 0 °C to 250 °C, or from ambient temperature (e.g., 23 °C) to 150 °C. In various processes, the deposition of the polymerized organometallic material on the substrate occurs at a rate inversely proportional to the surface temperature.

[0051] In some embodiments, EUV-patternable films are fabricated using wet deposition equipment and processes known in the art and deposited on a semiconductor substrate. For example, the organometallic material is formed on the surface of the semiconductor substrate by spin coating.

[0052] The thickness of the EUV-patternable film formed on the surface of the semiconductor substrate can vary according to surface characteristics, the materials used, and the processing conditions. In various embodiments, the film thickness can be in the range of 0.5 nm to 100 nm and can be thick enough to absorb most of the EUV light under EUV patterning conditions. The EUV-patternable film can support absorption of 30% or more, thereby significantly reducing the available EUV photons towards the bottom of the EUV-patternable film. High EUV absorption results in more crosslinking and densification near the top of the EUV exposure film compared to the bottom of the EUV exposure film. If crosslinking is insufficient, the resist may be prone to lift-off or collapse during wet development, but such risks do not exist in dry development. The all-dry lithography approach can facilitate more efficient utilization of EUV photons by a more opaque resist film. Efficient utilization of EUV photons can be achieved with an EUV-patternable film with a higher overall absorption rate, although it will be understood that in some cases the EUV-patternable film can be less than about 30%. For comparison, since the maximum overall absorption rate of most other resist films is less than 30% (e.g., 10% or less, or 5% or less), the resist material at the bottom of the resist film is sufficiently exposed. In some embodiments, the film thickness is 10 nm to 40 nm, or 10 nm to 20 nm. Without limiting the mechanisms, functions, or utilities of the present disclosure, the processes of the present disclosure have few limitations on the surface adhesion properties of the substrate and can thus be applied to a wide variety of substrates. Further, as described above, the deposited film closely conforms to the surface features and can provide advantages when forming a mask on a substrate, such as a substrate having underlying features, without "filling" or planarizing such features.

[0053] In addition to depositing a metal-containing EUV resist thin film on a semiconductor substrate at block 102 of process 100, some metal-containing EUV resist materials may form as residues on the inner surfaces of the process chamber. The inner surfaces may include the chamber walls, floor, and ceiling of the process chamber. Other inner surfaces may include the showerhead, nozzle, and substrate support surface. The metal-containing EUV resist materials can be formed as a result of a dry deposition process such as a CVD or ALD process. The thickness of the residues of the metal-containing EUV resist materials may increase over time as a result of additional processing (e.g., deposition) operations performed within the process chamber. The residues tend to peel off from the inner surfaces of the process chamber, drop particles, or exfoliate, causing contamination in downstream processes.

[0054] At block 150 of process 100, dry chamber cleaning is performed after depositing the metal-containing EUV resist thin film at block 102 of process 100. This enables the deposition and dry cleaning to be performed within the same process chamber. However, it will be understood that in some embodiments, the dry chamber cleaning may be performed in a process chamber different from the deposition operation. In fact, the dry chamber cleaning may be performed after a bevel edge and / or backside cleaning, bake, develop, or etching operation, which may or may not be the same as the deposition chamber, because residues may also form in the chamber in which any of these operations are performed.

[0055] The dry-deposited EUV resist materials to be removed generally consist of Sn, O, and C, but the same cleaning technique can be extended to other metal oxide resist and material films. In addition, this technique can be used for film stripping and photoresist reprocessing.

[0056] In block 104, an optional cleaning process is performed to clean the back surface and / or bevel edge of the semiconductor substrate. The back surface and / or bevel edge cleaning can non-selectively etch the EUV resist film and evenly remove films with various levels of oxidation or cross-linking on the substrate back surface and bevel edge. During the application of an EUV patterning-capable film by wet deposition or dry deposition processes, unintentional deposition of resist material may occur on the bevel edge and / or back surface of the substrate. Due to the unintentional deposition, undesirable particles may later move to the upper surface of the semiconductor substrate and become particle defects. Further, this bevel edge and back surface deposition may also cause downstream processing problems, including contamination of patterning (scanner) and development tools. Conventionally, this bevel edge removal and back surface deposition have been performed by wet cleaning techniques. In the case of a spin-coated photoresist material, this process is called edge bead removal (EBR) and is carried out by inducing a solvent flow from above and below the bevel edge while the substrate is spinning. The same process can be applied to a soluble organotin oxide-based resist deposited by vapor deposition techniques.

[0057] The bevel edge and / or back surface cleaning of the substrate may be a dry cleaning process. In some embodiments, the dry cleaning process involves a vapor and / or plasma having one or more of the following gases: HBr, HCl, BCl3, SOCl2, Cl2, BBr3, H2, O2, PCl3, CH4, methanol, ammonia, formic acid, NF3, HF. In some embodiments, the dry cleaning process may use the same chemicals as the dry development process described herein. For example, organic acids such as trifluoroacetic acid or other organic vapors can be used for bevel edge and / or back surface cleaning. For the bevel edge and / or back surface cleaning process, it is necessary to limit the vapor and / or plasma to a specific area of the substrate so that only the back surface and bevel are surely removed without degrading the film on the front side of the substrate.

[0058] The process conditions can be optimized for bevel edge and / or backside cleaning. In some embodiments, it is possible to increase the etching rate by higher temperature, higher pressure, and / or higher reactant flow rate. Process conditions suitable for dry bevel edge and backside cleaning can be as follows: depending on the photoresist film as well as the composition and properties, a reactant flow rate of 100 to 10,000 sccm (e.g., 500 sccm of HCl, HBr, HI, or H2 and Cl2 or Br2, BCl3 or H2, or other halogen-containing compounds), a temperature of 20 to 140 °C (e.g., 80 °C), a pressure of 20 to 1000 mTorr (e.g., 100 mTorr), or a pressure of 50 to 765 Torr (e.g., 760 Torr), a plasma power of 0 to 500 W at high frequency (e.g., 13.56 MHz), and a time of about 10 to 20 seconds. Bevel and / or backside cleaning can be achieved using the Coronus® tool available from Lam Research in Fremont, California, although a wider range of process conditions can be used depending on the capabilities of the processing reactor.

[0059] Bevel edge and / or backside cleaning can instead be extended to a complete photoresist removal or photoresist “rework” where the applied EUV photoresist is removed and the semiconductor substrate is prepared for re - application of the photoresist, such as when the original photoresist is damaged or has other defects. Since photoresist rework should be achieved without damaging the underlying semiconductor substrate, oxygen - based etching should be avoided. Instead, variants of organic vapor chemicals or halogen - containing chemicals as described herein can be used. It will be understood that the photoresist rework operation can be applied at any stage during process 100. Thus, the photoresist rework operation can be applied after deposition, after bevel edge and / or backside cleaning, after PAB treatment, after EUV exposure, after PEB treatment, after development, or after hard bake. In some embodiments, photoresist rework may be performed to non - selectively remove both exposed and unexposed regions of the photoresist, but selectively remove with respect to the underlying layer.

[0060] In some embodiments, the photoresist rework process involves vapors and / or plasmas having one or more of the following gases: HBr, HCl, HI, BCl3, Cl2, BBr3, H2, PCl3, CH4, methanol, ammonia, formic acid, NF3, HF. In some embodiments, photoresist rework can use the same chemicals as the dry development process described herein. For example, organic acids such as trifluoroacetic acid or other organic vapors can be used for photoresist rework.

[0061] Process conditions can be optimized for photoresist rework. In some embodiments, higher temperature, higher pressure, and / or higher reactant flow rates can increase the etching rate. Process conditions suitable for photoresist rework can be as follows: Depending on the photoresist film as well as composition and properties, a reactant flow rate of 100 - 500 sccm (e.g., 500 sccm of HCl, HBr, HI, BCl3 or H2 and Cl2 or Br2), a temperature of 20 - 140 °C (e.g., 80 °C), a pressure of 20 - 1000 mTorr (e.g., 300 mTorr), or a pressure of 50 - 765 Torr (e.g., 760 Torr), plasma power of 0 - 800 W (e.g., 500 W) at a high frequency (e.g., 13.56 MHz), a wafer bias of 0 - 200 V b (higher bias can be used the harder the underlying substrate material), and a time of about 20 seconds to 3 minutes sufficient to completely remove the EUV photoresist. These conditions are suitable for some processing reactors, e.g., the Kiyo etch tool available from Lam Research in Fremont, California, but it should be understood that a wider range of process conditions can be used depending on the capabilities of the processing reactor.

[0062] In block 150 of process 100, the dry chamber cleaning operation may be performed after the bevel edge and / or backside cleaning in block 104 of process 100. This enables the bevel edge and / or backside cleaning and the dry chamber cleaning to be performed in the same process chamber. However, it will be understood that in some embodiments, the dry chamber cleaning may be performed in a different process chamber than the bevel edge and / or backside cleaning.

[0063] In block 106 of process 100, an optional post-application bake (PAB) is performed after the deposition of the metal-containing EUV resist film and before EUV exposure. The PAB process can involve a combination of heat treatment, exposure to chemicals, and moisture to increase the EUV sensitivity of the metal-containing EUV resist film, thereby reducing the EUV dose and developing a pattern in the metal-containing EUV resist film. The PAB treatment temperature can be adjusted and optimized to increase the sensitivity of the metal-containing EUV resist film. For example, the treatment temperature can be about 90°C to about 200°C, or about 150°C to about 190°C. In some embodiments, the PAB treatment can be performed at a pressure between atmospheric pressure and vacuum for a treatment period of about 1 to 15 minutes, such as about 2 minutes. In some embodiments, the PAB treatment is performed at a temperature of about 100°C to 230°C for about 1 to 2 minutes.

[0064] In block 150 of process 100, a dry chamber cleaning operation may be performed after the PAB treatment in block 106 of process 100. This enables baking and dry chamber cleaning to be performed in the same process chamber. However, it will be understood that in some embodiments, the dry chamber cleaning may be performed in a process chamber different from the PAB treatment.

[0065] In block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally speaking, EUV exposure causes changes in the chemical composition and cross-linking in the metal-containing EUV resist film, resulting in a contrast in etch selectivity that can be utilized in subsequent development.

[0066] Next, the metal-containing EUV resist film can typically be patterned by exposing the film region to EUV light, typically under relatively high vacuum. EUV devices and imaging methods useful herein include methods known in the art. In particular, as described above, the exposed region of the film is formed by EUV patterning in which the physical or chemical properties are changed compared to the unexposed region. For example, in the exposed region, cleavage of the metal-carbon bond may occur by elimination of beta hydride, leaving reactive and accessible metal hydride functional groups that can be converted to hydroxide and crosslinked metal oxide moieties via metal-oxygen bridges during a subsequent post-exposure bake (PEB) step. This process can be used to form a chemical contrast for development as a negative resist. Generally, the higher the number of beta Hs in the alkyl group, the higher the sensitivity of the film. This can also be explained as a weak Sn-C bond with more branching. Following exposure, baking the metal-containing EUV resist film can cause further crosslinking of the metal oxide film. The difference in properties between the exposed and unexposed regions can be utilized in subsequent processing, such as dissolving the unexposed region or depositing material on the exposed region. For example, a dry method can be used to develop the pattern and form a metal oxide-containing mask.

[0067] In particular, in various embodiments, the hydrocarbyl-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed region of the imaging layer, particularly when the exposure is performed in vacuum using EUV. However, removing the exposed imaging layer from vacuum to air, or introducing oxygen, ozone, H2O2, or water in a controlled manner, may oxidize the surface Sn-H to Sn-OH. The difference in properties between the exposed and unexposed regions can be utilized in subsequent processing by, for example, reacting one or both of the irradiated region, non-irradiated region, or both with one or more reagents to selectively add material to the imaging layer or remove material from the imaging layer.

[0068] Without limiting the mechanism, function, or utility of the present technology, for example, EUV exposure at a dose of 10 mJ / cm 2 ~100 mJ / cm 2 results in cleavage of the Sn-C bond, thereby causing the loss of the alkyl substituent, reducing steric hindrance, and thus enabling the collapse of the low-density film. In addition, the reactive metal-H bond generated by the beta-hydrogen elimination reaction can react with adjacent active groups such as hydroxyl in the film, which leads to further cross-linking and densification and can form a chemical contrast between the exposed and unexposed regions.

[0069] After exposing the metal-containing EUV resist film to EUV light, a photopatterned metal-containing EUV resist is provided. The photopatterned metal-containing EUV resist includes an EUV exposure region and an EUV unexposed region.

[0070] In block 110 of process 100, an optional post-exposure bake (PEB) is performed to further enhance the contrast in etching selectivity of the photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist can be heat-treated in the presence of various chemical species to promote cross-linking in the EUV exposure region, or simply baked on a hot plate in ambient air at, for example, 100°C to 250°C for 1 to 5 minutes (e.g., 2 minutes at 190°C).

[0071] In various embodiments, the bake strategy involves careful control of the bake atmosphere, introduction of reactive gases, and / or careful control of the ramp rate of the bake temperature. Examples of useful reactive gases include, for example, air, H2O, H2O2 vapor, CO2, CO, O2, O3, CH4, CH3OH, N2, H2, NH3, N2O, NO, alcohol, acetylacetone, formic acid, Ar, He, or mixtures thereof. The PEB process is designed to (1) drive complete evaporation of organic fragments generated during EUV exposure, (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated by EUV exposure to metal hydroxides, and (3) promote cross-linking between adjacent Sn-OH groups to form a more densely cross-linked SnO2-like network. The bake temperature is carefully selected to achieve optimal EUV lithography performance. If the PEB temperature is too low, cross-linking will be insufficient, and as a result, the chemical contrast for development at a given dose may decrease. If the PEB temperature is too high, adverse effects such as intense oxidation and film shrinkage in the non-exposed region (the region removed by development of the patterned film to form the mask in this example), and unwanted interdiffusion at the interface between the photopatterned metal-containing EUV resist and the underlying layer may also occur, both of which may contribute to loss of chemical contrast due to insoluble scum and an increase in defect density. The PEB process temperature can be from about 100°C to about 300°C, from about 170°C to about 290°C, or from about 200°C to about 240°C. In some embodiments, the PEB process can be carried out at a pressure between atmospheric pressure and vacuum for a treatment period of about 1 to 15 minutes, for example about 2 minutes. In some embodiments, the PEB heat treatment can be repeated to further enhance the etching selectivity.

[0072] In block 150 of process 100, the dry chamber cleaning operation may be performed after the PEB process in block 110 of process 100. This enables baking and dry chamber cleaning to be performed within the same process chamber. However, it will be understood that in some embodiments, the dry chamber cleaning may be performed in a different process chamber from the PEB process.

[0073] In block 112 of process 100, the photo-patterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, the exposed areas are removed (positive type) or the unexposed areas are removed (negative type). In some embodiments, development may include selective deposition onto either the exposed or unexposed areas of the photo-patterned metal-containing EUV resist, followed by an etching operation. In some embodiments, development may be performed by exposure to one or more organic vapors (e.g., trifluoroacetic acid). Development can be performed without applying plasma in some embodiments. Alternatively, development may be performed by a flow of one or more organic vapors (e.g., trifluoroacetic acid) that are activated within a remote plasma source or by exposure to remote UV radiation. The photoresist for development may include elements selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The elements may have a high patterning radiation absorption cross-section. In some embodiments, the elements may have a high EUV absorption cross-section. In some embodiments, the metal-containing EUV resist can have an overall absorption rate of more than 30%. In an all-dry lithography process, this enables more efficient utilization of EUV photons and enables the development of thicker and more EUV-opaque resists.

[0074] Examples of the development process include subjecting an EUV-sensitive photoresist thin film containing an organotin oxide (e.g., having a thickness of 10 to 30 nm, e.g., 20 nm) to EUV exposure dose and post-exposure bake, and then developing it. The photoresist film may be deposited, for example, based on a gas-phase reaction of an organotin precursor such as isopropyl(tris)(dimethylamino)tin and water vapor, or may be a spin-on film containing tin clusters in an organic matrix.

[0075] In block 150 of process 100, dry chamber cleaning may be performed after dry development in block 112 of process 100. This enables dry development and dry chamber cleaning to be performed in the same process chamber. However, it will be understood that in some embodiments, dry chamber cleaning may be performed in a process chamber different from that for dry development. Further, it will be understood that dry chamber cleaning may be performed in the same process chamber as the etching operation or in a different process chamber. The etching operation may be applied to etch a substrate underlying layer of the semiconductor substrate.

[0076] In block 114 of process 100, the semiconductor substrate is optionally subjected to a hard bake. During the hard bake, the semiconductor substrate is exposed to a high temperature. For example, the semiconductor substrate may be exposed to a high temperature of about 50°C or higher, about 100°C to about 300°C, or about 170°C to about 290°C. The hard bake can remove residual solvent or etching gas from the development.

[0077] FIG. 2 shows a flow diagram of an exemplary method for dry developing a metal-containing resist according to some embodiments. The operations of process 200 may be performed in a different order and / or with a different, fewer, or additional number of operations. Aspects of process 200 may be described with reference to FIGS. 3A-3C and FIGS. 4A-4B. One or more operations of process 200 may be performed using the apparatus described in any one of FIGS. 7-11B. In some embodiments, the operations of process 200 may be implemented, at least in part, in accordance with software stored on one or more non-transitory computer-readable media.

[0078] In block 202 of process 200, a photopatterned metal-containing resist is provided on the surface of a semiconductor substrate within a process chamber. The metal-containing resist may be deposited on the surface of the semiconductor substrate. The metal-containing resist can be exposed to UV radiation (e.g., EUV radiation) by a scanner or EUV lithography tool to form a photopatterned metal-containing resist. In some embodiments, the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist. For example, the photopatterned metal-containing EUV resist is an organometallic oxide or an organometallic-containing film. The semiconductor substrate may be provided in the process chamber after being processed in a scanner and / or a PEB processing chamber.

[0079] In block 204 of process 200, a portion of the photopatterned metal-containing resist is selectively removed by dry-developing the photopatterned metal-containing resist and exposing it to a developing chemical containing organic vapor to form a resist mask. Dry-developing the photopatterned metal-containing resist includes selectively removing the EUV-unexposed portion of the resist relative to the EUV-exposed portion of the resist using a developing chemical to form a resist mask. Typically, development is performed using a wet-developing chemical. Wet development using a solvent generates an undesirable waste stream. Wet development generally involves moisture and / or oxygen and more readily causes scum formation. Wet development is limited by solubility and cluster size, while dry development is not limited by solubility and cluster size. Wet development is more likely to cause problems of pattern collapse and delamination that dry development avoids. Development in the present disclosure is performed in the gas phase using a dry-developing chemical instead of a wet-developing chemical.

[0080] Development using dry - developing chemical substances usually involves the vapor of boron trichloride (BCl3), hydrogen gas (H2) mixed with chlorine gas (Cl2) or bromine gas (Br2), or the vapor of hydrogen halides such as hydrogen bromide (HBr), hydrogen chloride (HCl), or hydrogen fluoride (HF), i.e., the vapor of halogens. However, such vapors may leave residues or scum after development. The residues may include residual etching by - products adsorbed on the surface of the semiconductor substrate and, in some cases, on the chamber walls. For example, the vapor of halogens may react with moisture or oxygen to form residual etching by - products that are difficult to remove. In some cases, the residual etching by - products contain bromides that are sticky and difficult to remove. The accumulation of residual etching by - products may cause process drift, and as a result, dangerous preventive measures may be taken in the process chamber. Furthermore, the residues adsorbed on the semiconductor substrate may desorb from the semiconductor substrate and contaminate downstream processing tools. In some cases, the residues may contain clusters of high - concentration metals or metal oxides that can contaminate downstream processing tools. Also, residual etching by - products are difficult to remove and do not volatilize easily, so separate plasma steps or separate chambers with plasma functions may be required. If they are not present, a high - temperature swing to volatilize the residues is carried out, which is often undesirable for the semiconductor substrate and the process chamber.

[0081] The developing chemical of the present disclosure is an organic vapor. The organic vapor may be an organic acid. In some embodiments, the organic acid includes a carboxylic acid. In some embodiments, the organic acid includes trifluoroacetic acid (CF3COOH). The organic vapor may be halogenated or at least fluorinated. In some embodiments, the organic vapor includes hexafluoroacetylacetone (CF3CCH2CCF3). In some embodiments, the organic vapor includes mixed halide acetic acids such as trifluoroacetic anhydride ((CF3CO)2O), acetic anhydride ((CH3CO)2O), trichloroacetic acid (CCl3COOH), monofluoroacetic acid (CFH2COOH), difluoroacetic acid (CF2HCOOH), chlorodifluoroacetic acid, sulfur-containing analogs of acetic acid, thioacetic acid (CH3COSH), or thioglycolic acid (HSCH2CO2H). In some embodiments, the developing chemical includes a mixture of a carboxylic acid and hydrogen halide in the gas phase. For example, the developing chemical includes a mixture of acetic acid or formic acid and hydrogen chloride or hydrogen bromide. In some embodiments, the organic vapor may be flowed with or without an inert / carrier gas such as helium (He), neon (Ne), argon (Ar), xenon (Xe), and nitrogen (N2).

[0082] Organic vapors may react with metal-containing resists to form by-products that are more volatile than the etching by-products formed from the vapor of halogens. As an example, the etching by-product of tin bromide can have a boiling point of about 200 °C or higher. However, the etching by-product of tin fluoroacetate can be less than about 200 °C. For example, hexatin(II)-di-μ-oxy-octakis-μ-trifluoroacetate(1F) is volatile at 191 °C at 1 Torr, and tin(IV) tetrakis(trifluoroacetate)(2F) is volatile at 84 °C at 1 Torr. Both 1F and 2F provide high thermal stability and volatility. The etching by-products formed from organic vapors that react with metal-containing resists can have excellent volatility. In particular, the etching by-products formed from trifluoroacetic acid that react with EUV non-exposed organometallic resists can have excellent volatility. Without being bound by any theory, trifluoroacetic acid or other fluorinated derivatives of organic acids can enhance the volatility of the etching by-products due to their electron-withdrawing effects. Trifluoroacetic acid or other fluorinated derivatives of organic acids can be strong organic acids.

[0083] The organic vapor of the present disclosure can be a strong organic acid. As used herein, a strong organic acid can have a pKa value of about 3.8 or less. The strength of an organic acid can increase by halogenation. In some embodiments, the strength of the organic acid can increase significantly by fluorination. For example, formic acid or acetic acid can etch a metal-containing resist material such as an organometallic resist material, while trifluoroacetic acid can more effectively etch such a metal-containing resist material. Less strong organic acids (e.g., acetic acid) can be assisted by plasma for selective removal of metal-containing resist materials, while stronger organic acids can selectively remove metal-containing resist materials without plasma assistance. Thus, in the present disclosure, dry development of the metal-containing resist can be performed without plasma assistance. However, as described below, plasma may optionally be used for desorption, descum, or smoothing operations after dry development. This plasma-based desorption, descum, or smoothing operation may be unnecessary when the etching by-products of the organic vapor are volatile.

[0084] The organic vapor of the present disclosure can perform dry development by a plasma-free thermal process. This means that dry development can be carried out in a process chamber without plasma function. In some embodiments, the dry development may be carried out without subsequent plasma-based descum or planarization operations. By eliminating exposure to plasma, plasma damage to the semiconductor substrate can be avoided, costs can be significantly reduced, and throughput can be increased. Further, the inner surface of the process chamber need not be resistant to plasma and can be made of a material resistant to the vapor of halogens such as hydrogen halide. The surfaces of chamber components such as chamber walls, ceilings, and showerheads may be prone to corrosion in the presence of moisture and halogen vapor. As a result, the inner surface of the process chamber is typically composed of a material stable in plasma, halogen vapor, and water vapor. However, in the case of the dry development chemical of the present disclosure such as trifluoroacetic acid, the inner surface of the process chamber of the present disclosure may be composed of a material that does not necessarily meet the above requirements. In some embodiments, the chamber wall of the process chamber may include aluminum oxide, anodized aluminum, or plastic.

[0085] By applying a plasma-free thermal approach, multiple wafers can be batch-developed simultaneously in a low-cost thermal vacuum chamber / oven, thus significantly improving productivity. However, in some embodiments, exposure to plasma may follow the thermal dry development process. The subsequent exposure to plasma may be performed for desorption, descum, planarization, or other processing operations.

[0086] Dry development of a photopatterned metal-containing resist can be combined with other dry processing operations such as dry deposition (e.g., CVD) of the metal-containing resist. In some embodiments, processing of a semiconductor substrate may combine all dry steps including film formation by vapor deposition, EUV lithography patterning, and dry development. Bake operations, bevel edge and / or backside cleaning operations, and chamber cleaning operations may also be dry operations. Such processing operations can avoid the material and production costs associated with wet processing operations such as wet development. Furthermore, dry processing provides additional tunability, resulting in additional critical dimension (CD) control and enabling scum removal. Generally, wet processing involves moisture and / or oxygen and is more likely to cause scum formation. Wet development is limited by solubility and cluster size, while dry development is not limited by solubility and cluster size. Wet development is more prone to pattern collapse and delamination problems that dry development avoids. Additionally, by using all-dry processing operations, integration within interconnected vacuum processing chambers can be facilitated without exposure to ambient air or trace contaminants contained therein and contamination therefrom. For example, a PEB heat treatment where the exposed areas undergo further crosslinking may be performed in the same chamber as development, but it will be understood that the PEB heat treatment may also be performed in a separate chamber.

[0087] In some embodiments, dry development can be performed by using a thermal process while flowing an organic vapor such as trifluoroacetic acid. For example, dry development can be performed in a heat treatment chamber. In some embodiments, the organic vapor such as trifluoroacetic acid can rapidly remove the unexposed portion of the photopatterned metal-containing resist relative to the exposed portion of the photopatterned metal-containing resist, thereby leaving a pattern of the exposed film that can be transferred to a lower layer of the semiconductor substrate by an etching process.

[0088] In some embodiments, the semiconductor substrate can be exposed to a dry development chemical such as a strong organic acid in a heat treatment chamber such as an oven. The heat treatment chamber can include a development chemical line for feeding an organic vapor into the heat treatment chamber. In some embodiments, the heat treatment chamber can include one or more heating elements for temperature control, such as a heating element coupled to a heating assembly facing the semiconductor substrate within the process chamber for substrate temperature control. In some embodiments, the one or more heating elements can be one or more LEDs. The one or more heaters can heat the semiconductor substrate to a high temperature during dry development to facilitate the volatilization of etching by-products.

[0089] In a thermal dry development process, the photopatterned metal-containing resist is exposed to a development chemical optimized for the etching selectivity between the exposed and unexposed regions. Generally, the contrast in etching selectivity can increase at lower temperatures and decrease at higher temperatures. As the temperature increases, the volatilization of etching by-products increases, which may limit the formation of residues on the semiconductor substrate. In some embodiments, the temperature can be less than about 200°C, about 20°C to about 190°C, about 40°C to about 120°C, or about 50°C to about 100°C. By reacting the photopatterned metal-containing resist with an organic vapor, volatile compounds are formed at a temperature less than about 200°C.

[0090] The chamber pressure can be adjusted, and the chamber pressure may affect the etching selectivity between the exposed area and the unexposed area during thermal dry development. In some embodiments, the chamber pressure is relatively low and may be without dilution, and the chamber pressure may be from about 0.1 mTorr to about 1000 mTorr, from about 0.2 mTorr to about 300 mTorr, or from about 0.5 mTorr to about 100 mTorr. In some embodiments, the chamber pressure may be from about 20 mTorr to about 2000 mTorr, or from about 20 mTorr to about 1000 mTorr, such as about 300 mTorr. In some embodiments, the chamber pressure is relatively high at high flow rates and may involve dilution, and the chamber pressure may be from about 100 Torr to about 765 Torr, or from about 200 Torr to about 760 Torr.

[0091] The gas flow rate of the dry development chemical can be adjusted, and the gas flow can affect the etching selectivity between the exposed area and the unexposed area during thermal dry development. In some embodiments, the gas flow may be from about 0.5 SLM to about 30 SLM, from about 1 SLM to about 20 SLM, or from about 2 SLM to about 15 SLM. The gas flow rate can include the total flow rate of the gas being flowed, including organic vapor and carrier gases such as nitrogen and argon. The organic vapor flow rate may be only a portion of the total flow rate, and the organic vapor flow rate can be from about 0.01 SLM to about 1 SLM. In the case of high flow rates, the organic vapor flow rate can be from about 1 SLM to about 10 SLM.

[0092] The exposure period can be adjusted in the thermal dry development process. The exposure time can depend on, among other factors, the amount of resist that is desired to be removed, the development chemical, the amount of crosslinking in the resist, as well as the composition and properties of the resist. In some embodiments, the exposure period can be from about 5 seconds to about 5 minutes, from about 10 seconds to about 3 minutes, or from about 10 seconds to about 1 minute.

[0093] In some embodiments, the photopatterned metal-containing resist is developed by a plasma-free thermal technique. In alternative embodiments, the photopatterned metal-containing resist is developed in a plasma development process. The photopatterned metal-containing resist is exposed to a developing chemical containing radicals / ions of one or more gases. The one or more gases may include an organic vapor such as trifluoroacetic acid. The process chamber for processing the semiconductor substrate for dry development may be a plasma generation chamber or may be coupled to a plasma generation chamber remote from the process chamber. The plasma generation chamber may be an inductively coupled plasma (ICP) reactor, a capacitively coupled plasma (CCP) reactor, or a capacitively coupled plasma (CCP) reactor that uses equipment and techniques known in the art. An electromagnetic field acts on the one or more gases to generate a plasma in the plasma generation chamber. Ions and / or radicals from the remote plasma can interact with the photopatterned metal-containing resist. The ions and / or radicals may include ions and / or radicals of an organic acid such as trifluoroacetic acid. In some embodiments, a vacuum line is coupled to the process chamber for pressure control, and a developing chemical line may be coupled to the plasma generation chamber for feeding one or more gases to the plasma generation chamber. The process chamber can include one or more heaters for temperature control, such as a heater coupled to a heating assembly facing the substrate for substrate temperature control. In some embodiments, the development of the photopatterned metal-containing resist is exposed to conditions optimized to produce a mild plasma characterized by high pressure and low power. In some embodiments, the RF power level can be adjusted, and the RF power may be about 1000 W or less, about 800 W or less, or about 500 W or less.

[0094] In addition to, or instead of, plasma activation, activation of one or more gases in a dry development process can be effected by photoactivation. In some embodiments, photoactivation can be achieved by exposure to ultraviolet (UV) radiation. For example, the process chamber may include a lamp, such as a UV lamp, configured to generate UV radiation. Exposure of one or more gases to UV radiation can generate radicals of one or more gases that can be used for dry development of a photopatterned metal-containing resist. Exposure of one or more gases to UV radiation can be performed without exposing the photopatterned metal-containing resist to UV radiation. In other words, the photopatterned metal-containing resist is not visible from the UV lamp.

[0095] It will be understood that the foregoing methods of thermal development, plasma development, and photoactivation development may be combined with each other. Such development methods can be applied simultaneously or sequentially. One or more development methods can be applied while flowing a dry development chemical in the gas phase. Development can result in a positive or negative type, with the dry development chemical selectively removing either the unexposed or exposed material, leaving the corresponding exposed or unexposed counterpart as a mask.

[0096] As described above, the etching selectivity during dry development is adjustable by controlling process conditions such as temperature, pressure, gas flow, gas composition, and plasma power, among other adjustable process conditions. By adjusting the etching selectivity in a single step or multiple steps, desired patterned characteristics can be achieved. In some embodiments, the etching selectivity during dry development is adjusted over one or more steps, thereby affecting the resist profile. More specifically, the amount of taper or recess angle in the resist profile can be controlled by applying dry development chemistries with different etching selectivities over one or more steps. Descum, photoresist rework, curing, smoothing, and cleaning operations can also be adjusted according to the adjustable etching selectivity.

[0097] Figures 3A to 3C show schematic cross-sectional views of various processing stages of dry development according to some embodiments. The examples shown in Figures 3A to 3C show negative-type dry development. As shown in Figure 3A, the wafer 300 includes a substrate 302 and a substrate layer 304 to be etched. In some embodiments, the substrate layer 304 includes a spin-on carbon (SoC) or other material, such as an ashing-capable hard mask of silicon, silicon oxide, silicon nitride, silicon carbide, etc. In some embodiments, the substrate layer 304 can be a layer stack disposed on the substrate 302. The wafer 300 further includes a photopatterned metal-containing EUV resist film 306. For example, the photopatterned metal-containing EUV resist film 306 may be an organometal-containing layer disposed on the substrate layer 304 to be etched. The photopatterned metal-containing EUV resist film 306 can have a thickness of about 5 nm to about 50 nm, or about 10 nm to about 30 nm. The photopatterned metal-containing EUV resist film 306 can be provided in the process chamber after photopatterning with an EUV scanner and / or after the above-described PEB process. The photopatterned metal-containing EUV resist film 306 includes a non-EUV exposure region 306a and an EUV exposure region 306b. As shown in Figure 3B, the non-EUV exposure region 306a of the photopatterned metal-containing EUV resist film 306 can be removed in the dry development process by exposing it to the flow of dry development chemicals without applying plasma. The dry development chemicals can include organic vapors such as organic acids. The organic acids can include halogenated carboxylic acids or fluorinated carboxylic acids. Examples of organic acids include, but are not limited to, trifluoroacetic acid, hexafluoroacetylacetone, trichloroacetic acid, monofluoroacetic acid, and difluoroacetic acid. Other examples of organic acids include mixed halide acetic acids such as chlorodifluoroacetic acid, sulfur-containing analogs of acetic acid, thioacetic acid, and thioglycolic acid. By removing the non-EUV exposure region 306a after development, a resist mask 308 is formed. Thereafter, the substrate layer 304 to be etched can be etched using the resist mask 308, providing the structure illustrated in Figure 3C.

[0098] The organometallic oxide film can have a tetrahedral coordination structure. The exposed region has a higher level of Sn-O-Sn bridging, resulting in a higher density and lower / slower reactivity with the halogenated carboxylic acid. The unexposed region exhibits a lower density due to the presence of bulky alkyl substituents that block the approach and condensation of the Sn-OH moieties. In the unexposed region, an acid such as trifluoroacetic acid more readily protonates the more "basic" and accessible oxygen lone pairs characteristic of the more tetrahedrally coordinated organotin oxide hydroxide, generating volatile by-products of trifluoroacetate that are removed from the unexposed region. Without being bound by any theory, trifluoroacetic acid may selectively protonate the oxygen lone pairs and form volatile by-products. When the alkyl group is isopropyl, at typical EUV patterning doses, at least two of the three isopropyl substituents are removed, causing the exposed region to condense after the PEB step to form a higher density, more SnO2-like material, which has lower reactivity with trifluoroacetic acid due to the adoption of a more six-coordinate tin structure with less accessible oxygen atoms, resulting in a very slow reactivity with trifluoroacetic acid.

[0099] In some cases, residues or scum may remain after development. Residues can result from slow etching components in inhomogeneous EUV resist formulations, including those applied by spin coating techniques. Such scum may contain high concentrations of metal, which can be problematic during subsequent pattern transfer.

[0100] Additionally or alternatively, roughness may form on the sidewalls of the etched features in the developed pattern after development. Some of this may be due to probabilistic or non-optimal Gaussian distributions of light where material that should remain unexposed in a region is partially or fully exposed, or vice versa, resulting in material that should be exposed being unexposed.

[0101] In some embodiments, dry development may involve a descum / smoothing operation. In some embodiments, the descum and smoothing operations can be an inert gas plasma desorption operation. For example, the inert gas plasma desorption operation may be a helium plasma desorption operation. The inert gas plasma desorption operation can be performed after dry development or repeatedly with dry development.

[0102] FIG. 4A shows a schematic cross-sectional view of dry development without applying an inert gas plasma according to some embodiments. The photo-patterned metal-containing EUV resist film includes an exposed region and an unexposed region. As shown in FIG. 4A, particles or clusters of metal oxide (e.g., SnO x ) may occupy the unexposed region. As dry development progresses, the clusters of metal oxide become more concentrated. The clusters of metal oxide are generally difficult to remove. The development may be selective with respect to the removal of organic materials. After removing the unexposed region, the clusters of metal oxide may remain on the surface of the substrate as scum. The clusters of metal oxide remaining on the sidewalls of the exposed region may cause roughness.

[0103] Figure 4B shows a schematic cross-sectional view of a dry development cycle inert gas plasma for descum according to some embodiments. The first stage involves dry development that removes a substantial portion of the unexposed regions of the photopatterned metal-containing EUV resist film. The dry development chemicals can include, for example, organic acids and / or hydrogen halides. Substantial portion can mean exceeding at least 70% by volume, exceeding 80% by volume, or exceeding 90% by volume of the unexposed region. Clusters of metal oxides concentrate on the surface of the remaining unexposed regions of the EUV resist film. The second stage involves applying an inert gas plasma, such as a helium plasma, for a short period at low power and high ion energy. The helium plasma removes the clusters of metal oxides. In addition, the helium plasma removes clusters from the sidewalls and smoothens the sidewalls. The helium plasma treatment can also help solidify or cure the patterned EUV resist film to form a denser metal oxide like a hard mask. After the helium plasma treatment, a dry etching step with low selectivity can be used to remove the residues remaining in the unexposed regions of the EUV resist film.

[0104] In some embodiments, the dry development may be repeated with the helium plasma treatment over one or more cycles until the unexposed regions of the EUV resist film are removed. The descum / smoothing of the helium plasma can be repeated with the dry development to improve the results, as described above. In this way, for example, most of the organic components in the unexposed regions of the pattern can be removed by dry development, and then a portion of the concentrated metal on the surface can be removed by a short helium plasma operation, thereby allowing access to the remaining underlying organic material, which can be removed in subsequent dry development operations / cycles. Another cycle of the helium plasma can be used to remove the remaining metal, leaving a clean and smooth feature surface. This cycling can continue until all or substantially all of the scum and roughness residues are removed, leaving a clean and smooth feature surface.

[0105] The process conditions for descum and smoothing operations can be controlled during or after development. In some embodiments, the flow rate of the reactant may be from about 50 sccm to about 1000 sccm, or from about 100 sccm to about 500 sccm, such as about 500 sccm of He. In some embodiments, the temperature may be from about -60 °C to about 120 °C, from about -20 °C to about 60 °C, or from about 20 °C to about 40 °C, such as about 20 °C. In some embodiments, the chamber pressure may be from about 1 mTorr to about 300 mTorr, from about 5 mTorr to about 100 mTorr, from about 5 mTorr to about 20 mTorr, such as about 10 mTorr. The plasma power may be relatively low when the ion energy is high. In some embodiments, the plasma power may be from about 50 W to about 1000 W, from about 100 W to about 500 W, or from about 100 W to about 300 W, such as about 300 W. In some embodiments, the wafer bias is from about 10 V to about 500 V, from about 50 V to about 300 V, such as about 200 V. The plasma can be generated using a high RF frequency. In some embodiments, the RF frequency is 13.56 MHz. The period of exposure to the inert gas plasma may be relatively short to avoid excessive exposure to UV radiation during plasma exposure. In some embodiments, the period of exposure is from about 0.5 second to about 5 seconds, from about 1 second to about 3 seconds, such as about 2 seconds.

[0106] The inert gas plasma treatment for descum and cleaning of non-exposed resist residues has the additional advantage of hardening and solidifying the exposed resist, thereby enhancing its hard mask function in subsequent operations for etching the underlying substrate. This resist solidification is achieved by exposing the EUV exposure resist to UV radiation generated by the inert gas plasma, which can continue even after descum / smoothing is completed with the bias turned off. If descum / smoothing is not required or not performed, inert gas plasma hardening may be performed instead.

[0107] The organic vapors of the present disclosure can be used not only in dry development processes, but also in dry chamber cleaning or other processing operations for dry removal of metal-containing resists, such as trifluoroacetic acid.

[0108] FIG. 5 shows a flowchart of an exemplary method of dry chamber cleaning according to some embodiments. The dry chamber cleaning may be performed after deposition, bevel and / or backside cleaning, baking, development, or etching. In some embodiments, the dry chamber cleaning can be performed in the same process chamber as the deposition of the resist material after the deposition of the resist material. The operations of process 500 may be performed in a different order and / or with a different, fewer, or additional number of operations. Aspects of process 500 can be described with reference to FIGS. 6A-6D. One or more operations of process 200 can be performed using the apparatus described in any one of FIGS. 7-11B. In some embodiments, the operations of process 500 may be implemented at least partially in accordance with software stored on one or more non-transitory computer-readable media.

[0109] In block 502 of process 500, a metal-containing resist material is deposited on the surface of a semiconductor substrate within a process chamber, and a portion of the metal-containing resist material forms residues on one or more surfaces of the process chamber. The composition and deposition of such metal-containing resist materials can be described, for example, in International Patent Application No. PCT / US2019 / 31618 filed on May 9, 2019, which is hereby incorporated by reference herein for its disclosure of methods and materials applicable to the present disclosure. The method includes a method of generating a polymerized organometallic material in the gas phase and depositing it on a semiconductor substrate. In some embodiments, the metal-containing resist material is a metal oxide-containing EUV resist material. For example, the elements in the metal-containing resist material are selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, the metal-containing resist material includes an organometallic oxide such as an organotin oxide.

[0110] In some embodiments, the process chamber in which the semiconductor substrate is provided may be a dry deposition chamber. In other embodiments, the process chamber in which the semiconductor substrate is provided can be a bevel edge and / or backside cleaning chamber, a PAB processing chamber, a PEB processing chamber, a development chamber, or an etching chamber. Any of the aforementioned chambers may accumulate metal-containing resist material on the inner surface over time. As the number of semiconductor substrates processed within the processing chamber increases, unintended metal-containing resist material may increase as residues on the inner surface. Regular cleaning is required to remove the unintended deposits of the metal-containing resist material. The cleaning can be performed "in situ", and dry chamber cleaning is performed within the same process chamber where the unintended metal-containing resist material is formed.

[0111] Residues can form on one or more surfaces of the process chamber, and the one or more surfaces can include one or more of the chamber walls, ceiling, floor, showerhead surface, nozzle surface, and substrate support surface. In some embodiments, the residues can be formed as a result of a dry deposition process such as a CVD or ALD process. The thickness of the residues on the one or more surfaces can increase over time as a result of additional processing (e.g., deposition) operations performed within the process chamber. In some embodiments, the average thickness of the residues is about 2 nm or more, about 3 nm or more, about 5 nm or more, or about 10 nm or more. Metal-containing resist materials tend to contaminate subsequent semiconductor substrates during processing by peeling off, dropping particles, or detaching from the one or more surfaces.

[0112] FIG. 6A shows a schematic cross-sectional view of a metal-containing EUV resist material 602 formed on a chamber wall 604 of a process chamber. The metal-containing EUV resist material 602 can include particles or clusters of metal oxide 606. The particles or clusters of metal oxide 606 can be difficult to remove. In some embodiments, the metal-containing EUV resist material 602 is formed by a vapor deposition method such as CVD or ALD. Over time, the metal-containing EUV resist material 602 can accumulate thickly on the chamber wall 604 of the process chamber. The metal-containing EUV resist material 602 can be an organotin oxide. The particles or clusters of metal oxide 606 can include tin oxide.

[0113] Returning to FIG. 5, in block 504 of process 500, a dry etchant containing an organic vapor is introduced into the process chamber, and the dry etchant at least partially removes residues on one or more surfaces of the process chamber. In some embodiments, the organic vapor is an organic acid. The organic acid may be a strong organic acid having a pKa of about 3.8 or less. In some embodiments, the organic acid includes a carboxylic acid. In some embodiments, the organic acid includes trifluoroacetic acid. The organic vapor may be halogenated or at least fluorinated. In some embodiments, the organic vapor includes hexafluoroacetylacetone. In some embodiments, the organic vapor includes mixed halide acetic acids such as trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, chlorodifluoroacetic acid, sulfur-containing analogs of acetic acid, thioacetic acid, or thioglycolic acid. In some embodiments, the dry etchant includes a mixture of a carboxylic acid and a hydrogen halide in the gas phase. For example, the dry etchant includes a mixture of acetic acid or formic acid and hydrogen chloride or hydrogen bromide. In some embodiments, the organic vapor may be flowed with or without an inert / carrier gas such as helium, neon, argon, xenon, and nitrogen.

[0114] In some embodiments, at least partial removal of the residues includes reacting the organic vapor with a metal-containing resist material to form volatile compounds at a temperature of less than about 200 °C. In some embodiments, at least partial removal includes substantial removal of the residues, where "substantial removal" refers to sufficient removal of the residues such that at least a portion of one or more surfaces is exposed after removal.

[0115] In some embodiments, the process chamber can be prepared under desired conditions for dry chamber cleaning before introducing the dry etchant. Preparation of the process chamber can achieve specific pressure conditions, levels of free particles or film impurities, moisture levels, temperature conditions, or protection of surfaces or components (e.g., substrate supports) within the process chamber from the dry etchant. In some embodiments, preparing the process chamber may include purging and / or pumping the process chamber to remove unwanted particles. To facilitate removal of unwanted particles within the process chamber, a purge gas can be flowed through the process chamber. Purging of the organometallic precursor can be useful to avoid unwanted by-products and ensure sufficient removal of the organometallic precursor prior to dry chamber cleaning.

[0116] In some embodiments, the chamber walls and other components can be heated to release unreacted precursors. Heat can additionally or alternatively facilitate removal of moisture within the process chamber. Without being limited by any theory, the presence of moisture may slow the reaction between the dry etchant and the metal-containing resist material for removing the metal-containing resist material. Additionally, as the temperature within the process chamber increases, the etching rate for removing the metal-containing resist material increases. One or more heaters within the process chamber can heat one or more surfaces to a high temperature. In some embodiments, the high temperature can be from about 20°C to about 180°C, from about 40°C to about 160°C, or from about 80°C to about 140°C.

[0117] In some embodiments, preparing the process chamber may include providing a dummy substrate on a substrate support within the process chamber. Thus, the semiconductor substrate on which the metal-containing resist material has been deposited can be transferred out of the process chamber before dry chamber cleaning. In this way, the semiconductor substrate is not exposed to the dry etchant when removing residues of the metal-containing resist material from one or more surfaces of the process chamber. The dummy substrate can be provided on the substrate support (e.g., an electrostatic chuck) to protect the substrate support from exposure to the dry etchant during dry chamber cleaning. Alternatively, protection of the substrate support may be accomplished by providing a protective cover over the substrate support during dry chamber cleaning.

[0118] The dry etchant can be introduced through a showerhead coupled to the process chamber or a separate chamber inlet. The dry etchant flows into the process chamber and reacts with residues of the metal-containing resist material to form volatile products. Without being limited by any theory, an organometallic oxide resist material may have a tetrahedral coordination structure, and an organic vapor such as trifluoroacetic acid can protonate an oxygen lone pair to form volatile by-products. After the volatile by-products are formed, the process chamber can be pumped and purged to remove the volatile by-products. Additionally, the process chamber may be pumped and purged to remove residual dry etchant, which may cause unwanted etching of subsequent semiconductor substrates.

[0119] Dry chamber cleaning can be optimized for the low etch selectivity or high etch rate of the resist material deposited in the process chamber. In this way, it is possible to quickly and efficiently remove the unwanted resist material. In some embodiments, higher temperature and / or higher pressure may reduce the etch selectivity of the dry etchant and increase the etch rate. For example, the resist material can be removed at an etch rate of up to 1 nm / second. During exposure to the dry etchant, the residue of the metal-containing resist material on one or more surfaces may be exposed to high temperature. The high temperature can be about 20 °C to about 180 °C, about 40 °C to about 160 °C, or about 80 °C to about 140 °C. In some embodiments, by reacting the residue of the metal-containing resist material with the organic vapor, volatile compounds are formed at a temperature below about 200 °C. During exposure to the dry etchant, the pressure in the process chamber may increase. In some embodiments, the chamber pressure is about 0.01 Torr to 765 Torr, about 0.1 Torr to 100 Torr, or about 0.1 Torr to about 6 Torr. In some embodiments, the chamber pressure is circulated between high and low pressures during exposure to the dry etchant. It is also possible to adjust the flow rate of the organic vapor to control the etch selectivity. In some embodiments, the flow rate of the organic vapor is about 0.05 SLM to about 10 SLM, or about 0.1 SLM to about 5 SLM.

[0120] As described above with respect to dry development, dry chamber cleaning is performed using organic vapors such as organic acids instead of halogen vapors. Halogen vapors such as hydrogen halide vapors tend to leave residual etching by-products after removal of the metal-containing resist material. However, organic vapors such as trifluoroacetic acid form more volatile etching by-products that are not so difficult to remove from the process chamber. Organic vapors such as trifluoroacetic acid can be used for dry chamber cleaning in a plasma-free thermal process. In other words, the residue of the metal-containing resist material is removed without applying plasma. Residual carbon, contaminants, or other remaining materials may or may not be removed by exposure to plasma. In some embodiments, following the introduction of the dry etchant, one or more surfaces may be exposed to an oxidizing gas such as oxygen (O2), ozone (O3), carbon dioxide (CO2), or carbon monoxide (CO).

[0121] Since there is no need to use plasma and the thermally deposited film (non-exposed or non-crosslinked) can be cleaned, the techniques described herein can also clean components downstream and upstream of the tool, beyond the process chamber (e.g., the exhaust line from the process chamber towards the vacuum pump). More generally, this dry cleaning method can be used to clean other contaminated parts and components having a similar composition of metal with volatile by-products from organic vapors.

[0122] In some embodiments, the inner surface of the process chamber can be compatible with the organic vapors of the present disclosure. Instead of the inner surface of the process chamber being resistant to plasma and to halogen vapors such as hydrogen halide, the inner surface may include any material that is simply resistant to the organic vapors of the present disclosure. In some embodiments, the chamber walls of the process chamber may include aluminum oxide, anodized aluminum, or plastic.

[0123] In some embodiments, the process chamber can include a chamber component temperature controller coupled to one or more surfaces (e.g., chamber walls) to control temperature. In some embodiments, the process chamber may include a gas inlet other than a showerhead for delivering a dry etchant. The gas inlet can be positioned in a region of the process chamber where the concentration of the metal-containing resist material is higher. The gas inlet can be positioned in a region of the process chamber that is less likely to be reached by the dry etchant being delivered through the showerhead. In some embodiments, the gas inlet can be positioned under the substrate support, on the wall of the process chamber, and / or near the exhaust port of the process chamber. It is also possible to use multiple gas inlets to deliver the dry etchant into the process chamber. This can ensure dry cleaning throughout the process chamber. In various embodiments, the dry etchant is delivered into the process chamber through one or more gas inlets separate from the showerhead, and the deposition gas can be delivered into the process chamber through the showerhead. In some embodiments, the showerhead can supply separate gases by keeping the gases largely isolated within the showerhead. The showerhead can include multiple plenum volumes. By using multiple exhaust lines, it is possible to reliably separate the gases downstream of the process chamber. By operably coupling a switch to the multiple exhaust lines, it may be possible to separate the dry etchant chemicals from the deposition gas / precursor.

[0124] To protect the showerhead, a pressure differential can be used to prevent the dry etchant from entering (e.g., flowing backward) into the showerhead. In some embodiments, the dry etchant can clean the inner surface of the showerhead by flowing the dry etchant through the showerhead. However, residual organic vapors or moisture may be retained within the channels of the showerhead. In some embodiments, the showerhead is made of a transparent material and can be heated with an appropriate light source. For example, an irradiation source tuned to an appropriate wavelength (e.g., IR or blue wavelength) can directly heat the residual organic vapors and / or moisture and remove the residual organic vapors and / or moisture. Alternatively, the residual organic vapors and / or moisture can also be removed by gas purging.

[0125] FIG. 6B shows a schematic cross-sectional view of chamber wall 604 after a dry etchant has removed the metal-containing EUV resist material 602 from the chamber wall 604. The dry etchant can include organic vapors such as organic acids, and the organic acid may include trifluoroacetic acid. The chamber wall 604 can be heated to a high temperature to promote low etch selectivity. The process chamber can be pressurized to a high pressure to promote low etch selectivity. The removal of the metal-containing EUV resist material 602 can be performed without using a plasma. Residual particles or clusters of metal oxide 606 may remain on the chamber wall 604 after being exposed to the dry etchant. In addition, residual dry etchant 608 may remain within the process chamber.

[0126] Returning to FIG. 5, at block 506 of process 500, the process chamber is optionally purged to remove residual dry etchant from the process chamber. The purge operation may include flowing a purge gas into the process chamber, or a combination of flowing a purge gas and pumping the process chamber to a desired chamber pressure. The purge gas may be an inert gas and / or a reactive gas. The reactive gas can react with the residual dry etchant and facilitate removal. The reactive gas may be, for example, a tin-based precursor such as an organotin precursor. The inert gas may be argon, helium, xenon, or nitrogen. The chamber pressure can be from about 0.1 Torr to about 6 Torr.

[0127] In some embodiments, the purge operation may proceed at an elevated temperature. The elevated temperature can facilitate the removal of organic vapors from the process chamber. In one example, one or more heaters coupled to one or more surfaces of the process chamber can heat the process chamber to an elevated temperature. In another example, one or more IR sources or LEDs can be installed within the process chamber to heat the process chamber to an elevated temperature. The elevated temperature can be from about 20°C to about 180°C, or from about 80°C to about 140°C.

[0128] In some embodiments, plasma-based processing, either direct or remote, is useful for facilitating the removal of residual dry etchant, which may coat the inner surface of the process chamber after cleaning the dry chamber. In other embodiments, non-plasma processing may be useful for accelerating the removal of residual dry etchant. The residual dry etchant may be oxidized by introducing an oxidizing gas. Thus, non-plasma processing may include delivering a flow of ozone and / or oxygen gas.

[0129] FIG. 6C shows a schematic cross-sectional view of the chamber wall 604 after removing the residual dry etchant 608 from the process chamber. By performing a pumping / purging operation, the residual dry etchant 608 can be exhausted from the process chamber. In some embodiments, it is possible to heat the chamber wall 604 or other components of the process chamber to facilitate the release of the residual dry etchant 608. In some embodiments, plasma-based processes, either direct or remote, may be applied to remove the residual dry etchant 608, and such plasma-based processes may include fluorine-based plasma processes, oxygen-based plasma processes, or combinations thereof. In some other embodiments, non-plasma processes may be applied to remove the residual dry etchant 608. Particles or clusters of the metal oxide 606 may remain on the chamber wall 604.

[0130] Returning to FIG. 5, at block 508 of process 500, one or more surfaces of the process chamber are optionally conditioned by forming a protective coating of a metal-containing resist material on one or more surfaces of the process chamber. The average thickness of the protective coating may be less than the average thickness of the residue of the metal-containing resist material. In some embodiments, the average thickness of the protective coating is about 1 nm or more, about 2 nm or more, about 3 nm or more, or from about 1 nm to about 5 nm. Alternatively, one or more surfaces are optionally conditioned by forming a protective coating made of a material different from the metal-containing resist material. Such a protective coating may be a modification of an organotin oxide. After exposure to a dry etchant, one or more surfaces remain exposed. The exposed surfaces within the process chamber can be particularly vulnerable to attack by halogen-based species. The conditioning operation can protect one or more surfaces. Additionally, the conditioning operation can cover residual particles or clusters of metal oxides adhering to one or more surfaces. In this way, the possibility that particles or clusters of metal oxides contaminate the wafer during subsequent processing is reduced.

[0131] Conditioning of one or more surfaces of the process chamber can be performed by a vapor-based deposition technique such as CVD or ALD techniques. The organometallic material is obtained in the vapor phase and deposited on one or more surfaces of the process chamber. The organometallic material can be deposited, for example, based on a gas-phase reaction of an organotin precursor such as isopropyl(tris)(dimethylamino)tin with water vapor. The flow of water vapor can be relatively low. During conditioning, the substrate support can be protected or covered by a dummy wafer or other protective cover. The protective coating may be formed on the chamber walls, floor, ceiling, or chamber components such as gas inlets, showerheads, and exhaust lines. After deposition of the protective coating of the metal-containing resist material, a pumping / purging operation may follow to remove excess precursor and / or reverse reactants. By conditioning one or more surfaces of the process chamber, residual particles of metal oxide can be captured and particle contamination can be limited.

[0132] FIG. 6D shows a schematic cross-sectional view of a metal-containing resist material 610 formed on a chamber wall 604 of a process chamber. The metal-containing EUV resist material 610 is redeposited during the conditioning operation, protects the chamber wall 604 during processing, and can capture particles or clusters of metal oxide 606 from contaminating the wafer. This is sometimes also referred to as chamber seasoning. The metal-containing EUV resist material 610 is formed by a vapor deposition method such as CVD or ALD. In some embodiments, the metal-containing EUV resist material 610 may be an organotin oxide. By conditioning / seasoning the chamber wall 604 and other inner surfaces of the process chamber, the impact of the undesirable first wafer is reduced when restarting the deposition operation on the semiconductor substrate.

[0133] The present disclosure frequently refers to the removal of exposed and / or developed EUV-sensitive films, but the described removal processes are for EUV films of similar composition (e.g., other MO x R yThe base film), for example, can be extended to other films containing metal oxides that can form volatile by-products with organic vapors, including non-exposed EUV resist films. In some embodiments, films other than EUV resist, such as hard masks, UV resists, or films of similar composition for other applications, can be removed by this method, and in this regard, the described removal process relates to the chemical composition of the film rather than its function.

[0134] Apparatus The apparatus of the present disclosure is configured to dry-remove EUV resist. The apparatus can be configured to perform dry development or dry chamber cleaning. The apparatus can be configured for other processing operations such as deposition, bevel and backside cleaning, post-application bake, EUV scanning, post-exposure bake, photoresist rework, descum, planarization, curing, and other operations. In some embodiments, the apparatus is configured to perform all drying operations. In some embodiments, the apparatus is configured to perform a combination of wet and dry operations. The apparatus can include a single wafer chamber or multiple stations within the same process chamber. If there are multiple stations within the same process chamber, the various processing operations as described in the present disclosure may be performed at different stations within the same process chamber. In one example, the PEB heat treatment can be performed at one station and the development can be performed at another station.

[0135] An apparatus configured to dry-remove EUV resist includes a process chamber having a substrate support. The apparatus can include a dry etching line coupled to the process chamber for feeding an etching gas. In some embodiments, the etching gas includes an organic vapor such as trifluoroacetic acid. The apparatus can include one or more heaters for temperature control. Such heaters can be provided in the process chamber and / or the substrate support. In some embodiments, a plurality of gas inlets can be positioned within the process chamber to flow the etching gas near regions where unintentional EUV resist tends to form. The apparatus can further include one or more sensors for sensing particle count, number of wafers, thickness number, or other parameters for triggering dry chamber cleaning and / or for triggering an end point of dry chamber cleaning.

[0136] In some embodiments, the process chamber is made of an inexpensive material such as plastic. In some other embodiments, the process chamber is made of a metal such as anodized aluminum or a ceramic such as aluminum oxide.

[0137] FIG. 7 illustrates a schematic diagram of an exemplary process station suitable for performing dry development, cleaning, rework, descum, and planarization operations according to some embodiments. A plurality of process stations 700 may be included in a common low-pressure process tool environment. For example, FIG. 8 illustrates one embodiment of a multi-station processing tool 800 such as the VECTOR® processing tool available from Lam Research Corporation of Fremont, California. In some embodiments, one or more hardware parameters of the processing tool 800 (including those described in detail below) can be programmatically adjusted by one or more computer controllers 850.

[0138] The process station can be configured as a module within a cluster tool. FIG. 10 illustrates a semiconductor process cluster tool architecture having a vacuum integrated deposition and patterning module suitable for implementation of the embodiments described herein. Such a cluster process tool architecture can include a resist deposition, resist exposure (EUV scanner), resist development, and etching module, as described above and further described below with reference to FIGS. 9 and 10.

[0139] In some embodiments, certain processing functions can be performed sequentially within the same module, such as, for example, dry development and etching or dry deposition and dry chamber cleaning. Also, embodiments of the present disclosure are directed to methods and apparatus for receiving a wafer including an EUV resist thin film layer disposed on a layer or layer stack to be etched into a dry development / etching chamber following photopatterning in an EUV scanner, dry developing the photopatterned EUV resist thin film layer, and then etching a lower layer using the patterned EUV resist as a mask, as described herein.

[0140] Returning to FIG. 7, the process station 700 is in fluid communication with a reactant delivery system 701 for delivering a process gas to a distribution showerhead 706. The reactant delivery system 701 includes a mixing vessel 704 for blending and / or conditioning the process gas delivered to the showerhead 706. One or more mixing vessel inlet valves 720 can control the introduction of the process gas into the mixing vessel 704. If plasma exposure is used, the plasma can also be delivered to the showerhead 706 or generated at the process station 700. As noted above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0141] FIG. 7 includes an optional vaporization point 703 for vaporizing the liquid reactant supplied to the mixing vessel 704. In some embodiments, a liquid flow controller (LFC) can be provided upstream of the vaporization point 703 to control the mass flow rate of the liquid that is vaporized and fed to the process station 700. For example, the LFC can include a thermal mass flow meter (MFM) located downstream of the LFC. Next, the plunger valve of the LFC can be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller that is in electrical communication with the MFM.

[0142] The showerhead 706 distributes the process gas toward the substrate 712. In the embodiment shown in FIG. 7, the substrate 712 is located below the showerhead 706 and is shown resting on the pedestal 708. The showerhead 706 can have any suitable shape and can have any suitable number and arrangement of ports for distributing the process gas to the substrate 712.

[0143] In some embodiments, the pedestal 708 can be raised or lowered to expose the substrate 712 to the volume 707 between the substrate 712 and the showerhead 706. It will be appreciated that in some embodiments, the height of the pedestal can be programmatically adjusted by a suitable computer controller 750. In some embodiments, the showerhead 706 can have a plurality of plenum volumes having a plurality of temperature control sections.

[0144] In some embodiments, the pedestal 708 can be temperature-controlled via a heater 710. In some embodiments, the pedestal 708 can be heated to a temperature above 0°C to above 300°C, such as 40°C to 160°C, such as about 80°C to 140°C, during non-plasma thermal exposure of the photopatterned resist to an organic vapor development chemical such as trifluoroacetic acid as described in the disclosed embodiments. In some embodiments, the heater 710 of the pedestal 708 can include a plurality of independently controllable temperature control zones.

[0145] Furthermore, in some embodiments, pressure control for the process station 700 can be provided by the butterfly valve 718. As shown in the embodiment of FIG. 7, the butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the process station 700 can also be adjusted by changing the flow rate of one or more gases introduced into the process station 700.

[0146] In some embodiments, the position of the showerhead 706 can be adjusted relative to the pedestal 708 to vary the volume 707 between the substrate 712 and the showerhead 706. Further, it will be understood that the vertical position of the pedestal 708 and / or the showerhead 706 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 708 may include a rotation axis for rotating the orientation of the substrate 712. It will be understood that one or more of these exemplary adjustments can be implemented programmatically by one or more suitable computer controllers.

[0147] For example, in a descum or smoothing operation where plasma can be used, the showerhead 706 and the pedestal 708 are in electrical communication with a radio frequency (RF) power source 714 and a matching network 716 to supply power to the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 714 and the matching network 716 can operate at any suitable power to form a plasma having a desired composition of radical species. An example of a suitable power is up to about 500 W.

[0148] In some embodiments, the instructions for the controller 750 may be provided via input / output control (IOC) sequence instructions. In one example, instructions for setting conditions for a process step may be included in the corresponding recipe step of the process recipe. In some cases, the process recipe steps may be arranged in sequence such that all instructions for a process step are executed simultaneously with that process step. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe step. For example, a recipe step may include instructions for setting the flow rate of a dry development chemical reaction gas such as trifluoroacetic acid, and a time delay instruction for the recipe step. In some embodiments, the controller 750 may include any of the features described below with respect to the system controller 850 of FIG. 8.

[0149] As described above, one or more process stations can be included in a multi-station processing tool. FIG. 8 shows a schematic diagram of one embodiment of a multi-station processing tool 800 having an inbound load lock 802 and an outbound load lock 804, either or both of which can include a remote plasma source. Robot 806 is configured to move wafers from a cassette loaded via pod 808 at atmospheric pressure to inbound load lock 802 via atmospheric port 810. The wafer is placed on pedestal 812 of inbound load lock 802 by robot 806, atmospheric port 810 is closed, and the load lock is pumped down. If inbound load lock 802 includes a remote plasma source, the wafer may undergo remote plasma processing to treat the substrate surface within the load lock before being introduced into process chamber 814. Further, the wafer may also be heated in inbound load lock 802, for example, to remove moisture and absorbed gas. Next, chamber transfer port 816 to process chamber 814 is opened, and another robot (not shown) places the wafer on the pedestal of the first station shown within the reactor for processing. Although the embodiment illustrated in FIG. 8 includes load locks, it will be understood that in some embodiments, wafers may be directly introduced into the process station.

[0150] The illustrated processing chamber 814 includes four process stations numbered from 1 to 4 in the embodiment shown in FIG. 8. Each station has a heating pedestal (shown as 818 for station 1) and a gas line inlet. It will be appreciated that in some embodiments, each process station may have different purposes or multiple purposes. For example, in some embodiments, the process station may be switchable between a dry development mode and an etching process mode. Additionally or alternatively, in some embodiments, the processing chamber 814 may include one or more corresponding pairs of dry development and etching process stations. Although the illustrated processing chamber 814 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, and in other embodiments, the processing chamber may have three or fewer stations.

[0151] FIG. 8 illustrates one embodiment of a wafer handling system 890 for transferring wafers within the processing chamber 814. In some embodiments, the wafer handling system 890 can transfer wafers between various process stations and / or between a process station and a load lock. It will be understood that any suitable wafer handling system may be used. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 8 also illustrates one embodiment of a system controller 850 used to control the process conditions and hardware state of the process tool 800. The system controller 850 can include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 can include a CPU or computer, analog and / or digital input / output connections, a stepping motor controller board, and the like.

[0152] In some embodiments, system controller 850 controls all of the activities of process tool 800. System controller 850 executes system control software 858 that is stored in mass storage device 854, loaded into memory device 856, and executed by processor 852. Alternatively, the control logic may be hard-coded into controller 850. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs) and the like can be used for these purposes. In the following description, whenever "software" or "code" is used, functionally equivalent hard-coded logic can be used instead. System control software 858 may include instructions for controlling timing, gas mixing, gas flow rate, chamber pressure and / or station pressure, chamber temperature and / or station temperature, wafer temperature, target power level, RF power level, substrate pedestal, chuck position and / or susceptor position, and other parameters of a particular process implemented by process tool 800. System control software 858 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components used to execute various process tool processes. System control software 858 may be coded in any suitable computer readable programming language.

[0153] In some embodiments, system control software 858 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored in mass storage device 854 and / or memory device 856 associated with system controller 850 may be used. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0154] The substrate positioning program can include program code for process tool components used to load a substrate onto pedestal 818 and control the spacing between the substrate and other parts of process tool 800.

[0155] The process gas control program can include code for controlling the organic vapor composition (e.g., trifluoroacetic acid as described herein) and flow rate to stabilize the pressure of the process station, and optionally code for flowing gas to one or more process stations prior to deposition. The pressure control program can include code for controlling the pressure of the process station, for example, by adjusting the throttle valve of the exhaust system of the process station, the gas flow to the process station, etc.

[0156] The heater control program can include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program can control the delivery of a heat transfer gas (such as helium) to the substrate.

[0157] The plasma control program can include code for setting the RF power level applied to the process electrodes within one or more process stations according to the embodiments herein.

[0158] The pressure control program can include code for maintaining the pressure within the reaction chamber according to the embodiments herein.

[0159] In some embodiments, there may be a user interface associated with system controller 850. The user interface can include a display screen, a graphical software display of the device and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0160] In some embodiments, the parameters adjusted by system controller 850 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (such as RF bias power level), etc. These parameters may be provided to the user in the form of a recipe and can be input using a user interface.

[0161] Signals for monitoring the process may be provided from various process tool sensors to the analog and / or digital input connections of system controller 850. Signals for controlling the process can be output through the analog and digital output connections of process tool 800. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with the data from these sensors to maintain process conditions.

[0162] System controller 850 can provide program instructions for performing the deposition process described above. The program instructions can control various process parameters such as DC power level, RF bias power level, pressure, temperature, etc. The instructions can control the parameters for operating development, cleaning, and / or etching processes according to the various embodiments described herein.

[0163] System controller 850 typically includes one or more memory devices and one or more processors configured to execute instructions to cause the apparatus to perform methods according to the disclosed embodiments. A machine-readable medium containing instructions for controlling process operations according to the disclosed embodiments can be coupled to system controller 850.

[0164] In some embodiments, system controller 850 is part of a system, and such a system may be part of the examples described above. Such a system can include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more processing platforms, and / or certain processing components (such as a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after the processing of semiconductor wafers or substrates. Such electronics may be referred to as a "controller" and may control various components or sub-components of one or more systems. System controller 850 may be programmed to control any of the processes disclosed herein, depending on the processing conditions and / or the type of system. Such processes include the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, the loading and unloading of wafers to and from tools connected or interfaced with a particular system and other transfer tools, and / or the loading and unloading of wafers to and from a load lock.

[0165] In a broad sense, the system controller 850 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, i.e., microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the system controller 850 in the form of various individual settings (or program files) that may define operating parameters for executing a particular process on or for a semiconductor wafer or for the system. The operating parameters may, in some embodiments, be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0166] In some embodiments, the system controller 850 may be part of a computer that is integrated or coupled with the system, or otherwise network-connected to the system, or coupled to such a computer, or a combination thereof. For example, the system controller 850 may be within the "cloud" or may be all or part of a fab host computer system. This enables remote access to wafer processing. The computer can enable remote access to the system, monitor the current progress of the fabrication operation, consider the history of past fabrication operations, consider trends or performance criteria from multiple fabrication operations, change the parameters of the current process, set the processing steps following the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, and such parameters and / or settings are then communicated from the remote computer to the system. In some examples, the system controller 850 receives instructions in the form of data. Such data specifies the parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tools that the system controller 850 is configured to interact with or control. Thus, as described above, the system controller 850 may be distributed, for example, by including one or more individual controllers that are network-connected to each other and cooperate towards a common purpose (such as the processes and controls described herein).As an example of a distributed controller for such purposes, one or more integrated circuits on a chamber, remotely located (e.g., at the platform level or as part of a remote computer) and communicable with one or more integrated circuits combined to control a process in the chamber, may be mentioned.

[0167] Exemplary systems can include, but are not limited to, a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, an EUV lithography chamber (scanner) or module, a development chamber or module, and any other semiconductor processing system that may be related to or used in the fabrication and / or manufacture of semiconductor wafers.

[0168] As described above, depending on one or more process steps performed by a tool, the system controller 850 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, proximate tools, tools located throughout the factory, a main computer, another controller, or a tool used for material transport to load and unload a wafer container to and from a tool location and / or load port within a semiconductor manufacturing factory.

[0169] In certain embodiments, an ICP reactor, which may be suitable for etching operations suitable for the implementation of some embodiments, is described herein. Although the ICP reactor is described herein, it should be understood that in some embodiments, a capacitively coupled plasma reactor may also be used.

[0170] FIG. 9 schematically shows a cross-sectional view of an inductively coupled plasma apparatus 900 suitable for implementing certain embodiments or aspects of embodiments, such as dry development, cleaning, and / or etching, an example of which is the Kiyo® reactor manufactured by Lam Research Corporation of Fremont, California. In other embodiments, it can be implemented using other tools or tool types having the function of performing the dry development, cleaning, and / or etching processes described herein.

[0171] The inductively coupled plasma apparatus 900 includes an integrated process chamber 924 structurally defined by a chamber wall 901 and a window 911. The chamber wall 901 can be fabricated from stainless steel, aluminum, or plastic. The window 911 can be fabricated from quartz or other dielectric materials. An optional internal plasma grid 950 divides the integrated process chamber into an upper sub-chamber 902 and a lower sub-chamber 903. In many embodiments, the plasma grid 950 can be removed, thereby allowing utilization of the chamber space consisting of sub-chambers 902 and 903. A chuck 917 is positioned within the lower sub-chamber 903 near the bottom inner surface. The chuck 917 is configured to receive and hold a semiconductor wafer 919 on which etching and deposition processes are performed. The chuck 917, if present, can be an electrostatic chuck for supporting the wafer 919. In some embodiments, an edge ring (not shown) surrounds the chuck 917 and has an upper surface that is substantially planar with the upper surface of the wafer 919 when present above the chuck 917. The chuck 917 also includes electrostatic electrodes for chucking and de-chucking the wafer 919. For this purpose, a filter and a DC clamp power supply (not shown) may be provided. Other control systems for lifting the wafer 919 from the chuck 917 may also be provided. The chuck 917 can be charged using an RF power supply 923. The RF power supply 923 is connected to a matching circuit 921 through a connection 927. The matching circuit 921 is connected to the chuck 917 through a connection 925. In this way, the RF power supply 923 is connected to the chuck 917. In various embodiments, the bias power of the electrostatic chuck may be set to about 50V or may be set to different bias powers depending on the process being performed according to the disclosed embodiments. For example, the bias power may be from about 20V to about 100V, or from about 30V to about 150V.

[0172] The element for plasma generation includes coil 933 and is positioned above window 911. In some embodiments, the coil is not used in the disclosed embodiments. Coil 933 is fabricated from a conductive material and includes at least one complete turn. The example of coil 933 shown in FIG. 9 includes three turns. The cross-section of coil 933 is indicated by symbols, where the coil with an "X" extends by rotating within the page, while the coil with a "●" extends by rotating out of the page. The element for plasma generation also includes RF power source 941 configured to supply RF power to coil 933. Generally, RF power source 941 is connected to matching circuit 939 through connection 945. Matching circuit 939 is connected to coil 933 through connection 943. In this way, RF power source 941 is connected to coil 933. Optional Faraday shield 949 is positioned between coil 933 and window 911. Faraday shield 949 can be maintained at a spaced-apart relationship with respect to coil 933. In some embodiments, Faraday shield 949 is disposed immediately above window 911. In some embodiments, Faraday shield 949 is between window 911 and chuck 917. In some embodiments, Faraday shield 949 is not maintained at a spaced-apart relationship with respect to coil 933. For example, Faraday shield 949 may be directly below window 911 without a gap. Coil 933, Faraday shield 949, and window 911 are each configured to be substantially parallel to each other. Faraday shield 949 can prevent metal or other species from depositing on window 911 of process chamber 924.

[0173] Process gas can flow into the process chamber through one or more main gas inlets 960 and / or one or more side gas inlets 970 positioned in the upper subchamber 902. Similarly, although not explicitly shown, similar gas inlets can be used to supply process gas to a capacitively coupled plasma processing chamber. A vacuum pump, e.g., a single- or two-stage mechanical dry pump and / or a turbomolecular pump 940, can be used to draw process gas out of the process chamber 924 and maintain the pressure within the process chamber 924. For example, a vacuum pump can be used to evacuate the lower subchamber 903 during a purge operation. To selectively control the application of the vacuum environment provided by the vacuum pump, a valve control conduit can be used to fluidly connect the vacuum pump to the process chamber 924. This can be done using a closed-loop control flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown), during a plasma processing operation. Similarly, a vacuum pump and valve control fluid connection to the capacitively coupled plasma processing chamber can also be used.

[0174] During operation of the apparatus 900, one or more process gases can be supplied through the gas inlets 960 and / or 970. In certain embodiments, the process gas can be supplied through only the main gas inlet 960 or only the side gas inlet 970. In some cases, the gas inlets shown in the figures may be replaced with more complex gas inlets, e.g., one or more showerheads. The Faraday shield 949 and / or optional grid 950 can include internal channels and holes that allow for the delivery of process gas to the process chamber 924. Either or both of the Faraday shield 949 and optional grid 950 can function as a showerhead for delivering process gas. In some embodiments, a liquid vaporization and delivery system can be disposed upstream of the process chamber 924 such that when a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process chamber 924 through the gas inlets 960 and / or 970.

[0175] High-frequency power is supplied from the RF power supply 941 to the coil 933 so that an RF current flows through the coil 933. The RF current flowing through the coil 933 generates an electromagnetic field around the coil 933. The electromagnetic field generates an induced current in the upper sub-chamber 902. Due to the physical and chemical interactions between the various generated ions and radicals and the wafer 919, the features of the wafer 919 are etched and a layer is selectively deposited on the wafer 919.

[0176] When the plasma grid 950 is used such that both the upper sub-chamber 902 and the lower sub-chamber 903 are present, the induced current acts on the gas present in the upper sub-chamber 902 to generate an electron-ion plasma in the upper sub-chamber 902. The optional internal plasma grid 950 limits the number of hot electrons in the lower sub-chamber 903. In some embodiments, the apparatus 900 is designed and operated such that the plasma present in the lower sub-chamber 903 is an ion-ion plasma.

[0177] Both the upper electron-ion plasma and the lower ion-ion plasma can contain positive and negative ions, but the ion-ion plasma has a higher ratio of negative ions to positive ions. Volatile etching and / or deposition by-products can be removed from the lower sub-chamber 903 through the port 922. The chuck 917 disclosed herein can operate at a high temperature in the range of about 10°C to about 250°C. The temperature depends on the process operation and a specific recipe.

[0178] When the apparatus 900 is installed in a clean room or a fabrication facility, it may be coupled to a facility (not shown). The facility includes piping that provides process gas, vacuum, temperature control, and environmental particle control. These facilities are coupled to the apparatus 900 when installed in the intended fabrication facility. In addition, the apparatus 900 can be coupled to a transfer chamber that allows a robot to use typical automated operations to move semiconductor wafers in and out of the apparatus 900.

[0179] In some embodiments, a system controller 930 (which can include one or more physical or logical controllers) controls some or all of the operations of process chamber 924. The system controller 930 can include one or more memory devices and one or more processors. In some embodiments, apparatus 900 includes a switching system for controlling flow rate and duration when the disclosed embodiments are implemented. In some embodiments, apparatus 900 can have a switching time of up to about 500 ms, or up to about 750 ms. The switching time can depend on the flowing chemical substances, the selected recipe, the reactor architecture, and other factors.

[0180] In some embodiments, the system controller 930 is part of a system, and such a system can be part of the examples described above. Such a system can include semiconductor processing equipment that includes one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal, a gas flow system, etc.). These systems can be integrated with electronics for controlling system operations before, during, and after the processing of semiconductor wafers or substrates. Such electronics can be integrated into the system controller 930 and can control various components or sub-components of one or more systems. The system controller 930 can be programmed to control any of the processes disclosed herein, depending on the processing parameters and / or the type of system. Such processes include the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, the loading and unloading of wafers to and from tools and other transfer tools connected or coupled to a particular system, and / or the loading and unloading of wafers to and from a load lock.

[0181] In a broad sense, system controller 930 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives commands, issues commands, controls operations, enables cleaning operations, enables endpoint measurements, etc. The integrated circuit may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, i.e., a microcontroller that executes program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that may define the operating parameters for performing a particular process on or for a semiconductor wafer or for the system. The operating parameters may, in some embodiments, be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0182] In some embodiments, the system controller 930 may be part of a computer that is integrated or coupled with the system or otherwise network-connected to the system, or may be coupled to such a computer, or may be a combination thereof. For example, the controller may be within the "cloud" or may be all or part of a fab host computer system. This enables remote access to wafer processing. The computer can enable remote access to the system, monitor the current progress of the fabrication operation, consider the history of past fabrication operations, consider trends or performance criteria from multiple fabrication operations, change the parameters of the current process, set the processing steps following the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system through a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, and such parameters and / or settings are then communicated from the remote computer to the system. In some examples, the system controller 930 receives instructions in the form of data. Such data specifies the parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tools that the controller is configured to interact with or control. Thus, as described above, the system controller 930 may be distributed, for example, by including one or more individual controllers that are network-connected to each other and cooperate towards a common purpose (such as the processes and controls described herein).As an example of a distributed controller for such purposes, one or more integrated circuits on a chamber, remotely located (e.g., at the platform level or as part of a remote computer) and communicable with one or more integrated circuits combined to control a process in the chamber, may be mentioned.

[0183] Exemplary systems can include, but are not limited to, a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a tracking chamber or module, an EUV lithography chamber (scanner) or module, a dry development chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacture of semiconductor wafers.

[0184] As described above, depending on one or more process steps performed by a tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or a tool used for material transport to load and unload a wafer container to and from a tool location and / or load port within a semiconductor manufacturing factory.

[0185] EUVL patterning can often be performed using any suitable tool, often referred to as a scanner, such as the TWINSCAN NXE:3300B (registered trademark) platform supplied by ASML of Veldhoven, the Netherlands). The EUVL patterning tool may be a stand-alone device for loading and unloading substrates therefrom for the deposition and etching described herein. Alternatively, as described below, the EUVL patterning tool may be a module on a larger multi-component tool. FIG. 10 illustrates a semiconductor process cluster tool architecture having a vacuum integrated deposition, EUV patterning, and dry development / etching module that interfaces with a vacuum transfer module suitable for implementing the processes described herein. The process can be performed without such a vacuum integrated apparatus, although such an apparatus may be advantageous in some embodiments.

[0186] FIG. 10 illustrates a semiconductor process cluster tool architecture having a vacuum integrated deposition and patterning module that interfaces with a vacuum transfer module suitable for implementing the processes described herein. The arrangement of transfer modules for "transferring" wafers between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. Depending on the requirements of a particular process, the deposition and patterning modules are vacuum integrated. Other modules, such as for etching, can also be included in the cluster.

[0187] The vacuum transfer module (VTM) 1038 interfaces with four processing modules 1020a - 1020d and can be individually optimized to perform various fabrication processes. As an example, the processing modules 1020a - 1020d can be implemented to perform deposition, evaporation, ELD, dry development, cleaning, etching, strip, and / or other semiconductor processes. For example, module 1020a can be an ALD reactor operable to perform non - plasma thermal atomic layer deposition as described herein, such as a Vector tool available from Lam Research of Fremont, California. And module 1020b can be a PECVD tool such as Lam Vector®. It should be understood that the figures are not necessarily drawn to scale.

[0188] The airlocks 1042 and 1046, also known as load locks or transfer modules, interface with the VTM 1038 and the patterning module 1040. For example, as described above, a suitable patterning module can be the TWINSCAN NXE:3300B® platform supplied by ASML of Veldhoven, Netherlands. This tool architecture enables the transfer of workpieces, such as semiconductor substrates or wafers, under vacuum so as not to react prior to exposure. The integration of deposition modules and lithography tools is facilitated by the fact that EUVL also requires a significantly reduced pressure, taking into account the strong light absorption of incident photons by ambient gases such as H2O, O2.

[0189] As described above, this integrated architecture is only one possible implementation of the tools for carrying out the described process. The process can also be carried out using more conventional stand-alone EUVL scanners and, as modules, stand-alone or integrated into a cluster architecture with other tools such as etching, stripping, etc. (e.g., Lam Kiyo or Gamma tools) without the integrated patterning module described, for example, with reference to FIG. 10, using deposition reactors such as the Lam Vector tool.

[0190] Airlock 1042 can be an "unload" load lock referring to the transfer of the substrate from the VTM 1038 that functions the deposition module 1020a to the patterning module 1040, and airlock 1046 may be a "load" load lock referring to the transfer of the substrate returning from the patterning module 1040 to the VTM 1038. The load load lock 1046 can also provide an interface to the outside of the tool for access and exit of the substrate. Each process module has a facet that interfaces the module to the VTM 1038. For example, the deposition process module 1020a has a facet 1036. Within each facet, sensors, such as sensors 1-18 shown in the figure, are used to detect the passage of the wafer 1026 when moving between the respective stations. The patterning module 1040 and the airlocks 1042 and 1046 can similarly be provided with additional facets and sensors not shown.

[0191] The main VTM robot 1022 transfers the wafer 1026 between modules including the airlocks 1042 and 1046. In one embodiment, the robot 1022 has one arm, and in another embodiment, the robot 1022 has two arms, and each arm has an end effector 1024 for lifting wafers such as the wafer 1026 for conveyance. The front-end robot 1044 is used therein to transfer the wafer 1026 from the outfeed airlock 1042 to the patterning module 1040 and from the patterning module 1040 to the infeed airlock 1046. The front-end robot 1044 can also transfer the wafer 1026 between the infeed load lock and the outside of the tool for access and exit of the substrate. Since the infeed airlock module 1046 has the ability to adapt the environment between atmospheric pressure and vacuum, the wafer 1026 can move between the two pressure environments without being damaged.

[0192] Note that EUVL tools typically operate at a higher vacuum than deposition tools. In this case, it is desirable to increase the vacuum environment of the substrate during transfer between the deposition tool and the EUVL tool to enable outgassing of the substrate before entering the patterning tool. The outfeed airlock 1042 can provide this function by holding wafers transferred at a low pressure that is not higher than the pressure within the patterning module 1040 over a certain period of time and discharging off-gas, thereby preventing the optical system of the patterning module 1040 from being contaminated by off-gas from the substrate. The appropriate pressure for the off-gas discharge airlock is 1E-8 Torr or less.

[0193] In some embodiments, system controller 1050 (which can include one or more physical or logical controllers) controls some or all of the operation of the cluster tool and / or its individual modules. Note that the controller can be local to the cluster architecture, or can be located external to the cluster architecture on the manufacturing floor, or can be located remotely and connected to the cluster architecture via a network. System controller 1050 can include one or more memory devices and one or more processors. The processor can include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor controller board, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions can be stored in a memory device associated with the controller or can be provided via a network. In certain embodiments, the system controller executes system control software.

[0194] The system control software can include instructions for controlling the timing of application and / or the magnitude of any aspect of tool or module operation. The system control software can be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components required to perform various process tool processes. The system control software can be coded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a semiconductor manufacturing process can include one or more instructions executed by the system controller. For example, instructions for setting process conditions for deposition, condensation, evaporation, patterning, and / or etching stages may be included in the corresponding recipe stage.

[0195] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus can include a processing chamber for patterning, deposition, and etching, and a controller including instructions for forming a negative pattern mask. The instructions can include code for patterning features in a chemically amplified (CAR) resist on a semiconductor substrate by EUV exposure to expose a surface of the substrate, developing the photopatterned resist, and etching an underlying layer or layer stack using the resist patterned as a mask. The development may be performed using an organic vapor such as an organic acid.

[0196] Note that a computer controlling the movement of the wafer can be local to the cluster architecture, or can be located external to the cluster architecture of the manufacturing floor, or can be located remotely and connected to the cluster architecture via a network. The controller described above with respect to any of FIGS. 7, 8, or 9 can be implemented using the tool of FIG. 10.

[0197] FIG. 11A shows an example of a deposition chamber for vapor-based deposition of a metal-containing resist material according to some embodiments. As can be seen, an apparatus 1100 having a process chamber 1102 including a lid 1108 is illustrated. The process chamber 1102 can include a wafer transfer passage 1104 through one of the walls of the process chamber 1102, and the wafer transfer passage 1104 is sized such that a substrate 1122 can pass through and enter the interior of the process chamber 1102, where the substrate 1122 can be placed on a wafer support 1124. The wafer transfer passage 1104 can have a gate valve 1106 or a similar door mechanism that can operate to seal or open the wafer transfer passage 1104, thereby enabling the environment within the process chamber 1102 to be isolated from the environment on the opposite side of the gate valve 1106. For example, the substrate 1122 may be provided to the process chamber 1102 via a wafer handling robot located in an adjacent transfer chamber. Such a transfer chamber may have, for example, a plurality of process chambers 1102 disposed around it, and each such process chamber 1102 is connected to the transfer chamber via a corresponding gate valve 1106.

[0198] The wafer support 1124 can include, for example, an electrostatic chuck (ESC) 1126 that can be used to provide a wafer support surface for supporting the substrate 1122. The ESC 1126 can include, for example, a base plate 1134 that is joined to a top plate 1128 that is placed on the base plate 1134. The top plate 1128 may be made of, for example, a ceramic material and may have several other components embedded therein. In the illustrated example, the top plate 1128 has two separate electrical systems embedded therein. One such system is an electrostatic clamp electrode system, which can have one or more clamp electrodes 1132 that can be used to generate an electric charge within the substrate 1122 and draw the substrate 1122 towards the wafer support surface of the top plate 1128. In the embodiment of FIG. 11A, there are two clamp electrodes 1132 that provide a bipolar electrostatic clamp system, but in some embodiments, only a single clamp electrode 1132 can be used to provide a unipolar electrostatic clamp system.

[0199] Other systems are thermal control systems that can be used to control the temperature of the substrate 1122 during processing conditions. In FIG. 11A, the thermal control system is a multi-zone thermal control system characterized by four annular resistive heater traces 1130a, 1130b, 1130c, and 1130d that are concentric with each other and positioned under the clamp electrode 1132. The central resistive heater trace 1130a may, in some embodiments, fill a substantially circular region, and each resistive heater trace 1130a / b / c / d may follow a substantially serpentine or meandering path within the corresponding annular region. By controlling each resistive heater trace 1130a / b / c / d individually, various radial heating profiles can be provided to the top plate 1128, and such a four-zone heating system may be controlled to maintain the substrate 1122, for example, with a temperature uniformity of ±0.5° C. in some cases. The apparatus 1100 of FIG. 11A features a four-zone heating system within the ESC 1126, but in other embodiments, a single-zone or multi-zone heating system having more or fewer than four zones can be used.

[0200] For example, in some embodiments of the temperature control mechanisms described above, a heat pump may be used instead of the resistive heating trace. For example, in some embodiments, the resistive heater trace may be replaced or augmented by a Peltier junction or other similar device that can be controlled to “pump” heat from one side to the other. Such a mechanism can be used, for example, to draw heat from the top plate 1128 (and thus the substrate 1122) and direct the heat to the base plate 1134 and the heat exchange passage 1136, thereby making it possible to cool the substrate 1122 more quickly and effectively as desired.

[0201] ESC1126 can also include a base plate 1134 that can be used, for example, to provide structural support under the top plate 1128 and can also act as a thermal dissipation system. For example, the base plate 1134 can include one or more heat exchange passages 1136 that are generally distributed throughout the base plate 1134. For example, the heat exchange passages 1136 may follow a serpentine, circular switchback, or spiral pattern around the center of the base plate 1134. During use, it is possible to circulate a heat exchange medium, such as water or an inert fluorinated liquid, through the heat exchange passages 1136. The flow rate and temperature of the heat exchange medium can be externally controlled to provide specific heating or cooling behavior within the base plate 1134.

[0202] ESC1126 may be supported, for example, by a wafer support housing 1142 that is connected to and supported by wafer support posts 1144. The wafer support posts 1144 may have routing passages 1148 and other passageways, for example, for sending cable wiring, fluid flow conduits, and other equipment under the base plate 1134 and / or the top plate 1128. For example, although not shown in FIG. 11A, the cable wiring for supplying power to the resistive heater traces 1130a / b / c / d may be sent through the routing passages 1148, similar to the cable wiring for supplying power to the clamp electrodes 1132. Other cables, such as cables for temperature sensors, may also be sent through the routing passages 1148 to locations inside the wafer support 1124. In embodiments having a temperature controllable base plate 1134, conduits for transporting the heat exchange medium between the base plates 1134 may also be sent through the routing passages 1148. Such cables and conduits are not shown in FIG. 11A to avoid excessive clutter, but it should be understood that they still exist.

[0203] The apparatus 1100 of FIG. 11A also includes a wafer support Z actuator 1146 that can provide movable support to the wafer support posts 1144. By operating the wafer support Z actuator 1146, the wafer support posts 1144, and thus the wafer support 1124 supported thereby, can be vertically moved up and down, for example, by up to several inches, within the reaction space 1120 of the process chamber 1102. When doing so, the gap distance X between the substrate 1122 and the underside of the showerhead 1110 can be adjusted according to various process conditions.

[0204] The wafer support 1124 may also include, in some embodiments, one or more edge rings that can be used to control and / or fine-tune various process conditions. In FIG. 11A, an upper edge ring 1138 is provided, for example, on top of lower edge rings 1140a and 1140b, which are supported by the wafer support housing 1142 and a third lower edge ring 1140c. The upper edge ring 1138 can, for example, generally be subjected to the same processing environment as the substrate 1122, while the lower edge rings 1140a / b / c can generally be shielded from the processing environment. Due to the increased exposure of the upper edge ring 1138, the upper edge ring 1138 has a limited lifespan and may require more frequent replacement or cleaning compared to the lower edge rings 1140a / b / c.

[0205] Apparatus 1100 can also include a system for removing process gas from process chamber 1102 during and after processing. For example, process chamber 1102 can include an annular plenum 1156 surrounding wafer support posts 1144. The annular plenum 1156 can then be in fluid connection with a vacuum foreline 1152 that can be connected to a vacuum pump, such as one that can be located under a basement floor under apparatus 1100. A regulating valve 1154 is provided between vacuum foreline 1152 and process chamber 1102 and can be actuated to control the flow to vacuum foreline 1152. In some embodiments, a baffle 1150, such as an annular plate or other structure, can be provided that can function to more uniformly disperse the flow around the circumference of wafer support posts 1144, thereby reducing the potential for flow non-uniformities in the reactants flowing across substrate 1122.

[0206] Showerhead 1110 is, as shown, a dual plenum showerhead 1110 and includes a first plenum 1112 to which process gas is supplied via a first inlet 1116 and a second plenum 1114 to which process gas is supplied via a second inlet 1118. In general, two plenums can be used to maintain separation between the precursor and the reactant prior to release of the precursor and the reactant. Showerhead 1110 can have three or more plenums in some embodiments. In some cases, a single plenum is used to feed the precursor into reaction space 1120 of process chamber 1102. Each plenum can have a corresponding set of gas distribution ports that fluidly connect the respective plenum to reaction space 1120 through a faceplate of showerhead 1110 (the faceplate is the portion of showerhead 1110 intervening between the lowermost plenum and reaction space 1120).

[0207] Process gas may be supplied to the first inlet 1116 and the second inlet 1118 of the showerhead 1110 via a gas supply system, which may be configured to supply one or more precursors and / or reverse reactants as described herein. The illustrated apparatus 1100 is configured to supply a plurality of precursors and a plurality of reverse reactants. For example, the first valve manifold 1168a may be configured to supply a precursor to the first inlet 1116, and the second valve manifold 1168b may be configured to supply another precursor or another reverse reactant to the second inlet 1118.

[0208] The first valve manifold 1168a may be configured to supply one or more precursors to the first inlet 1116, and the second valve manifold 1168b may be configured to supply another precursor or another reactant to the second inlet 1118. In this example, the first valve manifold 1168a includes, for example, a plurality of valves A1 - A5. Valve A2 may be, for example, a three-way valve having one port fluidly connected to the first vaporizer 1172a, another port fluidly connected to the bypass line 1170a, and a third port fluidly connected to a port on another three-way valve A3. Similarly, valve A4 may be another three-way valve having one port fluidly connected to the second vaporizer 1172b, another port fluidly connected to the bypass line 1170a, and a third port fluidly connected to a port on another three-way valve A5. One of the other ports on valve A5 may be fluidly connected to the first inlet 1116, and the remaining ports on valve A5 may be fluidly connected to one of the remaining ports on valve A3. Subsequently, the remaining ports on valve A3 may be fluidly connected to valve A1, which may be fluidly interposed between valve A3 and a purge gas source 1174, such as nitrogen, argon, or another suitable inert gas (with respect to the precursors and / or reverse reactants). In some embodiments, only the first valve manifold is used.

[0209] For purposes of the present disclosure, the term "fluidly connected" is used with respect to volumes, plenums, holes, etc. that can be connected to each other to form a fluid connection, in the same way the term "electrically connected" is used with respect to components that are connected to each other to form an electrical connection. The term "fluidly interposed" can be used, when used, to refer to a component, volume, plenum, or hole that is fluidly connected to at least two other components, volumes, plenums, or holes such that fluid flowing from one of those other components, volumes, plenums, or holes to the other of those components, volumes, plenums, or holes will first flow through the "fluidly interposed" component before reaching the other of those components, volumes, plenums, or holes. For example, if a pump is fluidly interposed between a reservoir and an outlet, fluid flowing from the reservoir to the outlet will first flow through the pump before reaching the outlet.

[0210] The first valve manifold 1168a can be controllable, for example, to flow vapor from one or both of the vaporizers 1172a and 1172b to the process chamber 1102 or to flow through the first bypass line 1170a to the vacuum foreline 1152. The first valve manifold 1168a may also be controllable to flow purge gas from a purge gas source 1174 to the first inlet 1116.

[0211] For example, to flow steam from the first vaporizer 1172a into the reaction space 1120, valve A2 can be actuated so that the steam from the first vaporizer 1172a can first flow into the first bypass line 1170a. This flow can be maintained for a period sufficient to allow the steam flow to reach steady-state flow conditions. After sufficient time has elapsed (or when used, after the flow meter indicates that the flow rate is stable), valves A2, A3, and A5 can be actuated to direct the steam flow from the first vaporizer 1172a to the first inlet. A similar operation using valves A4 and A5 can be performed to feed steam from the second vaporizer 1172b to the first inlet 1116. In some cases, it may be desirable to purge one of the vapors from the first plenum 1112 by actuating valves A1, A3, and A5 so that purge gas from the purge gas source 1174 flows into the first inlet 1116. In some additional embodiments, it may be desirable to simultaneously flow steam from one of the vaporizers 1172a or 1172b in parallel with flowing gas from the purge gas to the first inlet 1116. Such embodiments can be used to dilute the concentration of reactants contained in such steam.

[0212] It will be understood that the second valve manifold 1168b can be controlled in a similar manner, for example, by controlling valves B1 - B5, to supply steam from vaporizers 1172c and 1172d to the second inlet 1118 or the second bypass line 1170b. Furthermore, it will be understood that different manifold arrangements can be utilized as well, including a single integrated manifold that includes valves for controlling the flow of precursors, reverse reactants, or other reactants to the first inlet 1116 and the second inlet 1118.

[0213] As described above, some apparatuses 1100 can be characterized by a smaller number of steam sources, for example, only two vaporizers 1172, in which case it is possible to modify the valve manifold 1168 to have a smaller number of valves, for example, only valves A1 - A3.

[0214] As described above, an apparatus such as apparatus 1100 that can be used to perform dry deposition of a film can be configured to maintain a specific temperature profile within process chamber 1102. In particular, such an apparatus 1100 can be configured to maintain substrate 1122 at a temperature lower than that of most of the equipment of apparatus 1100 that is in direct contact with the precursor and / or reverse reactant, for example, at least 25 °C to 50 °C lower. In addition, the temperature of the equipment of apparatus 1100 that is in direct contact with the precursor and / or reverse reactant can be maintained at a high temperature level sufficient to prevent condensation of the vaporized reactant on the surface of such equipment. At the same time, the temperature of substrate 1122 may be controlled to a level that promotes condensation, or at least deposition, of the reactant on substrate 1122.

[0215] To provide such temperature control, various heating systems may be included in apparatus 1100. For example, process chamber 1102 may have a receptacle for receiving cartridge heater 1158. For example, although generally having a cylindrical internal volume, in the case of process chamber 1102 having a square or rectangular outer shape, it is possible to drill vertical holes for receiving cartridge heater 1158 at the four corners of the housing of chamber 1102. In some embodiments, showerhead 1110 may be covered with heater blanket 1160, which can be used to apply heat to the entire exposed upper surface of showerhead 1110 to keep the temperature of the showerhead high. It may also be beneficial to heat the various gas lines used to direct the vaporized reactant from vaporizer 1172 to showerhead 1110. For example, a resistive heater tape can be wrapped around such a gas line and used to heat the gas line to a high temperature. As shown in FIG. 11A, all gas lines through which precursors and / or reverse reactants may flow, including bypass line 1170, are shown as being heated. The only exception is the gas line from valve manifold 1168 to first inlet 1116 and second inlet 1118, which is very short and can be heated indirectly by showerhead 1110. Of course, these gas lines can also be actively heated if desired. In some embodiments, a heater can be provided in proximity to gate valve 1106 to supply heat to the gate valve as well.

[0216] The various operating systems of the apparatus 1100 can be controlled by a controller 1184, which may include one or more processors 1186 and one or more memory devices 1188 that are operably connected to each other and communicably connected to the various systems and subsystems of the apparatus 1100 to provide control functions for these systems. For example, the controller 1184 may be configured to control valves A1 to A5 and B1 to B5, various heaters 1158, 1160, a vaporizer 1172, a regulating valve 1154, a gate valve 1106, a wafer support Z actuator, and the like.

[0217] Another feature that the apparatus 1100 may include is shown in FIG. 11B, which illustrates an enlarged side cross-sectional view and a plan view of a portion of the substrate 1122, the top plate 1128, and the upper edge ring 1138 of FIG. 11A. As can be seen, in some embodiments, the substrate 1122 may be raised from most of the top plate 1128 by a plurality of small mesas 1176, which may be shallow bosses that project a small distance from the nominal top surface of the top plate 1128 so as to provide a backside gap 1178 between the underside of the substrate 1122 and most of the top plate 1128. A peripheral wall feature 1177 may be provided at the periphery of the top plate 1128. The peripheral wall feature 1177 may extend around the entire perimeter of the top plate 1128 and may nominally be the same height as the mesa 1176. During processing operations, a generally inert gas such as helium can flow into the backside gap 1178 through one or more gas ports 1182. This gas can then flow radially outward before encountering the peripheral wall feature 1177, after which such radial outward flow is restricted and a high-pressure region of the gas is confined between the substrate 1122 and the top plate 1128. Inert gas leaking past the peripheral wall 1177 can ultimately flow out through a radial gap 1180 between the outer edge of the substrate 1122 and a portion of the upper edge ring 1138. Such gas can function to protect the underside of the substrate from undesirable effects of the processing operations being performed by preventing the gas emitted by the showerhead 1110 from reaching the underside of the substrate 1122. At the same time, the gas released into the region of the backside gap 1178 can also act to increase the thermal coupling between the substrate 1122 and the top plate 1128, thereby enabling the top plate 1128 to more effectively heat or cool the substrate 1122. Due to the high pressure provided by the peripheral wall, the gas within the region of the backside gap 1178 can also be denser than the gas in the rest of the chamber and can thus provide a more effective thermal coupling between the substrate 1122 and the top plate 1128.

[0218] The controller 1184 can be configured to cause the apparatus 1100 to perform various operations consistent with the above disclosure, for example, via the execution of computer-executable instructions.

[0219] When a metal-containing resist film is deposited on the substrate 1122, the substrate 1122 can be transferred to one or more subsequent process chambers or tools for additional operations (e.g., any of those described herein) as described above. A further deposition apparatus is described in International Patent Application No. PCT / US2020 / 038968, filed on June 22, 2020, and entitled "APPARATUS FOR PHOTORESIST DRY DEPOSITION", the entire disclosure of which is incorporated herein by reference.

[0220] Conclusion Processes and apparatus for dry development of metal and / or metal oxide photoresists for forming a patterning mask, for example, in the context of EUV patterning, are disclosed.

[0221] It is understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes will be suggested to those skilled in the art in light of them. Although various details are omitted for clarity, various design alternatives can be implemented. Accordingly, this example is to be regarded as illustrative and not restrictive, and the present disclosure is not limited to the details given herein and can be modified within the scope of the present disclosure.

Claims

1. A method comprising: providing a photopatterned metal-containing resist on a surface of a semiconductor substrate within a process chamber; dry-developing the photopatterned metal-containing resist by selectively removing a portion of the photopatterned metal-containing resist by exposing it to a developing chemical comprising an organic vapor, thereby forming a resist mask; The method comprising the above steps.

2. The method according to claim 1, wherein the organic vapor comprises a carboxylic acid.

3. The method according to claim 2, wherein the organic vapor comprises trifluoroacetic acid.

4. The method according to claim 1, wherein the organic vapor comprises trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, chlorodifluoroacetic acid, thioacetic acid, or thioglycolic acid.

5. The method according to claim 1, wherein the organic vapor comprises hexafluoroacetylacetone.

6. The method according to any one of claims 1 to 5, wherein the developing chemical comprises a gas-phase mixture of a halogenated carboxylic acid and a hydrogen halide.

7. The method according to any one of claims 1 to 5, wherein dry-developing the photopatterned metal-containing resist comprises reacting the organic vapor with the photopatterned metal-containing resist to form a volatile compound at a temperature of less than about 200 °C.

8. The method according to any one of claims 1 to 5, wherein dry-developing the photopatterned metal-containing resist comprises exposing it to at least the organic vapor in a plasma-free thermal process.

9. The method according to any one of claims 1 to 5, wherein the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist, and the photopatterned metal-containing EUV resist is an organometallic oxide or an organometallic-containing film.

10. The method according to any one of claims 1 to 5, wherein Dry developing the photopatterned metal-containing resist includes selectively removing the non-EUV-exposed portion of the photopatterned metal-containing resist with the developing chemical substance to form the resist mask, a method.

11. A method comprising: Depositing a metal-containing resist material on a surface of a semiconductor substrate in a process chamber, wherein a portion of the metal-containing resist material forms a residue on one or more surfaces of the process chamber; depositing the metal-containing resist material; Introducing a dry etchant containing an organic vapor into the process chamber, the dry etchant at least partially removing the residue on the one or more surfaces of the process chamber; introducing the dry etchant; A method comprising.

12. The method according to claim 11, wherein The organic vapor contains a carboxylic acid.

13. The method according to claim 12, wherein The organic vapor contains trifluoroacetic acid.

14. The method according to claim 11, wherein The organic vapor contains trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, monofluoroacetic acid, difluoroacetic acid, chlorodifluoroacetic acid, thioacetic acid, or thioglycolic acid.

15. The method according to claim 11, wherein The organic vapor contains hexafluoroacetylacetone.

16. The method according to any one of claims 11 to 15, wherein The dry etchant contains a gas-phase mixture of a halogenated carboxylic acid and a hydrogen halide.

17. The method according to any one of claims 11 to 15, wherein At least partial removal of the residue includes reacting the organic vapor with the metal-containing resist material to form a volatile compound at a temperature of less than about 200 °C.

18. The method according to any one of claims 11 to 15, wherein At least partial removal of the residue includes exposing at least to the organic vapor in a plasma-free thermal process.

19. The method according to any one of claims 11 to 15, wherein The metal-containing resist material is an organometallic oxide or an organometallic-containing film.

20. The method according to any one of claims 11 to 15, wherein After introducing the dry etchant, purging the process chamber to remove residual dry etchant from the process chamber, and conditioning one or more surfaces of the process chamber by forming a protective coating of the metal-containing resist material on the one or more surfaces of the process chamber A method further comprising.

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