Oxide semiconductor film

Abstract

To provide an oxide semiconductor film with a new structure suitable for use in a semiconductor device, and provide a semiconductor device using an oxide semiconductor film with a new structure.SOLUTION: An oxide semiconductor film includes an amorphous region mainly composed of amorphous material, and a crystal region near the surface containing crystal grains of In2Ga2ZnO7, and the crystal grains are oriented such that the c-axes are approximately perpendicular to the surface, alternatively, a semiconductor device using such an oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technical field of the disclosed invention relates to a semiconductor film containing an oxide semiconductor. Or, it relates to a semiconductor device using the semiconductor film.

Background Art

[0002] The field-effect transistor is one of the most widely used semiconductor devices. The materials used for field-effect type transistors are various depending on their applications. In particular, semiconductor materials containing silicon are widely used.

[0003] Field-effect transistors using silicon satisfy the characteristics required for many applications. For example, for applications such as integrated circuits that require high-speed operation, single-crystalline silicon is used, and the requirements are satisfied. Also, for large-area applications such as display devices, amorphous silicon is used to meet the requirements.

[0004] Thus, silicon has high versatility and can be used for various applications. However, in recent years, there has been a tendency to require further performance along with versatility for semiconductor materials. For example, from the perspective of high-performance of large-area display devices, in order to achieve high-speed operation of switching elements, a semiconductor material that is easy to form into a large area and has performance superior to that of amorphous silicon is required. .

[0005] In such a situation, technologies related to field-effect transistors (also called FETs) using oxide semiconductors have attracted attention. For example, in Patent Document 1, a homologous compound InM O3(ZnO) (M = In, Fe, Ga, or Al, m is an integer of 1 or more and less than 50) is used m ​ A transparent thin film field effect transistor has been disclosed.

[0006] Further, Patent Document 2 discloses a field effect transistor using an amorphous oxide semiconductor containing In, Ga, and Zn and having an electron carrier concentration of less than 10 18 / cm 3 . In this document, the atomic ratio of the amorphous oxide semiconductor is In:Ga:Zn =1:1:m (m < 6).

[0007] Furthermore, Patent Document 3 discloses a field effect transistor having an amorphous oxide semiconductor containing microcrystals as an active layer.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0009] In Patent Document 3, there is a disclosure that the composition in the crystalline state is InGaO3(ZnO) m (m is an integer less than 6 ). Further, in Example 1 of Patent Document 3, the case of InGaO3 (ZnO)4 is disclosed. However, in fact, even when such an oxide semiconductor is used, sufficient characteristics have not been obtained.

[0010] In view of the above problems, an object of the present invention is to provide an oxide semiconductor film having a new structure suitable for use in a semiconductor device. Another object of the present invention is to provide a semiconductor device using an oxide semiconductor film having a new structure. **Means for Solving the Problems**

[0011] The disclosed invention provides an oxide semiconductor film having a predetermined crystal structure in the vicinity of the surface. Alternatively, the disclosed invention provides a semiconductor device including the oxide semiconductor film. The predetermined crystal structure is, for example, a crystal structure having electrical anisotropy. Alternatively, it is a crystal structure having a function of suppressing the intrusion of impurities.

[0012] It is preferable that the region excluding the crystal structure of the oxide semiconductor film mainly has an amorphous structure. Here, the "vicinity of the surface (near the surface)" refers to, for example, a region having a distance (depth) of 20 nm or less from the surface. Further, "mainly" means, for example, a state occupying 50% or more. Examples of the means for solving the problems include the following.

[0013] One aspect of the disclosed invention has an amorphous region mainly composed of an amorphous oxide semiconductor containing In, Ga, and Zn, and a crystal region near the surface containing crystal grains of In2Ga2ZnO7, and the crystal grains are oriented such that their c-axis is substantially perpendicular to the surface. The oxide semiconductor film. Here, "substantially perpendicular" means a state within ±10° from the vertical direction.

[0014] In the above, the crystal grains of In2Ga2ZnO7 include a first layer containing In, a second layer not containing In, a third layer not containing In, and a layer containing In. ​​​​​​​​​​​​It is preferable to include a stacked structure of a fourth layer and a fifth layer that does not contain In. Furthermore, in the first layer containing In or the fourth layer containing In, it is preferable that one 5s orbital of In has an overlap with the 5s orbitals of adjacent In.

[0015] Also, in the above amorphous region, the content (atomic %) of Zn is preferably less than the content (atomic %) of In or Ga. Further, the crystal grains preferably have a length (size) in the c-axis direction of less than 5 times the length (size) in the a-axis direction or the b-axis direction.

[0016] Another aspect of the disclosed invention is a semiconductor device having a gate electrode layer, a gate insulating layer on the gate electrode layer, a semiconductor layer on the gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to a part of the semiconductor layer, and applying the above oxide semiconductor film as the semiconductor layer.

[0017] Another aspect of the disclosed invention is a semiconductor device having a semiconductor layer, a gate insulating layer on the semiconductor layer, a gate electrode layer on the gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to a part of the semiconductor layer, and applying the above oxide semiconductor film as the semiconductor layer.

[0018] In the above semiconductor device, it is preferable to have an insulating layer covering the semiconductor layer. Also, the source electrode layer or the drain electrode layer and the semiconductor layer are preferably electrically connected on the upper surface or the lower surface of the semiconductor layer.

[0019] Note that in this specification, etc., the terms "upper" and "lower" are not limited to being directly above or directly below. ​​​​​​​​​​​​is not. For example, in the expression "gate insulating layer on the gate electrode layer", other components between the gate electrode layer and the gate insulating layer are not excluded. Also, the terms "above" and "below" are merely expressions used for convenience of explanation, and unless otherwise specified, they include the case where the above and below are swapped. When there are other components between the layer and the gate insulating layer, it is not excluded. Also, the terms "above" and "below" are merely expressions used for convenience of explanation, and unless otherwise specified, they include the case where the above and below are swapped. The words "above" and "below" are just expressions used for convenience of explanation, and unless otherwise specified, they include the case where the above and below are swapped. is also included.

Advantages of the Invention

[0020] In an oxide semiconductor film having a crystal structure with electrical anisotropy near the surface, compared with an oxide semiconductor film not having the crystal structure, the electrical characteristics of the oxide semiconductor film change. For example, the conductivity in the direction parallel to the surface of the oxide semiconductor film is improved, and the insulation in the direction perpendicular to the surface of the oxide semiconductor film is improved. In an oxide semiconductor film having a crystal structure with a function of suppressing the intrusion of impurities near the surface, compared with an oxide semiconductor film not having the crystal structure, the intrusion of impurities into the oxide semiconductor film is suppressed. For example, the intrusion of water, hydrogen, etc. that have an adverse effect on the oxide semiconductor is suppressed. is suppressed.

[0021] Therefore, according to one aspect of the disclosed invention, an oxide semiconductor film having excellent electrical characteristics is provided. Also, a highly reliable oxide semiconductor film is provided. Also, according to another aspect of the disclosed invention, a semiconductor device having excellent characteristics is provided. Also, a highly reliable semiconductor device is provided. In an oxide semiconductor film having a crystal structure with a function of suppressing the intrusion of impurities near the surface, compared with an oxide semiconductor film not having the crystal structure, the intrusion of impurities into the oxide semiconductor film is suppressed. For example, the intrusion of water, hydrogen, etc. that have an adverse effect on the oxide semiconductor is suppressed. is suppressed.

[0022] For this reason, according to one aspect of the disclosed invention, an oxide semiconductor film having excellent electrical characteristics is provided. Also, a highly reliable oxide semiconductor film is provided. Also, a highly reliable oxide semiconductor film is provided.

[0023] Also, according to another aspect of the disclosed invention, a semiconductor device having excellent characteristics is provided. Also, a highly reliable semiconductor device is provided. Also, a highly reliable semiconductor device is provided.

Brief Description of the Drawings

[0024]

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[0025] Hereinafter, embodiments will be described in detail with reference to the drawings. However, the invention is not limited to the description of the embodiments shown below, and the form and details can be changed without departing from the gist of the invention disclosed in this specification and the like. Also, the configurations according to different embodiments can be implemented in combination as appropriate. In the configuration of the invention described below, the same reference numerals are used for the same parts or parts having similar functions, and the repeated description thereof will be omitted. from departing from and details can be changed without departing from the gist of the invention disclosed in this specification and the like. Also, the configurations according to different embodiments can be implemented in combination as appropriate. In the configuration of the invention described below, the same reference numerals are used for the same parts or parts having similar functions, and the repeated description thereof will be omitted. the same reference numerals are used for the same parts or parts having similar functions, and the repeated description thereof will be omitted. .

[0026] (Embodiment 1) In this embodiment, details of an oxide semiconductor film and a method for manufacturing the same according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 14. using FIGS. 1 to 14.

[0027] [Configuration of Oxide Semiconductor Film] First, the configuration of the oxide semiconductor film will be described with reference to FIGS. 1 and 2.

[0028] FIG. 1 shows an example of a configuration in which an oxide semiconductor film 100 is provided on a surface to be formed of a substrate 110. Note that the substrate 110 can be any material as long as it can support the oxide semiconductor film 100. Also, the oxide semiconductor film 100 is not limited to being provided on the surface to be formed of the substrate 110, and may be a free-standing film. the substrate 110 can be any material as long as it can support the oxide semiconductor film 100. Also, the oxide semiconductor film 100 is not limited to being provided on the surface to be formed of the substrate 110, and may be a free-standing film. the surface to be formed of the substrate 110, and may be a free-standing film. not limited to being provided on the surface to be formed of the substrate 110, and may be a free-standing film.

[0029] The above oxide semiconductor film 100 has an amorphous region 120 mainly composed of an amorphous oxide semiconductor and a crystalline region 140 containing crystal grains 130 in the vicinity of the surface (see Fig. 1(A)). Further, the crystal grains 130 are oriented such that their c-axes are in a direction substantially perpendicular to the surface of the oxide semiconductor film 100. Here, "substantially perpendicular" means a state within ±10° from the perpendicular direction. Let it be so.

[0030] Examples of the oxide semiconductor material constituting the oxide semiconductor film 100 include, for example, In-Ga- Zn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn -O system, Al-Zn-O system, In-O system, Sn-O system, Zn-O system oxide semiconductor materials. There are.

[0031] Among them, the In-Ga-Zn-O system oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high field-effect mobility. Therefore, it is suitable as a semiconductor material used in semiconductor devices. Among them, the In-Ga-Zn-O system oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high field-effect mobility. Therefore, it is suitable as a semiconductor material used in semiconductor devices. It is suitable as a semiconductor material used in semiconductor devices.

[0032] Typical examples of the In-Ga-Zn-O system oxide semiconductor material include InGaO3(ZnO) m (m>0). Note that the composition according to this notation is based on the crystal structure, and it does not mean that the entire oxide semiconductor material has this composition. Also, in the above, using M instead of Ga, it can be expressed as InMO3(ZnO) and it does not mean that the entire oxide semiconductor material has this composition. Also, in the above, using M instead of Ga, it can be expressed as InMO3(ZnO) (m>0). m (m>0) can also be expressed as follows. Here, M is gallium (Ga), iron (Fe), nickel One metal element selected from ruthenium (Ni), manganese (Mn), cobalt (Co), etc. or A plurality of metal elements are shown. In the In-Ga-Zn-O-based oxide semiconductor material, Ga is used as M will be selected. In addition to the case of only Ga, there are cases where Ga and Ni, Ga and Fe, etc., include the case where the above metal elements other than Ga are selected. In addition to the metal elements included as M it may contain transition metal elements and their oxides as impurities.

[0033] The amorphous region 120 is mainly composed of an amorphous oxide semiconductor. Note that "mainly" refers to, for example, a state of occupying 50% or more. In this case, the amorphous oxide semiconductor occupies 50% or more by volume% (or weight%). That is, in addition to the amorphous oxide semiconductor, there may be included crystals of oxide semiconductors, etc., but the content is preferably less than 50% by volume% (or weight%). Note that the essence of the disclosed invention lies in the structure of the crystal region 140, so the structure of the amorphous region 120 does not need to be limited to the above as long as the required characteristics can be ensured.

[0034] When using an In-Ga-Zn-O-based oxide semiconductor material, the composition of the above amorphous region 120 is preferably such that the content of Zn (atomic%) is less than the content of In or Ga (atomic%). By setting the composition in this way, it becomes easy to form crystal grains 130 of a predetermined composition in the crystal region 140.

[0035] The crystal region 140 near the surface has crystal grains 130 with the c-axis (c-axis) oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 100 (see Fig. 1(B)). For example, In- ​​When using an oxide semiconductor material of the Ga-Zn-O system, the crystal region 140 is In2Ga such that the c-axis of the In2Ga2ZnO7 crystal grains is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 100 . The "vicinity of the surface (near the surface)" refers to, for example, a region where the distance (depth) from the surface is 20 nm or less. However, this is not always the case when the thickness of the oxide semiconductor film 100 increases. For example, when the thickness of the oxide semiconductor film 100 is 200 nm or more , the "vicinity of the surface (near the surface)" refers to a region where the distance (depth) from the surface is 10% or less of the thickness of the oxide semiconductor film .

[0036] The crystal of In2Ga2ZnO7 can be regarded as having a laminated structure of layers parallel to the a-axis (a-axis) and the b-axis (b-axis), containing any of In, Ga, and Zn (see Fig. 2). That is, the crystal of In2Ga2ZnO7 has a first layer containing In, a second layer not containing In (containing Ga or Zn), a third layer not containing In (containing Ga or Zn), a fourth layer containing In , and a fifth layer not containing In (containing Ga or Zn), laminated in the c-axis direction .

[0037] Since the electrical conduction of the In2Ga2ZnO7 crystal is mainly controlled by In, the electrical properties in the directions parallel to the a-axis and the b-axis of the first layer containing In and the fourth layer containing In are good. This is because in the first layer containing In or the fourth layer containing In, one In 5s orbital overlaps with the adjacent In 5s orbitals , thereby forming a carrier path. On the other hand, perpendicular to the above layers ​​​​​​ Regarding the straight direction (i.e., the c-axis direction), it can be said that the insulation property is improved.

[0038] When the crystal grains having such electrical anisotropy are oriented, it also affects the electrical characteristics of the oxide semiconductor film 100. Specifically, for example, the electrical characteristics in the direction parallel to the surface of the oxide semiconductor film 100 are improved. This is because the c-axis of the In2Ga2ZnO7 crystal grains is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 100, and in the In2Ga2ZnO7 crystal, current flows in the directions parallel to the a-axis

[0039] and the b-axis. Note that the crystal region 140 may include things other than the crystal grains 130. Also, the crystal structure of the crystal grains is not limited to the above, and crystal grains with other crystal structures may be included. For example, when using an oxide semiconductor material of the In-Ga-Zn-O system, in addition to the crystal grains of In2Ga2ZnO7, crystal grains of InGaZnO4 may be included. Of course, when crystal grains of In2Ga2ZnO7 exist throughout the entire crystal region 140, it is more effective and preferable.

[0040] Also, it is preferable that the length (size) of the crystal grains in the c-axis direction is less than 5 times the length (size) in the a-axis direction or the b-axis direction, and it is even better if it is less than 3 times. If the thickness of the crystal region 140 becomes too large (that is, if the crystal grains 130 become too long in the c-axis direction), the characteristics of the oxide semiconductor film 100 may depend only on the crystal region 140 and the desired characteristics may not be obtained.

[0041] As described above, in the oxide semiconductor film 100, the crystal region 140 is provided near the surface. By having it, good electrical characteristics can be realized. In particular, the crystal region 140 is In2Ga2Z In the case where the c-axis of the nO7 crystal grains is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 100 When it is configured to include, due to the anisotropy of the electrical characteristics of the In2Ga2ZnO7 crystal grains , excellent electrical characteristics are realized.

[0042] Further, since the crystal region 140 is more stable than the amorphous region 120, by having this in the vicinity of the surface of the oxide semiconductor film 100, impurities (such as moisture, etc.) in the amorphous region 120 Can be suppressed from being incorporated. Therefore, the reliability of the oxide semiconductor film 100 can be improved.

[0043] <Method for manufacturing an oxide semiconductor film> Next, the method for manufacturing the above oxide semiconductor film 100 will be described with reference to FIG. 3.

[0044] The oxide semiconductor film 200, which is the precursor of the oxide semiconductor film 100, is formed using the oxide semiconductor material shown in the above <Structure of the oxide semiconductor film> section. Further, the oxide semiconductor film 200 is Formed by a sputtering method or the like in an atmosphere of a noble gas such as argon, an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen (see FIG. 3(A)). In the sputtering method By using a target containing 2% by weight or more and 10% by weight or less of SiO2, SiO in the oxide semiconductor film 200 (x>0) can be included to suppress the crystallization of the oxide semiconductor film 200 x This method is particularly effective when it is desired to obtain an amorphous oxide semiconductor film 200.

[0045] For example, a metal oxide target containing In, Ga, and Zn (In:Ga:Zn = 1: 1:0.5 [atom%], In:Ga:Zn = 1:1:1 [atom%], In:Ga :Zn = 1:1:2 [atom%] and using a target having such a composition ratio), the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the DC power is 0.5 kW, and the atmosphere is an oxygen (oxygen flow rate ratio 100%) atmosphere, so that as the oxide semiconductor film 200, I n-Ga-Zn-O-based amorphous oxide semiconductor film can be obtained. When using a pulse DC power supply as the power supply it is possible to reduce powdery substances (also called particles and dust) generated during film formation, and since the film thickness distribution can be made uniform, it is suitable for this purpose.

[0046] The thickness of the oxide semiconductor film 200 can be appropriately set according to the intended use and characteristics For example, it may be about 20 nm to 10 μm.

[0047] The crystal region 140 is formed by heat treatment after forming the oxide semiconductor film 200 (see Fig. 3(B)). Note that by this heat treatment, H2, H, OH, etc. in the oxide semiconductor film 200 are desorbed, so this heat treatment can also be called a dehydration treatment or a dehydrogenation treatment.

[0048] For the above heat treatment, RTA (Rapid Thermal Anneal) treatment using a high-temperature inert gas (such as nitrogen or rare gas) can be applied. Here, the temperature of the heat treatment is preferably 500 °C or higher. Regarding the upper limit of the heat treatment temperature, there is no requirement from the essential part of the invention but when using the base material 110 as the support, the upper limit of the heat treatment temperature needs to be within the range of its heat-resistant temperature. The time of the heat treatment is 1 minute or more and 10 minutes or less ​This is preferable. For example, an RTA treatment at 650°C for about 3 to 6 minutes is good. As described above By applying the RTA treatment as described above, heat treatment can be performed in a short time, so the influence of heat on the base material 1 10 can be reduced. That is, compared with the case of performing heat treatment for a long time it is possible to raise the upper limit of the heat treatment temperature. Also, it is possible to selectively form crystal grains having a predetermined structure near the surface.

[0049] Note that the above heat treatment may be performed at any timing as long as it is after the oxide semiconductor film 200 is formed. However, in order to promote dehydration or dehydrogenation, it is preferably performed before providing other components on the surface of the oxide semiconductor film 200. Also, the above heat treatment is not limited to once and may be performed multiple times. It is desirable that the treatment atmosphere does not contain hydrogen (including water) or the like. For example, the purity of the inert gas introduced into the heat treatment apparatus is 6N (99.9999%, that is, the impurity concentration is 1 ppm or less), preferably 7N (99.99999%, that is, the impurity concentration is 0.1 ppm or less) or more.

[0050] Note that in the above heat treatment, it is desirable that the treatment atmosphere does not contain hydrogen (including water) or the like. For example, the purity of the inert gas introduced into the heat treatment apparatus is 6N (99.9999%, that is, the impurity concentration is 1 ppm or less), preferably 7N (99.99999%, that is, the impurity concentration is 0.1 ppm or less) or more. 9%, that is, the impurity concentration is 1 ppm or less) or more, preferably 7N (99.99999%, that is, the impurity concentration is 0.1 ppm or less) or more.

[0051] By the above heat treatment, an oxide semiconductor film 100 having a crystal region 140 having crystal grains 130 in which the c-axis is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film and an amorphous region 120 mainly composed of amorphous is formed (see FIG. 3(C)). Note that the above crystal region 140 has a function of suppressing the intrusion of impurities into the film. However, when a large amount of impurities are present, it is hard to say that the intrusion can be completely suppressed. Therefore

[0052] Note that the above crystal region 140 has a function of suppressing the intrusion of impurities into the film. However, when a large amount of impurities are present, it is hard to say that the intrusion can be completely suppressed. Therefore when a large amount of impurities are present, it is difficult to completely suppress the intrusion. Therefore Next, after the above heat treatment, the oxide semiconductor film 100 should be kept from contacting with water, hydrogen, etc. as much as possible. This is important. This can be achieved by not exposing it to the atmosphere during the heat treatment and the subsequent cooling process. For example, the heat treatment and the subsequent cooling process can be carried out in the same atmosphere. Of course, the atmosphere during the cooling process can be different from the heat treatment atmosphere. In this case, the atmosphere during the cooling process can be, for example, an atmosphere such as oxygen gas, N2O gas, ultra-dry air (dew point of -4 0°C or lower, preferably -60°C or lower).

[0053] <Regarding the crystal grain growth mechanism> Hereinafter, as an example, the crystal grain growth mechanism in an In-Ga-Zn-O-based amorphous oxide semiconductor film will be described with reference to FIGS. 4 to 14. First, the state in which In2Ga2ZnO7 crystal grains are c-axis oriented near the surface of the In-Ga-Zn-O-based amorphous oxide semiconductor film is shown together with the results of experimental observations.

[0054] First, the state in which In2Ga2ZnO7 crystal grains are c-axis oriented near the surface of the In-Ga-Zn-O-based amorphous oxide semiconductor film is shown together with the results of experimental observations. As the In-Ga-Zn-O-based amorphous oxide semiconductor film, one formed on a glass substrate with a thickness of 50 nm by the DC sputtering method was used.

[0055] As the In-Ga-Zn-O-based amorphous oxide semiconductor film, one formed on a glass substrate with a thickness of 50 nm by the DC sputtering method was used. Also, as the sputtering target, a target having a composition ratio of In:Ga:Zn = 1:1:0.5 [atom%] was used. Other film formation conditions were a DC power of 0.5 kW, a film formation pressure of 0.6 Pa, a film formation atmosphere of oxygen (oxygen flow ratio 100%) atmosphere, and the temperature of the substrate was room temperature. To c-axis orient the In2Ga2ZnO7 crystal grains near the surface, RTA treatment was applied to the above In-Ga-Zn-O-

[0056] O-based amorphous oxide semiconductor film. The heat treatment conditions were the atmosphere Next, after the above heat treatment, the oxide semiconductor film 100 should be kept from contacting with water, hydrogen, etc. as much as possible. The atmosphere was nitrogen at atmospheric pressure, the temperature was 650°C, and the time was 6 minutes.

[0057] To observe the cross section of the sample prepared in this way, the specimen was mechanically polished and then ionized with Ar. The specimen was then sliced by the FIB milling method (accelerating voltage: 5 kV) or the FIB milling method (irradiated ion beam). The specimen was cut into thin sections using a neutron detector (Ga, acceleration voltage: 40 kV, followed by processing at 5 kV). For ion milling, we used Gatan's PIPS, and for FIB milling, we used Hitachi's N B-5000 and FB-2100, respectively, were used.

[0058] Figure 4 shows a Bright-field TEM image of the surface of the sample. TEM images were taken using a Hitachi H-9000NAR at an accelerating voltage of 300 kV. As shown in Fig. 4, the surface of the In-Ga-Zn-O oxide semiconductor film with a thickness of 50 nm is A crystal containing grains with a width of 1 nm to 3 nm and a depth of 2 nm to 4 nm near the surface It can be seen that a region has been formed.

[0059] FIG. 5(A-1) shows a cross-sectional TEM image of the vicinity of the sample surface. The electron diffraction pattern corresponding to the labeled 1 is shown in FIG. 5(A-2), and the labeled 1 is shown in the cross-sectional TEM image. The electron diffraction pattern corresponding to the obtained 2 is shown in FIG. 5(A-3), and the The electron diffraction pattern corresponding to the sample 3 is shown in FIG. 5(A-4), and the The electron diffraction pattern corresponding to 4 is shown in FIG. 5(A-5), and the mark The electron beam diffraction patterns corresponding to 5 are shown in FIG. The graph shows clear spots with d values of 0.29 nm to 0.30 nm. The direction of the spot corresponds to the direction of the c-axis of the crystal.

[0060] Figure 5(B) is a cross-sectional TEM image showing the relationship between the c-axis direction and the surface. The arrow in the figure indicates the c-axis direction of the crystal grains at that point. From Figure 5(B), it can be seen that the c-axis (<001> direction) is substantially perpendicular to the surface. Also, it can be seen that the direction of the c-axis reflects the flatness of the surface.

[0061] Next, in order to determine the crystal structure of the above crystal grains, a detailed analysis of the electron diffraction pattern was performed. Figures 6(A-1) to 6(A-3) show typical measured data of the electron diffraction pattern, and Figures 6(B-1) to 6(B-3) show the simulation results corresponding to the measured data (assuming an In2Ga2ZnO7 crystal). From the comparison between the measured data and the simulation results, it can be confirmed that the crystal structure of the crystal grains is In2Ga2ZnO7.

[0062] Figure 7 compares and shows the crystal structure of m = 1 in the homologous structure InGaO3(ZnO) m (m: natural number) (InGaZnO4) (see Figure 7(A)) and the In2Ga2ZnO7 crystal structure (see Figure 7 (B)).

[0063] In the InGaZnO4 structure, there are two layers of GaO or ZnO layers between the layers (InO layers) composed of In and O perpendicular to the c-axis (<001> direction), whereas in the In2Ga2 ZnO7 structure, between the InO layers, a structure having one layer of GaO or ZnO layer and a structure having two layers alternately appear repeatedly. Also, the lattice constant in the c-axis direction is 2.61 nm for InGaZnO4 and 2.95 nm for In2Ga2ZnO7. is as follows.

[0064] Next, the observation of HAADF( high-angle annular dark field)-STEM images in the InGaZnO4 crystal structure and the In2Ga2ZnO7 crystal structure will be described. Figure 8(A-1) shows the simulation result of the InGaZnO4 crystal structure, and Figure 8(A-2) is the HAADF-STEM image of the InGaZnO4 crystal structure. Also, Figure 8(B-1) is the simulation result of the In2Ga2ZnO7 crystal structure, and Figure 8(B-2) is the HAADF-STEM image of the In2Ga2ZnO7 crystal structure. Note that Figures 8(A-1) and 8(B-1) show the crystal structures viewed from the (100) plane.

[0065] In the HAADF-STEM image, since a contrast proportional to the square of the atomic number is obtained, brighter points represent heavier atoms. That is, in the above quaternary system, brighter points represent I n atoms, and darker points represent Ga atoms or Zn atoms. Also, O atoms do not appear as an image because their mass is small compared to the above atoms. Thus, the HAADF-STEM image can be said to be an epoch-making observation means in that it can directly image the atomic-level structure easily. .

[0066] HAADF-STEM images related to the cross-section of In2Ga2ZnO7 crystal grains near the sample surface are shown in FIGS. 9 and 10. For the observation, a Schottky type field emission STEM with a spherical aberration correction function (HD-2700 manufactured by Hitachi, spherical aberration Cs: 5 μm or less) was used. Also, the acceleration voltage was 200 kV, and the detection angle was set to 40 mrad or more and 210 mrad or less. In FIGS. 9 and 10, as in FIG. 8, In atoms and Ga atoms or Zn atoms are shown. The intensity difference is not clear. This is presumably due to the fact that the crystal grains are fine and sufficient signal intensity cannot be obtained.

[0067] Upon detailed observation of FIG. 9, it is possible to confirm a structure in which two layers containing Ga or Zn are present between the In-containing layers (distance between the In-containing layers: 0.89 nm), and a structure in which one layer containing Ga or Zn is present between the In-containing layers (distance between the In-containing layers: 0.62 nm). Further, in FIG. 10, a more characteristic structure can be confirmed. In many regions, the outermost layer is not an In-containing layer. From this, it is suggested that the outermost surface is a layer containing Ga or Zn. This is an interesting fact in understanding the crystal grain formation mechanism.

[0068] Next, based on the above observation results, the mechanism of crystal nucleus generation and crystal growth near the surface of the oxide semiconductor film was confirmed by computer simulation.

[0069] To investigate the crystal plane orientation of the seed crystal related to crystal growth, the surface energies of In2Ga2ZnO7 (crystal symmetry: P63 / MMC), In2O3 (crystal symmetry: R-3C), Ga2O3 (crystal symmetry: R-3C), and ZnO (crystal symmetry: P63MC) were obtained by first-principles calculations. Here, the surface energy refers to the energy per unit area required to cut out a crystal plane from the bulk crystal. That is, the larger the surface energy, the more energetically unstable the surface structure is and the less likely it is to become a seed crystal.

[0070] For the above calculations, CASTEP, a first-principles calculation software based on density functional theory, was used. 。In the above calculation, the surface energy was obtained from the following equation (1).

[0071]

Equation

[0072] Ga and Zn are adjacent in the periodic table and have similar atomic radii, so their arrangements are random. That is, Zn may be arranged at the site where Ga is arranged, and Ga may be arranged at the site where Zn is arranged. To handle such random arrangements, the virtual crystal approximation was used in the calculation. Specifically, virtual atoms with a composition ratio of Ga:Zn = 2:1, i.e., 66.7% Ga and 33.3% Zn, were arranged at the sites where Ga or Zn is arranged. More specifically, the pseudo-potentials of each atom were mixed at the above ratio and assigned to the virtual atoms. % Zn, were arranged at the sites where Ga or Zn is arranged. More specifically, the pseudo-potentials of each atom were mixed at the above ratio and assigned to the virtual atoms.

[0073] The crystal structure used for the surface energy calculation of the (001) plane of In2Ga2ZnO7 is shown in Fig. 11( A), and the surface structures used for the surface energy calculation are shown in Figs. 11(B) to 11(D), respectively. Here, Fig. 11(B) shows the structure where O is on the outermost surface on the (001) plane (denoted as "(00 1):(Ga,Zn)O"), Fig. 11(C) shows the structure where In is on the outermost surface on the (001) plane (denoted as "(001):In"), and Fig. 11(D) shows the structure where Ga or Zn is on the outermost surface on the (001) plane (denoted as "(001):Ga,Zn"). The lattices in Figs. 11(B) to 11(D) were taken as the minimum unit of the periodic structure in the in-plane direction. Therefore, the size of the lattice in the (001) plane in the in-plane direction depends on the surface structure. Note that 1):(Ga,Zn)O"), Fig. 11(C) shows the structure where In is on the outermost surface on the (001) plane (denoted as "(001):In"), and Fig. 11(D) shows the structure where Ga or Zn is on the outermost surface on the (001) plane (denoted as "(001):Ga,Zn"). The lattices in Figs. 11(B) to 11(D) were taken as the minimum unit of the periodic structure in the in-plane direction. Therefore, the size of the lattice in the (001) plane in the in-plane direction depends on the surface structure. Note that the outermost surface (denoted as "(001):In"), and Fig. 11(D) shows the structure where Ga or Zn is on the outermost surface on the (001) plane (denoted as "(001):Ga,Zn"). The lattices in Figs. 11(B) to 11(D) were taken as the minimum unit of the periodic structure in the in-plane direction. Therefore, the size of the lattice in the (001) plane in the in-plane direction depends on the surface structure. Note that the outermost surface (denoted as "(001):Ga,Zn"). The lattices in Figs. 11(B) to 11(D) were taken as the minimum unit of the periodic structure in the in-plane direction. Therefore, the size of the lattice in the (001) plane in the in-plane direction depends on the surface structure. Note that the outermost surface (denoted as "(001):Ga,Zn"). The lattices in Figs. 11(B) to 11(D) were taken as the minimum unit of the periodic structure in the in-plane direction. Therefore, the size of the lattice in the (001) plane in the in-plane direction depends on the surface structure. Note that the outermost surface (denoted as "(001):Ga,Zn"). The lattices in Figs. 11(B) to 11(D) were taken as the minimum unit of the periodic structure in the in-plane direction. Therefore, the size of the lattice in the (001) plane in the in-plane direction depends on the surface structure. Note that , Figures 11(B) to 11(D) show the structures after structural optimization by first-principles calculations. Before the structural optimization, in the (001) plane, Ga or Zn was on the outermost surface, but due to the structural optimization, the structure has changed to one with O on the outermost surface.

[0074] The calculations were performed in the following procedure: after obtaining the most stable structure of the crystal including the lattice, a crystal plane was cut out, the lattice was fixed, and only the atomic arrangement was structurally optimized. The thickness of the vacuum region where there are no atoms was set to 1 nm. The details of the calculation conditions are shown in Figure 12. Considering that there is no periodicity in the direction perpendicular to the surface, the number of k-points was set to 1. Similar calculations were also performed for the (100) plane of In2Ga2ZnO7, In2O3, Ga2O3, and ZnO.

[0075] The calculation results of the surface energy are shown in Figure 13. From Figure 13, it can be seen that in the surface structure of In2Ga2ZnO7, the surface energy of (001):(Ga, Zn)O is the smallest. In, Ga, and Zn are metallic, and they become energetically unstable due to the presence of surface charges. In contrast, when the bonds are terminated with O, the surface energy can be reduced.

[0076] From the calculation results of the surface energy, it can be easily understood that it is difficult to form (001):In. This can also be supported by the observation results such as in Figure 10.

[0077] Also, by comparing the surface energy of (001):(Ga, Zn)O with the surface energy of the (001) plane of ZnO, the formation mechanism and growth mechanism of In2Ga2ZnO7 crystal grains can be understood. Hereinafter, the formation mechanism of In2Ga2ZnO7 crystal grains ​​​​​​​​​​​The growth mechanism will be briefly described with reference to FIG. 14.

[0078] The vapor pressure of ZnO is high and it is easy to evaporate. Therefore, when heat treatment is performed, near the surface of the In-Ga-Zn -O-based amorphous oxide semiconductor film, the composition ratio of Zn becomes small and the composition ratio of Ga becomes large (see FIG. 14(A)). (001): The surface energy of (Ga, Zn)O and the surface energy of the (001) plane of ZnO are compared. The surface energy of (001):(Ga, Zn)O is small, and a layer composed of ZnO and GaO is formed on the surface. However, there is little ZnO on the surface. Therefore, a layer composed of GaO is stably formed (see FIG. 14(B)). Then, crystal grains of In2Ga2ZnO7 grow from the above-mentioned layer composed of GaO (see FIG. 14(C)). In FIG. 10, if the outermost surface is a layer containing Ga and the second layer is a layer containing In, it will be easy to understand.

[0079] Note that the (001):(Ga, Zn)O of In2Ga2ZnO7 is smaller than the surface energies of the main planes of In2O3, Ga2O 3, and ZnO. Therefore, as far as judged from the surface energy, In2O3, Ga2O3, and ZnO do not phase-separate on the surface of the oxide semiconductor film.

[0080] In crystal growth, a plane with a small surface energy is more likely to form crystal grains and tend to grow crystals compared to a plane with a large surface energy. Therefore, the (001):(Ga, Zn)O of In2Ga2Zn O7 is more likely to crystallize compared to In2O3, Ga2O3, ZnO, etc. Also, the (100) plane of In2Ga2ZnO7 and (001):In, ​​​​(001): Even when compared with Ga and Zn, the surface energy of (001):(Ga, Zn)O is small. Therefore, the outermost surface is likely to be (001):(Ga, Zn)O, and the c-axis is likely to be oriented.

[0081] From the above, it is understood that by heating the surface, c-axis oriented In2Ga 2ZnO7 crystal grains are formed and grow in the vicinity of the surface of the oxide semiconductor film. The oxide semiconductor film has excellent electrical characteristics and is suitable for semiconductor devices. Or, the oxide semiconductor film has high reliability and is suitable for semiconductor devices.

[0082] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0083] (Embodiment 2) In this embodiment, an example of a transistor as a semiconductor device and a method for manufacturing the same will be described with reference to FIGS. 15 and 16.

[0084] First, a conductive layer 302 is formed on a substrate 300 (see FIG. 15(A)).

[0085] The substrate 300 may be any substrate having an insulating surface. For example, it can be a glass substrate. The glass substrate is preferably a non-alkali glass substrate. Examples of non-alkali glass substrates include glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass. Alternatively, as the substrate 300, an insulating substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon whose surface is coated with an insulating material, or a conductive substrate made of a conductor such as metal or stainless steel One can use a substrate whose surface is coated with an insulating material. Also, a plastic substrate can be used on condition that it can withstand the heat treatment in the manufacturing process.

[0086] The conductive layer 302 is preferably formed of a conductive material such as aluminum (Al), copper (Cu), molybdenum (Mo), tungsten (W), titanium (Ti), etc. As the forming method, there are a sputtering method, a vacuum evaporation method, a CVD method, etc. When using aluminum (or copper) for the conductive layer 302, since there are problems such as low heat resistance and easy corrosion with aluminum alone (or copper alone), it is preferable to form it in combination with a heat-resistant conductive material.

[0087] As the heat-resistant conductive material, a metal containing an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), an alloy containing the above-described elements as components, an alloy combining the above-described elements, or a nitride containing the above-described elements as components can be used. These heat-resistant conductive materials and aluminum (or copper) can be laminated to form the conductive layer 302.

[0088] Although not shown in the figure, an underlayer may be provided on the substrate 300. The underlayer has a function of preventing the diffusion of alkali metals (Li, Cs, Na, etc.), alkaline earth metals (Ca, Mg, etc.), and other impurities from the substrate 300. That is, by providing the underlayer, the problem of improving the reliability of the semiconductor device can be solved. The underlayer can be formed in a single-layer structure or a laminated structure using various insulating materials such as silicon nitride and silicon oxide. Specifically, for example Preferably, a structure in which silicon nitride and silicon oxide are sequentially laminated from the substrate 300 side is adopted. This is because silicon nitride has a high blocking effect against impurities. On the other hand, when silicon nitride is in contact with a semiconductor, there is a possibility that defects may occur in the semiconductor element. Therefore, it is preferable to apply silicon oxide as the material in contact with the semiconductor.

[0089] Next, a resist mask 304 is selectively formed on the conductive layer 302, and the conductive layer 302 is selectively etched using the resist mask 30 4 to form a conductive layer 306 that functions as a gate electrode (see Fig. 15(B)).

[0090] The resist mask 304 is formed through processes such as application of a resist material, exposure using a photomask, and development. The application of the resist material can be performed by methods such as the spin coating method. Also, the resist mask 304 may be selectively formed using a droplet discharge method, a screen printing method, etc. In this case, since processes such as exposure and development using a photomask are not required, it is possible to solve the problem of productivity improvement. Note that the resist mask 304 is removed after the conductive layer 306 is formed by etching the conductive layer 302.

[0091] The resist mask 304 may be formed using a multi-tone mask. Here, a multi-tone mask refers to a mask capable of performing exposure with multi-level light amounts. By using this, a resist mask having a plurality (typically two types) of thicknesses can be formed through one exposure and development process. Therefore, by using a multi-tone mask, an increase in the number of processes can be suppressed. ​​​​​​​

[0092] For the above etching, dry etching or wet etching may be used. Also, in order to improve the covering property of a gate insulating layer or the like formed later and prevent step discontinuity, it is preferable to etch so that the end portion of the conductive layer 306 has a tapered shape. For example, it is preferable to have a tapered shape such that the taper angle is 20° or more and less than 90°. Here, the "taper angle" means the angle formed by the side surface and the bottom surface of the layer having the tapered shape when observed in the cross-sectional direction of the layer. Next, an insulating layer 308 that functions as a gate insulating layer is formed so as to cover the conductive layer 306 (see FIG. 15(C)). The insulating layer 308 can be formed using materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, and tantalum oxide. Also, a film composed of these materials may be laminated and formed. These films are preferably formed to have a thickness of 5 nm or more and 250 nm or less using a sputtering method or the like. For example, as the insulating layer 308, a silicon oxide film can be formed to a thickness of 100 nm using a sputtering method. Further, a laminated insulating layer 308 may be formed by combining a sputtering method and a CVD method (such as a plasma CVD method). For example, the lower layer of the insulating layer 308 (the region in contact with the conductive layer 306) can be formed by a plasma CVD method, and the upper layer of the insulating layer 308 can be formed by a sputtering method. Since the plasma CVD method can easily form a film with good step coverage property, it is suitable as a method for forming a film directly above the conductive layer 306.

[0093]

[0094] ​​​​​​​​​​​​​​​, in the sputtering method, it is easier to reduce the hydrogen concentration in the film compared to the plasma CVD method. Therefore, by providing a film formed by the sputtering method in a region in contact with the semiconductor layer, diffusion of hydrogen in the insulating layer 308 into the semiconductor layer can be prevented. In particular, in the case of an oxide semiconductor film, the influence of hydrogen on the characteristics is extremely large, and adopting such a configuration is effective.

[0095] In addition, in this specification and the like, oxynitride refers to a substance in which the oxygen content (number of atoms) is larger than the nitrogen content in its composition. For example, silicon oxynitride means that oxygen is 50 atomic% or more and 70 atomic% or less, nitrogen is 0.5 atomic% or more and 15 atomic% or less, silicon is 25 atomic% or more and 3 5 atomic% or less, and hydrogen is 0.1 atomic% or more and 10 atomic% or less. Also, nitroxide refers to a substance in which the nitrogen content (number of atoms) is larger than the oxygen content in its composition. For example, silicon nitride oxide means that oxygen is 5 atomic% or more and 30 atomic% or less, nitrogen is 2 0 atomic% or more and 55 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 10 atoms % or more and 25 atomic% or less. However, the above ranges are for the case of measurement using the Rutherford Backscattering Spectrometry (RBS) or the Hydrogen Forward Scattering (HFS). Also, the total of the content ratios of the constituent elements does not exceed 100 atomic%. trometry) or the Hydrogen Forward Scattering). Also, the total of the content ratios of the constituent elements does not exceed 100 atomic%.

[0096] Next, a semiconductor layer 310 is formed so as to cover the insulating layer 308 (see Fig. 15(D)). In this embodiment, the oxide semiconductor film described in the previous embodiment is applied to the semiconductor layer 310 ​Use it. Regarding the details of the oxide semiconductor film, the previous embodiments can be referred to.

[0097] In addition, in this embodiment, the case where the semiconductor layer 310 is formed as a single layer is shown. The semiconductor layer 310 may have a stacked structure. For example, two or more oxide semiconductor films having different compositions may be stacked on the insulating layer 308 to form the semiconductor layer 310. Also, two or more oxide semiconductor films having different crystallinities may be stacked to form the semiconductor layer 310.

[0098] Next, a resist mask 312 is selectively formed on the semiconductor layer 310, and the semiconductor layer 310 is selectively etched using the resist mask 312 to form the semiconductor layer 314 (see Fig. 16(A)). Here, the resist mask 312 can be formed in the same manner as the resist mask 304. Also, the resist mask 312 is removed after the semiconductor layer 314 is formed by etching the semiconductor layer 310.

[0099] As a method for etching the semiconductor layer 310, wet etching or dry etching can be used. For example, by wet etching using a mixed solution of acetic acid, nitric acid, and phosphoric acid, unnecessary portions of the semiconductor layer 310 can be removed to form the semiconductor layer 314. Note that the etchant (etching solution) that can be used for the above wet etching only needs to be able to etch the semiconductor layer 310 and is not limited to those described above.

[0100] When performing dry etching, for example, it is advisable to use a gas containing chlorine or a gas in which oxygen is added to a gas containing chlorine. By using a gas containing chlorine, the conductive layer This is because the etching selectivity between the underlying layer and the semiconductor layer 310 becomes easier to achieve.

[0101] For dry etching, an etching apparatus using the reactive ion etching method (RIE method) or an etching apparatus using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) can be used. Also, compared with an ICP etching apparatus an etching apparatus in the ECCP (Enhanced Capacitively Coupled Plasma) mode that can obtain uniform discharge over a wide area can also be used. Even in the case of using a substrate of the 10th generation or later as the substrate, it is easy to handle with an etching apparatus in the CCP mode.

[0102] Next, a conductive layer 316 is formed so as to cover the insulating layer 308 and the semiconductor layer 314 (see FIG. 1 6(B)). The conductive layer 316 can be formed by the same materials and methods as the conductive layer 302. For example, the conductive layer 316 can be formed in a single-layer structure of a molybdenum layer or a titanium layer. Furthermore, the conductive layer 316 may be formed in a single-layer structure of an aluminum layer containing silicon.

[0103] Next, a resist mask 318 and a resist mask 320 are selectively formed on the conductive layer 316, and the conductive layer 316 is selectively etched using the resist masks to form a conductive layer 322 that functions as one of the source electrode or the drain electrode and a conductive layer 324 that functions as the other of the source electrode or the drain electrode (see FIG. 16(C)). Here, the resist mask 318 and the resist mask 320 can be formed in the same manner as the resist mask 304. Also, the resist mask 318 and the resist mask 320 are removed after the conductive layer 322 and the conductive layer 324 are formed by etching the conductive layer 316. Next, a resist mask 318 and a resist mask 320 are selectively formed on the conductive layer 316, and the conductive layer 316 is selectively etched using the resist masks to form a conductive layer 322 that functions as one of the source electrode or the drain electrode and a conductive layer 324 that functions as the other of the source electrode or the drain electrode (see FIG. 16(C)). Here, the resist mask 318 and the resist mask 320 can be formed in the same manner as the resist mask 304. Also, the resist mask 318 and the resist mask 320 are removed after the conductive layer 322 and the conductive layer 324 are formed by etching the conductive layer 316. Next, a resist mask 318 and a resist mask 320 are selectively formed on the conductive layer 316, and the conductive layer 316 is selectively etched using the resist masks to form a conductive layer 322 that functions as one of the source electrode or the drain electrode and a conductive layer 324 that functions as the other of the source electrode or the drain electrode (see FIG. 16(C)). Here, the resist mask 318 and the resist mask 320 can be formed in the same manner as the resist mask 304. Also, the resist mask 318 and the resist mask 320 are removed after the conductive layer 322 and the conductive layer 324 are formed by etching the conductive layer 316. Next, a resist mask 318 and a resist mask 320 are selectively formed on the conductive layer 316, and the conductive layer 316 is selectively etched using the resist masks to form a conductive layer 322 that functions as one of the source electrode or the drain electrode and a conductive layer 324 that functions as the other of the source electrode or the drain electrode (see FIG. 16(C)). Here, the resist mask 318 and the resist mask 320 can be formed in the same manner as the resist mask 304. Also, the resist mask 318 and the resist mask 320 are removed after the conductive layer 322 and the conductive layer 324 are formed by etching the conductive layer 316. Next, a resist mask 318 and a resist mask 320 are selectively formed on the conductive layer 316, and the conductive layer 316 is selectively etched using the resist masks to form a conductive layer 322 that functions as one of the source electrode or the drain electrode and a conductive layer 324 that functions as the other of the source electrode or the drain electrode (see FIG. 16(C)). Here, the resist mask 318 and the resist mask 320 can be formed in the same manner as the resist mask 304. Also, the resist mask 318 and the resist mask 320 are removed after the conductive layer 322 and the conductive layer 324 are formed by etching the conductive layer 316. Next, a resist mask 318 and a resist mask 320 are selectively formed on the conductive layer 316, and the conductive layer 316 is selectively etched using the resist masks to form a conductive layer 322 that functions as one of the source electrode or the drain electrode and a conductive layer 324 that functions as the other of the source electrode or the drain electrode (see FIG. 16(C)). Here, the resist mask 318 and the resist mask 320 can be formed in the same manner as the resist mask 304. Also, the resist mask 318 and the resist mask 320 are removed after the conductive layer 322 and the conductive layer 324 are formed by etching the conductive layer 316. Next, a resist mask 318 and a resist mask 320 are selectively formed on the conductive layer 316, and the conductive layer 316 is selectively etched using the resist masks to form a conductive layer 322 that functions as one of the source electrode or the drain electrode and a conductive layer 324 that functions as the other of the source electrode or the drain electrode (see FIG. 16(C)). Here, the resist mask 318 and the resist mask 320 can be formed in the same manner as the resist mask 304. Also, the resist mask 318 and the resist mask 320 are removed after the conductive layer 322 and the conductive layer 324 are formed by etching the conductive layer 316. Next, a resist mask 318 and a resist mask 320 are selectively formed on the conductive layer 316, and the conductive layer 316 is selectively etched using the resist masks to form a conductive layer 322 that functions as one of the source electrode or the drain electrode and a conductive layer 324 that functions as the other of the source electrode or the drain electrode (see FIG. 16(C)). Here, the resist mask 318 and the resist mask 320 can be formed in the same manner as the resist mask 304. Also, the resist mask 318 and the resist mask 320 are removed after the conductive layer 322 and the conductive layer 324 are formed by etching the conductive layer 316.

[0104] Note that, as the method of etching the conductive layer 316, either wet etching or dry etching can be used. Note that, as the method of etching the conductive layer 316, either wet etching or dry etching can be used.

[0105] Next, an insulating layer 326 is formed so as to cover the conductive layer 322, the conductive layer 324, the semiconductor layer 314, etc. (see FIG. 16(D)). Here, the insulating layer 326 corresponds to a so-called interlayer insulating layer. The insulating layer 326 can be formed using materials such as silicon oxide, aluminum oxide, tantalum oxide, etc. Also, a film made of these materials may be laminated and formed. Thus, the transistor 350 using the oxide semiconductor film is completed (see FIG. 16(D)). Next, an insulating layer 326 is formed so as to cover the conductive layer 322, the conductive layer 324, the semiconductor layer 314, etc. (see FIG. 16(D)). Here, the insulating layer 326 corresponds to a so-called interlayer insulating layer. The insulating layer 326 can be formed using materials such as silicon oxide, aluminum oxide, tantalum oxide, etc. Also, a film made of these materials may be laminated and formed. Thus, the transistor 350 using the oxide semiconductor film is completed (see FIG. 16(D)). Next, an insulating layer 326 is formed so as to cover the conductive layer 322, the conductive layer 324, the semiconductor layer 314, etc. (see FIG. 16(D)). Here, the insulating layer 326 corresponds to a so-called interlayer insulating layer. The insulating layer 326 can be formed using materials such as silicon oxide, aluminum oxide, tantalum oxide, etc. Also, a film made of these materials may be laminated and formed. Thus, the transistor 350 using the oxide semiconductor film is completed (see FIG. 16(D)). Next, an insulating layer 326 is formed so as to cover the conductive layer 322, the conductive layer 324, the semiconductor layer 314, etc. (see FIG. 16(D)). Here, the insulating layer 326 corresponds to a so-called interlayer insulating layer. The insulating layer 326 can be formed using materials such as silicon oxide, aluminum oxide, tantalum oxide, etc. Also, a film made of these materials may be laminated and formed. Thus, the transistor 350 using the oxide semiconductor film is completed (see FIG. 16(D)). Next, an insulating layer 326 is formed so as to cover the conductive layer 322, the conductive layer 324, the semiconductor layer 314, etc. (see FIG. 16(D)). Here, the insulating layer 326 corresponds to a so-called interlayer insulating layer. The insulating layer 326 can be formed using materials such as silicon oxide, aluminum oxide, tantalum oxide, etc. Also, a film made of these materials may be laminated and formed. Thus, the transistor 350 using the oxide semiconductor film is completed (see FIG. 16(D)).

[0106] As shown in this embodiment, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (for example, moisture, etc.) into the oxide semiconductor film. Therefore, the reliability of the semiconductor device can be improved. As shown in this embodiment, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (for example, moisture, etc.) into the oxide semiconductor film. Therefore, the reliability of the semiconductor device can be improved. As shown in this embodiment, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (for example, moisture, etc.) into the oxide semiconductor film. Therefore, the reliability of the semiconductor device can be improved. As shown in this embodiment, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (for example, moisture, etc.) into the oxide semiconductor film. Therefore, the reliability of the semiconductor device can be improved.

[0107] In addition, by fabricating a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device having good electrical characteristics.

[0108] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0109] (Embodiment 3) In this embodiment, another example of a transistor as a semiconductor device and a method for manufacturing the same will be described with reference to FIGS. 17 and 18. Note that since many parts of the manufacturing process of the semiconductor device in this embodiment are common to the previous embodiment, the description of the overlapping parts will be omitted below, and the different points will be described in detail.

[0110] First, a conductive layer 402 is formed on a substrate 400 (see FIG. 17(A)). For the substrate 400, the conductive layer 402, and other details, refer to the previous embodiment (such as the description part of FIG. 4(A)). Also, an underlayer may be provided on the substrate 400. For details of the underlayer, the previous embodiment can also be referred to.

[0111] Next, a resist mask 404 is selectively formed on the conductive layer 402, and the conductive layer 402 is selectively etched using the resist mask 40 4 to form a conductive layer 406 that functions as a gate electrode (see FIG. 17(B)). For the resist mask 404, the conductive layer 406, the etching, and other details, refer to the previous embodiment (such as the description part of FIG. 15(B)).

[0112] Next, an insulating layer 408 that functions as a gate insulating layer is formed so as to cover the conductive layer 406. (see Fig. 17(C)). For the insulating layer 408 and other details, refer to the previous embodiment (the description part of Fig. 1 5(C), etc.).

[0113] Next, a conductive layer 410 is formed so as to cover the insulating layer 408 (see Fig. 17(D)). The conductive layer 410 can be formed by the same material and method as the conductive layer 402. That is, for details, refer to the previous embodiment (the description part of Fig. 15(A), Fig. 16(B), etc.).

[0114] Next, a resist mask 412 and a resist mask 414 are selectively formed on the conductive layer 410, and by selectively etching the conductive layer 410 using the resist mask, a conductive layer 416 that functions as one of the source electrode or the drain electrode and a conductive layer 418 that functions as the other of the source electrode or the drain electrode are formed (see Fig. 18(A)). The resist mask 412 and the resist mask 414 can be formed in the same manner as the resist mask 404. Also, as a method of etching the conductive layer 410, either wet etching or dry etching can be used. That is, for details of the resist mask and etching, refer to the previous embodiment (the description part of Fig. 15(B), Fig. 16(C), etc.).

[0115] Next, a semiconductor layer 420 is formed so as to cover the insulating layer 408, the conductive layer 416, the conductive layer 418, etc. (see Fig. 18(B)). In this embodiment, the oxide semiconductor film described in the previous embodiment is applied to the semiconductor layer 420. For details of the oxide semiconductor film, refer to the previous embodiment. ​​​The form can be taken into consideration.

[0116] Next, a resist mask 422 is selectively formed on the semiconductor layer 420, and the semiconductor layer 420 is selectively etched using the resist mask 4 22 to form a semiconductor layer 424 (see Fig. 18(C)). For details of the resist mask and etching, refer to the previous embodiments (such as the description parts of Fig. 15(B) and Fig. 16(A)). The form can be taken into consideration.

[0117] Next, an insulating layer 426 is formed so as to cover the conductive layer 416, the conductive layer 418, the semiconductor layer 424, etc. (see Fig. 18(D)). Here, the insulating layer 426 corresponds to a so-called interlayer insulating layer. The insulating layer 426 can be formed using materials such as silicon oxide, aluminum oxide, tantalum oxide, etc. Also, a film composed of these materials may be laminated and formed. As described above A transistor 450 using an oxide semiconductor film is completed (see Fig. 18(D)). By fabricating a semiconductor device using the oxide semiconductor film shown in the previous embodiment as shown in this embodiment, it is possible to suppress the incorporation of impurities (such as moisture) into the oxide semiconductor film. Therefore, the reliability of the semiconductor device can be improved. Also, by fabricating a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device with good electrical characteristics.

[0118] As shown in this embodiment, by fabricating a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (such as moisture) into the oxide semiconductor film. Therefore, the reliability of the semiconductor device can be improved. Also, by fabricating a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device with good electrical characteristics. The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

[0119] The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments. The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

[0120] The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments. The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

[0121] (Embodiment 4) In this embodiment, another example of a transistor as a semiconductor device and a method for manufacturing the same will be described with reference to FIGS. 19 and 20. Note that since many parts of the manufacturing process of the semiconductor device in this embodiment are common to the previous embodiment, the description of the overlapping parts will be omitted below, and the different points will be described in detail. First, a semiconductor layer 502 is formed on a substrate 500 (see FIG. 19(A)). After a resist mask 504 is selectively formed on the semiconductor layer 50 2, the semiconductor layer 502 is selectively etched using the resist mask 504 to form a semiconductor layer 506 (see FIG. 19(B

[0122] ). In this embodiment, an oxide semiconductor film described in the previous embodiment is applied to the semiconductor layer 502. For details of the oxide semiconductor film, the previous embodiment can be referred to 2. Also, for other details, the previous embodiment can be referred to. ). )). For details, the previous embodiment can be referred to. Next, a conductive layer 508 is formed so as to cover the semiconductor layer 506 (see FIG. 19(C)). After a resist mask 510 and a resist mask 512 are selectively formed on the conductive layer 508, the conductive layer 508 is selectively etched using the resist mask to form a conductive layer 514 that functions as one of a source electrode or a drain

[0123] electrode and a conductive layer 516 that functions as the other of the source electrode or the drain electrode (see FIG. 19(D)). For details, the previous embodiment can be referred to 508, and then a resist mask 510 and a resist mask 512 are selectively formed on the conductive layer 508. Then, the conductive layer 508 is selectively etched using the resist mask to form a conductive layer 514 that functions as one of a source electrode or a drain electrode and a conductive layer 516 that functions as the other of the source electrode or the drain electrode (see FIG. 19(D)). For details, the previous embodiment can be referred to electrode. For details, the previous embodiment can be referred to. Next, an insulating layer 518 that functions as a gate insulating layer is formed so as to cover the semiconductor layer 506, the conductive layer 514, and the conductive layer 516 (see FIG. 20(A)). Then, a conductive layer is formed on the insulating layer 518

[0124] layer. layer is formed on the insulating layer 518 Form layer 520 (see FIG. 20(B)), and selectively form resist mask 52 2 on the conductive layer 520. After that, use the resist mask 522 to selectively etch the conductive layer 520 to form a conductive layer 524 that functions as a gate electrode (see FIG. 20(C)). For details, the previous embodiments can be referred to. Thus, a transistor 550 using an oxide semiconductor film is completed (see FIG. 20(D)). As described in this embodiment, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (such as moisture) into the oxide semiconductor film. Therefore, the reliability of the semiconductor device can be improved.

[0125] As shown in this embodiment, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device with good electrical characteristics.

[0126] Also, by manufacturing a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device with good electrical characteristics.

[0127] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0128] (Embodiment 5) In this embodiment, another example of a transistor as a semiconductor device and its manufacturing method will be described with reference to FIGS. 21 and 22. Note that since the manufacturing process of the semiconductor device in this embodiment is common to the previous embodiment in many parts, the description of the overlapping parts will be omitted below, and the different points will be described in detail.

[0129] ​​​​​​​​​First, a conductive layer 602 is formed on a substrate 600 (see Fig. 21(A)). After selectively forming a resist mask 604 and a resist mask 606 on the conductive layer 602, the conductive layer 602 is selectively etched using the resist mask to form a conductive layer 608 that functions as one of a source electrode or a drain electrode and a conductive layer 610 that functions as the other of the source electrode or the drain electrode (see Fig. 21(B)). For details, the previous embodiments can be referred to. After selectively forming a resist mask 604 and a resist mask 606 on it, the conductive layer 602 is selectively etched using the resist mask. to form a conductive layer 608 that functions as one of a source electrode or a drain electrode and a conductive layer 610 that functions as the other of the source electrode or the drain electrode. (See Fig. 21(B)). For details, the previous embodiments can be referred to.

[0130] Next, a semiconductor layer 612 in contact with the conductive layer 608 and the conductive layer 610 is formed (see Fig. 21(C)). After selectively forming a resist mask 614 on the semiconductor layer 612, the semiconductor layer 612 is selectively etched using the resist mask 614 to form a semiconductor layer 616 (see Fig. 21(D)). In this embodiment, an oxide semiconductor film described in the previous embodiment is applied to the semiconductor layer 612. For details of the oxide semiconductor film, the previous embodiments can be referred to. Also, for other details, the previous embodiments can be referred to. After selectively forming a resist mask 614 on the semiconductor layer 612, the semiconductor layer 612 is selectively etched using the resist mask 614. to form a semiconductor layer 616. (See Fig. 21(D)). In this embodiment, an oxide semiconductor film described in the previous embodiment is applied to the semiconductor layer 612. For details of the oxide semiconductor film, the previous embodiments can be referred to. Also, for other details, the previous embodiments can be referred to.

[0131] Next, an insulating layer 618 that functions as a gate insulating layer is formed so as to cover the semiconductor layer 616, the conductive layer 608, and the conductive layer 610 (see Fig. 22(A)). Then, a conductive layer 620 is formed on the insulating layer 618 (see Fig. 22(B)). After selectively forming a resist mask 622 on the conductive layer 620, the conductive layer 620 is selectively etched using the resist mask 622 to form a conductive layer 624 that functions as a gate electrode (see Fig. 22(C)). For details, the previous embodiments can be referred to. As described above, a transistor 650 using an oxide semiconductor film is completed (see Fig. 22(D)). After selectively forming a resist mask 622 on the conductive layer 620, the conductive layer 620 is selectively etched using the resist mask 622. to form a conductive layer 624 that functions as a gate electrode. (See Fig. 22(C)). For details, the previous embodiments can be referred to. As described above, a transistor 650 using an oxide semiconductor film is completed (see Fig. 22(D)). ​​

[0132] As shown in this embodiment, by fabricating a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to suppress the incorporation of impurities (such as moisture) into the oxide semiconductor film. Therefore, the reliability of the semiconductor device can be improved.

[0133] Also, by fabricating a semiconductor device using the oxide semiconductor film shown in the previous embodiment, it is possible to provide a semiconductor device with good electrical characteristics.

[0134] The configurations, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, methods, etc. shown in other embodiments.

[0135] (Embodiment 6) In this embodiment, as an example using the semiconductor device described in the previous embodiment, the configuration of a display device using an electrophoretic element will be described with reference to FIG. 23. Note that in this embodiment, although an example of a display device using an electrophoretic element is described, the display devices to which a semiconductor device, which is one aspect of the disclosed invention, can be applied are not limited to this. A semiconductor device, which is one aspect of the disclosed invention, can be applied to display devices using various display elements such as liquid crystal display elements and electroluminescence elements.

[0136] FIG. 23(A) shows a plan view of a pixel of the display device, and FIG. 23(B) shows a cross-sectional view corresponding to A-B in FIG. 23(A). The display device shown in FIG. 23 includes a substrate 700, a transistor 702 and a capacitor element 704 on the substrate 700, and on the transistor 702 and the capacitor element 704 It has an electrophoresis element 706 and a substrate 708 with translucency on the electrophoresis element 706. . In Fig. 23(A), for simplicity, the electrophoresis element 706 is omitted.

[0137] The transistor 702 is composed of a conductive layer 710, an insulating layer 712 covering the conductive layer 710, a semiconductor layer 714 on the insulating layer 7 12, and conductive layers 716 and 718 in contact with the semiconductor layer 714. Here, the conductive layer 710 functions as the gate electrode of the transistor, the insulating layer 712 functions as the gate insulating layer of the transistor, and the conductive layer 716 functions as the first terminal (one of the source terminal or the drain terminal) of the transistor, and the conductive layer 718 functions as the t he second terminal (the other of the source terminal or the drain terminal) of the transistor. For details , the previous embodiments can be referred to.

[0138] Also, in the above, the conductive layer 710 is electrically connected to the gate line 720, and the conductive layer 716 is electrically connected to the source line 722. The conductive layer 710 may be integral with the gate line 720, and the conductive layer 716 may be integral with the source line 722.

[0139] The capacitive element 704 is composed of the conductive layer 718, the insulating layer 712, and the conductive layer 724. The capacitive element 704 has the role of holding the signal input to the pixel. The above components constituting the capacitive element 704 can be formed together when forming the components of the transistor.

[0140] In the above, the conductive layer 724 is electrically connected to the capacitive wiring 726. The conductive layer 718 functions as one terminal of the capacitive element, the insulating layer 712 functions as a dielectric, and the conductive layer 72 ​4 functions as the other terminal. The conductive layer 724 may be integrated with the capacitive wiring 726 .

[0141] The electrophoretic element 706 includes a pixel electrode 728, a common electrode 730 (which may also be referred to as a counter electrode) , and a layer 732 containing charged particles provided between the pixel electrode 728 and the common electrode 730 . As the charged particles contained in the layer 732 containing charged particles, titanium oxide or the like can be applied as positively charged particles, and carbon black or the like can be applied as negatively charged particles. In addition, a single material selected from conductors, insulators, semiconductors, magnetic materials , liquid crystal materials, ferroelectric materials, electroluminescent materials, electrochromic materials, magnetophoretic materials, or a composite material thereof can also be applied.

[0142] In the above, the pixel electrode 728 is electrically connected to the conductive layer 718 through openings provided in the insulating layer 7 34 and the insulating layer 736 that cover the transistor 702 and the capacitive element 704 , and the common electrode 730 is electrically connected to the common electrodes of other pixels.

[0143] With the above configuration, the electric field applied to the layer 732 containing charged particles can be controlled, and the arrangement of the charged particles in the layer 732 containing charged particles can be controlled. And thereby, display can be realized. Note that the above configuration is merely an example, and it is not necessary to limit the display device using the semiconductor device, which is one aspect of the disclosed invention, to the above configuration. The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0144]

[0145] ​​​ (Embodiment 7) In this embodiment, regarding the application forms of the display device shown in the previous embodiment, specific examples will be shown and described with reference to FIGS. 24(A) to 24(D). (A) to FIG. 24(D).

[0146] FIG. 24(A) shows a portable information terminal, which includes a housing 801, a display unit 802, operation buttons 803, etc. The display device described in the previous embodiment can be applied to the display unit 802.

[0147] FIG. 24(B) shows an example of an electronic book equipped with the display device described in the previous embodiment. The first housing 811 has a first display unit 812, the first housing 811 has operation buttons 813, and the second housing 814 has a second display unit 815. The display device described in the previous embodiment can be applied to the first display unit 812 and the second display unit 815. Also, the first housing 811 and the second housing 814 can be opened and closed by a support unit 816. With this configuration, it is possible to perform operations similar to those of a paper book. The first housing 811 has a first display unit 812, the first housing 811 has operation buttons 813, and the second housing 814 has a second display unit 815. The display device described in the previous embodiment can be applied to the first display unit 812 and the second display unit 815. Also, the first housing 811 and the second housing 814 can be opened and closed by a support unit 816. With this configuration, it is possible to perform operations similar to those of a paper book. The first housing 811 has a first display unit 812, the first housing 811 has operation buttons 813, and the second housing 814 has a second display unit 815. The display device described in the previous embodiment can be applied to the first display unit 812 and the second display unit 815. Also, the first housing 811 and the second housing 814 can be opened and closed by a support unit 816. With this configuration, it is possible to perform operations similar to those of a paper book. The first housing 811 has a first display unit 812, the first housing 811 has operation buttons 813, and the second housing 814 has a second display unit 815. The display device described in the previous embodiment can be applied to the first display unit 812 and the second display unit 815. Also, the first housing 811 and the second housing 814 can be opened and closed by a support unit 816. With this configuration, it is possible to perform operations similar to those of a paper book. The first housing 811 has a first display unit 812, the first housing 811 has operation buttons 813, and the second housing 814 has a second display unit 815. The display device described in the previous embodiment can be applied to the first display unit 812 and the second display unit 815. Also, the first housing 811 and the second housing 814 can be opened and closed by a support unit 816. With this configuration, it is possible to perform operations similar to those of a paper book. With this configuration, it is possible to perform operations similar to those of a paper book.

[0148] FIG. 24(C) shows a display device 820 for vehicle advertising. When the advertising medium is a paper print, the advertisement is replaced manually, but by using the display device, the advertisement display can be changed in a short time without manual effort. Also, a stable image can be obtained without the display being distorted. When the advertising medium is a paper print, the advertisement is replaced manually, but by using the display device, the advertisement display can be changed in a short time without manual effort. Also, a stable image can be obtained without the display being distorted. When the advertising medium is a paper print, the advertisement is replaced manually, but by using the display device, the advertisement display can be changed in a short time without manual effort. Also, a stable image can be obtained without the display being distorted. When the advertising medium is a paper print, the advertisement is replaced manually, but by using the display device, the advertisement display can be changed in a short time without manual effort. Also, a stable image can be obtained without the display being distorted.

[0149] FIG. 24(D) shows an outdoor advertising display device 830. By using a display device made using a flexible substrate and swinging it, the advertising effect can be enhanced. By using a display device made using a flexible substrate and swinging it, the advertising effect can be enhanced. By using a display device made using a flexible substrate and swinging it, the advertising effect can be enhanced.

[0150] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

Description of Reference Numerals

[0151] 100 Oxide semiconductor film 110 Substrate 120 Amorphous region 130 Crystal grain 140 Crystal region 200 Oxide semiconductor film 300 Substrate 302 Conductive layer 304 Resist mask 306 Conductive layer 308 Insulating layer 310 Semiconductor layer 312 Resist mask 314 Semiconductor layer 316 Conductive layer 318 Resist mask 320 Resist mask 322 Conductive layer 324 Conductive layer 326 Insulating layer 350 Transistor 400 Substrate 402 Conductive layer 404 Resist mask 406 Conductive layer 408 Insulating layer 410 Conductive layer 412 Resist mask 414 Resist mask 416 Conductive layer 418 Conductive layer 420 Semiconductor layer 422 Resist mask 424 Semiconductor layer 426 Insulating layer 450 Transistor 500 Substrate 502 Semiconductor layer 504 Resist mask 506 Semiconductor layer 508 Conductive layer 510 Resist mask 512 Resist mask 514 Conductive layer 516 Conductive layer 518 Insulating layer 520 Conductive layer 522 Resist mask 524 Conductive layer 550 Transistor 600 Substrate 602 Conductive layer 604 Resist mask 606 Resist mask 608 Conductive layer 610 Conductive layer 612 Semiconductor layer 614 Resist mask 616 Semiconductor layer 618 Insulating layer 620 Conductive layer 622 Resist mask 624 Conductive layer 650 Transistor 700 Substrate 702 Transistor 704 Capacitor element 706 Electrophoretic element 708 Substrate 710 Conductive layer 712 Insulating layer 714 Semiconductor layer 716 Conductive layer 718 Conductive layer 720 Gate line 722 Source line 724 Conductive layer 726 Capacitor wiring 728 Pixel electrode 730 Common electrode 732 Layer containing charged particles 734 Insulating layer 736 Insulating layer 801 Housing 802 Display unit 803 Operation button 811 Housing 812 Display unit 813 Operation Button 814 Housing 815 Display Unit 816 Support Unit 820 Display Device 830 Display Device

Claims

【Claim 1】 An amorphous region mainly composed of an amorphous oxide semiconductor containing In, Ga, and Zn, and In the vicinity of the surface, In ２ Ga ２ ZnO ７ and a crystal region containing crystal grains of, The oxide semiconductor film in which the c-axis of the crystal grains is oriented so as to be substantially perpendicular to the surface.

Images