Semiconductor test device

Abstract

To prevent generation of inrush current and surge voltage during power module testing.SOLUTION: A power module 117 is arranged on a heating / cooling plate, a connection structure 218a is connected to an electrode terminal of the power module 117, and a gate driver circuit 113 is connected to a gate signal terminal g. A switch circuit 124a is connected to the connection structure 218a. A test current from the power supply device 121 is supplied to the power module 117 via the switch circuit 124a. Upon turned on, a switch circuit 124b short-circuits an output terminal of the power supply device 121. When a test current is supplied to the power module 117, an on-signal is applied to the gate signal terminal g of the power module 117, and then the switch circuit 124a is turned on. The switch circuit 124b is turned on before the switch circuit 124a is turned on, and the switch circuit 124b is turned off after the switch circuit 124a is turned off.SELECTED DRAWING: Figure 44

Description

Technical Field

[0001] The present invention relates to a semiconductor test apparatus for performing a power cycle test on semiconductor elements such as SiC, IGBT, MOS-FET, GaN, and bipolar transistors, a test method for semiconductor elements, and the like.

[0002] Provided are a semiconductor test apparatus and a test method for semiconductor elements that can efficiently reproduce stress close to a failure mode in the usage environment of semiconductor elements and can evaluate power semiconductor elements and the like with high reliability.

Background Art

[0003] A power semiconductor is a semiconductor that can handle high voltages and large currents. For example, a combination of an inverter incorporating the latest power semiconductor and a motor, such as HEV / EV which is an "advanced technology", is currently seeing widespread popularity. In the future, this combination is expected to become the "core" and contribute to the electrification of various transportation equipment such as railways, ships, airplanes, and satellites.

[0004] Power semiconductors range from small power supplies used in CPUs, memories, etc. to large power supplies for driving motors, so their sizes and types are very diverse.

[0005] From the further improvement of energy conversion efficiency, the development of new materials in wide-gap power semiconductors such as SiC (silicon carbide) and GaN (gallium nitride) is also progressing.

[0006] Since power semiconductors can handle a large amount of power, they also generate a large amount of heat by themselves and need to be cooled efficiently. Therefore, in terms of the reliability of mounting, it is necessary to consider many items.

[0007] The lifespan of a power semiconductor device includes the lifespan due to the thermal fatigue phenomenon caused by the heat generation of the power semiconductor device itself and the lifespan due to the thermal fatigue phenomenon caused by the temperature change of the external environment of the power semiconductor device. In addition, there is the lifespan due to voltage fatigue caused by the applied voltage to the gate insulating film of the power semiconductor device, etc.

[0008] Generally, in the lifespan test of a power semiconductor device, the semiconductor device is repeatedly energized and turned off. For example, the applied voltage and current are set at the emitter terminal (source terminal), collector terminal (drain terminal), etc. of the transistor of the semiconductor device, and a periodic on / off signal (operation / non-operation signal) is applied to the gate terminal to conduct the test.

[0009] The current applied to the semiconductor device during the test is as large as several hundred amperes, and low-resistance wiring is required to avoid heat generation and voltage drop. Since the test current is large, it is necessary to connect the connection part between the semiconductor device and the wiring with low resistance.

[0010] Many semiconductor devices to be tested are connected in multiple stages. When the semiconductor device is a transistor, etc., the inter-channel voltage varies greatly depending on the test conditions, etc. If the test signal applied to the semiconductor device is not appropriate, the semiconductor device may be damaged by the test signal applied.

[0011] There are also many types of tests for semiconductor devices, and it is necessary to change the wiring connection according to the type of test. The work of changing the wiring connection requires a lot of time, and connection failures and connection mistakes may occur. The power semiconductor device is also progressing towards smaller packaging, and with the smaller packaging, the connection area of the terminals of the package, etc. is also becoming smaller.

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0013] In a conventional semiconductor test apparatus, a test of a power semiconductor element (such as a transistor) is performed by turning on and off the transistor 117 and flowing a constant current Id through the channel of the transistor.

[0014] The test items to be performed by a semiconductor element test apparatus (power cycle test apparatus) are diverse, and it is necessary to change the setting conditions or test conditions in accordance with the test items.

[0015] Power semiconductors need to perform a variety of reliability tests, but there is a problem that conventional semiconductor element test apparatuses cannot efficiently perform a variety of reliability tests.

[0016] The test items to be performed by a semiconductor test apparatus (power cycle test apparatus) are diverse, and it is necessary to change the connection with the transistor 117 (change the wiring) in accordance with the test items.

[0017] The constant current Id is often a current of several hundred A or more, and it is necessary to use a thick wire for the connection wiring 211 and the power supply wiring 212 through which the current flows. Also, a large current Id flows through the semiconductor electrode terminal. If there is a contact resistance between the connection electrode terminal of the semiconductor element and the connection wiring, there is a problem that the contact portion generates heat and the semiconductor element is destroyed.

[0018] In recent years, the power semiconductor element has also been miniaturized. Along with the miniaturization of the power semiconductor element, the size of the connection electrode of the power semiconductor element has also become smaller.

[0019] When the connection terminal of the power semiconductor element becomes smaller, it becomes difficult to connect with the connection wiring of the connection substrate. Also, the connection resistance becomes higher. Since a large current flows through the power semiconductor element, when the connection resistance becomes higher, the connection portion generates heat and the power semiconductor element burns out.

[0020] In a power semiconductor device test apparatus, it cannot be fixed by soldering or the like. In a power semiconductor device test apparatus, it is necessary to make the power semiconductor device to be tested detachable.

[0021] Changing the connection of the thick wire wiring to correspond to the test items requires a long time and also requires a work space for changing the wiring connection. Therefore, there is a problem that the test apparatus becomes large.

Means for Solving the Problem

[0022] The semiconductor device test apparatus of the present invention includes a power switching unit that energizes other devices during the period when one device is powered off, a plurality of power supply devices, a plurality of temperature measurement devices, and a noise control device. The semiconductor device of the present invention can arbitrarily set the period and the on time for turning on (operating) the semiconductor device.

[0023] By changing or controlling any one of the period tc, on time ton, and off time toff of the power semiconductor device, the time and interval during which a predetermined current flows through the power semiconductor device are controlled.

[0024] When the power semiconductor device is energized for the on time ton1, the temperature of the power semiconductor device gradually rises. The temperature information of the power semiconductor device is acquired in real time and converted into temperature. When the power semiconductor device reaches the target temperature Ta, the on time of the power semiconductor device is changed to ton2, and the on time of the power semiconductor device is controlled so that the temperature of the power semiconductor device becomes a constant value Ta.

[0025] The power semiconductor device 117 has an electrode terminal 226 formed or arranged on the flat surface portion of the back surface and a signal terminal 227 formed or arranged on the side surface. Alternatively, the electrode terminal 226 and the signal terminal 227 are formed or arranged on the flat surface portion of the back surface of the power semiconductor device 117. On the connection substrate 514, an electrode pattern 505 for connecting to the electrode terminal 226 and an electrode pattern 506 for connecting to the signal terminal 227 are formed. The power semiconductor device 117 is inserted into the sample hole 512 of the sample placement plate 511 and positioned with the electrode terminal 226 facing upward.

[0026] An anisotropic conductive rubber 504 is disposed between the signal terminal 227 and the connection substrate 514. When the connection substrate 514 is pressed, the signal terminal 227 and the electrode pattern 506 are electrically connected.

[0027] As described above, the anisotropic conductive rubber 504 is sandwiched between the electrode terminal 226 and the signal terminal 227 of the semiconductor device 117, and between the electrode pattern 506 and the signal terminal 227 of the connection substrate 514. The anisotropic conductive rubber 504 electrically connects the electrode pattern 506 and the signal terminal 227. A heat-resistant resist 523 is formed between the electrode pattern 505 and the electrode pattern 506. The electrode pattern is connected to the connection portion 507, and a test current is applied to the connection portion 507 to test the semiconductor device 117.

Advantages of the Invention

[0028] In the semiconductor device test apparatus and the semiconductor test method of the present invention, the device state can be displayed in real time, and the temperature of the semiconductor device can be accurately measured. Also, the test can be stopped before the complete destruction of the semiconductor device, the thermal resistance can be measured in real time, and the K factor can be automatically measured. In the semiconductor device test apparatus of the present invention, the signal terminal 227 and the electrode pattern 506 are electrically connected by the anisotropic conductive rubber 504 during pressing.

[0029] The power semiconductor device 117 to be tested can be removed by removing the anisotropic conductive rubber 504. Also, various tests can be performed by matching the shape of the power semiconductor device 117 to be tested with the wiring pattern of the connection substrate 514 and considering the wiring connection pattern.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0031] Hereinafter, with reference to the attached drawings, a power semiconductor test apparatus such as a power cycle test and a test method for a power semiconductor element according to an embodiment of the present invention will be described.

[0032] In the embodiments described in the specification, among power semiconductor elements, IGBT will be taken as an example for explanation. The present invention is not limited to IGBT, and can be applied to various power semiconductor elements such as SiC, MOSFET, JFET, and transistors.

[0033] The present invention is not only applicable to transistors, but the present invention can also be applied to two-terminal elements such as diodes. Further, it can also be applied to other power semiconductor elements such as thyristors and triacs. The present invention is not limited to power semiconductor devices. Needless to say, the present invention can also be applied to semiconductor devices for low power use and semiconductor devices for small signal control.

[0034] The present invention performs tests by applying current, voltage, etc. to elements or components. Therefore, the test object is not limited to power semiconductor devices. For example, it goes without saying that the present invention can also be applied to power resistive elements, thermistors, potistars, ZNRs, phototransistors, photodiodes, Schottky diodes, high-speed diodes, speakers, motors, mechanical relays, etc.

[0035] In each of the drawings for explaining the embodiments for carrying out the invention, elements having the same function are denoted by the same reference numerals, and the description may be omitted. Also, the embodiments described in this specification can be combined with each other.

[0036] FIG. 1 is an explanatory diagram and an equivalent circuit diagram of a semiconductor element 117 to be tested. FIG. 1(a) is an explanatory diagram schematically showing a state of a semiconductor element 117 to be tested as an example, viewed from the back side. FIG. 1(b) is an equivalent circuit diagram of the semiconductor element.

[0037] In FIG. 1(a), as the shape of the semiconductor element or the like, SOP (Small Outline Package) is exemplified. On the back surface of the SOP, electrode terminals 226a and electrode terminals 226b are formed. In the SOP, signal terminals 227 are formed or arranged on the back surface of the package (the surface on which the electrode terminals 226 are formed) and on the side surface portion.

[0038] A transistor is exemplified as the semiconductor element 117. The transistor 117 has a P terminal (collector terminal of the transistor 117) to which a large current is applied and an N terminal (emitter terminal of the transistor 117) to which a large current is applied.

[0039] A plating film 524 (not shown) is formed on the electrode terminal 226. Although the plating film 524 is described as a Ni-P film, a thin film may alternatively be formed of Ni or Ni-B. The plating film 524 (not shown) may be made of any material as long as it can be joined in good adhesion with the electrode pattern. In addition to nickel (Ni), for example, tin, silver, gold, copper, lead, zinc, or an alloy thereof, etc. are exemplified.

[0040] The film thickness of the plating film 524 (not shown) is preferably set to a film thickness of 1 μm or more and 20 μm or less. In particular, it is preferably set to a film thickness of 2 μm or more and 6 μm or less. It is preferable to form a gold plating film 525 (not shown) on the plating film 524.

[0041] The plating film 524 formed on the electrode terminal 226 is made thicker than the plating film 524 formed on the terminal 227. Or, a plating film 524 is formed on the electrode terminal 226, and no plating film 524 is formed on the terminal 227. Or, the plating film 524 formed on the signal terminal 227 is made thinner than the plating film 524 formed on the electrode terminal 226.

[0042] The film thickness obtained by adding the film thickness of the plating film 524 (not shown) and the gold plating film 525 (not shown) is preferably set to a film thickness of 1 μm or more and 10 μm or less. In particular, it is preferably set to a film thickness of 2 μm or more and 6 μm or less.

[0043] It is preferable to form a gold plating 525 (not shown) on the plating film 524. When the plating film 524 is not formed on the electrode terminal 226 or the signal terminal 227 portion, it is preferable to form the gold plating film 525 on the electrode terminal 226 or the signal terminal 227 portion.

[0044] The film thickness of the gold plating film 525 (not shown) is 0.01 μm or more. The gold plating film 525 (not shown) has a function of preventing or suppressing oxidation or contamination of the surface of the plating film 524.

[0045] Figure 2 is a cross-sectional view of the semiconductor element 117 in Figure 1. Figure 2(b) is a cross-sectional view taken along line AA' of Figure 2(a). Figure 2(c) is a cross-sectional view taken along line BB' of Figure 2(a). Electrode terminals 226 are arranged on the surface of the package of the semiconductor element 117, and signal line terminals are arranged on the side surface of the package of the semiconductor element 117.

[0046] Figure 3 is an explanatory diagram showing the connection state between the electrode terminal 226 of the semiconductor element 117 and the connection part 507, and the connection state between the signal terminal 227 and the connection pin 502 of the connector 202.

[0047] The electrode terminal 226a and the connection part 507a are electrically connected by a connection wiring 503. The electrode terminal 226b and the connection part 507b are electrically connected by a connection wiring 503. Eight connection pins 502 are arranged in the connector 202.

[0048] The connection pin 502a and the signal terminal 227d of the semiconductor element 117 are electrically connected by a signal wiring. The connection pin 502b and the signal terminal 227c of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502c and the signal terminal 227b of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502d and the signal terminal 227a of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502e and the signal terminal 227h of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502f and the signal terminal 227f of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502g and the signal terminal 227g of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502h and the signal terminal 227e of the semiconductor element 117 are electrically connected by a signal wiring 508.

[0049] Figure 4 is an explanatory diagram and an equivalent circuit diagram of the semiconductor element 117 for testing. Figure 4(a) is an explanatory diagram schematically showing the state of the semiconductor element 117 viewed from the back side. Figure 4(b) is an equivalent circuit diagram of the semiconductor element.

[0050] In FIG. 4(a), a QFN (Quad Flat No leaded package) is exemplified as the shape of a semiconductor element or the like. On the back surface of the QFN, electrode terminals 226a and 226b are formed. In the QFN, signal terminals 227 are formed or arranged on the back surface of the package (the surface on which the electrode terminals 226 are formed).

[0051] A transistor is exemplified as the semiconductor element 117. The transistor 117 has a P terminal (the collector terminal of the transistor 117) to which a large current is applied and an N terminal (the emitter terminal of the transistor 117) to which a large current is applied.

[0052] A plating film 524 (not shown) is formed on the electrode terminal 226. Although the plating film 524 is described as a Ni - P film, a thin film may be formed of Ni or Ni - B instead. The plating film 524 (not shown) may be any material as long as it can be joined to the electrode pattern with good adhesion. In addition to nickel (Ni), for example, tin, silver, gold, copper, lead, zinc, or alloys thereof are exemplified.

[0053] The film thickness of the plating film 524 (not shown) is preferably 1 μm or more and 20 μm or less. In particular, it is preferably 2 μm or more and 6 μm or less. It is preferable to form a gold plating film 525 (not shown) on the plating film 524.

[0054] The plating film 524 formed on the electrode terminal 226 is made thicker than the plating film 524 formed on the signal terminal 227. Or, a plating film 524 is formed on the electrode terminal 226, and no plating film 524 is formed on the signal terminal 227. Or, the plating film 524 formed on the signal terminal 227 is made thinner than the plating film 524 formed on the electrode terminal 226.

[0055] The sum of the film thickness of the plating film 524 (not shown) and the gold plating film 525 (not shown) is preferably 1 μm or more and 10 μm or less. In particular, it is preferably 2 μm or more and 6 μm or less.

[0056] In addition, in either the SOP or QFN package shape, it is also preferable to make the electrode terminal 226 part higher (thicker in thickness) than the signal terminal 227 part. It is exemplified that the electrode terminal 226 part is made 10 μm to about 0.5 mm higher than the signal terminal 227 part.

[0057] Similar to the case of the SOP in FIG. 1, it is preferable to form a gold plating 525 (not shown) on the plating film 524. When the plating film 524 is not formed on the electrode terminal 226 or the signal terminal 227 part, it is preferable to form the gold plating film 525 on the electrode terminal 226 or the signal terminal 227 part.

[0058] Also, similar to the SOP in FIG. 1, the film thickness of the gold plating film 525 (not shown) is set to 0.01 μm or more. The gold plating film 525 (not shown) has a function of preventing or suppressing oxidation or contamination of the surface of the plating film 524.

[0059] FIG. 5 is a cross-sectional view of the semiconductor element 117 in FIG. 4. FIG. 4(b) is a cross-sectional view taken along line AA' in FIG. 4(a). FIG. 4(c) is a cross-sectional view taken along line BB' in FIG. 4(a). Electrode terminals 226 are arranged on the surface of the package of the semiconductor element 117, and signal line terminals are arranged on the side surface of the package of the semiconductor element 117.

[0060] In the example of FIG. 4, as shown in FIG. 4(b), two transistors 117 (transistor 117m, transistor 117s) are arranged or formed in the QFN. As shown in FIG. 4(a), on the back surface of the QFN, the electrode terminal 226a of the P terminal of the transistor 117s, the electrode terminal 226a of the P terminal of the transistor 117s, the electrode terminal 226c of the O terminal of the transistor 117m, and the electrode terminal 226b of the N terminal of the transistor 117m are formed or arranged.

[0061] A collector terminal cm, a gate terminal gm, and an emitter terminal em are arranged for the transistor 117m. A collector terminal cs, a gate terminal gs, and an emitter terminal es are arranged for the transistor 117s.

[0062] In the example of FIG. 4, the semiconductor element (transistor) 117s has a diode Ds for temperature measurement formed therein. The diode Ds is formed in the same process as the transistor 117. The diode Ds is used to measure the temperature information Tj of the transistor 117s. The diode Ds is connected to an anode terminal as and a cathode terminal ks. The anode terminal as is the signal terminal 227a, and the cathode terminal km is the signal terminal 227b.

[0063] The semiconductor element (transistor) 117m has a diode Dm for temperature measurement formed therein. The diode Dm is formed in the same process as the transistor 117. The diode Dm is used to measure the temperature information Tj of the transistor 117m. The diode Dm is connected to an anode terminal am and a cathode terminal km. The anode terminal am is the signal terminal 227e, and the cathode terminal km is the signal terminal 227g.

[0064] The transistor 117m has a collector terminal cm, a gate terminal gm, and an emitter terminal em arranged thereon. A signal Vgs for turning the transistor 117 on and off is applied to the gate terminal gm. A constant current Icm is passed from the constant current circuit 118 to the diode Dm through the anode terminal am and the cathode terminal km.

[0065] The transistor 117s has a collector terminal cs, a gate terminal gs, and an emitter terminal es arranged thereon. The gate terminal gs is short-circuited to the emitter terminal es, and the semiconductor element is tested in a diode-connected state.

[0066] FIG. 5 is a cross-sectional view of the semiconductor element 117 in FIG. 4. FIG. 5(b) is a cross-sectional view taken along line AA' in FIG. 4(a). FIG. 5(c) is a cross-sectional view taken along line BB' in FIG. 4(a). An electrode terminal 226 is arranged on the surface of the package of the semiconductor element 117, and signal line terminals are arranged on the side surface of the package of the semiconductor element 117.

[0067] FIG. 6 is an explanatory diagram showing the connection state between the electrode terminal 226 of the semiconductor element 117 and the connection portion 507, and the connection state between the signal terminal 227 and the connection pin 502 of the connector 202.

[0068] The electrode terminal 226a and the connection portion 507a are electrically connected by a connection wiring 503. The electrode terminal 226b and the connection portion 507b are electrically connected by a connection wiring 503. The electrode terminal 226c and the connection portion 507c are electrically connected by a connection wiring 503.

[0069] Eight connection pins 502 are arranged in the connector 202, and the connection pin 502a and the signal terminal 227d of the semiconductor element 117 are electrically connected by a signal wiring. The connection pin 502b and the signal terminal 227c of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502c and the signal terminal 227b of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502d and the signal terminal 227a of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502e and the signal terminal 227h of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502f and the signal terminal 227f of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502g and the signal terminal 227g of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502h and the signal terminal 227e of the semiconductor element 117 are electrically connected by a signal wiring 508.

[0070] In the embodiments of the present invention, the shapes of semiconductor elements and the like are exemplified by SOP and QFN, but are not limited thereto. As long as it can be connected to the electrode terminal 226, the signal terminal 227, and the electrode patterns 505 and 506 of the connection substrate 514 using a connection portion on a substantially flat surface such as the anisotropic conductive rubber 504, any shape may be used. For example, it goes without saying that BGA (Ball Grid Array), COG (Chip On Glass), flip chip bonding IC, pin grid array, etc. may also be used.

[0071] Note that the anisotropic conductive rubber 504 may be replaced with an anisotropic conductive paste, an anisotropic conductive adhesive, a conductive paste, an anisotropic conductive film, or a conductive bonding material. Needless to say, the above matters also apply to other embodiments.

[0072] The P terminal is connected to the electrode terminal 226a. The N terminal is connected to the electrode terminal 226b. The electrode terminal 226 is formed in a planar shape on the back surface of the SOP and QFN. A nickel (Ni) plating film is formed on the surface of the electrode terminal 226 as required. The electrode terminal 226 is electrically connected to the electrode pattern 505 of the connection substrate 514 via the anisotropic conductive rubber 504.

[0073] In the example of FIG. 1, the semiconductor element (transistor) 117 has a diode Dm for temperature measurement formed therein. The diode Dm is formed in the same process as the transistor 117. The diode Dm is used to measure the temperature information Tj of the transistor 117.

[0074] The diode Dm is connected to an anode terminal am and a cathode terminal km. The anode terminal am is the signal terminal 227e, and the cathode terminal km is the signal terminal 227g.

[0075] Also, the collector terminal cm of the transistor 117 is connected to the signal terminal 227d, the emitter terminal em of the transistor 117 is connected to the signal terminal 227h, and the gate terminal gm of the transistor 117 is connected to the signal terminal 227f. The signal terminal 227 is formed or arranged on the side surface of the SOP. Also, the back surface of the SOP is configured to be electrically connectable to the electrode pattern 506 of the connection substrate 514.

[0076] In the example of FIG. 1, eight signal terminals 227 are arranged on the side surface of the SOP, and in the example of FIG. 4, eight signal terminals 227 are arranged on the back surface of the QFN. The signal terminals 227 are electrically connected to the electrode pattern 506 of the connection substrate 514 via the anisotropic conductive rubber 504. The signal terminals 227, the electrode terminals 226, the electrode pattern 505, and the electrode pattern 506 of the connection substrate 514 are simultaneously electrically connected by a single anisotropic conductive rubber 504. Alternatively, only the signal terminals 227 and the electrode pattern 506 are electrically connected via the anisotropic conductive rubber 504.

[0077] As an example of the anisotropic conductive rubber 504, a low load compression type in which gold-plated metal wires are arranged in a narrow pitch in silicone rubber is illustrated. The wire diameter of the metal wire is illustrated to be 0.02 mm or more and 0.04 mm or less. The thickness is illustrated to be 0.2 mm or more and 2 mm or less. The metal wire may be formed of gold or a gold alloy. The gold-plated metal wire is preferably a non-magnetic type. By making it a non-magnetic type, it becomes possible to test and evaluate the semiconductor element 117 to be tested for high frequency.

[0078] As an example of the configuration of the metal wires arranged on a sheet such as silicone rubber, a configuration in which the metal wires are arranged parallel in the thickness direction (perpendicular to the plane of the sheet) is illustrated. Among them, it is preferable that the metal wires are inclined by 10° (DEG.) to 35° (DEG.) with respect to an axis perpendicular to the plane of the metal wire sheet.

[0079] By inclining the metal wires with respect to the vertical axis, the flexibility of the sheet in the thickness direction becomes good. In addition, the metal wires are in a state of piercing obliquely into the electrode pattern 505 and the electrode terminal 226, and the electrode pattern 506 and the signal terminal 227, resulting in good electrical contact (electrical connection). High-precision contact performance can be realized with a low contact load. In addition, the maintenance cycle can be improved, and it can be used repeatedly for a long period of time.

[0080] In addition to silicone rubber, butyl rubber, ethylene propylene rubber, ethylene vinyl acetate copolymer material, epichlorohydrin rubber, acrylic rubber, etc. can also be used.

[0081] The anisotropic conductive rubber 504 is not limited to anisotropic conductive rubber. For example, it can be replaced with an anisotropic conductive film (ACF), an anisotropic conductive adhesive, etc. In this specification, for the sake of easy explanation, 504 will be described as anisotropic conductive rubber 504.

[0082] An anisotropic conductive film is a conductive film formed by molding into a film shape a mixture of fine metal particles in a thermosetting resin or a thermoplastic resin. In this semiconductor device, since it is preferable that the semiconductor element 117 to be tested can be detached, it is preferable to use an ACF of a thermoplastic resin.

[0083] The structure of the conductive particles is mainly a sphere with a diameter of 3 to 5 μm, having a nickel layer, a gold plating layer, and an insulating layer stacked from the inside to the outermost layer. An ACF is sandwiched between the electrode part and the electrode part of the component, and thermocompression bonding is performed with a heater or the like.

[0084] An anisotropic conductive adhesive can electrically connect and fix the opposing electrodes all at once. Also, it can be used for materials that cannot be joined by soldering or materials that cannot withstand the high temperature during soldering. The material of the anisotropic conductive adhesive is composed of an adhesive (binder) for fixing between the electrodes and conductive particles uniformly dispersed in this binder.

[0085] As a binder component, it must be a material that not only has adhesive force but also maintains insulation so as not to conduct with adjacent electrodes and has each reliability. If these basic characteristics are satisfied, any resin such as synthetic rubber, thermoplastic resin, and thermosetting resin can be used as a binder according to the specifications.

[0086] Examples of this conductive material include metals (nickel or a composite material with a gold coating on nickel), materials obtained by plating a metal on a core of plastic or resin, or materials having an insulating film that is broken by heat, pressure, etc. on them. In addition, a shape close to a spherical shape is selected, and for the particle size, a material with a particle size ranging from several μm to several tens of μm is selected according to each specification, particularly the distance between electrodes and the like.

[0087] For the transistor 117, a collector terminal cm, a gate terminal gm, and an emitter terminal em are arranged. A signal Vgs for turning the transistor 117 on and off is applied to the gate terminal gm. A constant current Icm is passed through the diode Dm from the constant current circuit 118 to the anode terminal am and the cathode terminal km.

[0088] FIG. 7 is an explanatory diagram and an equivalent circuit diagram of the semiconductor element 117 for conducting a test in another example. FIG. 7(a) is an explanatory diagram schematically showing the state of the semiconductor element 117 viewed from the back side. FIG. 7(b) is an equivalent circuit diagram of the semiconductor element. In FIG. 7, an SOP package is illustrated. A transistor is illustrated as the semiconductor element 117. Note that although the same applies to other examples, the semiconductor element 117 is not limited to a transistor.

[0089] For example, a variety of devices such as the semiconductor element in FIG. 55, a power resistor, a potistor, and a thermistor can be applied. Needless to say, those in which a plurality of elements such as a resistance element and a transistor are formed in one SOP or QFN can also be applied.

[0090] In FIG. 7(b), the transistor 117 has a P terminal (collector terminal of the transistor 117) to which a large current is applied and an N terminal (emitter terminal of the transistor 117) to which a large current is applied. A diode Dm is formed or arranged between the emitter terminal em and the collector terminal cm of the transistor Qm. The cathode terminal of the diode Dm is connected to the collector terminal cm of the transistor Qm, and the anode terminal of the diode Dm is connected to the emitter terminal em of the transistor Qm.

[0091] In FIG. 7(a), electrode terminals 226a and 226b are formed on the back surface of the SOP. The P terminal is connected to the electrode terminal 226a. The N terminal is connected to the electrode terminal 226b. The electrode terminals 226 are formed in a planar shape on the back surface of the SOP. A nickel (Ni) plating film is formed on the surface of the electrode terminals 226 as required. Also, gold plating is formed on the surface of the electrode terminals 226 for anti-oxidation. The electrode terminals 226 are electrically connected to the electrode pattern 505 of the connection substrate 514 via the anisotropic conductive rubber 504.

[0092] In the example of FIG. 7, the semiconductor element (transistor) 117 has a diode Dm for temperature measurement formed therein. The diode Dm is formed in the same process as the transistor 117. The diode Dm is used to measure the temperature information Tj of the transistor 117.

[0093] Note that the diode Dm may use the parasitic diode of the transistor. Needless to say, obtaining the temperature information Tj, etc. using the parasitic diode Dm can also be applied in other embodiments of the present invention.

[0094] The collector terminal cm of the transistor 117 is connected to the signal terminal 227d, and the emitter terminal em of the transistor 117 is connected to the signal terminal 227h. The gate terminal gm of the transistor 117 is connected to the signal terminal 227f. The signal terminals 227 are formed or arranged on the side surface of the QFN. Also, the signal terminals 227 are configured to be electrically connectable to the electrode pattern 506 of the connection substrate 514 on the back surface of the QFN.

[0095] Similar to other examples, in the example of FIG. 7, eight signal terminals 227 are arranged so as to be connectable to the electrode pattern 506 on the side surface and the back surface of the SOP. The signal terminals 227 are electrically connected to the electrode pattern 506 of the connection substrate 514 via the anisotropic conductive rubber 504. The signal terminals 227, the electrode terminals 226, the electrode pattern 505, and the electrode pattern 506 of the connection substrate 514 are electrically connected simultaneously with a single anisotropic conductive rubber 504 or the like.

[0096] Note that the signal terminal 227, the electrode terminal 226, and the electrode patterns 505 and 506 of the connection substrate 514 are not limited to being electrically connected simultaneously by a single anisotropic conductive rubber 504 or the like. Needless to say, the anisotropic conductive rubber 504 or the like connecting the signal terminal 227 and the electrode pattern 506 of the connection substrate 514 and the anisotropic conductive rubber 504 or the like connecting the electrode terminal 226 and the electrode pattern 505 of the connection substrate 514 may be separate anisotropic conductive rubbers 504. The above matters are the same in other embodiments of the present invention.

[0097] Collector terminal cm, gate terminal gm, and emitter terminal em are arranged on the transistor 117. A signal Vgs for turning the transistor 117 on and off is applied to the gate terminal gm. The emitter terminal em and the collector terminal cm are configured such that a constant current Icm can flow from an externally provided constant current circuit 118 to the diode Dm.

[0098] FIG. 8 is an explanatory diagram and an equivalent circuit diagram of the semiconductor element 117 for conducting a test in another example. The example of FIG. 8 is configured by arranging or forming two semiconductor elements 117 in FIG. 7(b) within one QFN. Needless to say, two or more semiconductor elements 117 may be arranged or formed within one package such as a QFN as described above. A plurality of semiconductor elements 117 are arranged within the QFN, and signal terminals 227 and electrode terminals 226 are formed or arranged on the QFN or the like according to the number of semiconductor elements 117. FIG. 8(a) is an explanatory diagram schematically showing the state of the semiconductor element 117 viewed from the back side. FIG. 8(b) is an equivalent circuit diagram of the semiconductor element.

[0099] In the example of FIG. 8, as shown in FIG. 8(b), two transistors 117 (transistor 117m, transistor 117s) described in FIG. 7(b) are arranged or formed within the QFN.

[0100] As shown in FIG. 8(a), on the back surface of the QFN, the electrode terminal 226a of the P terminal of the transistor 117s, the electrode terminal 226a of the P terminal of the transistor 117s, the electrode terminal 226c of the O terminal of the transistor 117m, and the electrode terminal 226b of the N terminal of the transistor 117m are formed or arranged.

[0101] The diode Ds is connected between the emitter terminal es and the collector terminal cs of the transistor 117s. The diode Dm is connected between the emitter terminal em and the collector terminal cm of the transistor 117m.

[0102] For the transistor 117m, a collector terminal cm, a gate terminal gm, and an emitter terminal em are arranged. For the transistor 117s, a collector terminal cs, a gate terminal gs, and an emitter terminal es are arranged.

[0103] In the example of FIG. 8, the semiconductor element (transistor) 117s has a diode Ds for temperature measurement formed therein. The semiconductor element (transistor) 117m has a diode Dm for temperature measurement formed therein.

[0104] The diodes Ds and Dm are formed in the same process as the transistor 117. The diode Ds is used to measure the temperature information Tj of the transistor 117s. The diode Dm is used to measure the temperature information Tj of the transistor 117m. The present invention acquires the temperature information Tj of the transistor 117 (transistor 117m or transistor 117s) using one of the diodes D (diode Dm or diode Ds) for testing the transistors 117s and 117m.

[0105] For the transistor 117m, a collector terminal cm, a gate terminal gm, and an emitter terminal em are arranged. A signal Vgs for turning the transistor 117 on and off is applied to the gate terminal gm. For the transistor 117s, a collector terminal cs, a gate terminal gs, and an emitter terminal es are arranged.

[0106] When testing transistor 117m, the gate terminal gs is short-circuited with the emitter terminal es, and transistor 117s is diode-connected to perform the test on transistor 117m. When testing transistor 117s, the gate terminal gm is short-circuited with the emitter terminal em, and transistor 117m is diode-connected to perform the test on transistor 117s. Needless to say, both transistors 117m and 117s can be put in the transistor operating state and both transistors (transistor 117m, transistor 117s) can be tested simultaneously. The above matters are the same in other embodiments of the present invention. FIG. 9 is a plan view and an explanatory view of a sample placement plate 511 in the semiconductor test apparatus of the present invention.

[0107] A semiconductor element 117 or the like to be tested is arranged in a sample hole 512 of the sample placement plate 511. In this specification, as the semiconductor element 117, mainly an SOP-shaped package and a QFN-shaped package are exemplified and described.

[0108] The thickness of the sample placement plate 511 is a plate thickness thinner than the thickness of the semiconductor element 117 to be tested. The sample placement plate is made of an insulating material.

[0109] In FIG. 9, fixing holes 510 are formed at four corners of the sample placement plate 511. The fixing holes 510 are through holes. Two positioning holes 509 are formed in the sample placement plate 511. The positioning holes 509 are through holes.

[0110] FIG. 10 is a plan view and an explanatory view of a connection substrate 514. As shown in FIG. 10(a), fixing holes 510 are formed at four corners of the connection substrate 514. The fixing holes 510 are through holes. Two positioning holes 509 are formed in the sample placement plate 511. The positioning holes 509 are through holes.

[0111] Examples of the material of the heat-resistant substrate of the connection substrate 514 include a glass epoxy material, a ceramic material, a phenolic resin material, an insulated aluminum material, a polyimide film, and a PET material.

[0112] On the connection substrate 514, an electrode pattern 505 corresponding to the electrode terminal 226 of the semiconductor element 117 to be tested and an electrode pattern 506 corresponding to the signal terminal 227 of the semiconductor element 117 are formed. A connector 202 is mounted on the connection substrate 514, and a control signal is applied to the terminal of the semiconductor element 117 via the connection pin 502 of the connector 202.

[0113] On the connection substrate 514, a connection portion 507 is formed or arranged. The basic material of the connection portion 507 is thick copper, and the surface is nickel (Ni) plated. In addition to copper for the connection portion 507, silver, copper alloy, silver alloy, and gold alloy can also be used.

[0114] FIG. 10(b) is a cross-sectional view of the connection substrate 514 taken along the line CC' in FIG. 10(a). On the heat-resistant substrate 526, an electrode pattern 505, an electrode pattern 506, a signal wiring 508 (not shown), and a connection wiring 503 (not shown) are formed. Further, a heat-resistant resist 523 is formed between the electrode pattern 505 and the electrode pattern 506. A two-component alkaline developable solder resist is exemplified, for example, the heat-resistant and heat-dissipating resist HRS-2-6 series of Yamashita Materials Co., Ltd. Examples of the material of the electrode pattern 505 and the electrode pattern 506 include copper. A plating film 524 is formed on the surfaces of the electrode pattern 505 and the electrode pattern 506. The plating film 524 is exemplified by a thin film (Ni-P film) by Ni-P plating, and a gold plating film 525 is formed on the surface of the Ni-P film.

[0115] The plating film 524 is described as a Ni-P film, but alternatively, a thin film may be formed of Ni or Ni-B. The plating film 524 may be made of any material as long as it can be joined in good adhesion with the electrode pattern. In addition to nickel (Ni), for example, tin, silver, gold, copper, lead, zinc, or alloys thereof are exemplified. The film thickness of the plating film 524 is preferably 1 μm or more and 10 μm or less. In particular, the film thickness is preferably 2 μm or more and 6 μm or less. The film thickness of the gold plating film 525 is 0.01 μm or more. The gold plating film 525 has a function of preventing or suppressing oxidation or contamination of the surface of the plating film 524.

[0116] The sum of the film thickness of the plating film 524 and the film thickness of the gold plating film 525 is preferably 1 μm or more and 10 μm or less. In particular, the film thickness is preferably 2 μm or more and 6 μm or less.

[0117] Also, from the plane of the heat-resistant resist 523, the sum of the film thickness of the plating film 524 and the film thickness of the gold plating film 525 is preferably formed as a convex portion with a film thickness of 1 μm or more and 10 μm or less. In particular, it is preferably formed as a convex portion with a film thickness of 2 μm or more and 6 μm or less.

[0118] By forming the plating film 524 or the like on the electrode pattern 505 and the electrode pattern 506, a convex structure is formed in which the electrode patterns 505 etc. protrude more than the heat-resistant resist 523 film. Therefore, the anisotropic conductive rubber 504 is deformed by the convex electrode patterns 505 etc. Due to the deformation of the anisotropic conductive rubber 504, the electrode terminal 226 and the electrode pattern 505, and the signal terminal 227 and the electrode pattern 506 are favorably electrically connected.

[0119] A relatively large current of several hundred amperes (A) or more flows through the electrode pattern 505, so the electrode area is formed large. The electrode pattern 506 is often used as a terminal to which the control signal of the transistor 117 is applied. Therefore, since a large current rarely flows, the electrode pattern 506 has a relatively small area.

[0120] A plurality of electrode patterns 506 can be made common (electrically connected) to apply a large current. In this case, a plurality of signal terminals 227 for applying the same signal are formed or arranged.

[0121] In FIG. 10(b), plating 524 having the same film thickness is formed or arranged on the electrode pattern 505 and on the electrode pattern 506. Also, a gold plating film 525 is formed on the plating film 524.

[0122] In FIG. 10(c), plating 524 having a film thickness thicker than that on the electrode pattern 506 is formed or arranged on the electrode pattern 505. That is, a plating film 524b is formed with a thicker plating film 524 than the plating film 524a. Also, a gold plating film 525 having the same film thickness is formed on the plating film 524.

[0123] In the embodiment of FIG. 10(c), the anisotropic conductive rubber 504 is sandwiched between the signal terminal 227 and the electrode pattern 506 and electrically connected. The electrode terminal 226 and the electrode pattern 505 are directly brought into close contact and electrically connected.

[0124] FIG. 10 is an embodiment in which the film thickness of the plating film 524 is made different and the electrode pattern 505 portion is configured as a convex portion rather than the electrode pattern 506 portion. Needless to say, in addition to making the film thickness of the plating film 525 different, the thicknesses of the electrode pattern 505 and the electrode pattern 506 may be changed to configure or form the electrode pattern 505 as a convex portion rather than the electrode pattern 506. FIG. 10 is an embodiment in which the thickness of the connection substrate 514 is uniform (flat, planar). FIG. 57 is an embodiment in which the thickness of the connection substrate 514 is made different. FIG. 57(b) is a cross-sectional view taken along the line CC' of FIG. 57(a). In FIG. 57, an arrangement recess 239 is formed in the connection substrate 514.

[0125] The placement recess 239 is formed, for example, by scraping off the heat-resistant resist 523 of the connection substrate 514. Alternatively, when forming the heat-resistant resist 523, the placement recess 239 is formed using a molding die.

[0126] The electrode pattern 506 is formed in the placement recess 239. Also, as shown in FIG. 57(b), the thickness of the electrode pattern 506 is formed thinner than the thickness of the electrode pattern 505.

[0127] A plating film 524 is formed on the electrode pattern 505 and the electrode pattern 506, and a gold plating 525 is formed on the plating film 524. In FIG. 57(b), the plating film 525b and the plating film 525a are shown to have the same film thickness, but as shown in FIG. 10, it goes without saying that the film thickness of the plating film 525b and the film thickness of the plating film 525a may be made different. Other points are the same as or similar to those of other embodiments of the present invention, so the description is omitted.

[0128] FIG. 57(c) is an explanatory diagram showing a state in which a semiconductor element 117 such as SOP117 or QFN117 is attached to the electrode pattern 505 and the electrode pattern 506 in FIGS. 57(a) and 57(b).

[0129] Anisotropic conductive rubber 504a is inserted or placed in the placement recess 239. The anisotropic conductive rubber 504a is sandwiched between the signal terminal 227 and the electrode pattern 506. The electrode terminal 226 and the electrode pattern 505 are directly electrically connected.

[0130] As described with reference to FIG. 11, the anisotropic conductive rubber 504a is pressed, and the signal terminal 227 and the electrode pattern 506 are electrically connected by the conductive wire 230. In FIG. 13, the placement recess 239 is formed in the peripheral portion of the anisotropic conductive rubber 504a.

[0131] In the embodiment of FIG. 57, since the placement recess 239 is formed, even if there is thickness in the anisotropic conductive rubber 504a, it is stored in the placement recess 239 within the anisotropic conductive rubber 504a, and the electrode pattern 505 and the electrode terminal 226 are in close contact, and good electrical connection can be realized due to the close contact.

[0132] FIG. 11(a) is an explanatory diagram when the electrode terminal 226 and the electrode pattern 505 of SOP and QFN, and the signal terminal 227 and the electrode pattern 506 of SOP and QFN are aligned through the anisotropic conductive rubber 504.

[0133] In the embodiment of FIG. 11, with one anisotropic conductive rubber 504, the electrode terminal 226 and the electrode pattern 505, and the signal terminal 226 and the electrode pattern 506 can be electrically connected simultaneously.

[0134] Note that it may be configured such that the electrode terminal 226 and the electrode pattern 505 are electrically connected by the first anisotropic conductive rubber 504, and the signal terminal 226 and the electrode pattern 506 are electrically connected by the second anisotropic conductive rubber 504.

[0135] The formation area of the electrode pattern 505a is formed wider than the formation area of the electrode terminal 226a. The formation area of the electrode pattern 505b is formed wider than the formation area of the electrode terminal 226b. The formation area of the electrode pattern 505c is formed wider than the formation area of the electrode terminal 226c.

[0136] As described above, by making the electrode area of the electrode pattern 505 larger than the formation area of the electrode terminal 226, alignment becomes easier, and connection with the anisotropic conductive rubber 504 also becomes easier.

[0137] The formation area of the electrode pattern 506a is formed wider than the formation area of the signal terminal 227a. The formation area of the electrode pattern 506b is formed wider than the formation area of the signal terminal 227b. The formation area of the electrode pattern 506c is formed wider than the formation area of the signal terminal 227c. The formation area of the electrode pattern 506d is formed wider than the formation area of the signal terminal 227d. The formation area of the electrode pattern 506e is formed wider than the formation area of the signal terminal 227e. The formation area of the electrode pattern 506f is formed wider than the formation area of the signal terminal 227f. The formation area of the electrode pattern 506g is formed wider than the formation area of the signal terminal 227g. The formation area of the electrode pattern 506h is formed wider than the formation area of the signal terminal 227h.

[0138] As described above, by making the electrode area of the electrode pattern 506 larger than the formation area of the signal terminal 227, alignment becomes easy and connection with the anisotropic conductive rubber 504 also becomes easy.

[0139] SOP and QFN as the semiconductor element 117 to be tested are arranged in the sample holes 512 in the sample placement plate 511 with the electrode terminals 226 and the signal terminals 227 facing upward. The anisotropic conductive rubber 504 is arranged on the electrode terminals 226 and the signal terminals 227. The connection substrate 514 is arranged on the anisotropic conductive rubber 504.

[0140] It is preferable to use the anisotropic conductive rubber 504 having a Shore hardness of 30 or more and 100 or less. If the Shore hardness is less than 30, it will be deformed by pressing, and if the Shore hardness is greater than 100, the deformation by pressing will be small and the electrical connection will deteriorate.

[0141] The connection substrate 514 and the sample placement plate 511 are positioned by the positioning posts 518 inserted into the positioning holes 509, whereby the electrode terminals 226 and the electrode pattern 505, and the signal terminals 227 and the electrode pattern 506 are aligned.

[0142] By pressing downward from the side of the connection substrate 514, the anisotropic conductive rubber 504 is deformed, and through the anisotropic conductive rubber 504, the electrode terminal 226 and the electrode pattern 505, and the signal terminal 227 and the electrode pattern 506 are electrically connected. FIGS. 11(b) and 11(c) schematically illustrate the direction of the conductive wire 230.

[0143] In the anisotropic conductive rubber 504, gold-plated metal wires are arranged as the conductive wires 230 at a narrow pitch in silicone rubber. The wire diameter of the metal wire is 0.02 mm or more and 0.04 mm or less, and the thickness of the silicone rubber is 0.2 mm or more and 2 mm or less. The silicone rubber has a thickness of 10 μm or less under pressure.

[0144] The arrangement pitch of the conductive wires 230 is exemplified as 0.05 mm or more and 0.4 mm or less. The metal wires arranged on a sheet such as silicone rubber are preferably arranged such that the metal wires are inclined by 10° (DEG.) to 35° (DEG.) with respect to an axis perpendicular to the plane of the metal wire sheet.

[0145] FIG. 11(b) schematically illustrates a state in which the conductive wires 230 are arranged in the vertical direction with respect to the paper surface. FIG. 11(c) is an explanatory diagram schematically illustrating the arrangement direction of the conductive wires 230 in the cross section of the anisotropic conductive rubber 504.

[0146] By inclining the metal wire with respect to the vertical axis, the flexibility of the sheet in the thickness direction is improved. The gold-plated metal wire is preferably a non-magnetic type. By using a non-magnetic type, the semiconductor element 117 to be tested can be tested and evaluated for high-frequency compatibility.

[0147] As shown in FIG. 11(b), the signal terminal 227 has a rectangular shape, and the anisotropic conductive rubber 504 is arranged such that the longitudinal direction of the conductive wire 230 substantially coincides with the longitudinal direction of the rectangular shape.

[0148] The conductive wires 230 within the anisotropic conductive rubber 504 can penetrate into the electrode pattern 506 and the signal terminal 227, and the electrode pattern 505 and the electrode terminal 226 under pressure, enabling a good electrical connection to be achieved.

[0149] FIG. 12 is a plan view and an explanatory diagram of a connection substrate 514 when there are three electrode terminals 226 (electrode terminal 226a, electrode terminal 226b, electrode terminal 226c) as shown in FIG. 5. Three connection parts 507 (connection part 507a, connection part 507b, connection part 507c) are also formed or arranged. Since other configurations, structures, etc. are the same as or similar to the content described in FIG. 10, the description thereof is omitted.

[0150] FIG. 13(a) is an explanatory diagram when the electrode terminal 226 and the electrode pattern 505 of the SOP·QFN and the signal terminal 227 and the electrode pattern 506 of the SOP·QFN, where there are three electrode terminals 226 (electrode terminal 226a, electrode terminal 226b, electrode terminal 226c) as shown in FIG. 5 etc., are aligned through the anisotropic conductive rubber 504. FIG. 13(b) schematically shows a state in which the conductive wires 230 are arranged in the vertical direction with respect to the plane of the paper. As shown in FIG. 13(b), the anisotropic conductive rubber 504a is arranged at the signal terminal 227 portion. The anisotropic conductive rubber 504 is not arranged on the electrode pattern 505. The anisotropic conductive rubber 504 has a rectangular shape, and one anisotropic conductive rubber 504 covers (overlaps) a plurality of signal terminals 227. The conductive wires 230 within the anisotropic conductive rubber 504 are arranged in the longitudinal direction of the rectangular shape of the anisotropic conductive rubber 504.

[0151] The anisotropic conductive rubber 504 shown in FIG. 13(b) expands and contracts under pressure or the like. Since it has a rectangular shape, it is particularly easy to expand and contract in the longitudinal direction. Therefore, the conductive wires 230 are likely to move in the longitudinal direction (orientation direction) of the conductive wires 230. Due to the movement of the conductive wires 230, the signal terminal 227 and the electrode pattern 506 can achieve a good electrical connection.

[0152] As described above, when the anisotropic conductive rubber 504 has a rectangular shape, as shown in FIG. 13(b), the conductive wire 230 is arranged, oriented, or formed in the longitudinal direction of the anisotropic conductive rubber 504. Further, when the signal terminal 227 and the electrode pattern 506 have a rectangular shape, the conductive wire 230 is arranged, oriented, or formed in the longitudinal direction of the signal terminal 227 and the electrode pattern 506.

[0153] Although it has been described that the conductive wire 230 is arranged, oriented, or formed in the longitudinal direction of the signal terminal 227 and the electrode pattern 506, the direction of formation of the conductive wire 230 or the like may be within ±45° (DEG.) with respect to the longitudinal direction. Preferably, the direction of formation of the conductive wire 230 or the like is preferably within ±20° (DEG.) with respect to the longitudinal direction.

[0154] Since other configurations, structures, etc. are the same as or similar to those described in FIG. 11, the description thereof is omitted. Needless to say, the above matters are also applicable to other embodiments of this specification, such as the embodiment of FIG. 57.

[0155] FIG. 14 is a plan view and an explanatory view of the pressing plate 515. It has a structure or configuration with good flatness and capable of insulating at least the conductive portion of the connection substrate. Examples of the material of the pressing plate include copper, stainless steel, aluminum, and brass. Further, ceramics and phenolic resin are exemplified.

[0156] The pressing plate 515 is disposed on the connection substrate 514. By pressing from above the pressing plate 515, the connection substrate 514 is uniformly pressed. By the pressing, the anisotropic conductive rubber 504 disposed in close contact with the electrode pattern 505 and the electrode pattern 506 of the connection substrate 514 is pressed. The electrode pattern 505 and the electrode terminal 226 are electrically connected by the anisotropic conductive rubber 504. Further, the electrode pattern 506 and the signal terminal 227 are electrically connected.

[0157] Fixing holes 510 are formed at the four corners of the pressing plate 515. The fixing holes 510 are through holes. Two positioning holes 509 are formed in the pressing plate 515. The positioning holes 509 are through holes. FIG. 15 is an explanatory diagram of a connection state in which the SOP117 or QFN117 and the connection substrate 514 are connected by the anisotropic conductive rubber 504.

[0158] As shown in FIG. 15, it is arranged on the positioning support plate 519. The positioning support plate 519 is formed of a material with good thermal conductivity. Examples of the material of the positioning support plate 519 include copper, stainless steel, aluminum, brass, and ceramics. Note that the surface plate 520 shown in FIG. 16 and the like is also formed of a material with good thermal conductivity, similar to the positioning support plate 519. This is to better transfer the heat of the heating and cooling plate 134.

[0159] The SOP117 or QFN117 is adhered to the positioning support plate 519. Also, if necessary, a grease with good thermal conductivity is applied between the SOP117 or QFN117 and the positioning support plate 519.

[0160] The SOP117 or QFN117 is fitted and arranged in the sample hole 512 of the sample placement plate 511. Also, if necessary, a variable mechanism is configured and added to vary the size of the sample hole 512 according to the size of the SOP117 or QFN117 so that various SOP117s or QFN117s can be clamped and fixed.

[0161] The anisotropic conductive rubber 504 is arranged on the electrode terminals 226 and signal terminals 227 of the SOP117 or QFN117. The anisotropic conductive rubber 504 generates electrical conduction in the vertical direction under pressure.

[0162] On the anisotropic conductive rubber 504, the electrode patterns 505 and 506 of the connection substrate 514 are positioned. A heat-resistant resist 523 is formed or arranged between the electrode terminals 226 and the signal terminals 227 and the like.

[0163] On the electrode patterns 505 and 506, a plating film 524b is formed, and it is convex by about several μm from the surface of the heat-resistant resist 523. When the electrode pattern 505 itself is convex from a flat part such as the heat-resistant resist 523, it is not necessary to make it convex with the plating film 524 or the like. It is preferable to make it convex with the plating film 524a also on the signal terminal 227 and the electrode terminal 226 of SOP117 or QFN117.

[0164] As shown by the dotted line in FIG. 15, the anisotropic conductive rubber 504 is pressed more strongly by the plating film 524, so that the electrode pattern 505 of the connection substrate 514 and the electrode terminal 226, and the electrode pattern 506 and the signal terminal 227 are electrically connected.

[0165] In the embodiment of FIG. 15, the electrode terminal 226 and the signal terminal 227 are electrically connected to the electrode pattern 505 or the electrode pattern 506 using a common (single) anisotropic conductive rubber 504.

[0166] However, the present invention is not limited to this, and the electrode pattern 505 and the electrode terminal 226 may be electrically connected by the first anisotropic conductive rubber 504, and the electrode pattern 506 and the signal terminal 227 may be electrically connected by the second anisotropic conductive rubber 504. Even in the above cases, the matters described in FIGS. 11 and 13 are implemented. FIG. 56 is an explanatory diagram of a state in which the semiconductor element 117 is connected to the connection substrate 514. Basically, the state of FIG. 15 is applicable. In FIG. 56, an anisotropic conductive rubber 504a is disposed between the electrode pattern 506 of the connection substrate 514 and the signal terminal 227.

[0167] A plating film 524 is formed on the electrode patterns 505 and 506, and a gold plating 525 is formed on the plating film 524. In FIG. 56, the plating film 524 on the electrode pattern 505 is formed thicker than the plating film 524a on the electrode pattern 506.

[0168] In FIG. 56, since the plating film 524b is thickly formed, even if the anisotropic conductive rubber 504 has a certain thickness, the electrode pattern 505 and the electrode terminal 226 are in close contact with each other by pressing, and a good electrical connection is achieved.

[0169] The anisotropic conductive rubber 504 is sandwiched between the signal terminal 227 and the electrode pattern 506. The electrode terminal 226 and the electrode pattern 505 are directly electrically connected. As described with reference to FIG. 13, the anisotropic conductive rubber 504 electrically connects the signal terminal 227 and the electrode pattern 506 by the conductive wire 230 under pressure.

[0170] In the embodiment of FIG. 56, even if the anisotropic conductive rubber 504 has a thickness, the electrode pattern 505 and the electrode terminal 226 are in close contact with each other, and a good electrical connection can be achieved by the close contact. It goes without saying that the configuration or structure of the arrangement recess 239 in FIG. 57 can also be applied to FIG. 56.

[0171] FIGS. 16 and 17 are explanatory views for explaining the mounting portion of the semiconductor element 117 to be tested by the semiconductor test apparatus of the present invention. FIG. 16(a) is an explanatory view schematically showing the mounting portion when viewed from above. FIG. 16(b) is a cross-sectional view taken along the line AA' of FIG. 16(a).

[0172] In FIG. 17, the plating film 524 is thickly formed on the electrode pattern 505. The anisotropic conductive rubber 504a is disposed between the signal terminal 227 and the electrode pattern 506. The electrode pattern 505 and the electrode terminal 226 are in close contact with each other, and an electrical connection is made by pressing.

[0173] Two struts 518 (strut 518a and strut 518b) are attached to the positioning strut plate 519. The strut 518a is inserted into the positioning holes 509a of the sample placement plate 511, the positioning holes 509a of the connection substrate 514, and the positioning holes 509a of the pressing plate 515. The strut 518b is inserted into the positioning holes 509b of the sample placement plate 511, the positioning holes 509b of the connection substrate 514, and the positioning holes 509b of the pressing plate 515.

[0174] The SOP117 and QFN117 are inserted into the sample holes 512. By inserting the support column 518 into the positioning hole, the electrode pattern of the connection substrate 514 and the electrode terminals 226 and signal terminals 227 of the QFN are positioned. It is pressed in the B direction from the side of the pressing plate 515. FIG. 18 is an explanatory diagram for explaining a method of attaching a test semiconductor element 117 to the semiconductor test apparatus of the present invention. As shown in FIG. 18(a), the sample placement plate 511 is formed with sample holes 512, positioning holes 509, and fixing holes 510.

[0175] As shown in FIG. 18(b), the semiconductor element 117 is arranged in the sample hole 512 of the sample placement plate 511. The semiconductor element 117 of QFN or SOP is arranged with the electrode terminal 226 facing upward. Anisotropic conductive rubber 504 is arranged on the electrode terminal 226.

[0176] As shown in FIG. 18(c), the connection substrate 514 is arranged on the anisotropic conductive rubber 504. It is arranged so that a current power supply device can be connected to the connection portion 507 of the connection substrate 514.

[0177] Next, as shown in FIG. 18(d), the pressing plate 515 is arranged on the connection substrate 514. The sample placement plate 511, the connection substrate 514, and the pressing plate 515 are positioned by the positioning support column 518 inserted into the positioning hole 509.

[0178] Next, as shown in FIG. 18(e), a fixing support column (not shown) or the like is inserted into the fixing hole 510, and a pressing tool 516 is attached to the fixing support column to press the anisotropic conductive rubber 504.

[0179] FIG. 9 and the like show the case where there is one sample hole 512 in the sample placement plate 511, but the present invention is not limited to this. FIG. 19 is an example in the case where two semiconductor elements 117 are connected and tested in the connected state. In the example of FIG. 9(b), two semiconductor elements 117 of FIG. 1 are connected. The electrode terminal 226b of the semiconductor element 117s and the electrode terminal 226a of the semiconductor element 117m are connected by a connection wiring 503. The connection wiring 503 is formed on a connection substrate 514. Since other configurations and the like are described in other examples in the specification, the description is omitted.

[0180] In the case of the example of FIG. 19, as shown in the sample placement plate 511 of FIG. 20, a sample hole 512a for the semiconductor element 117s and a sample hole 512b for the semiconductor element 117m are formed in the sample placement plate 511. The present invention can test a plurality of semiconductor elements 117 by appropriately setting the number of sample holes 512 formed in the sample placement plate 511.

[0181] FIG. 27 is a configuration diagram of a power cycle test apparatus (semiconductor test apparatus) of the present invention. The power cycle test apparatus includes a chiller (cooling / warming device) 136, a heating / cooling plate 134, and a circulating water pipe 135 that circulates between the heating / cooling plate 134 and the chiller 136. A transistor 117 as a semiconductor element to be tested is mounted on the heating / cooling plate 134. Actually, in order to correspond to various shapes of semiconductor elements 117, a surface plate 520 is attached on the heating / cooling plate 134, a positioning support plate 519 is attached on the surface plate 520, and the semiconductor element 117 is arranged on the positioning support plate 519.

[0182] The device fixing / connecting device 610 includes a heating / cooling plate 134 and a circulating water pipe 135 that circulates between the heating / cooling plate 134 and the chiller 136. Further, a transistor 117 as a semiconductor element to be tested is mounted on the heating / cooling plate 134, and a sample connection circuit 203 (not shown) is configured or arranged. The heat from the heating and cooling plate 134 is transmitted to the semiconductor element 117 via the surface plate 520 and the positioning support plate 519.

[0183] The heat from the heating and cooling plate 134 sets the test conditions by changing the current Id, the gate voltage Vgs, and the voltage Vce so that the temperature information Tj of the transistor 117 to be tested reaches a predetermined value.

[0184] When the temperature information Tj changes, it is determined that the transistor 117 is deteriorating or its characteristics are changing, and the test of the transistor 117 is stopped or the control method is changed.

[0185] Although the current flowing through or applied to the transistor 117 is described as a constant current Id, the present invention is not limited thereto. Needless to say, Id may be a current that changes at a predetermined period or a predetermined time or the like. Further, the present invention is not limited to current, and voltage may also be used.

[0186] The change in the temperature information Tj determines or determines the characteristic change of the transistor 117. Further, the characteristic change, reliability, and life of the transistor 117 are evaluated from the time when the voltage Vce reaches a predetermined voltage, the time until the transistor 117 is destroyed, and the like.

[0187] In the semiconductor test method of the present invention, the external conditions are changed according to the deterioration or characteristic change of the transistor 117. For example, when the transistor 117 generates heat, the water temperature is lowered. When the water temperature is lowered and the current flowing through the transistor 117 is decreased, the deterioration and characteristic change of the transistor 117 do not progress, and as a result, the life of the transistor 117 is extended. Therefore, the life, reliability characteristics of the transistor 117 with respect to the predetermined set conditions can be quantitatively measured and judged.

[0188] By heating or cooling the circulating water of the chiller 136, the temperature of the transistor 117 is maintained at a specified value or a predetermined value. Also, the temperature of the transistor or the like is periodically changed in accordance with the test conditions, and is also cooled constantly and heated. Further, the temperature information Tj of the test transistor is measured, and the chiller 136 is controlled so as to maintain the measured temperature information Tj at a constant value.

[0189] The chiller is configured to be able to keep the temperature of equipment or the like constant by circulating while controlling the liquid temperature of water or a heat medium. It is mainly used for cooling in many cases, but it can not only cool but also warm. It is configured to be able to perform various temperature controls.

[0190] The control rack 131 has a power supply device 132 that supplies a test current and a test voltage to the transistor 117, and a control circuit 133 that controls the transistor 117 or sets test conditions.

[0191] The temperature information Tj of the transistor 117 is input to the control circuit 133, and the chiller 136 is controlled based on the temperature information Tj. Alternatively, the chiller 136 is controlled so that the temperature information Tj becomes a predetermined value.

[0192] In this specification, it is described as circulating water, but it is not limited to water. Ethylene glycol, glycerin, freon, etc. may be used, or forced air cooling may be used. The chiller 136 controls the liquid in the circulating water pipe 135 in the range of, for example, minus 1 ° C to plus 100 ° C of the water temperature and supplies it to the heating and cooling plate 134 of the test unit. The heating and cooling plate 134 has a sufficiently large heat capacity.

[0193] In the above embodiment, the heating and cooling plate 134 is used, but the heating plate and the cooling plate may be separate bodies, and heating and cooling may be performed using heat sources and cold heat sources other than the heating and cooling plate.

[0194] FIG. 68 shows a voltage-current application jig (device) for a double-sided cooling sample (power semiconductor device). By adopting a double-sided cooling structure for the semiconductor device, it becomes possible to apply a large current.

[0195] In FIGS. 38 and 43, the heat pipe 223 is illustrated as being disposed on the back surface of the connection structure 218. The present invention is not limited thereto. As illustrated in FIGS. 68 and 69, the heat pipe 223 may be disposed on the side surface of the connection structure 218, and the side surface of the connection structure 218 may be pressed and fixed from above with a pressing member 608. The voltage-current application jig (device) can suppress heat generation at the contacts and wiring and reproduce test conditions according to the purpose.

[0196] In FIG. 68, the test current and control signal are supplied from the device fixing / connecting device 610. The test current is applied to the connection structure 218. A terminal connection portion 609 for connecting to the connection terminal of the power semiconductor device is disposed at one end of the connection structure 218. The heat pipe 223 is disposed on the connection structure 218. A cooling fan 229 is disposed at the lower or upper part of the connection structure 218. The air flow generated by the cooling fan 229 passes between the connection structure 218, the heat pipe 223, and the pressing member 608, suppressing the temperature rise of the connection portion with the device 117, the contacts, the connection structure 218, etc. Inside the device fixing / connecting device 610, there is the connection structure 218

[0197] As illustrated in FIGS. 27, 28, and 29, inside the device fixing / connecting device 610, there are arranged a heating / cooling plate 134, a device for fixing or holding the semiconductor element 117 having the semiconductor element 117 to be tested, a pressing head 530, etc., and a sample connection circuit 203. The cover of the device fixing / connecting device 610 is composed of a structure capable of electrostatic shielding and electromagnetic shielding, and the cover is grounded.

[0198] A heat pipe 223 is adhered to the connection structure 218. A thermally conductive grease or a heat dissipation silicone oil compound may be applied between the surface of the connection structure 218 and the heat pipe 223.

[0199] Although the material of the connection structure 218 is described as copper, it is not limited to copper. Examples of the material of the connection structure 218 include copper (linear expansion coefficient 16.8), brass (linear expansion coefficient 19), iron (linear expansion coefficient 12.1), and stainless steel (SUS304) (linear expansion coefficient 17.3).

[0200] Examples of the material of the heat pipe 223 having a large linear expansion coefficient include aluminum (linear expansion coefficient 23), tin (linear expansion coefficient 26.9), and lead (linear expansion coefficient 29.1). Among them, it is preferable to adopt copper (linear expansion coefficient 16.8) as the material of the connection structure 218 and aluminum (linear expansion coefficient 23) as the material of the heat pipe. Alternatively, an alloy obtained by mixing a second metal such as molybdenum with aluminum may be adopted.

[0201] FIG. 69 is a perspective view of FIG. 68 seen from the opposite direction of the side surface. A circulating water pipe 135 for supplying or discharging circulating water is attached inside the device fixing / connecting device 610. The cooling fan 229 may be arranged on the upper part of the connection structure 218, or may be arranged on the side surface. Alternatively, it may be arranged at two or more positions such as up, down, left, and right.

[0202] A pressing member 608 is attached to the support column 534 to fix and hold the connection structure 218. Further, the pressing member 608 can be moved up and down the support column 534, and the pressing member 608 can be held at a predetermined pressure.

[0203] FIGS. 70, 71, and 72 are devices used for a high heat dissipation general-purpose (such as a TO package) used in the semiconductor element test device of the present invention. In the case of a TO-247 package, it is used as a power semiconductor element. A current application circuit and an on-off pulse driver circuit applied to the gate terminal of the transistor are mounted or formed on the connection substrate 514.

[0204] The connection substrate 514 can be custom-designed according to the semiconductor device to be tested, and can accommodate various device shapes. For example, it can correspond to the chip shape or structure of various semiconductor elements 117 described in FIGS. 2, 5, 7, 58, etc.

[0205] In FIG. 72, a heating and cooling plate 134b is disposed under the positioning support plate 519a. A power semiconductor device 117 to be tested is disposed on the positioning support plate 519a. The connection terminals of the power semiconductor device and the electrodes of the connection substrate 514 are electrically connected. A gate signal and a test current from the connection substrate 514 are applied to the power semiconductor device 117. The device stage 611 is a stage for disposing the semiconductor device element 117, and is made of a resin material that suppresses static electricity and has flexibility and springiness.

[0206] A pressing column 531 is disposed so that the connection terminals of the power semiconductor device 117 are in close contact with the connection substrate 514. By being pressed, the connection terminals of the power semiconductor device and the connection substrate 514 are electrically well connected. When the semiconductor element 117 has the configurations shown in FIGS. 2, 5, etc., the connection substrate 514 may have the configurations shown in FIGS. 10, 12, 54, 57, etc., and the anisotropic conductive rubber 504 may be used to connect the electrode pattern 506 and the signal terminal 227.

[0207] The positioning support plate 519b is disposed on the upper surface of the power semiconductor device 117 to fix the position of the power semiconductor device. The heating and cooling plate 134a cools or warms the power semiconductor device from the upper surface of the power semiconductor device 117.

[0208] FIGS. 70 and 71 are a configuration diagram of a jig for surface-mounted components used in the semiconductor element test apparatus of the present invention and an explanatory diagram at the time of mounting the device element 117. It can also be applied to surface-mounted devices such as QFN packages and SOP packages.

[0209] A surface plate 520 made of a metal material with good thermal conductivity is arranged on the heating and cooling plate 134b. A positioning support plate 519 is arranged on the surface plate 520. The semiconductor element 117 is arranged on the connection substrate 514 and also on the device stage 611. The connection terminals of the semiconductor element 117 are pressed by the insulating pressing plate 513, and the connection terminals of the conductor element 117 and the electrodes of the connection substrate 514 are connected. Connection is made with the electrodes formed on the connection substrate 514. The positioning support plate 519 presses and fixes the connection substrate 514 so that the connection substrate 514 has flatness. FIG. 22 is an explanatory diagram of the semiconductor test apparatus of the present invention. A heating and cooling plate 134 is arranged on the base 522. The base 522 is exemplified by an anti-vibration surface plate.

[0210] FIGS. 23 to 25 are explanatory diagrams of the test method of the semiconductor element 117 mainly when attaching to the SOP117 or QFN117 in the semiconductor test apparatus of the present invention. Needless to say, it can also be applied to semiconductor chips such as FIG. 58.

[0211] A surface plate 520 is attached to the base 522. The surface plate 520 is a plate for attaching the positioning support plate 519. By changing the surface plate 520, the positioning support plate 519 can be easily changed.

[0212] The positioning support plate 519 needs to be changed corresponding to the shape of the sample placement plate 511 and the position of the positioning hole 509. Also, the sample placement plate 511 has the size and position of the sample hole 512 changed corresponding to the shapes of the SOP117 and QFN117.

[0213] As shown in FIG. 23, the positioning supports 518 of the positioning support plate 519 are inserted into the positioning holes 509 of the sample placement plate 511, and the sample placement plate 511 is fixed.

[0214] The thickness of the sample placement plate 511 is configured to be thinner than the thicknesses of SOP117 and QFN117. SOP117 and QFN117 are arranged with the electrode terminals 226 of the sample holes 512 facing upward.

[0215] The positioning support plate 519 is composed of a base material made of a metal material with good heat transfer properties. For example, copper, stainless steel, and aluminum are exemplified. The surface of the positioning support plate 519 is plated with nickel (Ni) or silver (Ag).

[0216] Anisotropic conductive rubber 504 (not shown) is arranged on the electrode terminals 226 of SOP117 and QFN117. The anisotropic conductive rubber 504 is rectangular, and its area is the same as or slightly larger than the area including the arrangement areas of the electrode terminals 226 and the signal terminals 227. The sample placement plate 511 is countersunk, and the anisotropic conductive rubber 504 is configured to fit exactly into the countersunk area.

[0217] As shown in FIG. 24, a connection substrate 514 is arranged on the anisotropic conductive rubber 504. The electrode pattern 505 of the connection substrate 514 is arranged to correspond to the electrode terminals 226 of SOP117 and QFN117, and the electrode pattern 506 of the connection substrate 514 is arranged to correspond to the signal terminals 227 of SOP117 and QFN117.

[0218] The support column 534 is attached to the base 522. An arm base 533 is attached to the support column 534. An arm 532 is attached to the arm base 533. The arm 532 is configured to be rotatable about the central axis. The length of the arm 532 is set and configured such that, as shown in FIG. 21, the position of the pressing head 530 is above the anisotropic conductive rubber 504.

[0219] Needless to say, the matters described above are also applicable to the device of the present invention shown in FIGS. 68 and 72. Also, it goes without saying that the configurations, members, structures, and operations shown in FIGS. 25, 68, and 72 can be applied in whole or in part in combination with each other.

[0220] A pressing column 531 is attached to the pressing head 530, and an arm 532 is attached to the pressing column 531. By sliding the pressing column 531, the position of the pressing head 530 moves up and down. By moving the position of the pressing head 530 up and down, the pressing of the anisotropic conductive rubber 504 is adjusted or set.

[0221] A rubber 517 is attached to the pressing head 530. The rubber 517 may be any elastic material or elastic object. By using an elastic material, the anisotropic conductive rubber 504 can be pressed uniformly as a whole.

[0222] Examples of the elastic material or elastic object include sponge, foam, soft plastic, air pack, liquid pack, gel pack, rubber metal, metal or resin spring, leaf spring.

[0223] As an example, a pressure motor is used for pressing. A pressure motor is a prime mover or actuator that converts the pressure of a liquid into rotational motion among fluid machines that convert mechanical motion. A pressure cylinder is a device that converts the pressure of a fluid into linear motion.

[0224] A pump converts rotational energy into pressure energy. Since a pressure motor converts pressure energy into rotational energy, its basic structure is the same as that of a pump. Different from an electric motor, it can operate stably even in a high-temperature environment. Also, even when the power source stops, it can operate by storing pressure in an accumulator or the like. A pressure sensor is provided to detect the pressure.

[0225] FIG. 25 shows that pressure is applied to the anisotropic conductive rubber 504 by the pressing head 530 from above the connection substrate 514. However, the connection substrate 514 is often made of a glass epoxy material or the like, and the connection substrate 514 is thin and easily deformed during pressing.

[0226] For this countermeasure, a pressing plate 515 shown in FIG. 14 is arranged on the connection substrate 514. The pressing plate 515 is composed of a material and thickness that have good thermal conductivity, such as a metal material, are smooth, and are difficult to bend. By applying pressure from above the pressing plate 515 with the pressing head 530, anisotropic conductive rubber 504 can be uniformly pressured at a constant pressure.

[0227] FIG. 21 is an explanatory diagram showing a state in which pressure is applied to the anisotropic conductive rubber 504 using the pressing head 530. FIG. 21 shows a case where pressure is applied from above the connection substrate 514 via the rubber 517. The pressure is indicated by an arrow.

[0228] Among the electrode patterns (electrode pattern 505, electrode pattern 506) and the plating film 524, at least one of them is convex with respect to the flat portion composed of the heat-resistant resist 523 or the like. Therefore, the convex portion is pressed by the anisotropic conductive rubber 504, and the electrode pattern 505 and the electrode terminal 226, and the electrode pattern 506 and the signal terminal 227 are electrically connected via the anisotropic conductive rubber 504.

[0229] For the electrical connection state, a monitor terminal (not shown) for measuring the resistance between the electrode pattern 505 and the electrode terminal 226, and the electrode pattern 506 and the signal terminal 227 is provided on the connection substrate 514. Press with the pressing head 530, monitor the resistance value of the monitor terminal, and when the resistance value becomes equal to or less than a predetermined resistance value, maintain the pressing of the pressing head 530 as the connection is completed.

[0230] FIG. 22 shows a case where pressure is applied by the pressing head 530 supported by the one-way arm 532 attached to the arm base 533. In this case, the pressing head 530 may be inclined.

[0231] For this countermeasure, as shown in FIG. 26, an arm 532 is provided between the support columns 534a and 534b. That is, the support columns 534a, 534b, and the arm 532 are configured in a "gate" shape.

[0232] The arm 532 is supported by left and right columns (column 534a and column 534b). Therefore, the pressing column 531 that moves the pressing head 530 can be stably maintained. Since the anisotropic conductive rubber 504 can be uniformly pressed, a good electrical connection can be achieved.

[0233] FIG. 28 is a configuration diagram of a semiconductor test apparatus of the present invention (for example, a power cycle test apparatus for testing a power transistor). FIG. 44 is an equivalent circuit diagram or an explanatory diagram of the semiconductor test apparatus.

[0234] The current power supply device 121 outputs a constant current Id with a large current for testing the transistor 117. The current power supply device 121 supplies power (current, voltage) in synchronization with a control signal from the control circuit board 111, and drives the load at a set constant current or constant voltage using the supplied power. The current power supply device 121 can set the maximum voltage value to be output. The current power supply device 121 constantly outputs at least one of current and voltage.

[0235] The switch circuit 122a (SWa) turns on (supplies) or off (cuts off) the supply of the constant current output by the current power supply device 121. The switch circuit 122a is set or controlled to be on (outputs a constant current) or off (cuts off the constant current) based on a signal from the control circuit board 111. Usually, the switch circuit 122a is turned on before the start of the test and is maintained in the on state at all times during the test of the semiconductor element.

[0236] In FIG. 28, one current power supply device 121 is illustrated. The current power supply device 121 is not limited to one. For example, in the semiconductor test apparatus of the present invention, two or more current power supply devices 121 may be provided. The more the number of current power supply devices 121 increases, the more various current waveforms Id or voltage waveforms can be generated.

[0237] In the embodiments of the present invention, the current power supply device 121 is described, but the current power supply device 121 is not limited to outputting a constant current. For example, a device that can set the maximum voltage is used for the current power supply device 121. It is exemplified that under certain conditions, it functions to output a predetermined constant current at the set maximum voltage. Also, when outputting a constant current, it is exemplified that the output terminal voltage can be configured to set a predetermined maximum voltage. In the semiconductor test device of the present invention, it goes without saying that the current power supply device 121 is not a device that only outputs a constant current, but may be a power supply device that can output voltage and current.

[0238] In the embodiments such as FIG. 28, it is described that the current Id is generated by the current power supply device 121, but the current Id can also be realized by adjusting the applied voltage according to the on-resistance state of the transistor 117. Therefore, in the semiconductor test device of the present invention, it goes without saying that it is not limited to the current power supply device 121 that outputs current, and it may be configured with a voltage output power supply device.

[0239] The current Id can also be realized by controlling the voltage value of the gate voltage of the transistor 117. In this specification, it is described that a predetermined current is applied to the transistor 117 by the control of the current power supply device 121. However, it goes without saying that it is not limited to this, and the voltage of the gate terminal g of the transistor 117 and the voltage of the collector terminal c of the transistor 117 may be adjusted or controlled.

[0240] In the embodiments of the test method of the semiconductor element of the present invention, for the sake of easy explanation, the constant current Id is assumed to be generated by the current power supply device 121. The constant current Id flowing through the transistor 117 is supplied by operating the current power supply device 121. The current power supply device 121 is turned on / off controlled by a signal from the control circuit board 111. The device control circuit board 209 is timing controlled by the control circuit board 111.

[0241] The emitter terminal e of transistor 117 is grounded (connected to the ground line). The gate driver circuit 113 is connected to the gate terminal g of transistor 117.

[0242] Inside the sample connection circuit 203, a gate driver circuit 113, a variable resistance circuit 125, a constant current circuit 118, and an operational amplifier (buffer circuit) 116 are arranged or formed. The sample connection circuit 203 is arranged separately from the device control circuit board 209 so that it can be arranged at a position close to the transistor 117 to be tested.

[0243] It is preferable to provide one sample connection circuit 203 for each transistor 117 to be tested in the sample connection circuit 203, but it is not limited thereto. One sample connection circuit 203 including a plurality of signal circuits may be arranged for a plurality of transistors 117.

[0244] The sample connection circuit 203 is connected to the transistor 117 by the connection pin 206 of the connector 202. The gate driver circuit 113 and the gate terminal g of the transistor 117 are arranged so as to have a short distance of 30 mm or less. If the distance between the gate driver circuit 113 and the gate terminal g of the transistor 117 is long, noise or the like is superimposed on the gate terminal g, which directly leads to malfunction of the transistor 117 and destruction of the transistor 117.

[0245] As shown in FIG. 29, the device control circuit board 209 is arranged in the B chamber of the housing 210 of the semiconductor test apparatus. The housing 210 is a frame or the main body of the semiconductor test apparatus in which a power supply device 132, a drive circuit, and a heating and cooling plate 134 are incorporated. The sample connection circuit 203 is arranged in the C1 chamber of the housing 210 of the semiconductor test apparatus in order to be arranged at a position close to the transistor 117 to be tested. The sample connection circuit 203 is connected to a connector 208 arranged on the side surface of the housing 210. The wiring connected to the connection pin 206 of the connector 208 is connected to the device control circuit board 209 in the B chamber.

[0246] The housing 210 may not only be box-shaped, but may also be, for example, a room. It is an image that the current power supply device 121 is arranged in the room. The partition walls 214, 215, and 217 may be the walls of the room.

[0247] As shown in FIG. 29, the semiconductor element 117 (such as a transistor) to be tested is arranged in the C1 chamber. The transistor 117 etc. are arranged and fixed on the heating and cooling plate 134.

[0248] The device fixing and connecting device 610 has a heating and cooling plate 134 and a circulating water pipe 135 that circulates between the heating and cooling plate 134 and the chiller 136. Further, a transistor 117 as a semiconductor element to be tested is loaded on the heating and cooling plate 134, and a sample connection circuit 203 (not shown) is configured or arranged.

[0249] In FIG. 29, for the sake of easy illustration and easy understanding, the SOP117, QFN117, etc. are illustrated as being arranged and fixed on the heating and cooling plate 134. Actually, as shown in FIG. 16(b), a surface plate 520 with good thermal conductivity and a positioning support plate 519 are arranged on the heating and cooling plate 134, and the SOP117 and QFN117 are arranged on the support plate 519. The above matters are the same in FIGS. 27, 29, 30, 36, 38, 39, 43, etc.

[0250] As shown in FIG. 29, the connector 208 is provided on the side surface of the housing 210, and the connector 208 and the device control circuit board 209 arranged in the B chamber are connected by a signal wiring 235. Control signals or output signals of the gate driver circuit 113, gate signal control circuit 112, temperature measurement circuit 115, variable resistance circuit 125, and operational amplifier circuit 116 are input and output from the device control circuit board 209.

[0251] As necessary, as shown in FIG. 36, the transistor 117 etc. are sandwiched and fixed between the heating and cooling plate 134a and the heating and cooling plate 134b. As described above, in the present invention, the housing 210 is divided into a plurality of regions such as the C1 chamber. The C1 chamber is configured to be injected with dry air (dry gas, gas with a low dew point temperature). The C1 chamber is under air pressure, and the air injected into the C1 chamber is discharged through the opening 216 etc.

[0252] The connection structure 218 is inserted from the opening 216 of the partition wall 217 from the C2 chamber. By inserting the connection structure 218, an electrical connection is established between the connection portion 507 of the transistor 117 and the connection structure 218, and a constant current (test current) Id can be applied to the transistor 117. The connection structure 218 is formed of copper or a copper alloy, and its surface is plated with silver or nickel.

[0253] The partition wall 217 has functions as an electrostatic shield and for holding the connection structure 218. Needless to say, when separately arranging or configuring an electrostatic shield functional component and a fixing or holding base for the connection structure 218, the partition wall 217 can be omitted. Also, when there is no partition wall 217, it goes without saying that the connection portion 507 of the transistor 117 may be positioned and fixed to the connection structure 218.

[0254] The partition walls (partition walls 214, 215, 217) have functions of separating each chamber (C1 chamber, C2 chamber, A chamber, B chamber) and preventing outside air from flowing in. In particular, since the C1 chamber may dew in a low-temperature test, dry air with a dew point of -20°C or lower is allowed to flow into the C1 chamber. The dry air that has flowed into the C1 chamber is discharged from the opening 216 to other chambers. However, if the opening of the opening 216 is large, a large amount of dry air is required. Therefore, the opening 216 is preferably sized such that the fork plug 205 as a connection member and the connection structure 218 can be just inserted.

[0255] As shown in FIG. 30, a fixing screw 221 is attached to the other end of the connection structure 218, and the connection wiring 211 is connected to the connection structure 218. A fork plug 205 shown in FIG. 31 etc. as a connection member is attached to the other end of the connection wiring 211.

[0256] In FIGS. 30, 38, and 43, a pressing member 608 for fixing the connection structure 218 is arranged. By the pressing member 608, the connection structure 218 is fixed, and a terminal connection portion 609 composed of connection fittings 232 and connection fittings 233 is stably fitted with the connection portion 507 of the device 117 to be tested. When separating the device 117 and the connection structure 218, it is performed after removing the pressing member 608.

[0257] The fixing screw 221 of the connection structure 218 is not limited to a screw, and any one can be used as long as it can electrically connect the connection wiring 211 to the connection structure 218. Needless to say, the fixing screw 221 may also be one that can be contacted by pressing with a spring (not shown).

[0258] The sample connection circuit 203 is connected to the device control circuit board 209 by the connection pins 206 of the connector 208. The sample connection circuits 203 are individually arranged corresponding to the respective transistors 117 to be tested, and the sample connection circuits 203 are configured to be easily removable. The connectors 208 and 213 are not limited to connectors, and any one can be used as long as it can electrically connect and disconnect wiring.

[0259] FIG. 35 is an explanatory diagram of the connection structure 218 in the semiconductor test apparatus of the present invention. A heat pipe 223 is adhered to the concave portion 234 on the surface of the connection structure 218. A heat conductive grease or a heat dissipation silicone oil compound may be applied between the surface of the connection structure 218 and the heat pipe.

[0260] The recess 234 is formed in the heat pipe fitting 231. The heat pipe 223 is disposed so as to be fitted into the recess 234. By disposing the heat pipe 223 in the recess, the risk of damage to the heat pipe 223 is reduced.

[0261] The heat pipe fitting 231 is made of a metal that has electrical conductivity and good thermal conductivity. Examples of the metal include copper and silver. In addition, carbon or the like other than metal can also be adopted.

[0262] As the thermally conductive grease, it is preferable to use one containing boron nitride. As the silicone oil compound for heat dissipation, it is preferable to use one in which a powder with good thermal conductivity such as alumina is blended with silicone oil as the base oil. The heat pipe 223 is a structure in which a small amount of liquid (working fluid) is vacuum-sealed in a sealed container and has a capillary structure (wick) on the inner wall.

[0263] When a part of the heat pipe is heated, the working fluid evaporates (absorbing the latent heat of vaporization) in the heated part, and the vapor moves at high speed (sonic speed) to the low-temperature part. The vapor condenses (releasing the latent heat of vaporization) in the low-temperature part, and the condensed working fluid returns to the heated part by the capillary action of the wick. By continuously repeating the above phase changes without an external force, heat moves instantaneously, so that the heat generated at the terminal part of the semiconductor element can be transferred at high speed and efficiently.

[0264] The heat pipe 223 is configured by arranging a plurality of containers (copper pipes). The inside of the container is in a highly vacuum state and has a wick (capillary structure) and an appropriate amount of working fluid (pure water or the like). As the working fluid, in addition to pure water, methanol (methyl alcohol), acetone, sodium, mercury, a fluorocarbon refrigerant, or ammonia may be used. As the wick material, aluminum, copper, stainless steel, sintered alloy, wire mesh, foamed metal, ceramic, or the like is used.

[0265] The connection structure 218 is not limited to metals. For example, it goes without saying that it may be composed of non-metallic substances such as ceramics, graphite, and composite materials of graphite and copper or aluminum. In the case of a configuration in which current is directly passed through the connection structure 218, the connection structure 218 is composed of a metal material such as copper. The surface of the connection structure 218 is preferably plated with silver, nickel, etc. FIG. 35 is an explanatory diagram of the configuration of the connection structure 218. FIG. 35(a) is a diagram schematically showing the back surface, and FIG. 35(b) is a diagram schematically showing the side surface.

[0266] The connection structure 218 mainly consists of a heat pipe fitting 231, a connection fitting 232, and a connection fitting 233. The connection fitting 232 and the connection fitting 233, etc. constitute a terminal connection portion 609. The connection portion 507 of the semiconductor element is inserted into the terminal connection portion 609.

[0267] Between the connection fitting 232 and the connection fitting 233, contact portions 225a and 225b are arranged. As the contact portion 225, platinum, gold, silver, tungsten, copper, nickel, or an alloy combining them is used. It is also preferable to use a silver-oxide contact material (Ag+ZnO, Ag+SnO2, Ag+SnO2In2O3, Ag+, Ag+SnO2Sn2Bi2O7).

[0268] The connection fitting 233 is fixed to the heat pipe fitting 231 with a fixing screw 224a. The connection fitting 232 is fixed to the connection fitting 233 with a fixing screw 224b. By tightening the fixing screw 224b, the connection portion 507 of the semiconductor element is fixed. A connection wiring 211 is fixed to the left end of the heat pipe fitting 231 with a fixing screw 221.

[0269] FIG. 36 is an explanatory diagram of the state in which the connection portion 507 is connected to the connection structure 218. The connection portion 507 is clamped between the contact portion 225a and the contact portion 225b. The connection fitting 232 is fixed to the connection portion 507 with a fixing screw 224b.

[0270] The transistor 117 is fixed to the heating and cooling plate 134a and further clamped by the heating and cooling plate 134b. The transistor 117 is appropriately maintained at the test temperature by the heating and cooling plate 134. A heat pipe 223 is attached in the recess 234.

[0271] A test constant current Id is applied from the connection structure 218 to the connection part 507. The constant current Id is as large as several hundred amperes (A). The connection part 507 usually has a relatively small area, and there is a contact resistance between the contact part 225 and the connection part 507. Therefore, when a large current flows through the connection part 507, heat is generated at the contact part 225.

[0272] The heat generation is conducted to the transistor 117 being tested, overheating the transistor 117. There is a possibility that the transistor 117 deteriorates or the connection part 507 burns due to overheating. Also, heat is generated at the electrode terminals 226 of the SOP117, QFN117, etc., and the generated heat conducts through the connection substrate 514. The conducted heat raises the temperature of the connection part 507. Therefore, it is necessary to quickly dissipate the heat generated at the contact part 225.

[0273] The connection structure 218 of the present invention has a heat pipe 223. The heat generation at the contact part 225 is transferred by the heat pipe 223. Therefore, the heat of the contact part 225 is quickly removed from the contact part 225. Also, the heat of the connection part 507 and the heat of the connection substrate 514 are removed.

[0274] A partition wall 217 is arranged between the C1 chamber and the C2 chamber. As shown in FIG. 37, an opening 216 is formed in the partition wall 217. The connection structure 218a1 is inserted into the opening 216a1, and the connection structure 218b1 is inserted into the opening 216b1. The connection structure 218a2 is inserted into the opening 216a2, and the connection structure 218b2 is inserted into the opening 216b2. The connection structure 218an is inserted into the opening 216an, and the connection structure 218bn is inserted into the opening 216bn.

[0275] For example, in the semiconductor test apparatus of FIG. 37, the P terminal of the transistor 117Q1 to be tested is sandwiched and electrically connected between the connection fittings 232 and 233 of the connection structure 218a1. Also, the N terminal of the transistor 117Q1 to be tested is sandwiched and electrically connected between the connection fittings 232 and 233 of the connection structure 218b1.

[0276] Similarly, the P terminal of the transistor 117Q2 to be tested is sandwiched and electrically connected between the connection fittings 232 and 233 of the connection structure 218a2. Also, the N terminal of the transistor 117Q2 to be tested is sandwiched and electrically connected between the connection fittings 232 and 233 of the connection structure 218b2.

[0277] Similarly, the P terminal of the transistor 117Qn to be tested is sandwiched and electrically connected between the connection fittings 232 and 233 of the connection structure 218an. Also, the N terminal of the transistor 117Qn to be tested is sandwiched and electrically connected between the connection fittings 232 and 233 of the connection structure 218bn.

[0278] An electrostatic shielding plate or an electrostatic shielding net is disposed on the partition wall 217, noise from the power supply device 132 and the drive circuit system in the B chamber is shielded, and the noise is not applied to the C1 chamber. Also, the noise generated by the on / off of the transistor 117 is not applied to the drive circuit system in the B chamber.

[0279] FIG. 38 is an explanatory diagram for explaining the connection state between the transistor 117 and the connection structure 218. The transistor 117 is fixed to the heating and cooling plate 134a. Actually, on the heating and cooling plate 134a, a surface plate 520, a positioning support plate 519, etc. are disposed or formed, but they are omitted for easy understanding and for easy drawing.

[0280] Fixing is performed by a spring (not shown). For close contact, a thermally conductive grease or a heat-dissipating silicone oil compound may be applied. If necessary, as shown in FIG. 36, a heating and cooling plate 134b is also arranged above the transistor 117 so that the transistor 117 can be set to a predetermined temperature condition. Note that it is not limited to a spring, and any structure or mechanism that can fix may be used.

[0281] A connector 202 is connected to the terminals (emitter terminal e, gate terminal g, collector terminal c) of the transistor 117. A signal wiring 222 is drawn out from the connector 202. A control signal Vgs applied to the gate terminal g of the transistor 117 and a constant current Ic from the constant current circuit 118 are applied to the signal wiring 222.

[0282] The connection structure 218a is inserted into the opening 216a of the partition wall 217 from the C2 chamber side. Similarly, the connection structure 218b is inserted into the opening 216b of the partition wall 217 from the C2 chamber side. When the connection structure 218 is inserted, a connection portion 507 is sandwiched between the connection fitting 232 and the connection fitting 233. In this state, by tightening the fixing screw 224b, the connection portion 507 of the transistor 117 and the connection structure 218 are electrically connected.

[0283] The transistor 117 to be tested needs to be fixed in close contact with a heating and cooling plate 134 or the like. In addition, since the electrode pattern 505 and the electrode terminal 226 are positioned and electrically connected by the anisotropic conductive rubber 504, it is difficult to remove it easily.

[0284] The mounting operation of the transistor 117 is to first fix a plurality of transistors 117 to be tested to a heating and cooling plate 134 or the like. Next, select the transistor 117 to be tested first and attach the connection structure 218 to the connection portion 507.

[0285] For the selected transistor 117, insert the connection structure 218 from the C2 chamber side into the opening 216 where the selected transistor 117 is located to make an electrical connection with the connection portion 507.

[0286] The electrical connection with the transistor 117 is easy because it only involves selecting the position to insert the connection structure 218. Also, by changing the applied signal of the connection wiring 211 connected to the connection structure 218, the test conditions and test content of the transistor 117 can be easily changed.

[0287] As shown in FIG. 36, the connection part 507 is clamped by applying pressure with the contact part 225a and the contact part 225b. One end of the connection structure 218 is connected to the connection wiring 211, and a constant current Id is applied from the connection wiring 211 to the transistor 117. A heat pipe 223 is arranged on the back side of the connection structure 218.

[0288] A current of several hundred amperes (A) flows through the connection part 507. Even if there is a slight resistance in the contact part 225, a large amount of heat is generated by the current of several hundred amperes (A), overheating the connection part 507. When overheated, the transistor 117 will also be overheated, and the transistor 117 will deteriorate or be damaged due to overheating.

[0289] In the present invention, the heat generated at the contact part 225 is transferred to the connection wiring 211 side of the connection structure 218 by the heat pipe 223. Therefore, the contact part 225 is not overheated. A cooling fan 229 is arranged below the connection structure 218 to dissipate the heat of the heat pipe 223. FIG. 38 is an explanatory diagram for explaining the cooling method of the connection structure 218 in the semiconductor test apparatus of the present invention.

[0290] As shown in FIG. 38, a cooling fan 229 for removing the heat of the heat pipe 223 is arranged on the back surface of the connection structure 218. The rotation speed of the cooling fan 229 is controlled according to the overheating situation of the connection part 507 and the heat pipe 223. FIG. 39 is an explanatory diagram for explaining the connection method between the semiconductor element 117 and the connection structure 218 in the semiconductor test apparatus of the present invention.

[0291] A partition wall 217 is provided between the C1 chamber and the C2 chamber. As shown in FIG. 37, an opening 216 is formed in the partition wall 217 corresponding to the position of the transistor 117 to be tested and the like. The connection structure 218 is positioned and fixed horizontally or stably by the opening 216 of the partition wall 217 and a fixing base (not shown) of the connection structure 218.

[0292] As shown in FIG. 39(a), the transistor 117 to be tested is positioned and fixed in close contact with the heating and cooling plate 134a. A heat conductive grease and a heat dissipation silicone oil compound are applied between the transistor 117 and the heating and cooling plate 134a.

[0293] A detachable connector 202 is connected to the terminals (emitter terminal e, gate terminal g, collector terminal c) of the transistor 117. A signal wiring 222 is connected to the connector 202, and the signal wiring 222 is connected to the sample connection circuit 203.

[0294] The signal wiring 222 between the sample connection circuit 203 and the connector 202 is formed to be as short as possible. If the signal wiring 222 is long, noise is superimposed on the signal wiring 222, and the transistor 117 may malfunction. For example, if noise is superimposed on the gate terminal g of the transistor 117, the transistor 117 may turn on and the transistor 117 may be damaged. The signal wiring 222 is a twisted wiring or a shielded wiring such as a coaxial cable is used.

[0295] As shown in FIG. 39(b), the connection structure 218a is inserted into the opening 216a. By inserting the connection structure 218a into the opening 216a, the connection portion 507a of the transistor 117 is sandwiched between the connection fittings 232 and 233 at the tip of the connection structure 218a. After connecting the connection structure 218a and the connection portion 507a, by tightening the fixing screw 224b1, a good electrical connection between the contact portion 225 and the connection portion 507 can be realized.

[0296] Similarly, the connection structure 218b is inserted into the opening 216b. By inserting the connection structure 218b into the opening 216b, the connection portion 507b of the transistor 117 is sandwiched between the connection fittings 232 and 233 at the tip of the connection structure 218b. After connecting the connection structure 218b and the connection portion 507b, by tightening the fixing screw 224b2, a good electrical connection can be achieved between the contact portion 225 and the connection portion 507.

[0297] In the embodiment of FIG. 38, the heat pipe 223 was attached to the recess 234 of the heat pipe fitting 231 of the connection structure 218. However, the present invention is not limited to this.

[0298] For example, as shown in FIG. 40, the connection structure 218 may be configured. In FIG. 40, FIG. 40(a) schematically shows the back surface (lower surface) of the connection structure 218, and FIG. 40(a) schematically shows the front surface (upper surface) of the connection structure 218.

[0299] In FIG. 40, the heat pipe 223a is disposed in the concave surface 234a. The heat pipe 223a is formed or disposed up to the connection fitting 233 portion. By forming or disposing up to the connection fitting 233 portion, the heat generated by the connection portion 507 can be transferred more efficiently.

[0300] As shown in FIG. 40(b), the heat pipe 223b is disposed in the concave surface 234b. By disposing the heat pipe 223 on both surfaces of the connection structure 218, the heat generated by the connection portion 507 can be transferred more efficiently.

[0301] In the embodiment of FIG. 38 and the like, the heat pipe 223 and the like are cooled by the cooling fan 229, but the present invention is not limited to this. For example, as shown in FIG. 41, the heat dissipation fins 228 may be formed or disposed so as to be in close contact with the heat pipe 223. The heat transferred in the heat pipe 223 is efficiently transferred to the heat dissipation fins 228, and the heat transfer and heat dissipation effects of the heat pipe 223 are further enhanced.

[0302] The heat dissipation fins 228 in FIG. 41 are not formed or arranged at the location corresponding to the opening 216. The connection structure 218 is inserted from the C2 chamber side to the C1 chamber side through the opening 216. In order to maintain the airtightness of the C1 chamber, the opening 216 has an opening size of the cross-sectional area of the connection structure 218 + α. Therefore, if the heat dissipation fins 228 are formed or arranged on the connection structure 218, they cannot be inserted into the opening 216. Therefore, no heat dissipation fins 228 are formed or arranged on the side connected to the connection portion 507 of the transistor 117 with respect to the partition wall 217 as a reference.

[0303] As shown in FIG. 42, a circulating water pipe 135 may be formed or arranged in the connection structure 218 to cool the connection structure 218. The connection structure 218 is cooled by the refrigerant flowing in the circulating water pipe, and the heat transfer in the heat pipe 223 is efficiently transmitted to the connection structure 218. Therefore, the heat generated at the connection portion 507 is efficiently dissipated.

[0304] In the transistor 117 (SOP117, QFN117, semiconductor element 117) of FIG. 1, as shown in FIG. 3, the electrode terminal 226a is connected to the connection portion 507a, and the electrode terminal 226b is connected to the connection portion 507b. Therefore, the connection portion 507 has two terminals, the connection portion 507a (P) and the connection portion 507b (N).

[0305] As shown in FIG. 6, there is also a connection portion 507 of the transistor 117 having three terminals, the connection portion 507a (P), the connection portion 507b (N), and the connection portion 507c. As shown in FIG. 6, the electrode terminal 226a is connected to the connection portion 507a, the electrode terminal 226b is connected to the connection portion 507b, and the electrode terminal 226c is connected to the connection portion 507c. The semiconductor test apparatus and the semiconductor element test method of the present invention can test various semiconductor elements 117.

[0306] As shown in FIG. 4, the semiconductor element 117 in FIG. 6 has two transistors, i.e., transistor 117m and transistor 117s, which are arranged in one SOP or QFN package.

[0307] The collector terminal cs of the transistor 117s is connected to the connection portion 507a. The emitter terminal es of the transistor 117s and the collector terminal cm of the transistor 117m are connected, and the midpoint is connected to the connection portion 507c. The emitter terminal em of the transistor 117m is connected to the connection portion 507b.

[0308] The emitter terminal em, the gate terminal gm, and the collector terminal cm are connected to the transistor 117m. The emitter terminal es, the gate terminal gs, and the collector terminal cs are connected to the transistor 117s.

[0309] FIG. 43 is an explanatory diagram showing the connection state between the transistor 117 (semiconductor element 117) having three connection portions 507 (connection portion 507a (P), connection portion 507b (N), connection portion 507c (O)) and the connection structure 218.

[0310] In FIG. 43, an arrangement recess 239 is formed or configured on the connection substrate 514, and the anisotropic conductive rubber 504a is arranged in the arrangement recess 239. The anisotropic conductive rubber 504a electrically connects the signal terminal 227 and the electrode pattern 506. A pressing plate 515 is arranged on the connection substrate 514, and the pressing plate 515 is pressed by a pressing head 530 via a rubber (elastic material) 517.

[0311] In FIG. 43, the connection between the connection structure 218a and the connection portion 507a and the connection between the connection structure 218b and the connection portion 507b are the same as those described in FIGS. 38 and 39, so the description thereof is omitted.

[0312] In FIG. 43, a heat pipe 223a is formed or disposed in the connection structure 218a, and a heat pipe 223b is formed or disposed in the connection structure 218b, while no heat pipe 223 is formed or disposed in the connection structure 218c. The connection structure 218c is connected to the connection portion 507c.

[0313] A large current does not flow through the connection portion 507c(O) of the transistor 117. Therefore, the connection portion 507c is not overheated. There is no need to form a heat pipe 223 in the connection structure 218c. By forming the connection structure 218c thinner than the other connection structures 218 (the connection structure 218a and the connection structure 218b), the connection between the connection structure 218 and the connection portion 507 of the transistor 117 becomes easier. In addition, since the space for arranging the transistor 117 may be narrow, the number of transistors 117 that can be mounted on the heating and cooling plate 134 can be increased.

[0314] Needless to say, a heat pipe 223 may be formed or disposed in the connection structure 218c. Regarding other matters, since they are the same as or similar to the embodiments of FIGS. 38 and 39, the description is omitted.

[0315] FIG. 58 is a schematic diagram of a thermal cycle test (thermal shock test) in an embodiment of the semiconductor element test apparatus of the present invention. In FIG. 58, wiring electrodes 607a, 607b, and 607c are formed on the insulating substrate 602. A semiconductor chip 601 is connected to the wiring electrode 607a by solder 605.

[0316] A bonding terminal (not shown) of the semiconductor chip 601 and the wiring electrode 607b are electrically connected by an aluminum wire 606. A wiring electrode 607c is formed or disposed on the back surface of the insulating substrate 602 and is connected to the copper base 604 by solder 605.

[0317] The thermal cycle test (thermal shock test) shown in FIG. 58 is a test for predicting the life with respect to a relatively gentle temperature change that occurs at the start-up or stop of a product or system.

[0318] In a power module 117 (a power semiconductor device, a power semiconductor chip, a module on which a semiconductor device is mounted), etc., due to startup / shutdown, the case temperature (Tc) is relatively moderate and changes significantly in temperature. When this stress is repeated and cracks in the die bond (bonding material such as solder) reach under the power semiconductor chip, it causes an increase in thermal resistance, leading to thermal runaway and destroying the power module.

[0319] The semiconductor device test apparatus of the present invention heats the power module from the outside of the power module 117, heats it by the heat generation of the power module itself, or cools it from the outside. Further, heating or cooling is performed by cooling water or warm water from a chiller.

[0320] In the semiconductor device test apparatus and the semiconductor device test method of the present invention, the temperature of the power semiconductor device (such as a transistor) 117 is periodically changed in accordance with the test conditions, cooled to a constant temperature, and heated to a constant temperature. Further, the temperature information Tj of the transistor to be tested is measured, and the chiller 136 is controlled so as to maintain the measured temperature information Tj at a constant value.

[0321] The chiller 136 is configured to be able to keep the temperature of equipment etc. constant by circulating while managing the liquid temperature of water or a heat medium. It is mainly used for cooling in many cases, but can not only cool but also warm. It is configured to be able to perform various temperature controls.

[0322] The control rack 131 has a power supply device 132 that supplies a test current and a test voltage to the power semiconductor device 117 (such as a transistor), and a control circuit that controls the transistor 117 or sets test conditions.

[0323] Temperature information Tj of the transistor is input to the control circuit 132, and the chiller is controlled based on the temperature information Tj. Alternatively, the chiller 136 is controlled so that the temperature information Tj becomes a predetermined value.

[0324] Note that although this specification describes the circulating water, it is not limited to water. Ethylene glycol, glycerin, Freon, etc. may also be used, or forced air cooling may be employed. The chiller 136 controls the liquid in the circulating water pipe 135 and supplies it to the cooling / heating heat sink of the test unit, for example, in the temperature range from minus 1°C to plus 100°C of the water temperature. The cooling / heating heat sink 134 has a sufficiently large heat capacity.

[0325] By heating or cooling the power module 117, relatively gentle expansion and contraction occur. The semiconductor element test apparatus of the present invention can set the temperature and period of cooling or heating. The endurance test of the semiconductor module can be performed according to the temperature and period. The number of test cycles can be arbitrarily set from 100 to 100,000 cycles. Also, the cooling time and heating time can be arbitrarily set.

[0326] FIG. 59 is a schematic diagram of the power cycle test in the semiconductor element test apparatus of the present invention. Tests regarding the life and reliability in an operation pattern where the junction temperature changes frequently can be performed.

[0327] In the power cycle test, heat rises and falls according to the operating conditions of the power semiconductor element 117. The change in the case temperature (such as the mold resin of the semiconductor chip, the case of the module having the semiconductor chip 601, etc.) is small, and it is a test for the life in an operation pattern where the junction temperature changes frequently.

[0328] The heat generated by the semiconductor chip 601 is transferred through the aluminum wire 606 as shown by the arrow A, and also, the heat generated by the semiconductor chip 601 is transferred in the direction of the insulating substrate 602 as shown by the arrow B.

[0329] In power semiconductor devices 117 and power semiconductor modules 117, the power cycle test is an essential test item. In the structure of the power module 117, when the temperature of the joint changes due to the operation of the power semiconductor 117, cracks occur on the joint surface due to the stress caused by the difference in the coefficient of linear expansion between the aluminum wire 606 and the power semiconductor chip (such as a silicon chip) 601.

[0330] As the cracks progress, it leads to a failure in the peeling mode. In particular, for power semiconductors 117 used in inverters etc., it is necessary to consider this power cycle breakdown from the device design stage.

[0331] The semiconductor element test device of the present invention can arbitrarily set the rapid heat generation (expansion) temperature, change time, holding time, cooling (contraction) temperature, change time, and holding time associated with the operation of the power semiconductor element 117. Therefore, a durability test against stress due to differences in the coefficient of linear expansion etc. can be easily realized.

[0332] The number of test cycles can be arbitrarily set from 100 to 100,000 cycles. Also, the cooling time, heating time, holding time, and temperature change time can be arbitrarily set. Hereinafter, the test method of the semiconductor element of the present invention will be described. FIGS. 44, 45, and 46 are explanatory diagrams of the test method of the semiconductor element of the present invention.

[0333] The constant current circuit 118 supplies a constant current Ic to the diode Di of the transistor 117. The operational amplifier circuit 116 buffers and outputs the terminal voltage Vi of the diode Di. The terminal voltage Vi is applied to the temperature measurement circuit 115, and the temperature measurement circuit 115 obtains the temperature information Tj of the transistor 117 from the terminal voltage Vi and transfers it to the controller circuit board 11. The temperature information is output from the connector 213 of the device control circuit board 209 to the mother board 207 and sent to the control circuit board 111 (see FIG. 28 etc.).

[0334] The semiconductor device test apparatus and the semiconductor device test method of the present invention implement noise control technology. The noise control technology implements an inrush current removal method and a surge voltage removal method. FIG. 61 is an explanatory diagram of the inrush current removal method. FIG. 62 is an explanatory diagram of the surge voltage removal method.

[0335] New devices such as SiC / GaN have low on-resistance and good high-speed switching performance. Due to their characteristics, they are also sensitive to switching noise (such as surges) even during power cycle tests. Therefore, since there is a risk of device breakdown, noise control is important as a test apparatus or test method.

[0336] The noise control method, the inrush current removal method, the surge voltage removal method, etc. specifically implement the test methods described in FIGS. 46, 48, 51, and 52, and the implementation circuits use the configurations or operations of FIGS. 28, 29, 44, 45, 49, 50, and 51. With the improvement of the performance of semiconductor devices or due to the requirement for higher functionality, the circuit design margin using power semiconductor devices is decreasing.

[0337] In particular, the low on-resistance and high-speed switching due to new devices such as IGBT, SiC, and GaN increase the switching noise, and device breakdown due to noise (such as surges) occurs. In the semiconductor device test apparatus of the present invention, technologies such as noise control are established, and a test state that does not affect the inrush current and the surge voltage can be realized.

[0338] In the inrush current removal method shown in FIG. 61, as shown in FIGS. 44, 45, 49, 50, 51, etc., a switching circuit board 201 composed of MOS transistors or the like as switching elements is arranged or connected between the drain terminal and the source terminal (between channels) of the power semiconductor device 117 (power transistor) for which the test is being performed.

[0339] When the switch circuit 124b on the switch circuit board 201a is turned on, the drain terminal and the source terminal of the transistor 117 are short-circuited. Due to the short circuit, no voltage or current is applied across the channels of the transistor 117. Also, when the switch circuit 124b is turned on, the output terminal of the current power supply device 121 that supplies the test current to the transistor 117 is short-circuited to discharge the charge.

[0340] When the switch circuit 124b is turned on, current flows and discharges the charge of the current power supply device 121. Alternatively, the current output by the current power supply device 121 flows to the ground through the switch circuit 124b.

[0341] When an inrush current Is flows into the transistor under test, the transistor is destroyed due to the generation of the inrush current Is or the surge voltage Vs. To prevent the generation of the inrush current Is or the surge voltage Vs, the on / off control and the on / off sequence of the switch circuit are controlled.

[0342] As shown in FIG. 61, in the conventional example, the current (drain current Id) flowing between the channels of the transistor has been generated as an inrush current. In the present invention, by controlling the switch circuit 124 and the like, no inrush current is generated.

[0343] Similarly, by controlling the switch circuit 124, the surge voltage can be removed. As shown in FIG. 62, in the conventional example, a surge voltage is generated between the drain terminal and the source terminal of the transistor 117, but the present invention can remove the surge voltage by controlling the switch circuit board 201. In the semiconductor element test device (power cycle tester) and the semiconductor element test method of the present invention, the saturated thermal resistance can be measured.

[0344] As a composite function of the power cycle tester, the saturated thermal resistance can be measured at an arbitrary set current and / or an arbitrary set voltage. Also, the cycle time, the number of cycles, and the simultaneous measurement of a plurality of devices are possible.

[0345] The saturation thermal resistance, which is the thermal resistance of a semiconductor package, is the amount of heat generated per 1 W of power. The saturation thermal resistance can be measured from the junction temperature (Tj) and the ambient temperature (Ta) in a thermally saturated state at the specified power using a power cycle tester. The test flow is as follows. 1. Input the Ic (Id) current and the Vce (Vds) voltage as test conditions. 2. By starting the saturation thermal resistance test, measure the ambient temperature (temperature before energization) and the junction temperature. 3. Calculate the thermal resistance from the above 1 and 2. Display the thermal resistance value in the thermally saturated state. Rth = Tj - Ta / Pd However, Rth: Saturation thermal resistance (°C / W) Tj: Junction temperature (°C) Ta: Temperature before energization (°C)

[0346] In the power cycle tester, the gate voltage can be set according to the power control conditions. The gate voltage can be automatically varied to set the Vce voltage of the test conditions. The setting flow is as follows. 1. Specify the applied current: Ic (Id). 2. Specify the test execution power. 3. Automatically vary the gate voltage at the start of the test. Present the gate voltage corresponding to the specified power. By using this gate voltage, the test can be easily performed at the collector-emitter voltage (Vce) and the drain-source voltage (Vds) that meet the test conditions.

[0347] Figure 63 is a graph measuring the transition of the saturation thermal resistance of eight devices (Dev1 to Dev8). In the power cycle tester of the present invention, the transition of the saturation thermal resistance of a large number of power devices can be measured simultaneously, displayed on a display, etc., and visualized. Printing to a printer is also possible.

[0348] The semiconductor device test apparatus and the semiconductor device test method of the present invention can perform a short-pulse power cycle test. FIG. 64 shows an example of a measurement waveform when measuring a power cycle test using a current pulse.

[0349] FIG. 64(a) shows the gate voltage waveform applied to the gate terminal g of the semiconductor element 117 to be tested. The gate voltage is generated by the device control circuit board 209 and applied from the sample connection circuit 203 to the semiconductor element 117. The on-time ta and the period tc of the gate can be variably set by the device control circuit board 209. Also, although 0 (V) is the off voltage, depending on the type of the semiconductor element 117, it may be necessary to lower the off voltage level. In the semiconductor test apparatus of the present invention, in addition to the first off voltage of 0 (V), the magnitude of the second off voltage Vt and the application time tn2 can be set.

[0350] FIG. 64(b) is a graph showing the current (voltage) waveform applied to the collector terminal c or the drain (source) terminal of the semiconductor element 117 to be tested. The current (voltage) to be applied can be realized by controlling the switch circuit 124a of the switch circuit board 201b such as FIG. 45. By the operation timing of the switch circuit 124a, the lengths and timings of the te time, td time, and tf time can be set and controlled as shown in FIG. 62(b).

[0351] The semiconductor test apparatus of the present invention can perform a power cycle test using a current pulse of at least 10 ms (milliseconds). Even when applying a 10 ms pulse current, the surge absorption circuit absorbs the surge current / voltage generated at the current on / off timing to prevent the destruction of the test device.

[0352] Also, in the 10 ms pulse test, it is possible to acquire a log of measurement data. For example, in the case of a device equipped with a temperature-sensitive diode, accurate Tj measurement is possible even when applying a 10 ms pulse current. Therefore, it is possible to trace the process leading to the destruction of the semiconductor element.

[0353] The semiconductor device testing apparatus and the semiconductor device testing method of the present invention can implement the testing methods according to the JEITA, IEC, and AQG324 guidelines shown in FIG. 65. The semiconductor device testing apparatus and the semiconductor device testing method of the present invention can perform a pulse type power cycle test. Conventional semiconductor device testing apparatuses and semiconductor device testing methods could only perform tests in which a transistor is turned on and off.

[0354] For example, as shown in FIG. 66(a), when a power semiconductor device (such as a transistor) is turned on, a predetermined current flows. Then, as shown in FIG. 66(b), the temperature of the power semiconductor device gradually rises from t1 during energization. The energization current Ia becomes constant at time t2. At time t3, since the power semiconductor device is in the on state, the temperature exceeds the target temperature Ta.

[0355] To lower the temperature, it is necessary to change the cooling water temperature or the like. Changing the cooling water temperature requires time, and a predetermined test state cannot be maintained during the period when the target temperature is exceeded. The present invention can pulse-energize not only during the on and off times of the transistor, but also during the on period of the transistor.

[0356] FIG. 67 is an explanatory diagram of the semiconductor device testing apparatus and the semiconductor device testing method of the present invention. As shown in FIG. 67(a), by changing or controlling any of the period Tc, on time ton, and off time toff of the power semiconductor device, the time and interval during which a predetermined current flows through the power semiconductor device can be accurately controlled.

[0357] FIG. 67(a) shows an example in which, with the same cycle time tc, the on time ton1 and off time toff1 are set, and at time t4, the settings are changed to the on time ton2 and off time toff2.

[0358] As shown in FIG. 67, in the semiconductor test apparatus of the invention, temperature information Tj can be acquired in real time, compared with a target temperature Ta, and a test of a semiconductor element can be carried out. In FIGS. 64 and 67, ta, tc, and te are shown as the same time, but it goes without saying that they may be changed with time.

[0359] By turning on the power semiconductor element 17 (such as a transistor), a predetermined current flows. As shown in FIG. 67(b), the temperature of the power semiconductor element gradually rises. If the power semiconductor element 117 is in the off state, the temperature of the power semiconductor element 117 drops. When the power semiconductor element 117 reaches the target temperature Ta, the power semiconductor element 117 is turned off. If the power semiconductor element 117 exceeds the target temperature Ta, it is turned off. The present invention can confirm a failure location caused by pulse energization. The semiconductor element test apparatus of the present invention can also perform a pulse-type continuous energization test.

[0360] In the conventional continuous energization test, since a direct current is energized, it is impossible to energize up to a predetermined current for a sample with a high calorific value. With the change of the duty ratio of the pulse energization method of the present invention, it is possible to perform a test at a predetermined current density.

[0361] From the gate driver circuit 113, an on voltage Vg for turning on the gate of the transistor 117 at a set frequency and a set on voltage time is output. As an example, as shown in FIG. 46(a), the on-off cycle of the transistor 117 is tcycle, the on time is ton, and the off time is toff.

[0362] Based on the on-signal voltage Vgs in FIG. 46(a), the transistor 117 is controlled for on-off. The gate driver circuit 113 is controlled by the gate signal control circuit 112. The current power supply device 121 outputs a constant current Id and supplies it to the transistor 117.

[0363] The Vgs signal voltage output from the gate driver circuit 113 causes the transistor 117 to turn on and off. During the period when the transistor 117 is on, a current Id flows between the channels of the transistor 117.

[0364] The gate driver circuit 113 has a variable resistance circuit 125 inside. The value of the variable resistance circuit 125 is configured to be set to a predetermined value or stepwise between 0 (Ω) and 500 (Ω). While observing the waveform of the gate terminal g, the value of the variable resistance circuit 125 may be set by a control signal from the control circuit board 111.

[0365] A resistor R (not shown) may be arranged between the gate terminal g and the emitter terminal e or the collector terminal c of the transistor 117. By adjusting the value of the resistor R, the slope angles of the rising and falling voltage waveforms of the gate signal can be adjusted.

[0366] When the value of the variable resistance circuit 125 is large, the slope of the rising / falling waveform of the gate signal applied to the gate terminal of the transistor 117 becomes gentle.

[0367] On the other hand, when the resistance value of the variable resistance circuit 125 is small, the slope of the rising / falling waveform of the gate signal becomes steep. By changing the value of the variable resistance circuit 125 or setting it to a predetermined value, the on-time of the transistor 117 can be adjusted.

[0368] The gate driver circuit 113 can set the slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate voltage applied to the gate terminal g of the transistor 117. By adjusting the rise time Tr and the fall time Td separately, the on-time of the transistor 117 and the like can be adjusted arbitrarily.

[0369] The resistance value of the variable resistance circuit 125 is set by the control circuit board 111. The setting is not limited to a constant value. The slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate driver circuit 113 may be changed. The resistance value at the rising edge of the gate signal and the resistance value at the falling edge of the gate signal may be changed. Also, the resistance value may be variably controlled in real time. By variably controlling the variable resistance circuit 125, the on-time of the transistor 117 becomes stable.

[0370] When the resistance value at the rising edge of the gate signal is decreased, the waveform of the on-voltage applied to the gate terminal of the transistor 117 becomes steep, and the transistor 117 turns on at high speed. When the resistance value at the rising edge of the gate signal is increased, the waveform of the on-voltage applied to the gate terminal of the transistor 117 becomes gentle, and the transistor 117 turns on gently.

[0371] When the resistance value at the falling edge of the gate signal is decreased, the waveform of the on-voltage applied to the gate terminal of the transistor 117 becomes steep, and the transistor 117 turns off at high speed. When the resistance value at the falling edge of the gate signal is increased, the waveform of the on-voltage applied to the gate terminal of the transistor 117 becomes gentle, and the transistor 117 turns off gently.

[0372] As described above, the value of the variable resistance circuit connected to the gate terminal of the transistor 117, or the rise time / fall time of the gate driver circuit 113 can be controlled or adjusted or set. Therefore, as a function of the gate driver circuit 113, the inrush current Is and the surge voltage Vs generated in the transistor 117 can be changed or modified.

[0373] Needless to say, the operation of the transistor 117 can change or set not only the control of the on-voltage of the gate terminal of the transistor 117, but also the value of the constant current Id or the voltage Vm supplied by the current power supply device 121 to the transistor 117.

[0374] The variable resistance circuit 125 of the gate driver circuit 113 is controlled by the control circuit board 111. The period time tcycle, on-time ton, or off-time toff of the gate signal output by the gate driver circuit 113 illustrated in FIG. 46 is controlled by the gate signal control circuit 112, and the gate signal is applied to the gate terminal of the transistor 117. Further, the gate signal control circuit 112 is controlled by the control circuit board 111.

[0375] In FIGS. 44, 45, etc., the resistance value of the variable resistance circuit 125 of the gate driver circuit 113 is variable, but is not limited thereto. For example, it goes without saying that the variable resistance circuit 125 may be an external resistor, and the resistor may be connected to the gate terminal of the transistor 117 by a connector (not shown) or the like. The value of the resistor to be connected is set by observing the waveforms of the gate terminal of the transistor 117 and the channel current Id.

[0376] In FIGS. 44, 45, etc., a constant current circuit 118 is connected between the collector terminal c and the emitter terminal e of the transistor 117. The constant current circuit 118 passes a predetermined constant current Ic. The constant current Ic is for monitoring the temperature of the transistor 117.

[0377] Note that, for the purpose of description in this specification by exemplifying an IGBT, the terminals of the transistor 117 are the gate terminal g, the collector terminal c, and the emitter terminal e. In the case of the MOS transistor 117, the terminals of the transistor 117 are the gate terminal g, the drain terminal d, and the source terminal s.

[0378] A body diode or a channel diode Di is formed in the transistor 117. Note that the diode Di may be a diode of another semiconductor chip mounted on the semiconductor chip in which the transistor 117 is formed.

[0379] Diode Di may utilize a diode (parasitic diode) that is formed incidentally during the formation of transistor 117. The parasitic diode is formed incidentally due to the layer structure of transistor 117. Structurally, diode Di is formed in the vicinity of the channel portion of transistor 117.

[0380] Diode Di may be any element as long as it does not operate when transistor 117 is operating. For example, it is needless to say that it is not limited to a diode, and a transistor may be used in diode connection.

[0381] Also, it is not limited to semiconductors such as diodes, and devices such as resistors may be used. By applying a constant current Ic to a device such as a resistor, the terminal voltage of the resistor is measured. This voltage is measured as voltage Vi.

[0382] As described above, the element for obtaining the temperature may be not only a device such as a semiconductor but also a device such as a resistor. That is, any device can be applied as long as it can obtain a voltage value by passing a current or can obtain a current value by applying a voltage.

[0383] The resistance value of diode Di changes due to the heat generation of transistor 117. When a constant current Ic flows through diode Di, the voltage between the terminals of diode Di changes in proportion to the change in the resistance value of diode Di. By monitoring or measuring the voltage between the terminals, the temperature of transistor 117 or the change in temperature can be known. In order to monitor the temperature of transistor 117 from the voltage of diode Di, it is necessary to obtain the temperature coefficient in advance.

[0384] The temperature coefficient is obtained by setting the transistor 117 to a predetermined temperature in a thermostat, passing a constant current Ic through the diode Di, and measuring the terminal voltage of the diode Di. By changing the predetermined temperature and measuring the terminal voltage of the diode Di, the terminal voltage of the diode with respect to temperature can be obtained. Therefore, the temperature coefficient K of the transistor 117 can be determined from the terminal voltage of the diode Di with respect to temperature.

[0385] The temperature coefficient K may vary for each production lot of the transistor 117, but generally shows a constant value for each production lot. Therefore, if a transistor 117 for testing is extracted from each production lot and the temperature coefficient K is determined, it can also be used for the temperature coefficient K of other transistors 117.

[0386] To accurately obtain the temperature coefficient K, even within the same lot, the temperature coefficient K of each transistor 117 is individually measured and tested. The measurement of the temperature coefficient K is not limited to the use of a thermostat. For example, the temperature coefficient K is obtained by changing the water temperature flowing through the heat sink on which the transistor 117 is mounted.

[0387] During the test, a test current Id is intermittently applied to the transistor 117. Immediately after turning off the test current Id, or after turning it off and after a short predetermined time has elapsed, a constant current Ic for temperature measurement is passed from the constant current circuit 118.

[0388] To prevent the transistor 117 from generating heat due to the constant current Ic or to ensure that the constant current Ic has no influence, the constant current Ic is set to a current value that is sufficiently smaller than the constant current Id flowing through the channel of the transistor 117. The constant current Id is set to a current that does not generate heat and does not affect the temperature measurement.

[0389] Specifically, the constant current Ic is set to 1 / 1000 or less of the current Id flowing through the transistor 117 during the test. Preferably, the current Ic flowing through the transistor 117 is between 1 / 100000 and 1 / 10000 of the current Id. The constant current Ic is between 0.1 mA and 100 mA.

[0390] The channel current Id is changed, and the diode Di voltage (the voltage between the collector and emitter terminals of the transistor 117) is measured to obtain the temperature coefficient K. The obtained temperature coefficient K is stored in the temperature measurement circuit 115.

[0391] When measuring the temperature, if the diode Di is formed within the same chip as the transistor 117, the Vn voltage of the saturation voltage may change depending on the gate voltage Vgs. The gate voltage Vgs is preferably set to zero (0) voltage or a negative voltage (minus voltage).

[0392] As shown in FIG. 27, based on the temperature information Tj, the control circuit board 111 controls the chiller 136. The chiller 136 adjusts the temperature of the circulating water (circulating solution) and adjusts the temperature of the heating and cooling plate 134.

[0393] In the above embodiments, it was assumed that the temperature coefficient K was obtained in advance, but the semiconductor test method of the present invention is not limited thereto. Note that the temperature information Tj of the transistor 117 is obtained from the temperature coefficient and the diode terminal voltage, etc. The transistor 117 is disposed in close contact with the heating and cooling plate 134 so that the temperature of the heating and cooling plate 134 substantially coincides with that of the transistor 117.

[0394] The control circuit board 111 controls the chiller 136 to set the temperature of the heating and cooling plate 134 to a predetermined temperature, applies a constant current Ic to the transistor 117, and measures the terminal voltage of the diode Di.

[0395] The temperature coefficient K is obtained from the measurement results. The temperature of the heating and cooling plate 134 is set to a plurality of temperatures, the temperature coefficient K at each temperature is obtained, and the accuracy of the temperature coefficient value is improved from the results.

[0396] The temperature coefficient K is obtained by setting the temperature of the transistor 117 to a predetermined temperature using the heating and cooling plate 134, passing a constant current Ic through the diode Di, and measuring the terminal voltage. By changing the predetermined temperature and measuring the terminal voltage of the diode Di, the terminal voltage of the diode Di with respect to temperature can be obtained. Therefore, the temperature coefficient K of the transistor 117 can be determined from the terminal voltage of the diode Di with respect to temperature.

[0397] During the test of the transistor 117, the constant current Ic is passed through the diode Di when the channel current Id is not flowing. That is, when the transistor 117 is not turned on, the constant current Ic is passed through to measure the terminal voltage across the diode Di.

[0398] The operational amplifier circuit (buffer circuit) 116 outputs the terminal voltage Vi (terminal c - terminal e) of the diode Di. Note that the operational amplifier circuit 116 is not limited to being composed of operational amplifier elements. Any circuit with a high input impedance and a low output impedance may be used. The temperature measurement circuit 115 determines the temperature information Tj of the transistor 117 being tested from the temperature coefficient K and the voltage Vi that are being held.

[0399] The obtained temperature information Tj is sent to the control circuit board 111. When the temperature information Tj becomes equal to or higher than a predetermined set value, the control circuit board 111 determines that the transistor 117 is in a predetermined stress state or a deteriorated state, and performs control changes for the test or stops the test, etc.

[0400] The location where the transistor deteriorates during the test is mainly the junction within the transistor 117. The semiconductor itself does not deteriorate, but the junction (bonding, die bond, etc.) of the transistor 117 deteriorates, increasing the resistance value of the junction. As the resistance value increases, the voltage Vce increases, generating heat and raising the temperature of the transistor 117.

[0401] When the semiconductor deteriorates, it is often due to the deterioration of the gate oxide film (insulating film) of transistor 117. When the deterioration of the gate oxide film occurs, the oxide film (insulating film) is in a short-circuit state, and the voltage Vce decreases. Or, transistor 117 turns off, no current flows through transistor 117, and the voltage Vce rises to the maximum value of the power supply voltage.

[0402] The temperature information Tj changes between the minimum temperature T1 and the maximum temperature T2 at the start of the test. When stress is applied to transistor 117 by the test, the Vce voltage of transistor 117 changes, and usually changes in the direction of increasing the temperature information Tj. Therefore, as shown in FIG. 47(c), the minimum temperature rises above temperature T1, and the maximum temperature approaches the temperature information Tm (Tjmax). In the semiconductor test method of the present invention, the test ends when any of the following conditions is met. · When the temperature information Tj deviates from the predetermined range. · When the channel voltage Vce deviates from the predetermined voltage range. · When the thermal resistance deviates from the predetermined range.

[0403] In the embodiments of FIGS. 44, 45, etc., the switch circuits Ssa124a and Sab124b use the symbols of switch circuits. Any element can be used as the switch circuit as long as the resistance (on-resistance) when the switch circuits Ssa124a and Sab124b are closed (on) is small. For example, transistors, mechanical relays, phototransistors, photodiode switches, etc. are exemplified.

[0404] FIG. 45 is an equivalent circuit diagram of the semiconductor test apparatus in the first embodiment of the present invention. In this embodiment, the switch circuits Ssa and Sab use the power MOSFET 124 as shown in FIG. 45. The power MOSFET has a small voltage (Vsd) between channels.

[0405] Note that, as the switch circuit, components other than the power MOSFET may be adopted. Needless to say, the switch circuits Ssa and Sab may be not only power MOSFETs but also power transistors or the like. In addition, electromagnetic relays, electromagnetic switches, etc. are also exemplified.

[0406] The channel voltage (Vsdb) of the power MOSFET 124b when it is on is selected to be equal to or lower than the channel voltage (Vsda) of the power MOSFET 124a when it is on. That is, the channel voltage (Vsdb) of the power MOSFET 124b when it is on is made smaller than the channel voltage (Vsda) of the power MOSFET 124a when it is on. This is to completely short-circuit between the terminals of the current power supply device 121 and stably flow the current Im when the switch circuit 124b is turned on. The above matters are the same even when the switch circuit 124 is a power transistor or the like. In the case of the power transistor 124, the channel voltage is Vce. When the switch circuit 124a is turned on, the current Id output by the current power supply device 121 can be supplied to the transistor 117 as a test current.

[0407] The switch circuit 124 is mounted on the switch circuit board 201. The switch circuit 124 is connected to a conductor plate 204 (metal plate, conductive plate). The conductor plate 204 is, for example, a copper plate with a thickness of 5 mm and a width of 50 mm. The length has the width of the circuit board + the width for connecting the fork plug 205.

[0408] FIG. 31 illustrates the fork plug 205 and the connection (contact) state between the fork plug 205 and the conductor plate 204. Two conductor plates 204 are attached to the switch circuit board 201. The switch circuit board 201 has a full-surface ground layer (not shown), and the full-surface ground layer and the conductor plate 204 are thermally connected. The heat of the conductor plate 204 is dissipated through the full-surface ground layer. The conductor plate 204 and the switch circuit board 201 are screwed together.

[0409] The switch circuit 124 is connected to two conductor plates. When the switch circuit 124 is a MOS transistor as shown in FIG. 45, the drain terminal and the source terminal are connected to different conductor plates 204. When the switch circuit 124 is a bipolar transistor, the collector terminal and the emitter terminal are connected to different conductor plates 204. When the switch circuit 124 is turned on (conducted), the two conductor plates 204 are electrically connected. An IGBT can also be used as the switch circuit 124.

[0410] The fork plug 205 and the conductor plate 204 are electrically connected by being mechanically fitted. When the U-shaped portion of the fork plug 205 is inserted into the conductor plate 204, the U-shaped portion slightly expands, and the fork plug 205 and the conductor plate 204 are well joined. By being well joined or fitted, the electrical resistance of the connection portion becomes extremely small, and even when a large current flows through the connection portion, heat generation or voltage drop does not occur.

[0411] A connection bolt 219 is attached to the fork plug 205. A connection wiring 211 is connected to the connection bolt 219. The cross-section at AA' in FIG. 31(a) is shown in FIG. 31(b). The conductor plate 204 and the fork plug 205 are contacted at contact portions 220a and 220b formed on the fork plug 205. The surface of the contact portion 220 is silver-plated. The contact portion 220 is made of phosphor bronze and nickel alloy. Note that the connection bolt 219 is not limited to a bolt, and any thing may be used as long as the fork plug 205 and the wire can be electrically connected. The surface of the conductor plate 204 is silver-plated at least at the portion that contacts the fork plug 205.

[0412] FIG. 30 is a configuration diagram of the semiconductor test apparatus of the present invention. A connection structure 218a is inserted into the opening 216a of the partition wall 217, and a connection structure 218b is inserted into the opening 216b of the partition wall 217.

[0413] The connection structure 218a is connected to the connection part 507a of the transistor 117, and the connection structure 218b is connected to the connection part 507b of the transistor 117. A circulating water pipe 135 is incorporated in the heating and cooling plate 134.

[0414] A connector 202 is connected to the terminal of the transistor 117, and a signal wiring 222 connected to the connector 202 is connected to the sample connection circuit 203. The signal wiring 235 of the sample connection circuit 203 is connected to the device control circuit board 209 via the connector 208.

[0415] The fork plug 205 and the conductor plate 204 are brought into contact by inserting the fork plug 205 through the opening 216 of the partition wall 214 as shown in FIG. 30 and the like. At the time of contact, the U portion of the fork plug 205 is expanded by the conductor plate 204 and brought into firm contact.

[0416] FIG. 29 shows an arrangement diagram of each component of the semiconductor test apparatus of the present invention. The housing 210 of the semiconductor test apparatus is separated into three parts. The lower part of the housing is separated into an A chamber and a B chamber. A power supply device 132 is arranged in the A chamber. The A chamber and the B chamber are separated by a partition wall 215.

[0417] Each chamber is shielded. The power supply device 132, the switch circuit board 201, and the transistor 117 generate large noise by repeating operation / non-operation. Since the circuit board and the like malfunction due to the noise, malfunction is prevented by shielding. The shielding is realized by arranging a conductive plate, a metal plate, and a metal film around each chamber.

[0418] In the C1 chamber, a heating and cooling plate 134, a circulating water pipe 135, etc. shown in FIG. 27 are arranged, and a transistor 117 to be tested is arranged on the heating and cooling plate 134.

[0419] A partition wall 214 is formed between Chamber C1 and Chambers A and B. A water leakage sensor (not shown) is arranged around the heating and cooling plate in Chamber C1. When circulating water (cooling medium) or the like leaks, the water leakage sensor operates to stop the semiconductor test apparatus or issue an alarm.

[0420] In addition, a drain groove is formed around the heating and cooling plate. When circulating water (cooling medium) leaks from the heating and cooling plate, the circulating water (cooling medium) flows into the drain groove and is discharged outside the semiconductor test apparatus. As described above, the partition wall 214 is configured such that even if the circulating water pipe 135 is damaged, circulating water (cooling medium) or the like does not leak into the lower Chambers A and B.

[0421] A partition wall 215 is formed between Chamber A where the power supply device 132 is arranged and Chamber B where the drive circuit system is arranged. Electrostatic shielding plates are arranged on the partition walls 214, 215, and 217 to shield the noise of the power supply device 132, and the noise is not applied to the drive circuit system in Chamber B.

[0422] In the embodiment of the present invention, it will be described that the fork plug 205 is inserted from Chamber C2 and connected to the conductor plate 204 in Chamber B. The operation of pushing the fork plug 205 from the upper side to the lower side is easy. However, the present invention is not limited to this. For example, the conductor plate 204 may be arranged in Chamber C2, and the fork plug 205 may be inserted from Chamber B and electrically connected. In addition, the connection structure 218 is inserted from Chamber C2, and the connection portion 507 of the semiconductor element 117 and the connection structure 218 are connected.

[0423] As shown in FIG. 29 and the like, the connection structure 218 is inserted from the C2 chamber into the C1 chamber and electrically connected to the connection portion 507 of the transistor 117. Further, the fork plug 205 is inserted from the C2 chamber into the B chamber to electrically connect the fork plug 205 and the conductor plate 204. The transistor 117 is fixed to the heating and cooling plate 134, and the switch circuit board 201 is fixed at the position of the mother board 207. The connection structure 218 and the fork plug 205 are electrically connected by the connection wiring 211.

[0424] The position of the opening 216 can be selected by the connection structure 218, and the transistor 117 to be tested can be selected. By selecting the opening into which the fork plug 205 is inserted, the switch circuit board 201 that can be easily controlled can be selected, and the test method and test conditions can be changed. Therefore, according to the present invention, by using the connection structure 218 and the fork plug 205, the transistor 117 can be easily selected, and changes in the test method and the like can be implemented in a short time.

[0425] Examples of the partition walls 214, 215, and 217 include wall-like structures, plate-like structures, film-like objects, mesh-like objects, wire mesh-like objects, and the like. As an example, phenolic resin (phenolic resin, phenol-formaldehyde resin, carbolic acid resin) is exemplified. The partition wall may be any object as long as it separates the first part and the second part of the semiconductor test device.

[0426] As shown in FIG. 28, a connector 213 is attached to the mother board 207. The control circuit board 111, the device control circuit board 209, and the switch circuit board 201 are attached to the connector of the mother board 207. The switch circuit board 201 to be prepared according to the number of transistors 117 to be tested can be easily realized by changing the number of switch circuit boards 201 attached to the mother board 207.

[0427] The gate terminal g, collector terminal c, emitter terminal e, etc. of the semiconductor element 117 are electrically connected by the anisotropic conductive rubber 504a. As shown in FIG. 22, the electrical connection is performed by a pressing head 530 or the like.

[0428] Temperature information Tj, voltage Vi, control signals of the variable resistance circuit 125, control signals of the constant current circuit 118, etc. are transmitted to the mother board 207. Also, power supply wirings and ground wirings of each circuit are formed and supplied to each circuit board via the connector 213. The conductor plate 204 is arranged so as to protrude from the switch circuit board 201. A fork plug 205 is connected to this protruding portion.

[0429] The fork plug 205a is connected to the conductor plate 204a of the switch circuit board 201a. The power supply wiring 212 is connected to the switch circuit board 201a through the opening 216 of the partition wall 215. The fork plug 205d is connected to the conductor plate 204c of the switch circuit board 201b. The power supply wiring 212 is connected to the switch circuit board 201b through the opening 216 of the partition wall 215. The fork plug 205b is connected to the conductor plate 204b of the switch circuit board 201a. The power supply wiring 212 is connected to the switch circuit board 201a through the opening 216 of the partition wall 215.

[0430] As shown in FIG. 44 etc., a switch circuit 124a is arranged between the conductor plate 204d and the conductor plate 204c of the switch circuit board 201b to short-circuit between the conductor plate 204d and the conductor plate 204c. By short-circuiting, the current Id output from the current power supply device 121 is supplied to the transistor 117 as a test current.

[0431] A switch circuit 124b is arranged between a conductor plate 204a and a conductor plate 204b of a switch circuit board 201a. When the switch circuit 124b is turned on, the conductor plate 204a and the conductor plate 204b are short-circuited. By short-circuiting, the current Id output by the current power supply device 121 flows to the ground as a discharge current Im, and the channels of the transistor 117 are short-circuited. When the channels are short-circuited, no overvoltage or overcurrent is applied to the transistor 117.

[0432] A fork plug 205 is connected to the conductor plate 204. A fork plug 205c is connected to the conductor plate 204b. A fork plug 205b is connected to the conductor plate 204a. Also, a fork plug 205e is connected to the conductor plate 204d. A fork plug 205d is connected to the conductor plate 204c.

[0433] FIG. 31 is a configuration diagram of the fork plug 205. FIG. 31(a) shows a state in which the conductor plate 204 attached to the switch circuit board 201 and the fork plug 205 are coupled. FIG. 31(b) shows the coupling state of the conductor plate 204 and the fork plug 205 when viewed from the arrow direction in the cross-section taken along the line AA' of FIG. 31(a).

[0434] The material of the fork plug 205 is made of a metal such as aluminum, stainless steel, or copper. Also, the surface is nickel-treated as a base and then silver-plated. The fork flag 205 is formed with a screw groove so that the connection wiring 211 can be attached to the fork plug 205 with a connection bolt 219.

[0435] The convex contact portion 220 is made of phosphor bronze or a copper alloy. Also, the surface of the contact portion 220 is silver-plated. The insertion force of the fork plug 205 into the conductor plate 204 is configured to be 40 N or more and 60 N or less.

[0436] As the contact portion 220, platinum, gold, silver, tungsten, copper, nickel, or an alloy combining them is used. Also, it is preferable to use a silver-oxide contact material (Ag + ZnO, Ag + SnO2, Ag + SnO2In2O3, Ag +, Ag + SnO2Sn2Bi2O7).

[0437] In Fig. 28, two switch circuit boards 201 are illustrated. However, depending on the number of transistors 117 to be tested, two or more switch circuit boards 201 are required, and the switch circuit boards 201 are connected to the connectors 213 of the mother board 207.

[0438] As shown in Fig. 30, the fork plug 205c is inserted from the opening 216 of the partition wall 214 provided between the C2 chamber and the B chamber, and the conductor plate 204b and the fork plug 205c are connected. In the C1 chamber, the transistor 117 to be tested and the heating / cooling plate 134 are arranged, and in the B chamber, a drive circuit for testing the transistor 117 and the like are arranged. Since the C1 chamber, the C2 chamber, and the B chamber are separated by the partition wall 214, even if the refrigerant liquid leaks from the heating / cooling plate 134, it will not leak into the B chamber. Note that a water leakage sensor (not shown) is arranged around the heating / cooling plate 134. Also, when the coolant flows out, a groove for discharging the coolant outside the test device is formed. An electrostatic shielding plate is arranged on the partition wall 214 so that the drive circuit system in the B chamber does not malfunction due to noise generated from the transistor 117.

[0439] Since the current flowing through the transistor 117 to be tested is as large as several hundred amperes, the thickness of the connection wiring 211 to be used is also thick. Therefore, the connection wiring 211 has no slidability, and the connection wiring 211 is hard, making it not easy to change the connection of the connection wiring 211.

[0440] In the semiconductor test apparatus of the present invention, it can be connected to the switch circuit board 201 by the fork plug 205 inserted from the C2 chamber. Therefore, to change the connection to the switch circuit board 201 used according to the test conditions of the transistor 117, it is not necessary to change the connection wiring of the connection wiring 211, and only the position of the opening 216 where the fork plug 205 is inserted needs to be changed. Also, for the switch circuit board 201, it is only necessary to change the position of the connector 213 connected to the mother board 207.

[0441] As shown in FIGS. 28, 29, 30, 31, 33, 34, 38, 44, 45, etc., the connection wiring 211b connected to the transistor 117 is connected to the fork plug 205c. The connection wiring 211a connected to the transistor 117 is connected to the fork plug 205e.

[0442] Even if there are a plurality of transistors 117 to be tested, one switch circuit board 201a is sufficient for use. This is because the output current Id of the current power supply device 121 can be made to flow to the ground line as Im.

[0443] The switch circuit board 201b is required according to the number of transistors 117 to be tested. For example, if there are 12 transistors 117 to be tested, it is preferable to prepare 12 switch circuit boards 201b. It is also cost-effective to make the switch circuit board 201a and the switch circuit board 201b have the same specifications.

[0444] A plurality of transistors or the like as the switch circuit 124 are mounted on the switch circuit board 201. The larger the number of the switch circuits 124, the smaller the impedance for short-circuiting between the two conductor plates 204. The number of the switch circuits 124b mounted on the switch circuit board 201a is determined so that the on-resistance of the switch circuit 124b is smaller than the on-resistance of the transistor 117 to be tested.

[0445] Figs. 33 and 34 illustrate the state in which the fork plug 205 is inserted into the opening 216 of the partition wall 214. Fig. 33 is a view seen from the surface of the partition wall 214, and Fig. 34 is a view seen from the back surface of the partition wall 214.

[0446] As an example, a fork plug 205b and a plurality of fork plugs 205c (fork plugs 205c1 to 205c5) are connected to the conductor plate 204b in Fig. 33. A fork plug 205e1 is connected to the conductor plate 204d1, a fork plug 205e2 is connected to the conductor plate 204d2, a fork plug 205e3 is connected to the conductor plate 204d3, a fork plug 205e4 is connected to the conductor plate 204d4, and a fork plug 205e5 is connected to the conductor plate 204d5.

[0447] Test transistors 117 are respectively connected between the fork plug 205c and the fork plug 205e. Switch circuit boards 201b corresponding to the number of test transistors 117 are mounted on the mother board 207. The opening 216 is formed corresponding to the position of the conductor plate 204 of the switch circuit board 201.

[0448] Although not shown, a large amount of noise is generated when the switch circuit 124 of the switch circuit board 201 is turned on and off. As a countermeasure, a metal plate is arranged between the switch circuit boards 201, and the metal plate is grounded.

[0449] In each drawing, one switch circuit 124 is shown on the switch circuit board 201. However, actually, a plurality of switch circuits 124 are arranged between the conductor plates 204. By arranging a plurality of switch circuits 124 on the switch circuit board 201, the space between the conductor plates 204 (for example, between the conductor plates 204c and 204e) can be short-circuited with low resistance.

[0450] The heat generated by the switch circuit 124 is dissipated to the conductor plate 204. In addition, a heat sink is attached to the switch circuit 124. The ground terminal of the switch circuit 124 is connected to the ground of the switch circuit board 201, and heat is also dissipated through the ground copper foil.

[0451] As shown in FIG. 29, two conductor plates 204 are attached to the switch circuit board 201, and the switch circuit 124 is arranged so as to short-circuit the two conductor plates 204. Further, FIG. 44 is an equivalent circuit diagram of the semiconductor test apparatus of the present invention in the first embodiment.

[0452] As shown in FIGS. 29, 30, etc., conductor plates 204a and 204b are attached to the switch circuit board 201a. The conductor plate 204a is connected to the fork plug 205a. The fork plug 205a is connected to the output terminal of the current power supply device 121. The conductor plate 204b is connected to the fork plug 205b. The fork plug 205b is connected to the ground terminal of the current power supply device 121.

[0453] When the switch circuit 124b is turned on, the output terminals of the current power supply device 121 are short-circuited, and a short-circuit current Im flows. Therefore, the output current of the current power supply device 121 is not supplied to the transistor 117. When the switch circuit 124b is open, the output current Id of the current power supply device 121 is supplied to the transistor 117.

[0454] Conductor plates 204c and 204d are attached to the switch circuit board 201b. The conductor plate 204c is connected to the fork plug 205d. The fork plug 205d is connected to the output terminal of the current power supply device 121. The conductor plate 204d is connected to the fork plug 205e. The fork plug 205e is connected to the collector terminal of the transistor 117 for performing the test.

[0455] As shown in FIGS. 29, 30, 33, 34, etc., the fork plug 205e is inserted into the opening 216 opened in the partition wall 214 and is coupled to the conductor plate 204d. Further, the fork plug 205c is inserted into the opening 216 opened in the partition wall 214 and is coupled to the conductor plate 204d.

[0456] A switch circuit 124a is arranged on a switch circuit board 201b. When the switch circuit 124a is turned on, an output current Id from a current power supply device 121 is supplied to a transistor 117 as a test current flowing through the transistor 117.

[0457] The switch circuit board 201b is arranged in the B chamber of the housing 210. However, a fork plug 205 inserted from an opening 216 of a partition wall 214 from the C2 chamber electrically connects the switch circuit board 201b and the transistor 117 for performing a test.

[0458] As shown in FIGS. 29, 30, 33, 34, etc., the fork plug 205 and a conductor plate 204 are connected. In FIG. 30, the switch circuit board 201 is illustrated as being arranged in parallel. Actually, the switch circuit board 201 is inserted and arranged in parallel with a board rack. A mother board is arranged on a side surface of the board rack, and a control signal to each circuit board is applied from the mother board.

[0459] FIG. 46 is an explanatory diagram of a method for testing a semiconductor element according to the first embodiment. In FIG. 46, Vgs is a gate signal applied to a gate terminal of the transistor 117 to be tested. Id is a current flowing through the transistor 117 during the test. For the sake of easy explanation, it is assumed that a constant current Ia flows when the transistor 117 is turned on.

[0460] In FIG. 46(c), St1 is a timing signal for flowing a current Ic through a diode Di. When St1 is at the H level, a current flows through the diode Di of the transistor 117. An operational amplifier circuit 116 acquires a terminal voltage of the diode Di, and a temperature measurement circuit 115 converts the terminal voltage into temperature information Tj. The temperature information Tj is sent to a control circuit board 111, and the control circuit board 111 performs a test on the transistor 117 (semiconductor element 117) according to the temperature information Tj.

[0461] Id is the current flowing through the transistor 117 for which the test is being conducted, and it is the current output by the current power supply device 121. St1 and St2 are the time for which the measurement current is passed through the diodes for temperature measurement or the measurement time of the temperature. In FIG. 46(e), Ssa is the on / off signal of the switch circuit 124a, and in FIG. 46(f), Sab is the on / off signal of the switch circuit 124b.

[0462] In FIG. 46(g), Vce is the voltage at the c terminal of the transistor 117 (channel voltage of the transistor 117), and the temperature information Tj indicates the measured temperature change of the transistor 117.

[0463] As shown in FIG. 46(a), the gate signal Vgs is applied from the gate driver circuit 113 to the gate terminal g of the transistor 117. The gate signal Vgs has a cycle time tcycle and an on time ton. The cycle time tcycle and the on time ton can be set to arbitrary values by the gate signal control circuit 112. Also, the on voltage Vg can be set to an arbitrary voltage.

[0464] In FIG. 46(d), in the embodiment shown in FIG. 49, St2 is the timing signal for passing the current Ic through the diodes Dsa and Dsb. When St2 is at the H level, current flows through the diode Dsa or Dsb of the transistor 117. This is the case where a constant current Ic is passed through a device (diode) independent of the transistor 117 to obtain the temperature information Tj.

[0465] The operational amplifier circuit 116 acquires the voltage between the terminals of the diode Dsa or Dsb, and the temperature measurement circuit 115 converts the voltage between the terminals into the temperature information Tj. The temperature information Tj is sent to the control circuit board 111, and the control circuit board 111 conducts a test on the transistor 117 based on the temperature information Tj. Note that matters related to St2 will be described with reference to FIG. 49 and the like.

[0466] For ease of understanding, the measured temperature information Tj is described as changing between T1 and T2 as shown in FIG. 46(h). The temperature information Tj increases when the transistor 117 is energized and decreases when the current for energization stops. Also, the temperature information Tj changes with the change in the characteristics of the transistor 117.

[0467] FIG. 46(e) Ssa indicates the timing of the on / off control signal of the switch circuit Ssa. When Ssa becomes Von, the switch circuit Ssa closes (turns on). When it is 0, the switch circuit Ssa opens (turns off), and the application of current or voltage is cut off.

[0468] FIG. 46(f) Ssb indicates the timing of the on / off control signal of the switch circuit Ssb. When Ssb becomes Von, the switch circuit Ssb closes (turns on). When it is 0, the switch circuit Ssb opens (turns off).

[0469] FIG. 46(g) Vce is the channel voltage (voltage between the emitter terminal and the collector terminal) of the transistor 117. When the transistor 117 turns on and off, a surge voltage and a surge current are generated, and the Vce waveform changes temporally in a complex manner with the change in the on-resistance of the transistor 117. Also, when a current Ic flows through the diode Di, the Vce waveform of the transistor 117 changes.

[0470] In this specification and the drawings, for ease of explanation or for ease of drawing, it is described that when the transistor 117 is on, the voltage becomes Vn, and when the transistor is off, the voltage becomes Ve. The gate signal is applied to the gate terminal of the transistor 117 that is tested with a cycle tcycle, an on-time ton, and an off-time toff.

[0471] When the transistor 117 is an N-channel, the gate signal Vgs has a ground (GND) voltage of 0 (V) as the off-voltage and Vg as the on-voltage. When the transistor 117 is a P-channel, the potentials of the on-voltage and the off-voltage are changed.

[0472] Before turning on the transistor 117, the tn2 period is set to a Vt voltage that is negative with respect to the off voltage. Also, after turning off the transistor 117, the tn1 period is set to a Vt voltage that is negative with respect to the off voltage. The Vt voltage is lower than 0 (V) and higher than -4 (V). Therefore, Vt is a voltage that is -4 (V) or higher and lower than 0 (V).

[0473] When the transistor 117 is made of SiC, the off voltage is set to the Vt voltage, and when it is an IGBT, the off voltage is set to 0 (V). As described above, the semiconductor test apparatus of the present invention is configured so that the off voltage supplied to the transistor 117 can be changed according to the type of the transistor 117 to be tested.

[0474] When the Vt voltage is applied, St1 (St2) is set to the H level and the temperature of the transistor 117 is measured. A constant current Ic is passed through the diode Di during the period when the Vt voltage is applied. Also, a constant current Ic is passed through during the period when St1 (St2) is at the H level.

[0475] By applying the Vt voltage to the gate terminal of the transistor 117, the off state of the transistor 117 is stabilized, and the measurement of the temperature information Tj can be stably performed. Also, noise is less likely to be superimposed during the measurement of the temperature information Tj, and the measurement accuracy of the temperature information Tj is improved.

[0476] By applying the Vt voltage to the gate terminal of the transistor 117, the leakage current of the transistor 117 is reduced, the measurement accuracy of the Vi voltage is improved, and the measurement is stabilized.

[0477] The gate signal Vgs is set to the Vt voltage at the times of tn1 and tn2. As an example, the times of tn1 and tn2 are times that are 0.2 msec or more and 2 msec or less. The transistor 117 turns off at 0 (V).

[0478] Therefore, three voltages, namely Vg, 0 (V), and Vt, are applied to the gate terminal g of the transistor 117. During the period when Vt is applied, a current is passed through the diode Di of the transistor to measure the temperature information Tj.

[0479] When passing a constant current Ic through the diode Di, the switch circuit Ssa is turned off so that the current from the current power supply device 121 is not applied to the transistor 117.

[0480] By passing a constant current Ic through the diode Di, the terminal voltage of the diode Di is obtained, and the operational amplifier circuit 116 outputs a Vi voltage corresponding to the terminal voltage. The Vi voltage is input to the temperature measurement circuit 115, and the temperature measurement circuit 115 obtains temperature information Tj corresponding to the temperature of the transistor 117.

[0481] The temperature information Tj is transferred to the control circuit board 111, and the control circuit board 111 controls the test of the transistor 117 (semiconductor element 117), such as continuing, stopping, and changing conditions of the test of the transistor 117, based on the temperature information Tj.

[0482] In FIG. 46(e), Ssa is a timing signal for controlling the on / off of the switch circuit 124a. In FIG. 46(f), Ssb is a timing signal for controlling the on / off of the switch circuit 124b.

[0483] The switch circuit 124a turns on with a delay of tm2 hours after the Vgs signal of the transistor 117 becomes Vg. The tm2 hours is configured to be changeable by the control circuit board 111.

[0484] The switch circuit 124b turns on tb2 hours before the switch circuit 124a turns on. The on state of the switch circuit 124b is maintained until tb1 hours after the switch circuit 124a turns on. The tb2 hours and tb1 hours are configured to be independently changeable. In particular, the setting of tb1 is important. The time of tb1 is observed from the waveform of the Vce voltage of the transistor 117 and set or changed appropriately.

[0485] The switch circuit 124a turns off tm1 hours before the Vgs signal of the transistor 117 reaches Vt. The tm1 hours is configured to be changeable by the control circuit board 111.

[0486] The switch circuit 124b turns on ta2 hours before the switch circuit 124a turns off. The on state of the switch circuit 124b is maintained for ta1 hours after the switch circuit 124a turns off. The ta2 hours and ta1 hours are configured to be independently changeable. In particular, the setting of ta1 is important. The ta1 time is set or changed appropriately by observing or measuring the waveform of the Vce voltage of the transistor 117.

[0487] When the switch circuit Ssb turns on, the output terminal of the current power supply device 121 is short-circuited to the ground (ground line), and the charge is discharged. When the charge is discharged, the terminal voltage of the current power supply device 121 becomes 0 V (ground voltage). Also, the current Id output by the current power supply device 121 is made to flow to the ground (ground) as the current Im. Therefore, the current Ia is not applied to the transistor 117, and the collector voltage of the transistor 117 does not increase.

[0488] The tb2 hours is set by observing or measuring the time when the output voltage of the current power supply device 121 becomes 0 V or near 0 V, or the time when the output voltage of the current power supply device 121 is lower than the collector voltage of the transistor 117.

[0489] At the time when the above voltage relationship reaches a predetermined value (after tb2 has elapsed), the switch circuit 124a is turned on to apply the current Id from the current power supply device 121. However, at this time, since the switch circuit 124b is on, the current Id from the current power supply device 121 flows to the ground (ground line) as the current Im through the switch circuit 124b. Therefore, a constant current Id does not flow through the transistor 117. After the switch circuit 124a is turned on and tb1 hours have elapsed, the switch circuit 124b is turned off, and the test current Id is supplied to the transistor 117. As shown in FIG. 46, the test current Id is supplied to the transistor 117 in synchronization with the switch circuit 124a.

[0490] By operating the switch circuits 124a and 124b as described above, a surge voltage Vs or an inrush current Is is not applied to the transistor 117. Alternatively, the surge voltage Vs or the inrush current Is is suppressed, and a good test of the transistor 117 can be performed.

[0491] When stopping the test current Id to the transistor 117, the switch circuit 124b is turned on before ta2 when the switch circuit 124a is turned off. The constant current Id output by the current power supply device 121 flows to the ground as the current Im via the switch circuit Ssb and is not supplied to the transistor 117.

[0492] The ta2 time is set by observing the time when the output voltage of the current power supply device 121 becomes 0 (V) or near 0 (V), or the time when the output voltage of the current power supply device 121 is lower than the collector voltage of the transistor 117.

[0493] At the time when the above voltage relationship reaches a predetermined value (after ta2 has elapsed), the switch circuit 124a is turned off. After the switch circuit 124a is turned off and ta1 hours have elapsed, the switch circuit 124b is turned off.

[0494] By operating or controlling the switch circuits 124a and 124b as described above, a surge voltage Vs or an inrush current Is is not applied to the transistor 117. Alternatively, the surge voltage Vs or the inrush current Is is suppressed, and a good test of the transistor 117 can be performed.

[0495] When a constant current Id is supplied to the transistor 117, the temperature information Tj rises. When the supply of the constant current Id to the transistor 117 stops, the temperature information Tj falls. The temperature information Tj varies between T1 and T2. When the characteristics of the transistor 117 vary due to a test, the temperature information Tj gradually rises. To apply a current Id of a constant value to the transistor 117, operate the current power supply device 121 to apply the current Id to the transistor 117.

[0496] As shown in FIGS. 44, 45, 47, 49, 50, etc., the resistance value of the variable resistance circuit 125 of the gate driver circuit 113 can also be set. By increasing the resistance value, the rising / falling waveform of the gate signal Vgs can be changed as shown by the dotted line or the dashed-dotted line in FIG. 47(a).

[0497] Due to the change or setting of the gate signal Vgs, the current Id flowing through the transistor 117 can also be changed as shown by the dotted line or the dashed-dotted line in FIG. 47(b). By changing the rising waveform and the falling waveform of the current Id, the surge voltage or the inrush current can be adjusted or suppressed.

[0498] As shown in FIG. 47(c), as the characteristics of the transistor 117 change due to a test, the temperature information Tj changes from the solid line to the dotted line and from the dotted line to the dashed-dotted line. When the temperature information Tj reaches the level of Tm, the test is stopped. Alternatively, when the change rate of the temperature information Tj reaches a predetermined value, the test is stopped. Also, the test conditions are changed.

[0499] As shown in FIG. 48, when the switch circuit Ssa (switch circuit 124a) is in the off state, set the St1 signal to H and measure the temperature information Tj. The St1 signal is set to the H level when the gate signal is Vt. During the tn2 period, set it to the H level during the tc2 period and measure the temperature information Tj. During the tn1 period, measure the temperature information Tj during the tc1 period.

[0500] The temperature information Tj measured during the tc2 period is the temperature information Tj at the time when the transistor 117 is cooled. The temperature information Tj measured during the tc1 period is the temperature information Tj immediately after the current Id is stopped in the transistor 117. The stop of the test, the change of conditions, the change of control, etc. are determined based on the temperature information Tj measured during the tc2 period and the temperature information Tj measured during the tc1 period.

[0501] When the rate of change of the temperature information Tj measured during the tc1 period is large compared to the temperature information Tj measured during the tc2 period, or when the absolute value difference between the temperature information Tj measured during the tc1 period and the temperature information Tj measured during the tc2 period is large, etc., the test is controlled and changed corresponding to the measured value temperature information Tj.

[0502] Also, when the temperature information Tj measured during the tc2 period is different from the standard value and the predetermined value, it is determined whether there is a problem with the connection state of the transistor 117 and the test apparatus, and a determination such as "not starting the test" is made. During the tc2 or tc1 period, Vi is measured multiple times, and the temperature information Tj for Vi is obtained.

[0503] The embodiment of FIG. 49 is a semiconductor test apparatus in the second embodiment of the present invention. In the transistor 117 in FIG. 49, a diode Ds (diode Dsa, diode Dsb) for temperature measurement is separately provided. Note that the diode Ds is formed in the same process as the transistor 117.

[0504] In the embodiment of FIG. 49, the temperature information Tj is measured at the timing of the St2 signal in FIG. 46(d). When the switch circuit Ssa (switch circuit 124a) is in the off state, the St2 signal is set to H, and the temperature information Tj is measured. During the tn2 period, the temperature information Tj is measured by setting it to the H level during the tc2 period. During the tc1 period, the temperature information Tj may be measured during either the ton period or the tn1 period. The temperature information Tj measured during the tc2 period and the temperature information Tj measured during the tc1 period are averaged to obtain the temperature information Tj.

[0505] During the tc2 or tc1 period, Vi is measured multiple times, and temperature information Tj for Vi is obtained. The operations of other signals or the switch circuit in FIG. 46 are the same as or similar to those in the embodiments described in FIG. 28 and the like. The above embodiments were embodiments in which temperature information Tj was measured using a diode added to or formed on the transistor 117. In the embodiment of FIG. 49, a diode Ds that is not connected to the transistor (independent) is formed on the transistor 117.

[0506] The diode Dsa is formed in a direction in which a constant current Ic flows. The diode Dsb is formed in a direction in which a constant current Ic' flows. The constant current circuit 118 (Pc) generates the constant current Ic and the constant current Ic'.

[0507] The diodes Dsa and Dsb are diodes for temperature measurement. The structures of the diodes Dsa and Dsb are similar to or the same as the diode Di in FIG. 28 and the like.

[0508] The diode Di is connected to the terminals (terminal c, terminal e) of the transistor 117, while the diodes Dsa and Dsb are not connected to the terminals of the transistor 117 and are connected to independent terminals. The diode Di measures the temperature information Tj at the timing of St1 in FIG. 46(c), while the diodes Dsa and Dsb measure the temperature information Tj at the timing of St2 in FIG. 46(d). Except for this, they have the same operation or the same configuration.

[0509] In the embodiment of FIG. 49, the diode Ds is separated from the path through which the constant current Id flows. Even when a current Id is flowing through the transistor 117, a constant current Ic can be made to flow through the diode. Therefore, the time for measuring the temperature information Tj can be freely set. As shown in FIG. 46(d), the positions of tc1 and tc2 can be set.

[0510] However, in the case of tc2, as shown in FIG. 46(d), it is arranged or set during the period when the gate signal is Vt. The temperature information Tj measured during the period of tc2 is used as the value before the operation of the transistor 117. The period of tc1 is preferably just before the constant current Id of the transistor 117 is stopped. Note that it may also be immediately after the constant current Id is stopped. It is preferable that "just before" and "immediately after" mean within 1 millisecond. St2 in FIG. 46(d) is a timing signal for flowing the current Ic (or current Ic') of the diode Ds (Dsa, Dsb).

[0511] When St2 is at the H level, current flows through the diode Ds (Dsa, Dsb) of the transistor 117. The operational amplifier circuit 116 acquires the voltage between the terminals of the diode Ds, and the temperature measurement circuit 115 converts the voltage between the terminals into temperature information Tj.

[0512] The temperature information Tj is sent to the control circuit board 111, and the control circuit board 111 conducts, stops, or changes the control of the test of the transistor 117 according to the temperature information Tj.

[0513] When St2 is at the H level, the constant current circuit 118 flows a constant current Ic, and the constant current Ic flows through the diode Dsa. Also, the constant current circuit 118 flows a constant current Ic', and the constant current Ic' flows through the diode Dsb.

[0514] The constant current Ic and the constant current Ic' are currents of the same magnitude. However, when the threshold voltages of the diode Dsa and the diode Dsb are different, or when the characteristics of the diode Dsa and the diode Dsb are different, etc., it is preferable to make the magnitudes of the constant current Ic and the constant current Ic' different.

[0515] The operational amplifier circuit 116 acquires the voltage between the terminals of the diode Dsa or Dsb, and the temperature measurement circuit 115 converts the voltage between the terminals into temperature information Tj. The temperature information Tj is sent to the control circuit board 111, and the control circuit board 111 conducts the test of the transistor 117 based on the temperature information Tj.

[0516] The Tj obtained by passing a constant current Ic and the temperature information Tj obtained by passing a constant current Ic’ are averaged or weighted to obtain a single value of the temperature information Tj. Using this temperature information Tj, the control circuit board 111 conducts, stops, or changes the control of the test of the transistor 117. Since other matters are the same as or similar to those described in this specification and the drawings, the description thereof is omitted.

[0517] Needless to say, the present invention can be variously modified without departing from the gist thereof. Needless to say, the matters or contents described in this specification and the drawings can be combined with each other.

[0518] FIG. 50 is an explanatory diagram of a semiconductor test apparatus according to an embodiment of the present invention. The difference from FIG. 28 is that the diode-connected transistor 117s is arranged in the path of the current Id flowing through the transistor 117m that conducts the test. Since other parts are the same, the description thereof is omitted.

[0519] As an example, the transistor 117s is a transistor having the same specifications as the transistor 117m that conducts the test. The gate terminal g2 and the emitter terminal e2 of the transistor 117s are connected, and the transistor 117s can be regarded as a diode equivalently. The gate terminal g2 and the emitter terminal e2 of the transistor 117s are connected to the O terminal of the connection part 507. The collector terminal c2 of the transistor 117s is connected to the P terminal of the connection part 507.

[0520] The terminals (gate terminal g2, emitter terminal e2, collector terminal c2) of the transistor 117s are connected to the connector 202b as shown in FIG. 43, and the connector 202b is connected to the sample connection circuit 203 by the signal wiring 222b. The connection of the terminals (gate terminal g2, emitter terminal e2, collector terminal c2) of the transistor 117s is carried out in the sample connection circuit 203.

[0521] When the switch circuit 124b is turned on, the current Im flows and discharges the charge of the current power supply device 121. Alternatively, the current Id output from the current power supply device 121 flows to the ground via the switch circuit 124b.

[0522] When an inrush current Is flows into the transistor 117m to be tested, the transistor 117m is destroyed by the inrush current Is or the generation of the surge voltage Vs. In order to prevent the generation of the inrush current Is or the surge voltage Vs, the on / off control and the on / off sequence of the switch circuits 124a and 124b are controlled.

[0523] When the test of the transistor 117m is carried out by increasing the cycle tcycle, it is necessary to perform the on / off of the switch circuit 124a and the switch circuit 124b at high speed. In this case, an inrush current Is or a surge voltage Vs may be generated depending on the on / off timing of the switch circuit 124.

[0524] If the voltage Vm of the collector terminal of the transistor 117 is higher than the voltage Vp of the output part of the current power supply device, the current flows as the current Im toward the ground and does not flow or flows only slightly to the transistor 117m.

[0525] In order to create the relationship of Vm > Vp, in the embodiment shown in FIG. 50, the diode-connected transistor 117s is arranged in the path of the current Id. When a current flows through the transistor 117s, it accumulates on the voltage Vm by the channel voltage of the transistor 117s. Therefore, the voltage Vp becomes lower than the voltage Vm, and no inrush current is applied to the transistor 117m. The transistor 117m is not destroyed by the inrush current Is or the surge voltage Vs.

[0526] FIG. 60 is a voltage or waveform diagram of the channel (Vce, Vds) of the transistor when performing a power cycle test on a plurality of semiconductor elements (such as a power transistor). As specific circuit configurations and test methods, FIGS. 51 and 52 are exemplified.

[0527] In the semiconductor device test apparatus and the semiconductor device test method of the present invention, a simultaneous test method for a plurality of devices is performed. In the present invention, as an example of the simultaneous test method, a time-sharing method is implemented. Figure 60 is a waveform when performing power cycling of four devices using one semiconductor device test apparatus of the present invention. From time 2 (s) to 4 (s), the first device is on, and the other devices (the second device, the third device, and the fourth device) are off. From time 4 (s) to 6 (s), the second device is on, and the other devices (the first device, the third device, and the fourth device) are off. From time 6 (s) to 8 (s), the third device is on, and the other devices (the first device, the second device, and the fourth device) are off. From time 8 (s) to 10 (s), the fourth device is on, and the other devices (the first device, the second device, and the third device) are off. Next, at 4.5 (s) later (13.5 (s)), the first device turns on again, and thereafter, the second device, the third device, and the fourth device turn on sequentially.

[0528] In Figure 60, for example, it is illustrated that the second device turns on simultaneously when the first device turns off. However, actually, after the first device turns off, after a time interval of a predetermined time (1 to 100 ms), the second device turns on. The predetermined time tw is configured to be able to set a predetermined value or an arbitrary time.

[0529] The above is the same for the operation intervals with other devices, and the predetermined time tw between each device is configured to be arbitrarily settable. The above matters are the same in Figure 52 and the like.

[0530] In the semiconductor device test apparatus and the semiconductor test method of the present invention, the on-time ton of each device and the off-time toff of each device are configured to be set to predetermined values. When each semiconductor device is a transistor element, the test cycle tc (tcycle), the on-time ton or the off-time toff, and the predetermined time tw can be easily adjusted or set according to the pulse time and period applied to the gate terminal of the transistor. When a plurality of devices are tested with a plurality of semiconductor device test apparatuses, variations between the apparatuses are included in the test results, so that accurate comparison of the devices cannot be made.

[0531] In the semiconductor device test apparatus and the semiconductor device test method of the present invention, while one device is in the non-conductive (OFF) period, another device is energized (turned on). By repeating the energization on (ON) and off (OFF) at regular intervals, thermal stress is applied to the semiconductor device.

[0532] By testing a plurality of devices simultaneously (sequentially) in the same apparatus (test environment such as power supply, temperature measurement, control, bypass, etc.), it is possible to achieve a speedup of device testing and an accurate comparison of device performance.

[0533] FIG. 51 is an explanatory diagram of a semiconductor test apparatus according to an embodiment of the present invention. In FIG. 51, a plurality of transistors 117 (transistors 117Q1 to 117Qn) to be tested are connected in parallel to a current power supply device 121.

[0534] In the embodiment of FIG. 51, it is necessary to arrange a plurality of transistors 117 on a positioning support plate 519. Therefore, as shown in FIG. 53, positioning holes 512 (in FIG. 53, positioning holes 512a, 512b, 512c, 512d, 512e) corresponding to the number of transistors 117 (SOP117, QFN117) to be tested are formed in a sample placement plate 511. SOP117, QFN117, etc. are arranged in each positioning hole.

[0535] Also, as shown in FIG. 54, electrode patterns 505 and 506 corresponding to the number of SOP117s and the number of QFN117s are formed on the connection substrate 514. Anisotropic conductive rubber 504 is disposed on the electrode patterns, and pressing of a plurality of SOP117s and QFN117s is performed with one pressing head.

[0536] In the embodiment, it has one switch circuit board 201a and n switch circuit boards 201b (switch circuit boards 201b1 to 201bn). The number of transistors 117Q to be tested simultaneously or sequentially is n (transistors 117Q1 to 117Qn).

[0537] The collector terminal of transistor Q1 is connected to fork plug 205e1, and the emitter terminal of transistor Q1 is connected to fork plug 205c1.

[0538] The collector terminal of transistor Q2 is connected to fork plug 205e2, and the emitter terminal of transistor Q2 is connected to fork plug 205c2.

[0539] The collector terminal of transistor Q3 is connected to fork plug 205e3, and the emitter terminal of transistor Q3 is connected to fork plug 205c3.

[0540] Similarly hereinafter, the collector terminal of transistor Qn is connected to fork plug 205en, and the emitter terminal of transistor Qn is connected to fork plug 205cn.

[0541] The current Ic of the constant current circuit 118 is supplied to the diode Ds of the transistor 117Q1 when the switch circuit Ssa1 is turned on. The terminal voltage of the diode Ds is applied to the operational amplifier (buffer) 116 and output as the voltage Vi1 from the operational amplifier circuit 116.

[0542] The current Ic of the constant current circuit 118 is supplied to the diode Ds of the transistor 117Q2 when the switch circuit Ssa2 is turned on. The terminal voltage of the diode Ds is applied to the operational amplifier (buffer) 116 and output as the Vi2 voltage from the operational amplifier circuit 116.

[0543] Similarly, the current Ic of the constant current circuit 118 is supplied to the diode Ds of the transistor 117Qn when the switch circuit Ssan is turned on. The terminal voltage of the diode Ds is applied to the operational amplifier (buffer) 116 and output as the Vin voltage from the operational amplifier circuit 116. One voltage is selected from the voltages Vi1 to Vin by the selector 127 and output as Vi, which is then input to the temperature measurement circuit 115.

[0544] The temperature measurement circuit 115 obtains the temperature information Tj and outputs it to the control circuit board 111. In the embodiment of FIG. 51, the constant current circuit 118 is provided as one, but it is not limited thereto. A constant current circuit 118 may be arranged for each transistor 117Q. Also, a temperature measurement circuit 115 may be formed or arranged for each transistor 117Q. The voltage data Vi and the temperature information Tj are sent to the control circuit board 111 via the wiring of the mother board 207.

[0545] The connection portion 507 (P terminal) of the transistor 117Q1 is connected to the connection structure 218a1. The connection portion 507 (N terminal) of the transistor 117Q1 is connected to the connection structure 218b1.

[0546] The connection portion 507 (P terminal) of the transistor 117Q2 is connected to the connection structure 218a2. The connection portion 507 (N terminal) of the transistor 117Q2 is connected to the connection structure 218b2.

[0547] Similarly, the connection part 507 (P terminal) of the transistor 117Qn is connected to the connection structure 218an, and the connection part 507 (N terminal) of the transistor 117Qn is connected to the connection structure 218bn. Here, n is a positive number of 1 or more. The connection structure 218 is inserted through the opening 216 provided in the partition wall 217. The insertion of the connection structure 218 is carried out from the C2 chamber toward the C1 chamber.

[0548] The fork plug 205 is inserted into the B chamber from the C2 chamber side through the opening 216 formed in the partition wall 214. When the fork plug 205 is inserted, it is connected to the conductor plate 204 of the switch circuit board 201. The switch circuit board 201 can be selected according to the position of the opening 216 into which the fork plug 205 is inserted.

[0549] By changing the position of the switch circuit board 201 connected to the connector 213 of the mother board 207, the switch circuit board 201 selected by the fork plug 205 can be selected.

[0550] Two conductor plates 204 are arranged on the switch circuit board 201. The conductor plates 204 are arranged such that the conductor plate 204 closer to the C2 chamber is connected (contacted) to the fork plug 205.

[0551] In the embodiment of the present invention, it is assumed that the fork plug 205 and the conductor plate 204 are brought into contact and electrically connected, but the present invention is not limited thereto. Any mechanism that can change between an electrically connected state and a non-connected state by mechanical operation may be used. Also, any configuration may be used as long as it can stably maintain the connected state.

[0552] For example, instead of the fork plug 205, a rotary connector, a rotary joint, a high-current connector, etc. may be used. Instead of the conductor plate 204, a rotary connector, a rotary joint, a high-current connector, a cylindrical conductor bar, a rectangular conductor bar, a comb-shaped conductor plate, etc. may be used.

[0553] FIG. 52 is an explanatory diagram of a method for testing a semiconductor element in an embodiment of the present invention for explaining the operation of FIG. 51. It is possible to simultaneously turn on transistors 117Q (transistors 117Q1 to transistors 117Qn) to perform a semiconductor test. In this case, it is necessary to pass a constant current Id through all of the transistors 117Q (transistors 117Q1 to transistors 117Qn). Therefore, the current supply device 121 needs to be able to output a current of Id×n (n is a positive number of 1 or more) if there are n transistors 117Q. Therefore, a current supply device 121 with a large capacity is required.

[0554] If the transistors 117Q are sequentially turned on and a constant current Id is applied to the transistors 117Q for testing, the constant current output by the current supply device 121 may be Id. FIG. 52 is an example of a test method of a semiconductor test apparatus that sequentially turns on the transistors 117Q for testing. The semiconductor element changes depending on the number of times the constant current Id is turned on and off.

[0555] Therefore, by performing a test by sequentially turning on a semiconductor element (such as transistors 117Q) as shown in FIG. 52, the test can be efficiently performed, and the maximum output current capacity of the current supply device 121 can be reduced.

[0556] In FIG. 52, the transistor 117Q to be turned on is described as one, but it is not limited thereto. For example, a plurality of transistors 117Q may be turned on simultaneously. In this case, the maximum value of the constant current output by the current supply device 121 is the number of transistors 117Q to be turned on × Id.

[0557] In the embodiment of the present invention, the current supply device 121 is shown as one, but it is not limited thereto. Another current supply device 121b may be separately installed as the current supply device 121. Also, two or more current supply devices 121 may be installed. By installing a plurality of current supply devices 121, the current Id flowing through the transistor 117 can have various waveforms. The above matters are the same in the embodiments of the present invention.

[0558] As shown in FIG. 52(a), when the switch circuits St1(151s1) to Stn(151sn) are turned on, constant currents Id1 to Idn flow through the transistor 117. For example, the application time of the constant current Id is ton, and the constant currents Id1 and Id2 are sequentially applied to the transistor 117 at intervals of the time tcycle. When the transistor 117 is turned on, the channel voltage of the transistor 117Q changes sequentially (FIG. 52(c)).

[0559] Therefore, for example, the constant currents Id1 and Id2 do not overlap in time. Therefore, the output capacity of the current power supply device 121 may be the output capacity required for the test of one transistor 117Q.

[0560] The constant currents Id (Id1 to Idn) are controlled so as not to overlap. Also, preferably, there is a gap of 1 μs or more between the respective currents Id of the constant currents Id (Id1 to Idn). For each transistor 117Q, the driving method and control method described in FIG. 46 are implemented.

[0561] The constant current Ic supplied to each transistor 117Q is supplied to the diode Ds of each transistor 117Q by sequentially turning on the switch circuits Ssa (Ssa1 to Ssan).

[0562] The voltages Vi (Vi1 to Vin) corresponding to the terminal voltages of the diodes Ds are selected by the selector 127 in synchronization with the switch circuits Ssa (Ssa1 to Ssan). For example, when the current Ic is supplied to the transistor 117Q1, the selector 127 selects the terminal voltage of the diode Ds of the transistor 117Q1. When the current Ic is supplied to the transistor 117Q3, the selector 127 selects the terminal voltage of the diode Ds of the transistor 117Q3. The selected voltage Vi is supplied to the temperature measurement circuit 115. Since other configurations and operations are the same as those described in other embodiments, the description thereof is omitted. In the embodiment of the present invention, although the transistor 117 has been described by way of example as an IGBT, it is not limited thereto.

[0563] For example, it goes without saying that an N-channel JFET (FIG. 55(a)), a P-channel JFET (FIG. 55(b)), an N-channel MOSFET (FIG. 55(c)), a P-channel MOSFET (FIG. 55(d)), an N-channel bipolar FET (FIG. 55(e)), or a P-channel bipolar FET (FIG. 55(f)) may be used.

[0564] Also, the present invention is not limited to three-terminal devices, and two-terminal elements such as diodes shown in FIG. 55(g) may also be used. For two-terminal elements, a gate signal Vgs is not necessary. Needless to say, the semiconductor test apparatus and the semiconductor element test method of the present invention can be applied by flowing a constant current Id through the current power supply device 121 for testing.

[0565] Also, the present invention is not limited to transistors and diodes, and other semiconductor elements such as thyristors and triacs, varistors, diacs, or modules in which transistors, diode resistors, etc. are mixed or integrated can also be applied to the semiconductor test apparatus and the semiconductor element test method of the present invention.

[0566] Also, the present invention is not limited to semiconductor elements, and can be applied to, for example, resistance elements such as concrete resistors and hollow resistors or variable resistance elements, non-linear resistance elements such as thermistors and posistors, and bias elements such as transformers.

[0567] As described above, in this specification, specific descriptions have been made based on the embodiments. Needless to say, the present invention is not limited thereto, and various modifications can be made without departing from the gist thereof. Needless to say, the matters or contents described in this specification and the drawings can be combined with each other.

[0568] For example, the switch circuits 124a and 124b shown in FIG. 45 can also be applied to other embodiments. Needless to say, the configurations or operations shown in FIGS. 51 and 52 can also be applied to other embodiments such as FIGS. 49 and 50.

[0569] Needless to say, the devices of the present invention illustrated in FIGS. 25, 68, and 72, the operations of the devices, and the configurations of the devices can be partially or entirely combined with each other. Needless to say, the present invention described with reference to FIGS. 2, 5, 7, 58, etc. can be partially or entirely combined with each other.

[0570] Needless to say, the test methods, inspection methods, and driving methods of the test apparatuses of the present invention described with reference to FIGS. 46, 47, 48, 49, 50, 51, 53, 60, 61, 62, 63, 64, 65, 66, 67, etc. can be partially or entirely combined with each other.

Industrial Applicability

[0571] The present invention can provide a semiconductor test apparatus and a semiconductor test method that can be easily reconfigured according to the test content of semiconductor elements such as transistors and the number of semiconductor elements to be simultaneously tested, and can effectively reduce noise generated during testing.

Explanation of Reference Numerals

[0572] 111 Control circuit board (controller) 112 Gate signal control circuit 113 Gate driver circuit 115 Temperature measurement circuit (not shown) 116 Operational amplifier circuit (buffer amplifier) 117 Power transistor 121 Constant current circuit 122 Switch circuit 123 Switch circuit 124 Switch circuit 125 Variable resistance circuit 126 Variable resistance circuit 127 Switching circuit 128 Current detection circuit 129 Voltage detection circuit 130 Constant current setting circuit 131 Control rack 132 Power supply device 133 Control circuit 134 Heating and cooling plate 135 Circulating water pipe 136 Chiller 137 Short - circuit circuit 138 Isolated DCDC converter circuit 201 Switching circuit board 202 Connector 203 Sample connection circuit 204 Conductor plate 205 Fork plug 206 Connection pin 207 Mother board 208 Connector 209 Device control circuit board 210 Housing 211 Connection wiring 212 Power supply wiring 213 Connector 214 Partition wall 215 Partition wall 216 Opening 217 Partition wall 218 Connection structure 219 Connection bolt 220 Contact part 221 Fixing screw 222 Signal wiring 223 Heat pipe 224 Fixing screw 225 Contact point part 226 Electrode terminal 227 Signal terminal 228 Heat dissipation fin 229 Cooling fan 230 Conductive wire 231 Heat pipe fitting 232 Connection fitting 233 Connection fitting 234 Concave part 235 Signal wiring 239 Arrangement concave part 301 Test circuit module 302 Voltage selection circuit 502 Connection pin 503 Connection wiring 504 Anisotropic conductive rubber 505 Electrode pattern 506 Electrode pattern 507 Connection part 508 Signal wiring 509 Positioning hole 510 Fixing hole 511 Sample placement plate 512 Sample hole 514 Connection board 515 Pressing plate 516 Pressing tool 517 Rubber (elastic material) 518 Positioning support 519 Positioning support plate 520 Surface plate 521 Prototype plate 522 Base 523 Heat-resistant resist 524 Ni-P plating film 525 Heat-resistant substrate 525 Gold plating film 530 Pressing head 531 Pressing column 532 Arm 533 Arm base 534 Support 601 Semiconductor chip 602 Insulating substrate 604 Copper base 605 Solder 606 Aluminum wire 607 Wiring electrode 608 Pressing member 609 Terminal connection part 610 Device fixing and connecting device 611 device base

Claims

1. A semiconductor test device for testing a power module having a gate signal terminal, a first electrode terminal, and a second electrode terminal, comprising: a first connection structure connected to the first electrode terminal; a heating and cooling plate for cooling or heating the power module; a power supply device for supplying a test current or a test voltage to the first electrode terminal of the power module via the first connection structure; a pressing member for holding the first connection structure; a gate driver circuit for applying a gate signal to the gate signal terminal.

2. A semiconductor test device for testing a power module having a gate signal terminal, a first electrode terminal, and a second electrode terminal, comprising: a first connection structure connected to the first electrode terminal; a heating and cooling plate for cooling or heating the power module; a first switch circuit connected to the first connection structure; a power supply device for supplying a test current or a test voltage to the power module via the first switch circuit; a second switch circuit for short-circuiting the output terminals of the power supply device; a pressing member for holding the first connection structure; a gate driver circuit for applying a gate signal to the gate signal terminal.

3. A semiconductor test device for testing a power module having a gate signal terminal, a first electrode terminal, and a second electrode terminal, comprising: a first connection structure connected to the first electrode terminal; a heating and cooling plate for cooling or heating the power module; a first switch circuit connected to the first connection structure; a power supply device for supplying a test current or a test voltage to the power module via the first switch circuit; a pressing member for holding the first connection structure; a gate driver circuit for applying a gate signal to the gate signal terminal, wherein the power module is disposed in a first chamber, and the first switch circuit is disposed in a second chamber.

4. A semiconductor test device for testing a power module having a gate signal terminal, a first electrode terminal, and a second electrode terminal, comprising: a first connection structure connected to the first electrode terminal; a second connection structure connected to the second electrode terminal; a heating and cooling plate for cooling or heating the power module; A power supply device that supplies a test current or a test voltage to the power module via the first connection structure and the second connection structure; A pressing member that holds the first connection structure and the second connection structure; A gate driver circuit that applies a gate signal to the gate signal terminal; A constant current circuit that applies a constant current between the first electrode terminal and the second electrode terminal when the test current or the test voltage is not supplied to the power module; A semiconductor test device, comprising: a voltage output circuit that outputs a terminal voltage between the first electrode terminal and the second electrode terminal in a state where the constant current is applied.

5. A semiconductor test device for testing a power module having a gate signal terminal, a first electrode terminal, and a second electrode terminal, A first connection structure connected to the first electrode terminal; A heating and cooling plate for cooling or heating the power module; A power supply device that supplies a test current or a test voltage to the power module via the first connection structure; A pressing member that holds the first connection structure; A gate driver circuit that applies a gate signal to the gate signal terminal; A voltage output circuit that outputs a terminal voltage between the first electrode terminal and the second electrode terminal; The semiconductor test device, wherein the gate driver circuit varies the gate signal so that the power of the power module obtained from the terminal voltage output by the voltage output circuit and the test current becomes a specified power.

6. Having a connection substrate on which an electrode pattern is formed, The semiconductor test device according to claim 1, claim 2, claim 3, claim 4, or claim 5, wherein the electrode terminal and the electrode pattern are connected by conductive rubber.

7. The heating and cooling plate has a first heating and cooling plate and a second heating and cooling plate, The semiconductor test device according to claim 1, claim 2, claim 3, claim 4, or claim 5, wherein the power module is disposed between the first heating and cooling plate and the second heating and cooling plate.

8. A temperature adjustment device that is connected to the heating and cooling plate with a liquid circulation water pipe and adjusts the liquid temperature of the liquid flowing through the circulation water pipe; Further comprising a water leakage sensor that detects the leaked liquid. The semiconductor test apparatus according to claim 1, claim 2, claim 3, claim 4, or claim 5, wherein the operation of the water leakage sensor stops the semiconductor test apparatus or issues an alarm.

9. The semiconductor test apparatus according to claim 4 or claim 5, wherein based on the terminal voltage, the test is stopped, or the control method is changed, or the test conditions are changed.

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