Power device characteristic evaluation system, and power device test method

Abstract

To evaluate a characteristic of a power device on a wafer.SOLUTION: According to some examples, a system 1100 may have a parametric system matrix 1004 that is coupled to one or more test measurement devices 1002, and the system 1100 may also have an adapter circuit 1006 that is coupled to the parametric system matrix 1004, and the adapter circuit 1006 has a voltage clamp circuit 1126 that is coupled to the parametric system matrix 1004. Further, the system 1100 may have a probe circuit 1008, which is coupled to adapter circuit 1006, and is to be coupled to a power device 1012 arranged on a wafer.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present disclosure relates to a test measurement system, and more particularly to a system and method for performing static and dynamic characteristic evaluations of a device.

Background Art

[0002] For evaluating the characteristics of a device under test (DUT), such as semiconductor devices like silicon carbide (SiC) and MOSFETs (metal oxide semiconductor field effect transistors), generally, both static characteristic evaluations such as current / voltage (I / V) curves and dynamic characteristic evaluations such as switching parameters may be included. In conventional static characteristic evaluations, a dedicated static measurement platform has been used. Furthermore, for conventional dynamic characteristic evaluations of a DUT, different measurement platforms (in some cases, dedicated custom dynamic platforms) have been used.

[0003] Currently, on the market, there are many products for evaluating the characteristics of power devices and power modules, including tests such as dynamic evaluations (e.g., double pulse tests, dynamic drain-source on-resistance R DSon , leakage current (leak), breakdown (breakdown voltage), etc.). Usually, these evaluations are performed on packaged components or modules. In dynamic tests, generally, by combining an oscilloscope and a capacitor bank, high voltage and high current tests can be easily performed.

[0004] Conventionally, for evaluating the high-power characteristics of a device under test (DUT), a static measurement platform has usually been included. FIG. 1 shows an example of such a platform 10. In this example, the platform 10 includes a test measurement device 12, a test fixture 14 to which one or more DUTs (not shown) are connected, and a power expander 16.

[0005] To perform dynamic power characterization, a separate platform is required, which may be a large-scale floor model platform or a custom platform. FIG. 2 shows an example of such a platform 20, which may have some or all of the components shown. The test and measurement equipment 22 may actually include one or more test and measurement equipment, such as an oscilloscope and an impedance analyzer. The test and measurement equipment 22 connects the test board 26 and the DUT with a high voltage probe 24. The test board 26 may include a driver board 28, which is typically used to stably switch the power on and off and possibly provide power protection. The DC circuitry 32 may include a DC link capacitor, a DC voltage source, and a load inductor. A current transducer 30 and a signal generator 34 are connected to the test board 26 to enable testing of the test board 26. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2022-141621 A [Non-patent literature]

[0007] [Non-Patent Document 1] "Four-terminal sensing" article, Wikipedia (English version), [online], [Retrieved January 13, 2025], Internet<https: / / en.wikipedia.org / wiki / Four-terminal_sensing> [Non-Patent Document 2] "Four-terminal measurement method" article, Wikipedia (Japanese version), [online], [searched on January 13, 2025], Internet<https: / / ja.wikipedia.org / wiki / 四端子測定法> Summary of the Invention

Problems to be Solved by the Invention

[0008] There are problems in combining power measurements (such as dynamic R, double - pulse tests, etc.) and parametric tests for wafers by automated means. Currently, there is no commercial - based solution (solution method) that can incorporate parametric sensitivity measurements, perform characteristic evaluations at the production level of power devices on wafers, and meet the speed requirements of the production process. DSon

[0009] Embodiments of the disclosed apparatus and method address the drawbacks in the prior art.

Means for Solving the Problems

[0010] Generally, to statically or dynamically evaluate the characteristics of a device, separate large - scale devices and fixture platforms are required. Embodiments of the present application provide a composite characteristic evaluation system, which has two components. The interactive test measurement device is, for example, an oscilloscope, an impedance analyzer, a combination of these, or one or more of a number of other test measurement devices. For simplicity, in this application, this test component is referred to as a test measurement device. The other component is a power supply and measurement front - end with a DUT interface for attaching a test board, which may be referred to as a fixture in this disclosure. Embodiments of the present application generally include two separate components, but these can also be attached to one housing.

[0011] The term "high voltage" as used in this application refers to a voltage of 42 volts or more.

[0012] ​Embodiments of the present application provide a dual-purpose characteristic evaluation platform having several advantages. This system (consisting of two components: a test device and a fixture) is sized to be carried by an individual. The fixture encloses all high-voltage circuits for safety and may also be equipped with an interlock to prevent improper operation of the high-voltage system that could be caused by system failures. According to this system, the setup is simplified in that the user only needs to place the DUT into the fixture. Since the two components within the system are connected by simple cables, the system does not require reconnecting the cables between different tests. Through automatic switching of the measurement configuration, the user can obtain all desired parameters of the test. The fixture may further have a heating or cooling device and a protective barrier provided around the device to protect against damage to the device.

[0013] Regarding what was briefly summarized above, with reference to exemplary implementations, some of which are illustrated in the accompanying drawings, specific descriptions will be given to enable a detailed understanding of the above-mentioned features. However, it should be noted that the accompanying drawings only show examples of typical implementations and do not limit the scope of the claims.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, various features will be described with reference to the figures. Note that these figures may have the same or different scales, and elements with the same structure or function are represented by the same reference numbers throughout these figures. Note that these figures are only for the purpose of facilitating the explanation of the functions. These are not intended as an exhaustive description of the explanation or a limitation of the scope of the claims. In addition, the illustrated embodiments may not include all aspects and advantages described. Aspects or advantages described in connection with a particular embodiment are not necessarily limited to that embodiment, and may be implemented in any other embodiment even if not described or explicitly stated as such.

[0016] For ease of understanding, the same reference numerals are used as much as possible to indicate the same elements common to multiple drawings. It is assumed that the elements of one embodiment may be effectively incorporated into other embodiments.

[0017] FIG. 3 shows an embodiment of a test measurement system 300, which is also referred to as a platform and has a test measurement device 40 such as an oscilloscope or other test measurement device. For simplicity of explanation, the device 40 may sometimes be referred to as a test measurement device. Another part of the system is a static and dynamic power and measurement device 50. These terms are not intended to limit the function of either device, nor do they suggest such a limitation.

[0018] The test measurement device 40 may have various components, including a user interface 44 through which a user can interactively operate various menus. Through the user interface 44, the user can make selections regarding the tests to be executed, parameter settings, etc. via a touch screen or a display having various buttons and knobs. The test measurement device 40 has one or more processors 46, which may receive user input and send parameters and other selections to the measurement device, and may also receive power and the output from the measurement device 50 and generate a data-based output for the user. The test measurement device 40 has a measurement unit 47 that performs tests on the DUT and measures the parameters of the DUT. The remote device 42 is, for example, a computing device, a personal computer (PC), or a smartphone, etc., and may access the test measurement system 300 for remote operation via either the test measurement device 40 or the power and measurement device 50. As used in this application, the term "processor" means an electronic component such as a microcontroller, an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc. that can receive instructions and execute actions, as will be described in detail below.

[0019] The test measurement device 40 communicates with the power and measurement device 50 via a direct connection part 48 such as a cable. The two measurement devices 40, 50 and the direct connection part 48 are portable and configured to be carried by an individual. The direct connection part 48 is connected to each device via a connection circuit (not shown), whereby the measurement devices 40, 50 can switch the test configuration (settings: configurations) without rewiring the cable.

[0020] The power and measurement device 50 may further have several various elements. These may include one or more processors 52, a high-voltage circuit 56 that supplies a high voltage to one or more devices under test (DUTs) 70, an interlock 54 that functions as a protection mechanism for the high-voltage circuit 56, and the like. The DUT 70 may include one or more separate DUTs depending on the test configuration of the test measurement device 40 and the power and measurement device 50. The interlock 54 is designed to prevent damage to the device against any dangerous state caused by the high voltage generated by the high-voltage circuit 56. The DUT 70 is mounted on the DUT interface 58, which may be a universal DUT interface. Mounting the DUT on this allows the DUT 70 to be connected to various components within the power and measurement device 50.

[0021] When the high-voltage circuit 56 operates and the DUT 70 operates, heat may be generated. However, in order for the DUT 70 to operate, it may be necessary to maintain it within a specific temperature range. For this reason, the power and measurement device 50 may have a temperature control circuit 62 for controlling the temperature of the DUT 70. One or more processors 52 monitor the temperature and operate the temperature control circuit 62, which may have items such as a fan, a switchable heat sink, a cooling system, a heater, and the like. The power and measurement device 50 may further have a barrier 64 for protecting the power and measurement device 50 from damage by the DUT 70. The power and measurement device 50 may further have a switching circuit 60, which controls the operation of various components within the power and measurement device 50 to test the DUT and measure its characteristics.

[0022] Generally, during operation, the user supplies inputs remotely or directly via the user interface 44 to control the operation of the power and measurement device 50 to statically or dynamically evaluate the characteristics of the DUT 70. Typically, dynamic characteristic evaluation is realized using a half-bridge circuit such as the characteristic evaluation circuit 400 in the embodiment shown in FIG. 4. Generally, the characteristic evaluation circuit 400 is housed inside the power and measurement device 50, more specifically inside the switching circuit 60, but embodiments of the disclosed technology are not limited to such examples.

[0023] The characteristic evaluation circuit 400 includes a half-bridge circuit formed by two DUTs, DUT_top and DUT_bot, corresponding to the DUT illustrated in the test measurement system 300 of FIG. 3. In this description, DUT_top is referred to as the top device DUT_top, and DUT_bot may be referred to as the bottom device DUT_bot (bot = bottom). One way to perform dynamic characteristic evaluation (referred to as the double-pulse method in this application) is to use a half-bridge circuit. The double-pulse method or "double-pulse test" will be described in more detail below with reference to FIG. 6. In the characteristic evaluation circuit 400, the top device DUT_top and the bottom device DUT_bot of the half-bridge circuit are connected in series between the power supply voltage node and the reference voltage node. Each of the DUT_top and DUT_bot devices is a field effect transistor (FET) in the example of the embodiment of FIG. 4, and more specifically, an N-channel MOSFET.

[0024] In the overall operation, when the lower device DUT_bot is turned on, a desired current is obtained through the test inductor Test_L. Subsequently, the lower device DUT_bot is turned off, the upper device DUT_top is turned on, and the inductor current from the inductor Test_L circulates through the upper device DUT_top. Alternatively, if only one DUT70 is to be tested, the upper device DUT_top may be replaced with a diode. After a certain specified time (which depends on the characteristics of the upper and lower devices DUT_top and DUT_bot), the upper device DUT_top is turned off and the lower DUT_bot device is turned on again. The desired data for testing and characterizing the upper and lower devices can be collected during and during these transitions of the upper and lower devices DUT_top and DUT_bot, and the energy loss can also be calculated. This same platform can be used to extract static parameters depending on the control of the voltages and the flowing currents of the devices DUT_top and DUT_bot.

[0025] Replacing the upper device DUT_top with a diode or a short circuit enables gate control of the lower device DUT_bot, and as a result, a static current-voltage (I / V) curve can be extracted. If the upper device DUT_top is available or present, additional methods for extracting static data can be utilized. These may include pulse driving the potential of the independent gate / drain in the lower device DUT_bot. To do so, the system controls the voltage of the gate of the lower device DUT_bot to enable measurement of the appropriate transfer characteristics of this device. A test inductor Test_L is not necessary for static I / V device characterization, but including or having the test inductor Test_L allows both static (static) and dynamic (dynamic) characterization to be performed in the same circuit. If both the upper and lower devices DUT_top and DUT_bot are present in the characterization circuit 20 and are of the same type of device, the maximum power will be split between the upper and lower devices DUT_top and DUT_bot. If a full-power test of one of these devices DUT_top and DUT_bot is required, the other device will have to be replaced with a short circuit.

[0026] FIG. 4 also shows a number of measurement points or channels in the characterization circuit 400, where the power supply and measurement device 50 detect or sense the electrical parameters (i.e., voltage or current) of the upper and lower devices DUT_top and DUT_bot during the testing and characterization of these devices DUT_top and DUT_bot. Each measurement channel is indicated by an arrow with an angle and a related descriptor indicating the parameter detected at that measurement channel. For example, in the characterization circuit 400, as shown, there is a first current detection resistor R1 coupled in series with the test inductor Test_L, and second and third current detection resistors R2 and R3 coupled in series with the upper and lower devices DUT_top and DUT_bot. One measurement channel detects the current flowing through the resistor R1, which corresponds to the current Inductor_i flowing through the test inductor Test_L. Another measurement channel detects the current flowing through the resistor R2, which corresponds to the drain current Drain_i entering the upper device DUT_top. The third measurement channel detects the current flowing through the resistor R3, which corresponds to the source current Source_i flowing through the lower device DUT_bot.

[0027] The characterization circuit 400 has additional measurement channels for detecting voltage and current at various points within the characterization circuit. All measurement channels enable the power supply and measurement device 50 to capture the operating data of the upper and lower devices DUT_top and DUT_bot and use the captured operating data to perform the characterization of one or both of the upper and lower devices DUT_top and DUT_bot. Similar measurement channels are shown in the schematic diagrams of FIGS. 5 - 8, and the functions of these test points or channels can be understood from the above description of the measurement channels related to FIG. 4. Therefore, no more detailed description will be given in relation to these figures.

[0028] FIG. 5 shows an embodiment of a characteristic evaluation circuit 500 including a half - bridge switching circuit formed by an upper device DUT_top and a lower device DUT_bot, which has a switch SW1 used to enable selection between the upper and lower devices DUT_top and DUT_bot. This selection may be input to the power supply and measurement device 50 (FIG. 3) through the user interface 44 on the test measurement device 40 of FIG. 3, and at this time, this selection is transmitted to the power supply and measurement device 50 via the direct connection part 48. By adding the switch SW1, when both the upper and lower devices DUT_top and DUT_bot are attached, both DUT_top and DUT_bot can be evaluated for characteristics in both static and dynamic configurations. The configuration of the characteristic evaluation circuit 500 shown in FIG. 5 shows the selection to test or evaluate the characteristics of the lower device DUT_bot. During operation, the user, in addition to selecting static characteristic evaluation or dynamic characteristic evaluation through the user interface 44 on the test measurement device 40 within the test measurement system 300 of FIG. 3, also selects either one of the upper and lower devices DUT_top and DUT_bot. Then, one or more processors 46 of the test measurement device 40 send the selection content and any other parameters to the power supply and measurement device 50. One or more processors 52 within the power supply and measurement device 50 then supply a signal to the switching circuit 60 to appropriately set the switch SW1.

[0029] Embodiments of the test measurement system according to the present disclosure include one or both of the characteristic evaluation circuits 400 and 500 of FIGS. 4 and 5, and provide the ability to combine static and dynamic measurements without the need to use a plurality of setups and devices, and furthermore, without even the need to re - wire the cables to a specific configuration. The test measurement system outputs desired characteristic evaluation data regarding the DUT to be tested or characterized. This data may be generated on the user interface 44 of the test measurement device 40, or may be output to a file for further analysis, such as a file for an analysis software package. This may be realized by one or more processors 46, 52 in either the power supply and measurement device 50 or the test measurement device 40.

[0030] Embodiments of the present disclosure relate to a characteristic evaluation circuit for a test measurement system that eliminates the need for a conventional bias tee to perform static and dynamic characteristic evaluations of a DUT. As will be described in detail below, the solid-state bias tee includes a DUT and a gate drive voltage generation circuit, which supplies a DC pulse signal and an AC signal to the gate of this DUT so that this DUT supplies a necessary current signal and voltage signal to another DUT to be characterized. Since this characteristic evaluation circuit operates in various modes, it is possible to reverse the functions of the DUT in the solid-state bias tee and the DUT to be characterized. This enables the dynamic and static characteristic evaluations of both these DUTs without using a conventional bias tee. A conventional bias tee needs to be designed for a specific voltage and frequency range and usually includes discrete inductive, capacitive, and resistive components, making it complicated to incorporate a conventional bias tee into a dynamic characteristic evaluation platform. Therefore, eliminating the need for a conventional bias tee is beneficial. Also, a conventional bias tee has current and frequency limitations that restrict the impedance measurements that can be performed on a DUT to be characterized. Further embodiments of the present disclosure relate to a characteristic evaluation circuit coupled to first and second DUTs, which can simultaneously generate a gate charge characteristic evaluation parameter of one DUT and a body diode characteristic evaluation parameter of the other DUT.

[0031] FIG. 6 is a schematic diagram of an example of a characteristic evaluation circuit 600 for evaluating static and dynamic characteristics of one or more DUTs (DUT_top, DUT_bot), which is related to the test measurement system 300 of FIG. 3 according to an embodiment of the disclosed technology. The characteristic evaluation circuit 600 enables both static and dynamic characteristic evaluations of the DUTs (DUT_top and DUT_bot). At this time, in the reference in FIG. 6 and also in the reference to the DUTs in FIGS. 7 and 8 in the following description, again, the upper device DUT_top and the lower device DUT_bot will be referred to. Each of the upper and lower devices DUT_top and DUT_bot is an N-channel MOSFET in the example of FIG. 6. In a further embodiment, other types of power transistors may be included. Each DUT is described as having a drain, a source, and a gate node, which applies to the embodiment where each DUT is a MOSFET, but these nodes are also intended to apply to equivalent nodes related to different types of transistors.

[0032] In the characteristic evaluation circuit 600 of FIG. 6, the upper device DUT_top and the lower device DUT_bot form a half-bridge circuit, which is coupled in series with a current detection resistor RS1 between a power supply voltage node SVN and a reference voltage node RVN. The variable DC power supply voltage source DC_adj has a power supply resistor R_sup and is coupled between the voltage nodes SVN and RVN to supply a desired DC voltage between these nodes. The capacitor C may include one or more capacitors and filters the noise of the voltage nodes SVN and RVN.

[0033] The switching node SN is defined at the interconnection between the sources and drains of the upper and lower devices DUT_top and DUT_bot. The test inductor TEST_L is coupled in series with the current detection resistor RS2 between the switching node SN and the power supply voltage node SVN. By means of the test inductor TEST_L, the characteristic evaluation circuit 600 supplies a desired current flowing through the other of the upper and lower devices DUT_top and DUT_bot, or supplies a desired voltage across the two ends of the other of the upper and lower devices DUT_top and DUT_bot, as part of dynamically evaluating the characteristics of the other of the upper and lower devices DUT_top and DUT_bot through one of the upper and lower devices DUT_top and DUT_bot that functions as a signal source (source). Either one of the upper and lower devices DUT_top and DUT_bot whose characteristics are to be evaluated is sometimes referred to as the measured element in this description. The gate drive voltage generation circuit GD operates in combination with the amplifier AMP to supply a gate drive signal including a DC pulse or an AC signal to the lower device DUT_bot and detect the gate current of the lower device DUT_bot as part of measuring the gate-source capacitance Cgs of the lower device DUT_bot.

[0034] FIG. 6 shows the configuration of the characteristic evaluation circuit 600. At this time, the upper device DUT_top functions as a signal source (source) element, and the lower device DUT_bot is the element to be measured (i.e., the device to be evaluated for characteristics). The upper and lower devices DUT_top and DUT_bot are controlled to apply the AC and DC voltages necessary to measure the desired dynamic and static parameters of the lower device DUT_bot, thereby evaluating the characteristics of the lower device DUT_bot. For the static current and voltage device characteristic evaluation of the devices DUT_top and DUT_bot, the test inductor Test_L is not necessary, but the presence of the inductor enables both static and dynamic characteristic evaluations to be performed with the same characteristic evaluation circuit 600. In operation, the upper device DUT_top is initially off, and the lower device DUT_bot is initially turned on to supply the desired inductor current IL as the desired drain current flowing through the lower device DUT_bot. When the current flowing through the test inductor TEST_L reaches the desired value, the lower device DUT_bot turns off, and the inductor current IL recirculates through the body diode (not shown) of the upper device DUT_top. The gate drive voltage generation circuit GD supplies DC and AC signals to the devices DUT_bot and DUT_top, thereby enabling the measurement of dynamic parameters such as the gate-source capacitance Cgs, the gate-drain capacitance Cgd, and the drain-source capacitance Cds in addition to the static parameters of the lower device DUT_bot to be measured.

[0035] The characteristic evaluation circuit 600 can perform characteristic evaluations of the upper and lower devices DUT_top and DUT_bot, respectively, by switching the connection of the test inductor TEST_L and by switching the coupling of the amplifier AMP. To set the lower device DUT_bot as the signal source element and the upper device DUT_top as the element under measurement for which characteristics are to be evaluated, the terminal of the test inductor TEST_L coupled to the power supply voltage node SVN is instead coupled to the reference voltage node RVN. Further, the amplifier AMP is either coupled to the gate of the upper device DUT_top as shown for the lower device DUT_bot in FIG. 6, or the characteristic evaluation circuit 600 may have an additional amplifier (not shown) coupled to the gate of the upper device DUT_top.

[0036] The characteristic evaluation circuit 600 has a number of measurement points or channels Chan1 to Chan6, where the power supply and measurement device 50 detect or sense the electrical parameters, i.e., voltage or current, of the upper and lower devices DUT_top and DUT_bot during the test and characteristic evaluation of these devices. Through the detection of parameters at the measurement channels Chan1 to Chan6, the power supply and measurement device 50 capture the operation data of one of the upper and lower devices DUT_top and DUT_bot to be characterized. The power supply and measurement device 50 uses this captured operation data to evaluate the characteristics of the corresponding device (DUT_top or DUT_bot). The first measurement channel Chan1 detects the drain voltage Drain_bot of the lower device DUT_bot with reference to the reference voltage node srcB. The drain current flowing through the lower device DUT_bot is detected through the measurement point Chan2, and the gate-source voltage Vgs of the lower device DUT_bot is detected at the measurement channel Chan3. The measurement channel Chan4 measures the inductor current IL flowing through the test inductor TEST_L, the test channel Chan5 measures the gate-source voltage Vgs of the upper device DUT_top, and the test channel Chan6 measures the drain voltage Drain_top of the upper device DUT_top.

[0037] In the characteristic evaluation circuit 600, one of the devices DUT_top and DUT_bot may be configured to achieve an operation equivalent to that of a source bias tee during the double-pulse test. The double-pulse test is a test method for measuring dynamic characteristics such as the switching parameters of power switching elements such as power FETs. In the configuration of FIG. 6, the upper device DUT_top is a signal source element and functions as something equivalent to a source bias tee. In this configuration, the upper device DUT_top supplies the necessary DC voltage and the necessary AC signal so as to appropriately stimulate the element under measurement (in this case, the lower device DUT_bot is the object of characteristic evaluation).

[0038] The embodiment of FIG. 6 shows a configuration for current-mode driving of the upper device DUT_top by modulating the gate-source voltage Vgs of the upper device DUT_top. In this way, the upper device DUT_top functions as a signal source element for evaluating the characteristics of the lower device DUT_bot. When the upper device DUT_top is an FET, there is a quadratic relationship (i.e., ID = f(Vgs2)) between the gate-source voltage Vgs and the drain current ID of the upper device DUT_top. Therefore, the AC signal component supplied by the gate drive voltage generation circuit GD is usually provided at half of the desired measurement frequency. The drain current ID at twice the frequency of the AC signal component applied to the gate occurs because the frequency is doubled by this square of the AC signal component. This AC signal component generates an AC signal (i.e., the drain current ID flowing through the device DUT_bot) superimposed on the DC bias current. The measurement of the impedance of the lower device DUT_bot for obtaining the gate-source capacitance Cgs and the drain-source capacitance Cds is performed by decomposing the vector of the AC voltage supplied from the upper device DUT_top and superimposed on the drain (Drain_bot) of the lower device DUT_bot measured on channel Chan1, measuring the AC current Gate_i of the lower device DUT_bot supplied by the amplifier circuit AMP, and measuring the source current Source_i of the lower device DUT_bot on channel Chan2.

[0039] In the characteristic evaluation circuit 600, the upper device DUT_top may be used as a control current source to evaluate the characteristics of the lower device DUT_bot at a specific drain current ID flowing through the lower device DUT_bot. Also, the upper device DUT_top may be used to set a specific voltage (Chan1) at the drain of the lower device DUT_bot. In an embodiment of the characteristic evaluation circuit 600, the use of the upper device DUT_top as a control current source or for setting a specific drain voltage may be controlled in a sweep mode or a pulse mode to measure the characteristics of the lower device DUT_bot over a wide range of specific parameters. The control of the current or voltage value is to sweep or vary over the entire range of the value, but when applying a DC signal at the target value may damage or destroy the lower device DUT_bot whose characteristics are to be evaluated, it is pulsed.

[0040] The gate drive voltage generation circuit GD that drives the gates of the upper and lower devices DUT_top and DUT_bot provides the characteristic evaluation circuit 600 with the ability to enable the characteristic evaluation of both the upper and lower devices DUT_top and DUT_bot. Further, by the function of measuring the gate current and source current of each of the upper and lower devices DUT_top and DUT_bot compared with the AC signal applied to the drain of the lower device DUT_bot (i.e., the DUT whose characteristics are to be evaluated), all the impedances related to the lower device DUT_bot can be measured. With these measurement functions and the ability to switch the signal source element and the element to be measured, the characteristic evaluation circuit 600 fully measures the characteristics of each of DUT_top and DUT_bot.

[0041] FIG. 7 is a schematic diagram of a solid-state bias tee 700, which may be used in the characteristic evaluation circuits 600, 800, and 900 of FIGS. 6, 8, and 9 according to embodiments of the present disclosure. The solid-state bias tee 700 may also be used in other characteristic evaluation circuits, including those not configured to perform double-pulse tests, in addition to the characteristic evaluation circuits 600, 800, and 900. The solid-state bias tee 700 includes an FET 702 and a gate drive voltage generation circuit GD that supplies a DC pulse signal and an AC signal to the gate of the FET 702. The FET is an N-channel FET in the embodiment of FIG. 7, but may be other types of transistors in further embodiments. The bias tee 700 has a first node 704, a second node 706, and a third node 708 coupled to the gate, drain, and source of the FET 702, respectively. During operation, the gate drive voltage generation circuit GD supplies a drive signal including appropriate AC and DC pulse components to the first node 704 to control the FET 702 to function as a controlled current source that supplies a desired drain current ID or sets a specific voltage at the source of the FET 702. In this way, the gate drive voltage generation circuit GD and the FET 702 function as a bias tee for supplying a desired voltage or current having desired AC and DC components to the source S of the FET 702. In the example of the embodiment of FIG. 6, the gate drive voltage generation circuit GD and the upper device DUT_top correspond to the implementation example of the bias tee 700 of FIG. 7.

[0042] FIG. 8 is a schematic diagram of another example of a characteristic evaluation circuit 800 for statically and dynamically evaluating one or more DUTs associated with the test measurement system 300 of FIG. 3 according to an embodiment of the disclosed technology. Components within the characteristic evaluation circuit 800 are the same as the corresponding components within the characteristic evaluation circuit 600 of FIG. 6. In contrast to the characteristic evaluation circuit 600, the characteristic evaluation circuit 800 has a voltage feedback based on the drain Drain_top through a voltage feedback resistor R_vf for controlling a gate drive voltage generation circuit GD that drives the gate of the upper device DUT_top, and the upper device DUT_top functions as a signal source element in the example of the illustrated embodiment. In the characteristic evaluation circuit 800, the frequency of the modulation signal or AC signal supplied by the gate drive voltage generation circuit GD is the same as the desired frequency of the drain current ID supplied to the lower device DUT_bot to be evaluated for characteristics.

[0043] Both the characteristic evaluation circuits 600 and 800 can be used to measure the capacitances Cgd and Cds. To measure the gate-source capacitance Cgs, the gate-drive voltage generation circuit GD supplies an appropriate DC bias signal and a desired AC stimulus signal to the gate of the lower device DUT_bot, and the impedance is measured using the gate current Gate_i detected by the amplifier AMP and the gate voltage measurement at channel Chan3.

[0044] FIG. 9 is a schematic diagram of an example of a characteristic evaluation circuit 900 for gate charge characteristic evaluation and body diode characteristic evaluation of one or more DUTs associated with the test measurement system 300 of FIG. 3 according to an embodiment of the disclosed technology. In a conventional approach for measuring the gate charge curve of a FET, a source measure unit (SMU) or other equivalent device is used to supply a constant current to the gate of the FET and measure the resulting gate-source voltage Vgs over time. Further, the SMU or equivalent device supplies the necessary drain voltage and drain current to the FET simultaneously. In this approach, a dedicated device in the form of an SMU is required to generate the gate charge curve and perform a static characteristic evaluation of the FET.

[0045] According to the characteristic evaluation circuit 900, it is possible to evaluate the gate charge curve characteristics of each of the upper device DUT_top and the lower device DUT_bot without rewiring the connection between each device and an external test apparatus. The upper and lower devices DUT_top and DUT_bot are coupled in series with a switching node SN defined as the interconnection between these two devices. The test inductor TEST_L is coupled in series with a first current detection resistor R1 between the switch SW and the switching node SN. The variable DC voltage source DC_adj is coupled between the voltage nodes SVN and RVN to supply a desired DC voltage between these nodes, and the capacitor C filters the noise between these voltage nodes. In order to measure the currents I_top and I_bot passing through the upper and lower devices DUT_top and DUT_bot respectively, a second current resistor R2 is coupled between the power supply voltage node SVN and the drain of the upper device DUT_top, and a third current detection resistor R3 is coupled between the source of the lower device DUT_bot and the reference voltage node RVN. In FIG. 9, the switch SW is shown in a position where the lower device DUT_bot is the element to be measured (i.e., the device to be evaluated for characteristics), and the upper device DUT_top is the source element.

[0046] In the operation of the characteristic evaluation circuit 900, the gate charge characteristics of the lower device DUT_bot can be measured using the following process. First, the power supply DC_adj is set to a desired starting DC voltage level for the drain-source test voltage of the lower device DUT_bot. Initially, both the upper and lower devices DUT_top and DUT_bot are off. Next, by turning on the lower device DUT_bot for a certain period of time, a desired inductor current IL is made to flow through the test inductor TEST_L. The current IL flowing through the inductor TEST_L may be calculated by di / dt = V / L or may be continuously measured, and this measurement (determination: quantification) is made based on the expiration of a specific time or the measured inductor current reaching a desired current threshold.

[0047] When the inductor current IL reaches a desired current threshold value, the lower device DUT_bot turns off. At this point, the inductor current IL continues to flow through the inductor TEST_L and also flows through the body diode BD_top of the upper device DUT_top. When the upper device DUT_top is turned on at this point, the attenuation of the current IL due to the loss of the body diode BD_top can be reduced. Then, the lower device DUT_bot performs a delay and waits for a certain delay time to ensure that it is fully turned off. If the upper device DUT_top is turned on, when the upper device DUT_top is turned on, a delay and wait for a certain delay time are performed to ensure that the lower device DUT_bot does not turn on again until the upper device DUT_top is turned on.

[0048] At this point, the gate drive voltage generation circuit GD supplies a desired initial voltage Vg_bot to the gate of the lower device DUT_bot. This initial voltage is usually zero volts, but other levels may be required in some cases. Next, the gate drive voltage generation circuit GD supplies a constant current to the gate of the lower device DUT_bot. As one embodiment, the constant current source of the gate drive voltage generation circuit GD may be replaced by a voltage source connected in series with a resistor. Next, the voltage Vg_bot of the gate of the lower device DUT_bot is continuously measured or sampled over time.

[0049] The measured gate voltage Vg_bot and current (or, if the gate drive voltage generation circuit GD includes a voltage source with a resistor, the calculated current) are used to obtain the complete gate charge characteristics of the lower device DUT_bot with respect to the set drain current and the starting dynamic drain voltage Drain_bot. This entire process may be repeated, if necessary, at various drain-source voltages VDS of the lower device DUT_bot and also at various desired levels or values of the drain current ID flowing through the lower device DUT_bot. This process provides the gate charge parameters of the lower device DUT_bot at various current and voltage levels. To obtain these same gate charge parameters for the upper device DUT_top, switch SW is switched to the lower position so that the relevant terminal of the test inductor TEST_L is connected to the reference voltage node RVN instead of the power supply voltage node SVN. Here, if the operation of the upper and lower devices DUT_top and DUT_bot is reversed or switched from that described above, the gate charge curve characteristics of the upper device DUT_top can be measured. The operation of this characteristic evaluation circuit 900 is to evaluate the gate charge parameters of the upper and lower devices DUT_top and DUT_bot, and it is assumed that the gate control and measurement capabilities of this characteristic evaluation circuit are the same for both the upper and lower devices DUT_top and DUT_bot.

[0050] In addition to the gate charge curve parameters of the upper and lower devices DUT_top and DUT_bot, according to the characteristic evaluation circuit 900, it becomes possible to measure the dynamic characteristics of the body diodes BD_top and BD_bot of the upper and lower devices DUT_top and DUT_bot. The parameters of these body diodes are usually measured by a double pulse test. The characteristic evaluation circuit 900 can measure the parameters of the body diodes through the following process. First, the variable DC voltage source DC_adj is set to a desired starting DC voltage level, and both the upper and lower devices DUT_top and DUT_bot are turned off. Next, the lower device DUT_bot is turned on for a certain period of time until the current IL flowing through the inductor TEST_L reaches a desired current threshold. As described above, the value of the current IL may be calculated based on the time the lower device DUT_bot is on, or may be measured continuously.

[0051] When the current IL flowing through the inductor TEST_L reaches a desired threshold value, the lower device DUT_bot turns off. At this point, the inductor current IL flows through the body diode BD_top of the upper device DUT_top. During this period, the current and voltage parameters of the body diode BD_top can be extracted at the stationary part of the current flowing through the body diode, and the dynamic parameters during the transition of this current can also be extracted. Then, the lower device DUT_bot turns on, and a delay time is given to adjust the inductor current IL to the next desired value or level. After that, the lower device DUT_bot turns off, and the body diode parameters of the body diode BD_top are measured again at the new level of the inductor current. This process is repeated at various DC voltage levels supplied by the variable DC power supply voltage source DC_adj, and the timing for the lower DUT_bot device to turn on is adjusted considering the variation in the rate of change of the inductor current IL flowing through the inductor IL, or this current is directly measured until it reaches the threshold value. The entire process may be repeated at various gate-source voltages Vgs supplied by the gate drive voltage generation circuit GD coupled to the upper device DUT_top.

[0052] Through the above process, the characteristic evaluation circuit 900 extracts or measures the body diode parameters of the body diode BD_top of the upper device DUT_top. This process may be executed when the configuration of the switch SW is set to the first position shown in FIG. 9. To extract or measure the same parameters for the body diode BD_bot of the lower device DUT_bot, it is only necessary to set the switch SW to the second position, that is, to couple the relevant terminal of the inductor TEST_L to the reference voltage node RVN instead of the power supply voltage node SVN. When the switch SW is set to the second position, the parameters of the body diode BD_bot of the lower device DUT_bot are extracted or measured by controlling and measuring the upper and lower devices DUT_top and DUT_bot as described above.

[0053] According to the characteristic evaluation circuit 900, for both the upper and lower devices DUT_top and DUT_bot, a negative power supply voltage source is not required to perform a complete body diode characteristic evaluation. Further, in an embodiment of the characteristic evaluation circuit 900, the body diode parameters of one of the upper and lower devices DUT_top and DUT_bot may be measured while measuring the gate charge curve parameters of the other device. For example, while measuring the gate charge curve characteristics of the lower device DUT_bot as described above, the characteristics of the body diode BD_top of the upper device DUT_top may be measured during the period when the lower device DUT_bot of this gate charge curve characteristic evaluation process is off. The extraction of this parameter is performed simultaneously or in parallel during the operation of the characteristic evaluation circuit 900, thereby shortening the time required to evaluate the gate charge curve of one of the devices DUT_top and DUT_bot and the body diode characteristics of the other of the devices DUT_top and DUT_bot.

[0054] In the embodiment of FIG. 9, the upper and lower devices DUT_top and DUT_bot are illustrated as MOSFETs each having a corresponding body diode BD. However, the embodiment of the characteristic evaluation circuit 900 is not limited to the characteristic evaluation of other types of FETs such as MOSFETs or SiC MOSFETs having body diodes. More generally, the characteristic evaluation circuit 900 may evaluate the characteristics of the reverse current path of FETs without body diodes such as gallium nitride (GaN) FETs. In an embodiment of the characteristic evaluation circuit 900, when the upper and lower DUTs DUT_top and DUT_bot are FETs such as GaN FETs that do not include a body diode BD, when the characteristic evaluation circuit measures the reverse conduction state of any one of the upper and lower GaN FETs to be evaluated, the characteristic evaluation circuit 900 operates in the same manner as described above, except that a desired gate voltage is applied to the GaN FET to be evaluated. This desired gate voltage is applied at a time when the inductor current IL is expected to circulate through the GaN FET to be evaluated as a reverse current.

[0055] Embodiments of the disclosed technology relate to a characteristic evaluation circuit for a test measurement system used in parametric testing on a wafer. As described in more detail below, the present disclosure describes a system for performing characteristic evaluation at the production level of power devices on a wafer, which incorporates parametric sensitivity measurement and meets the speed requirements of the production process. The present disclosure includes solutions to these problems by integrating a parametric system or a semiconductor characteristic evaluation system with power device measurement. The present disclosure includes solutions to these problems by including some pins on a probe card for low voltage measurement and low current measurement, and other pins for power device evaluation (which may include high voltage measurement and high current measurement). The present disclosure includes solutions to these problems by replacing an oscilloscope with an ultra-high speed pulse measurement unit (PMU: Pulse Measure Unit), which enables short-time and high-speed voltage pulses while also measuring transient phenomena, thereby fulfilling two roles of the gate drive function for dynamic test measurement and effectively replacing the oscilloscope. The central components of the present disclosure involve utilizing circuits that perform functions such as voltage clamping, voltage division, and protection against a potential of 3 kV.

[0056] The integration of these components solves the above-mentioned problems and realizes a unique solution (solution method) without comparison. This solution provides several different functions. For example, the PMU functions as a test measurement device within the characteristic evaluation system. Customizable adaptive tests can be executed using the software on the characteristic evaluation system, and data analysis and parameter extraction are possible for dynamic drain-source on-resistance R DSon , double pulse, breakdown (breakdown voltage), leak (leakage current), threshold voltage measurement, etc. The extracted data is then transmitted to the system for comprehensive data report generation.

[0057] FIG. 10 shows an example of a characteristic evaluation measurement platform coupled to a wafer under test according to some embodiments.

[0058] The test measurement system 1000 includes a test measurement device 1002, a parametric system matrix 1004, an adapter circuit 1006, a probe circuit 1008, and a wafer 1010. As shown in FIG. 10, the test measurement device 1002 is coupled to the parametric system matrix 1004. The parametric system matrix 1004 is coupled to both the adapter circuit 1006 and the probe circuit 1008. The adapter circuit 1006 is, in turn, also coupled to the probe circuit 1008. The probe circuit 1008 is coupled to one or more DUTs 1012 of the wafer 1010.

[0059] The test measurement device 1002 can be any test measurement device used for testing the wafer 1010. For example, the test measurement device 1002 can be a pulse measurement unit (PMU), a source measure unit (SMU), or a digital multimeter. In some examples, the test measurement device 1002 can be the test measurement device 12, the test measurement device 22, or the test measurement device 40. In some examples, any number of test measurement devices 1002 can be coupled to the parametric system matrix 1004. Further details regarding the test measurement device 1002 are described with reference to FIG. 11 of the present application.

[0060] The parametric system matrix 1004 is a switch network coupled to the test measurement device 1002. In some examples, the parametric system matrix 1004 can be coupled to any number of test measurement devices 1002 and can also be coupled to other devices such as a ground supply. The parametric system matrix 1004 is configured to link the test measurement device 1002 to the adapter circuit 1006 and, in some examples, is configured to link to the probe circuit 1008. Further details regarding the parametric system matrix 1004 are described with reference to FIG. 11 of the present application.

[0061] As described above, the adapter circuit 1006 is coupled between the parametric system matrix 1004 and the probe circuit 1008. In some examples, the adapter circuit 1006 includes the functions of the characteristic evaluation circuit 400, the characteristic evaluation circuit 500, the characteristic evaluation circuit 600, the characteristic evaluation circuit 800, or the characteristic evaluation circuit 900. The adapter circuit 1006 can be any circuit used to evaluate the characteristics of the DUT 1012 on the wafer 1010. Further details regarding the adapter circuit 1006 are described with reference to FIG. 11 of the present application.

[0062] As described above, the probe circuit 1008 is coupled between the adapter circuit 1006 and the wafer 1010. In some examples, the probe circuit 1008 can be the DUT interface 58. The probe circuit 1008 can be any circuit used to couple the output 1114 of the adapter circuit 1006 or the parametric system matrix 1004 to the DUT 1012 on the wafer 1010. Further details regarding the probe circuit 1008 are described with reference to FIG. 11 of the present application.

[0063] The wafer 1010 may include any number of DUTs 1012. In some examples, the DUT can be a transistor. The DUTs 1012 on the wafer 1010 may all be composed of the same type of power device, or in other cases, the DUTs 1012 on the wafer 1010 may be composed of multiple types of power devices. In some examples, the probe circuit 1008 is coupled to any number of DUTs 1012 on the wafer 1010. The DUTs 1012 on the wafer 1010 as described in the present disclosure are not diced or packaged. Rather, the present disclosure includes testing the DUTs 1012 before dicing and packaging the DUTs 1012.

[0064] FIG. 11 shows an embodiment of a test measurement system according to an embodiment of the disclosed technology. Specifically, FIG. 11 provides further details and examples of a characteristic evaluation measurement platform coupled to a wafer under test, by way of several examples. The test measurement system 1100 of FIG. 11 illustrates two DUTs 1012 on the wafer 1010 of FIG. 10, but although the test measurement system via the probe circuit 1008 is not illustrated as such in FIG. 11, a plurality of DUTs 1012 are coupled to the wafer 1010.

[0065] As illustrated in FIG. 11, the parametric system matrix 1004 is coupled to the test measurement device 1002. Examples of the test measurement device 1002 include, but are not limited to, a PMU, an SMU, a ground, and a digital multimeter. For this reason, the parametric system matrix 1004 has a plurality of inputs for one or more test measurement devices 1002. The parametric system matrix 1004 also has outputs 1112 and 1114, which are coupled to the adapter circuit 1006 and, in some examples, also coupled to the probe circuit 1008. In some examples, the parametric system matrix 1004 is configured to output signals from at least one of the test measurement devices 1002. For example, the parametric system matrix 1004 supplies a first set of a plurality of signals from one test measurement device 1002 to a plurality of outputs 1112 coupled to the adapter circuit 1006, and supplies a second set of a plurality of signals from another test measurement device 1002 to a plurality of outputs 1114 coupled to the probe circuit 1008. Thus, in such examples, the test measurement system 1000 can perform a plurality of tests simultaneously. The test measurement system 1000 shows that the parametric system matrix 1004 is coupled to only one adapter circuit 1006 via each of the outputs 1112 and 1114 and is also coupled to only one other DUT 1012, but the test measurement system 1000 may have any number of adapter circuits 1006 and any number of outputs 1112 and 1114 to test any number of DUTs 1012 on the wafer 1010.

[0066] As described above, the adapter circuit 1006 is coupled between the parametric system matrix 1004 and the probe circuit 1008. The adapter circuit 1006 includes a voltage dividing circuit 1124, a clamping circuit 1126, and at least one buffer circuit 1128. In some examples, the adapter circuit 1006 further includes a block diode 1116, a current limiter 1118, a switchable load circuit 1120, a capacitor bank 1122, and a sense resistor 1130. As illustrated in FIG. 11, the adapter circuit 1006 has a plurality of inputs, which are coupled to a plurality of outputs 1112 of the parametric system matrix 1004. These inputs of the adapter circuit 1006 couple the outputs of the parametric system matrix to the block diode 1116, the voltage dividing circuit 1124, the clamping circuit 1126, and the buffer circuit 1128. The block diode 1116 is then coupled to the current limiter 1118, and the current limiter 1118 is coupled to the switchable load circuit 1120 and the capacitor bank 1122. The switchable load circuit 1120 is coupled to the output of the adapter circuit 1006. In some examples, the switchable load circuit 1120 includes an inductor and a diode. In another example, the switchable load circuit 1120 may have another component, and at this time, the capacitor bank 1122 is coupled to the sense resistor 1130 and the clamping circuit 1126. The sense resistor 1130 is coupled to the output of the adapter circuit 1006 and the buffer circuit 1128. The voltage dividing circuit 1124 of the adapter circuit 1006 is coupled to the clamping circuit and the output of the adapter circuit 1006. As described above, the clamping circuit 1126 is coupled to the input of the adapter circuit 1006, the voltage dividing circuit 1124, and the sense resistor 1130, and the clamping circuit 1126 is coupled to the output of the adapter circuit 1006. The buffer circuit 1128 is coupled to the detection circuit as described above and is also coupled to the output of the adapter circuit 1006. In some examples, the adapter circuit 1006 also has another buffer circuit 1128 coupled between the input of the adapter circuit 1006 and the output of the adapter circuit 1006. In some examples, the adapter circuit 1006 has a path directly connecting the input of the adapter circuit 1006 and the output of the adapter circuit 1006.

[0067] In some examples, the buffer circuit 1128 of the adapter circuit 1006 provides protection against high voltages. For example, the buffer circuit 1128 of the adapter circuit 1006 can provide protection against a potential of 3 kV. In a further embodiment, the buffer circuit 1128 can provide protection against high voltages by providing a high impedance. In some examples, the voltage divider circuit 1124 of the adapter circuit 1006 divides the input voltage from the output 1112 of the parametric system matrix 1004 into a smaller voltage suitable for testing the DUT 1012. For example, the voltage divider circuit 1124 supplies a high voltage (1 kV) from the drain to the PMU (measurable up to a maximum of 40 V), and for this purpose, the voltage divider circuit 1124 divides the high voltage from the drain by a factor of 25 and supplies it to the PMU. In some examples, the clamp circuit 1126 is configured to clamp the voltage entering the clamp circuit 1126, and in such examples, the clamp circuit 1126 can clamp the voltage based on a predetermined condition. For example, the clamp circuit 1126 clamps the voltage to 30 V.

[0068] In some examples, the clamp circuit 1126 of the adapter circuit 1006 is coupled to ground (GND: GND supply, the operating reference potential of the circuit) and provides ground to the remaining circuits within the adapter circuit 1006. In such examples, the test measurement system 1100 has a high current and low voltage path from the terminals of the DUT 1012, through the probe circuit 1008, and further through the sense resistor 1130 to the ground (GND) of the adapter circuit 1006. Similarly, in some examples, the test measurement system 1100 has a high current and high voltage (HV) path from the terminals of the DUT 1012, through the probe circuit 1008, through the switchable load circuit 1120, and further through the capacitor bank 1122 to the ground of the adapter circuit 1006. In some examples, the test measurement system 1100 has a high voltage path from the terminals of the DUT 1012 to the voltage divider circuit 1124 of the adapter circuit 1006 and to the clamp circuit 1126. In some examples, the test measurement system 1100 also has a high voltage path from one of the plurality of outputs 1112 of the parametric system matrix 1004 coupled to the block diode 1116, through the block diode 1116, through the current limiter 1118, to a node between the switchable load circuit 1120 and the capacitor bank 1122.

[0069] The probe circuit 1008 has an input coupled to the adapter circuit 1006 and an input coupled to the output 1114 of the parametric system matrix 1004. The probe circuit 1008 has a port or connection configured to be coupled to the DUT 1012 of the wafer 1010. The signal path of the probe circuit 1008 enables the test measurement system 1100 to be connected to the DUT 1012 under test. For example, the probe circuit 1008 enables the output 1114 of the parametric system matrix 1004 to be connected to the terminals of the DUT 1012. Similarly, the probe circuit 1008 enables the output of the adapter circuit 1006 to be connected to the terminals of the DUT 1012.

[0070] In some examples, DUT1012 has terminals coupled to the terminals DF (Drain, Force) and DS (Drain, Sense) of the probe circuit 1008. The DUT has a terminal coupled to the terminal G of the probe circuit 1008, a terminal coupled to the terminal SS (Source, Sense) of the probe circuit 1008, and a terminal coupled to the terminal SF (Source, Force).

[0071] The test measurement system 1100 as described in the present application can be used to perform various tests on the DUT1012 provided on the wafer 1010. As described above, since the wafer 1010 is not diced or packaged, the probe circuit 1008 is directly coupled to the DUT1012 on the wafer 1010. Depending on the test applied to the DUT1012, the test measurement device 1002 operates via the parametric system matrix 1004 and the adapter circuit 1006 to execute a test on the DUT1012. The tests include a test for obtaining the on-resistance R DSon between the dynamic drain and source, a double-pulse test, a breakdown test, a leakage test, and a threshold voltage measurement test. The tests performed on the DUT1012 are tests compliant with JEDEC (Joint Electron Device Engineering Council) standards.

[0072] FIG. 12 is a flowchart of a test of a power device on a wafer using the test measurement system of FIG. 11 according to some embodiments. The flowchart shows a process 1200 having steps 1202 and 1204. Step 1202 of process 1200 includes the process of coupling a test measurement system (e.g., test measurement system 1100 of FIG. 11) to a DUT (e.g., DUT1012) on a wafer (e.g., wafer 1010). In some examples, the process of coupling the test measurement system to the DUT includes the process of coupling the probe circuit of the test measurement system to the terminals of the DUT.

[0073] Step 1204 of process 1200 includes the process of performing tests on the DUT using a test measurement system. As described above, the DUT to which the test measurement system is coupled is not separated from the other parts of the wafer. That is, since the DUT is not diced or packaged, when performing any tests on the DUT, the test measurement system needs to pay attention to applying test signals to the DUT under test without affecting other devices on the wafer. Tests may include tests for obtaining dynamic (dynamic) R DSon tests, double-pulse tests, breakdown (breakdown voltage) tests, leak (leakage current) tests, and threshold voltage measurement tests.

[0074] The present disclosure includes integrating a parametric system or a semiconductor characterization system with power device measurements. The present disclosure further includes having dedicated pins on the probe circuit for low voltage and low current measurements and other pins for power device evaluation. In some examples, the probe circuit includes at least two low current and low voltage input pins. The present disclosure includes replacing an oscilloscope with a PMU that receives a signal supply from the characterization system, thereby enabling the forcing and measurement of rapid voltage transients, which serves two roles of the gate drive function for dynamic test measurements.

[0075] Aspects of the disclosed technology can operate on a specially programmed general-purpose computer that includes specially created hardware, firmware, a digital signal processor, or a processor operating in accordance with programmed instructions. The terms "controller" or "processor" as used herein are intended to include microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology can be realized by computer-usable data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including monitoring modules) and other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor within a computer or other device, perform a particular task or implement a particular abstract data type. The computer-executable instructions may be stored on a computer-readable storage medium, such as a hard disk, optical disk, removable storage medium, solid state memory, RAM, etc. As will be understood by those skilled in the art, the functions of the program modules may be combined or distributed as necessary in various embodiments. Further, such functions may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. One or more aspects of the disclosed technology can be more effectively implemented using particular data structures, and such data structures are considered to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0076] The disclosed embodiments may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may be implemented as instructions carried or stored by one or more computer-readable media readable by and executable by one or more processors. Such instructions may be referred to as a computer program product. As used herein, a computer-readable media means any media accessible by a computing device. By way of example and not limitation, a computer-readable media may include computer storage media and communication media.

[0077] Computer storage media means any media that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other removable or non-removable media implemented by any technology for storing volatile or nonvolatile information. Computer storage media excludes signals per se and transient forms of signal transmission.

[0078] Communication media means any media that can be used to communicate computer-readable information. By way of example and not limitation, communication media may include coaxial cable, fiber optic cable, air, or any other media suitable for communicating electrical, optical, radio frequency (RF), infrared, sound, or other types of signals.

[0079] In addition, the description of the present application refers to specific features. It should be understood that the disclosure herein includes all possible combinations of these specific features. When a particular feature is disclosed in relation to a particular aspect or embodiment, that feature can be used in relation to other aspects and embodiments as far as possible.

[0080] Also, in the present application, when referring to a method having two or more defined steps or processes, these defined steps or processes may be executed in any order or simultaneously as long as the circumstances do not exclude their possibilities. Example

[0081] Hereinafter, examples beneficial for understanding the technology disclosed in the present application are presented. Embodiments of this technology may include one or more of the examples described below and any combination.

[0082] Example 1 is a characteristic evaluation system for a power device, comprising a parametric system matrix coupled to one or more test measurement devices, and an adapter circuit coupled to the parametric system matrix, the adapter circuit having a voltage clamp circuit coupled to the parametric system matrix, and a probe circuit coupled to the adapter circuit and the power device on the wafer.

[0083] Example 2 is the system of Example 1, wherein the parametric system matrix is coupled to the probe circuit.

[0084] Example 3 is the system of Example 1 or Example 2, wherein the wafer may include a plurality of power devices, and the power device is one of the plurality of power devices on the wafer.

[0085] Example 4 is any one of the systems of Examples 1 to 3, wherein the adapter circuit may have a plurality of first inputs and a plurality of first outputs, the plurality of first inputs are coupled to a plurality of second outputs from a parametric system matrix, and the plurality of first outputs are coupled to a plurality of second inputs of the probe circuit.

[0086] Example 5 is any one of the systems of Examples 1 to 4, wherein the one or more test measurement devices may have a pulse measurement unit configured to generate a pulse and perform dynamic current and voltage measurements.

[0087] Example 6 is any one of the systems of Examples 1 to 5, wherein the adapter circuit is configured to determine the dynamic drain-source on-resistance of the power device.

[0088] Example 7 is any one of the systems of Examples 1 to 6, wherein the adapter circuit may include a voltage dividing circuit and one or more voltage protection circuits.

[0089] Example 8 is any one of the systems of Examples 1 to 7, wherein the probe circuit may include at least two low-current and low-voltage input pins.

[0090] Example 9 is any one of the systems of Examples 1 to 8, wherein the adapter circuit may include a block diode, a current limiter, a switchable load circuit, a capacitor, and a sense resistor.

[0091] Example 10 is any one of the systems of Examples 1 to 9, wherein the switchable load circuit is coupled to the power device via the probe circuit, and the switchable load circuit is coupled in series with a current limiter and a block diode.

[0092] Example 11 is any one of the systems of Examples 1 to 10, wherein the capacitor and the sense resistor are coupled in series to the power device via the probe circuit.

[0093] Example 12 is any one of the systems of Examples 1 to 11, wherein the voltage clamp circuit is coupled to a sense resistor, the sense resistor is coupled to the power device via the probe circuit, and by virtue of the availability and function of the voltage clamp circuit, accurate dynamic on-resistance between the drain and source (R DSon ) measurement becomes possible.

[0094] Example 13 is any one of the systems of Examples 1 to 12, wherein the system is configured to perform at least one test on the wafer, and the at least one test may include a dynamic on-resistance test between the drain and source, a double-pulse test, a breakdown (breakdown voltage) test, a leak (leakage current) test, or a threshold voltage test.

[0095] 09:28 Example 14 is any one of the systems of Examples 1 to 13, wherein the power device is a first power device, the parametric system matrix is coupled to a second power device on the wafer, and the system is configured to perform a first test on the first power device and a second test on the second power device simultaneously.

[0096] Example 15 is any one of the methods of Examples 1 to 14, wherein the power device is a transistor.

[0097] Example 16 is any one of the systems of Examples 1 to 15, wherein the adapter circuit is configured to test the power device using JEDEC (Joint Electron Device Engineering Council) standards.

[0098] Example 17 is any one of the systems of Examples 1 to 16, further comprising a parametric system having the parametric system matrix.

[0099] Example 18 is any one of the systems of Examples 1 to 17, wherein the parametric system is configured to enable data analysis and parameter extraction using the adapter circuit and the probe circuit.

[0100] Example 19 is a method for testing a power device, wherein a probe circuit is coupled to an adapter circuit, and the adapter circuit is coupled to a parametric system matrix. The method includes coupling the probe circuit to the power device on the wafer, and performing a test on the power device by transmitting a signal to the probe circuit via the parametric system matrix and via the adapter circuit.

[0101] Example 20 is the method of Example 19, wherein the test may be a dynamic drain-source on-resistance test, a double-pulse test, a breakdown (breakdown voltage) test, a leak (leakage current) test, or a threshold voltage test.

[0102] The above description of the present invention is merely set forth to explain the present invention and is not intended to be limiting. Modifying the disclosed embodiments by incorporating the gist of the present invention is conceivable to those skilled in the art, and the invention should be construed to include all within the scope of the present invention.

[0103] The above versions of the subject matter of the present disclosure have many effects that have been described or will be apparent to those skilled in the art. Nevertheless, not all of these effects or features are required in all versions of the disclosed apparatus, system, or method.

[0104] In addition, the description of the present application mentions specific features. All features disclosed in this specification, including the claims, the abstract and the drawings, and all steps in all methods or processes disclosed, may be combined arbitrarily as long as at least some of them are not mutually exclusive. Each of the features disclosed in this specification, including the claims, the abstract and the drawings, may be replaced by alternative features that serve the same, equivalent or similar purpose, unless otherwise specified.

[0105] Also, in the present application, when referring to a method having two or more defined steps or processes, these defined steps or processes may be executed in any order or simultaneously, as long as the circumstances do not exclude their possibilities.

[0106] For the sake of explanation, specific embodiments of the disclosed technology have been illustrated and described. However, it can be understood that various changes are possible without departing from the gist and scope of the disclosed technology. Therefore, the disclosed technology should not be limited except by the appended claims.

Explanation of Reference Numerals

[0107] 40 Test measurement device 42 Remote device 44 User interface 46 One or more processors 47 Measurement unit 48 Direct connection part 50 Static and dynamic power supplies and measurement devices 52 One or more processors 54 Interlock 56 High voltage circuit 58 DUT interface 60 Switching circuit 62 Temperature control circuit 64 Barrier 70 Device under test (DUT) 300 Test measurement system 400 Characteristic evaluation circuit 500 Characteristic evaluation circuit 600 Characteristic evaluation circuit 700 Solid - State Bias Tee 800 Characteristic Evaluation Circuit 900 Characteristic Evaluation Circuit 1000 Test Measurement System 1002 Test Measurement Device 1004 Parametric System Matrix 1006 Adapter Circuit 1008 Probe Circuit 1010 Wafer 1012 One or More DUTs 1100 Test Measurement System 1112 First Output of Parametric System Matrix 1114 Second Output of Parametric System Matrix 1116 Block Diode 1118 Current Limiter 1120 Swappable Load Circuit 1122 Capacitor Bank 1124 Voltage Divider Circuit 1126 Clamp Circuit 1128 Buffer Circuit 1130 Detection Resistance

Claims

1. A power device characteristic evaluation system, comprising: A parametric system matrix coupled to one or more test measurement devices; An adapter circuit coupled to the parametric system matrix, the adapter circuit having a voltage clamp circuit coupled to the parametric system matrix; A probe circuit coupled to the adapter circuit and the power device on the wafer; A power device characteristic evaluation system comprising the above.

2. The power device characteristic evaluation system according to Claim 1, wherein the parametric system matrix is coupled to the probe circuit.

3. The power device characteristic evaluation system according to Claim 1, wherein the adapter circuit has a plurality of first inputs and a plurality of first outputs, the plurality of first inputs are coupled to a plurality of second outputs from the parametric system matrix, and the plurality of first outputs are coupled to a plurality of second inputs of the probe circuit.

4. The power device characteristic evaluation system according to Claim 1, wherein the one or more test measurement devices have a pulse measurement unit configured to generate a pulse and perform dynamic current and voltage measurements.

5. The power device characteristic evaluation system according to Claim 1, wherein the adapter circuit is configured to obtain the dynamic drain-source on-resistance of the power device.

6. The power device characteristic evaluation system according to Claim 1, wherein the adapter circuit has a voltage division circuit and one or more voltage protection circuits.

7. The power device characteristic evaluation system according to Claim 1, wherein the adapter circuit has a blocking diode, a current limiter, a replaceable load circuit, a capacitor, and a detection resistor.

8. The power device characteristic evaluation system according to Claim 7, wherein the replaceable load circuit is coupled to the power device via the probe circuit, and the replaceable load circuit is coupled in series with the current limiter and the blocking diode.

9. The power device characteristic evaluation system according to Claim 7, wherein the capacitor and the detection resistor are coupled in series to the power device via the probe circuit.

10. The voltage clamp circuit is coupled to the detection resistor, and the detection resistor is coupled to the power device via the probe circuit. By virtue of the availability of the voltage clamp circuit and its function, accurate dynamic drain-source on-resistance (R DSon ) measurement becomes possible for the power device characteristic evaluation system according to claim 7.

11. The above system is configured to perform at least one test on the above wafer, and the at least one test includes a dynamic drain-source on-resistance test, a double-pulse test, a breakdown test, a leakage current test, or a threshold voltage test. The power device characteristic evaluation system of claim 1.

12. The power device is a first power device, and the parametric system matrix is coupled to a second power device of the wafer. The system is configured to simultaneously perform a first test on the first power device and a second test on the second power device. The power device characteristic evaluation system of claim 1.

13. A method for testing a power device, wherein a probe circuit is coupled to an adapter circuit, and the adapter circuit is coupled to a parametric system matrix. The process of coupling the probe circuit to a power device on the wafer, and the process of performing a test on the power device by transmitting a signal to the probe circuit via the parametric system matrix and via the adapter circuit A method for testing a power device comprising the above.

14. The above test includes a dynamic drain-source on-resistance test, a double-pulse test, a breakdown test, a leakage current test, or a threshold voltage test. The method of claim 13.

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