Nitride semiconductor device

Abstract

To provide a nitride semiconductor device in which on-resistance can be reduced.SOLUTION: A nitride semiconductor device 10 includes: an electron transit layer 16; an electron supply layer 18 provided on the electron transit layer 16; a gate layer 22 provided on the electron supply layer 18; a gate electrode 24 provided on the gate layer 22; a first passivation layer 28 covering the electron supply layer 18, the gate layer 22, and the gate electrode 24 and including a first source opening 28A and a first drain opening 28B disposed to sandwich the gate layer 22 therebetween in an X-axis direction and an auxiliary opening 28C disposed between the gate layer 22 and the first drain opening 28B; a source electrode 32 and a drain electrode 34 in contact with the electron supply layer 18; an auxiliary layer 50 in contact with the electron supply layer 18 exposed by the auxiliary opening 28C, the auxiliary layer comprising a nitride semiconductor having a larger bandgap than the electron transit layer 16; and a second passivation layer 30 covering the auxiliary layer 50.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device.

Background Art

[0002] Currently, the commercialization of high electron mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) (hereinafter sometimes simply referred to as "nitride semiconductors") is progressing (see, for example, Patent Document 1). A nitride semiconductor device having such a configuration includes, for example, an electron traveling layer, an electron supply layer formed on the electron traveling layer and having a larger bandgap than the electron traveling layer, a gate layer formed on the electron traveling layer and containing acceptor-type impurities, a gate electrode formed on the gate layer, and a passivation layer covering the electron supply layer, the gate layer, and the gate electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] By the way, in the HEMT as described above, it may be desirable to reduce the on-resistance.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes an electron transport layer composed of a nitride semiconductor, an electron supply layer provided on the electron transport layer and composed of a nitride semiconductor having a larger bandgap than the electron transport layer, a gate layer provided on the electron supply layer and composed of a nitride semiconductor containing acceptor-type impurities, a gate electrode provided on the gate layer, a first source opening and a first drain opening that cover the electron supply layer, the gate layer, and the gate electrode and are arranged with the gate layer sandwiched therebetween in a first direction, and a first passivation layer including an auxiliary opening arranged between the gate layer and the first drain opening. The nitride semiconductor device further includes a source electrode in contact with the electron supply layer exposed by the first source opening, a drain electrode in contact with the electron supply layer exposed by the first drain opening, an auxiliary layer in contact with the electron supply layer exposed by the auxiliary opening and composed of a nitride semiconductor having a larger bandgap than the electron transport layer, and a second passivation layer covering the auxiliary layer.

Brief Description of the Drawings

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[0007] [Detailed Description] Hereinafter, some embodiments of the nitride semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to a fixed scale. Also, for ease of understanding, in sectional views, the hatching lines may be omitted. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure. Terms such as "first", "second", "third", etc. in the present disclosure are merely used to distinguish objects and do not rank the objects.

[0008] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] (Embodiment) (Schematic Structure of Nitride Semiconductor Device) FIG. 1 is an exemplary schematic plan view of a nitride semiconductor device 10 according to an embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device 10 cut along the line F2 - F2 of FIG. 1. FIG. 3 is a schematic cross-sectional view for explaining the state of the nitride semiconductor device of FIG. 2. FIG. 4 is a schematic cross-sectional view for explaining the details of the configuration of the nitride semiconductor device of FIG. 2. In FIGS. 1 to 4, unless otherwise explicitly stated, "plan view" indicates viewing the object along the Z-axis direction of the nitride semiconductor device 10. FIGS. 2 to 4 show the cross-sectional structure along the XZ plane.

[0010] In one example, the nitride semiconductor device 10 may be a HEMT using GaN. Hereinafter, with reference to FIGS. 2 and 3, the cross-sectional structure of the nitride semiconductor device 10 will be described, and then with reference to FIG. 1, the planar structure of the nitride semiconductor device 10 will be described.

[0011] As shown in FIG. 2, the nitride semiconductor device 10 may include a semiconductor substrate 12 and a buffer layer 14 provided on the semiconductor substrate 12. The nitride semiconductor device 10 may further include an electron traveling layer 16 and an electron supply layer 18 provided on the electron traveling layer 16.

[0012] The semiconductor substrate 12 can be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 may be a Si substrate. The thickness of the semiconductor substrate 12 can be, for example, 100 μm or more and 1500 μm or less. In one example, the thickness of the semiconductor substrate 12 is 250 μm.

[0013] The buffer layer 14 may include one or more nitride semiconductor layers. The electron traveling layer 16 is provided on the buffer layer 14. In one example, the buffer layer 14 can be composed of any material that can facilitate the epitaxial growth of the electron traveling layer 16. The buffer layer 14 may include one or more nitride semiconductor layers.

[0014] For example, the buffer layer 14 can include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. In order to suppress the leakage current in the buffer layer 14, impurities may be introduced into a part of the buffer layer 14 to make the buffer layer 14 semi-insulating. In that case, the impurities are, for example, carbon (C) or iron (Fe), and the concentration of the impurities can be, for example, 4×10 16 cm -3 or more.

[0015] The electron transport layer 16 is composed of a nitride semiconductor. The electron transport layer 16 may be, for example, a GaN layer. The thickness of the electron transport layer 16 can be, for example, 0.5 μm or more and 2 μm or less. In addition, in order to suppress the leakage current in the electron transport layer 16, by introducing impurities into a part of the electron transport layer 16, the region other than the surface layer region of the electron transport layer 16 may be made semi-insulating. In this case, the impurity may be, for example, C. The impurity concentration in the electron transport layer 16 can be, for example, 1×10 16 cm -3 or more.

[0016] The electron supply layer 18 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the electron supply layer 18 which is an AlGaN layer has a larger bandgap than the electron transport layer 16 which is a GaN layer. In one example, the electron supply layer 18 is composed of Al α Ga (1-α) N with an Al composition ratio α. The Al composition ratio α may be 0.1 < α < 1. The Al composition ratio α may be 0.1 < α < 0.4, and preferably 0.1 < α < 0.3. The thickness T11 of the electron supply layer 18 may be 5 nm or more and 20 nm or less. In one example, the thickness T11 of the electron supply layer 18 may be 8 nm or more.

[0017] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 16 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 18 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 16 near the hetero-junction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads in the electron transport layer 16 at a position close to the hetero-junction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0018] (Gate layer and gate electrode) The nitride semiconductor device 10 further includes a gate layer 22 formed on the electron supply layer 18 and a gate electrode 24 formed on the gate layer 22. The gate layer 22 may be formed on a part of the electron supply layer 18.

[0019] The gate layer 22 is composed of a nitride semiconductor containing acceptor-type impurities. In the present embodiment, the gate layer 22 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 22 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. In one example, the gate layer 22 may be GaN containing at least one of Mg and Zn as an impurity. Further details of the gate layer 22 will be described later.

[0020] The gate electrode 24 may be composed of one or more metal layers. In one example, the gate electrode 24 may be composed of a titanium nitride (TiN) layer. In another example, the gate electrode 24 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 24 can form a Schottky junction with the gate layer 22. The gate electrode 24 can be formed in a region smaller than the gate layer 22 in plan view. The thickness of the gate electrode 24 may be, for example, 50 nm or more and 200 nm or less.

[0021] (Passivation layer) The nitride semiconductor device 10 may further include a passivation layer 26 that covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. The passivation layer 26 may be formed of, for example, at least one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the passivation layer 26 may be composed of a material containing SiN. The thickness of the passivation layer 26 may be, for example, 80 nm or more and 150 nm or less.

[0022] The passivation layer 26 includes a source opening 26A and a drain opening 26B spaced apart in the X-axis direction. In this specification, the X-axis direction is also referred to as the first direction, and the Y-axis direction is also referred to as the second direction. Therefore, the second direction is orthogonal to the first direction in plan view. The gate layer 22 is located between the source opening 26A and the drain opening 26B. More specifically, the gate layer 22 may be arranged between the source opening 26A and the drain opening 26B and closer to the source opening 26A than the drain opening 26B.

[0023] The passivation layer 26 includes a first passivation layer 28 and a second passivation layer 30. The first passivation layer 28 is disposed on the electron supply layer 18. The first passivation layer 28 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. In one example, the first passivation layer 28 is in contact with the electron supply layer 18, the gate layer 22, and the gate electrode 24. The second passivation layer 30 covers the first passivation layer 28 in one example.

[0024] The first passivation layer 28 and the second passivation layer 30 may be formed of a material containing SiN. In one example, the thickness T21 of the first passivation layer 28 in the Z-axis direction may be greater than the thickness T22 of the second passivation layer 30 in the Z-axis direction. The thickness T21 of the first passivation layer 28 may be equal to the thickness T22 of the second passivation layer 30, or may be smaller than the thickness T22 of the second passivation layer 30.

[0025] The source opening 26A of the passivation layer 26 penetrates through the first passivation layer 28 and the second passivation layer 30. It can be said that the source opening 26A is composed of a first source opening 28A of the first passivation layer 28 and a second source opening 30A of the second passivation layer 30. The drain opening 26B can be said to be composed of a first drain opening 28B of the first passivation layer 28 and a second drain opening 30B of the second passivation layer 30. Specifically, the first passivation layer 28 includes a first source opening 28A and a first drain opening 28B disposed with the gate layer 22 interposed therebetween. The first source opening 28A exposes a part of the electron supply layer 18. The first drain opening 28B exposes a part of the electron supply layer 18 that is different from the first source opening 28A. The second passivation layer 30 includes a second source opening 30A communicating with the first source opening 28A and a second drain opening 30B communicating with the first drain opening 28B.

[0026] (Source electrode and drain electrode) The nitride semiconductor device 10 further includes a source electrode 32 in contact with the electron supply layer 18 through the source opening 26A and a drain electrode 34 in contact with the electron supply layer 18 through the drain opening 26B. The source electrode 32 and the drain electrode 34 can be composed of one or a plurality of metal layers (for example, any combination such as a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer).

[0027] Since at least a part of the source electrode 32 is filled in the source opening 26A, it can make an ohmic contact with the 2DEG 20 directly under the electron supply layer 18 exposed by the source opening 26A. Similarly, since at least a part of the drain electrode 34 is filled in the drain opening 26B, it can make an ohmic contact with the 2DEG 20 directly under the electron supply layer 18 exposed by the drain opening 26B.

[0028] The source electrode 32 may include a source main body portion 32A disposed in the source opening 26A and a source extension portion 32B disposed on the peripheral edge of the source opening 26A in the passivation layer 26. The source opening 26A is composed of a first source opening 28A and a second source opening 30A communicating with the first source opening 28A. It can be said that the source main body portion 32A is disposed across the first source opening 28A and the second source opening 30A. The source extension portion 32B extends from the source main body portion 32A onto the second passivation layer 30 of the passivation layer 26.

[0029] The drain electrode 34 may include a drain main body portion 34A disposed in the drain opening 26B and a drain extension portion 34B disposed on the peripheral edge of the drain opening 26B in the passivation layer 26. The drain opening 26B is composed of a first drain opening 28B and a second drain opening 30B communicating with the first drain opening 28B. It can be said that the drain main body portion 34A is disposed across the first drain opening 28B and the second drain opening 30B. The drain extension portion 34B extends from the drain main body portion 34A onto the second passivation layer 30 of the passivation layer 26.

[0030] (Field plate electrode) The nitride semiconductor device 10 may further include a field plate electrode 32C that is formed on the passivation layer 26 and at least partially extends in a region between the gate layer 22 and the drain electrode 34 in a plan view. In the example shown in FIG. 2, the field plate electrode 32C is integrally formed with the source electrode 32. In one example, the field plate electrode 32C extends from the source extension 32B of the source electrode 32 toward the drain electrode 34. Among the integrally formed electrodes, the source electrode 32 may include at least a portion embedded in the source opening 26A of the passivation layer 26, and the field plate electrode 32C may include the remaining portion. Note that the field plate electrode 32C only needs to be electrically connected to the source electrode 32 and does not necessarily have to be continuous with the source electrode 32.

[0031] The field plate electrode 32C is separated from the drain electrode 34. The field plate electrode 32C may include a plate end 32D that is located between the gate layer 22 and the drain electrode 34 (drain opening 26B) in a plan view.

[0032] When a drain voltage is applied to the drain electrode 34 in an off state where the field plate electrode 32C disappears the channel of the 2DEG 20 in the electron traveling layer 16 directly under the gate layer 22, the field concentration near the end of the gate electrode 24 can be relaxed.

[0033] (Details of the gate layer) The gate layer 22 includes an upper surface 22A in contact with the gate electrode 24 and a lower surface 22B in contact with the electron supply layer 18.

[0034] The gate layer 22 may include a ridge portion 42, a first extending portion 44 and a second extending portion 46 that extend in opposite directions from both ends of the ridge portion 42. The ridge portion 42, the first extending portion 44, and the second extending portion 46 constitute a step structure of the gate layer 22.

[0035] The ridge portion 42 corresponds to a relatively thick portion of the gate layer 22. The upper surface of the ridge portion 42 constitutes the upper surface 22A of the gate layer 22. The lower surface of the ridge portion 42 constitutes a part of the lower surface 22B of the gate layer 22. The gate electrode 24 is in contact with the upper surface of the ridge portion 42, that is, a part of the upper surface 22A of the gate layer 22. The ridge portion 42 may have a rectangular shape or a trapezoidal shape in a cross section along the XZ plane of FIG. 2. The thickness T31 of the ridge portion 42 may be, for example, less than 60 nm. In one example, the thickness T31 of the ridge portion 42 may be 50 nm. The thickness T31 of the ridge portion 42 is the distance from the upper surface to the lower surface of the ridge portion 42 (the lower surface of the gate layer 22 in contact with the electron supply layer 18). The thickness of the ridge portion 42 (gate layer 22) may be determined in consideration of various parameters such as gate breakdown voltage.

[0036] The first extending portion 44 extends from the side surface 42A of the ridge portion 42 closer to the source electrode 32 toward the source opening 26A of the passivation layer 26. The second extending portion 46 extends from the side surface 42B of the ridge portion 42 closer to the drain electrode 34 toward the drain opening 26B of the passivation layer 26. The first extending portion 44 is thinner than the ridge portion 42. The second extending portion 46 is thinner than the ridge portion 42. It can be said that the gate layer 22 includes the ridge portion 42, the first extending portion 44 thinner than the ridge portion 42 extending from the ridge portion 42 toward the source opening 26A, and the second extending portion 46 thinner than the ridge portion 42 extending from the ridge portion 42 toward the drain opening 26B.

[0037] In one example, the second extending portion 46 extends longer from the ridge portion 42 than the first extending portion 44. However, the first extending portion 44 and the second extending portion 46 may have the same length. The thickness T32 of the first extending portion 44 may be, for example, 5 nm or more and 25 nm or less. The length L31 of the first extending portion 44 may be, for example, 100 nm or more and 300 nm or less in the direction (X-axis direction) from the ridge portion 42 toward the source opening 26A. The thickness T33 of the second extending portion 46 may be, for example, 5 nm or more and 25 nm or less. The length L32 of the second extending portion 46 may be, for example, 100 nm or more and 600 nm or less in the direction (X-axis direction) from the ridge portion 42 toward the drain opening 26B. The thickness T32 of the first extending portion 44 and the thickness T33 of the second extending portion 46 are equal to each other. Here, if the difference between the thickness T32 of the first extending portion 44 and the thickness T33 of the second extending portion 46 is within 10% of the thickness of the first extending portion 44, it can be said that the thickness of the first extending portion 44 and the thickness of the second extending portion 46 are equal to each other.

[0038] The gate layer 22 contains acceptor-type impurities. In one example, the gate layer 22 has a concentration profile in which the concentration of acceptor-type impurities varies in the Z direction. In one example, the gate layer 22 has a concentration profile in which the concentration of acceptor-type impurities decreases from the central portion in the direction from the upper surface 22A to the lower surface 22B toward the lower surface 22B. Therefore, the average concentration of acceptor-type impurities in the first extending portion 44 and the second extending portion 46 is lower than the average concentration of acceptor-type impurities in the ridge portion 42.

[0039] (Auxiliary layer) The nitride semiconductor device 10 includes an auxiliary layer 50. The auxiliary layer 50 is embedded in the passivation layer 26. The auxiliary layer 50 is in contact with the electron supply layer 18.

[0040] The passivation layer 26 includes a first passivation layer 28 and a second passivation layer 30. The first passivation layer 28 is disposed on the electron supply layer 18. The first passivation layer 28 is in contact with the electron supply layer 18.

[0041] The first passivation layer 28 includes an auxiliary opening 28C. The auxiliary layer 50 is in contact with the electron supply layer 18 within the auxiliary opening 28C. The auxiliary layer 50 may include a first portion 52 in contact with the electron supply layer 18 within the auxiliary opening 28C and a second portion 54 provided on the peripheral edge of the auxiliary opening 28C. In one example, since the first portion 52 is formed on the electron supply layer 18, it is formed by inheriting the crystal information of the electron supply layer 18. Therefore, the first portion 52 has the same properties as the electron supply layer 18. The second portion 54 is formed on the first passivation layer 28 and may be configured as amorphous. When the second portion 54 does not contain a donor-type impurity described later, it may function as an insulating layer.

[0042] The auxiliary layer 50 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16. The auxiliary layer 50 may be, for example, an AlGaN layer. The auxiliary layer 50 which is an AlGaN layer has a larger bandgap than the electron transport layer 16 which is a GaN layer. In one example, the auxiliary layer 50 is composed of Al β Ga (1-β) N. The Al composition ratio β may be 0.1 < β < 1. The auxiliary layer 50 may be the same as the material constituting the electron supply layer 18. The Al composition ratio β of the auxiliary layer 50 may be the same as the Al composition ratio α of the electron supply layer 18. The Al composition ratio β of the auxiliary layer 50 may be larger than the Al composition ratio α of the electron supply layer 18 or may be smaller than the Al composition ratio α of the electron supply layer 18.

[0043] The thickness T12 of the auxiliary layer 50 may be 5 nm or more and 10 nm or less. The thickness T12 of the auxiliary layer 50 may be smaller than the thickness T21 of the first passivation layer 28. The thickness T12 of the auxiliary layer 50 may be smaller than the thickness T32 of the first extension portion 44. It can be said that the thickness T32 of the first extension portion 44 may be larger than the thickness T12 of the auxiliary layer 50. The thickness T12 of the auxiliary layer 50 may be smaller than the thickness T33 of the second extension portion 46. It can be said that the thickness T33 of the second extension portion 46 may be larger than the thickness T12 of the auxiliary layer 50. The thickness T12 of the auxiliary layer 50 may be equal to or less than the thickness T11 of the electron supply layer 18.

[0044] The auxiliary layer 50 may contain donor-type impurities. The donor-type impurities may be, for example, Si. The concentration of the donor-type impurities may be, for example, 1×10 19 cm -3 or more and 1×10 20 cm -3 or less. In one example, the concentration of the donor-type impurities may be about 4×10 19 cm -3

[0045] The auxiliary opening 28C is provided between the gate layer 22 and the drain electrode 34 in the X-axis direction. The auxiliary opening 28C exposes a part of the electron supply layer 18 between the gate layer 22 and the drain electrode 34. The gate layer 22 includes a second extension portion 46 extending from the ridge portion 42 toward the drain electrode 34. The auxiliary opening 28C is provided between the second extension portion 46 and the drain electrode 34. Therefore, it can be said that the second extension portion 46 extends in the X-axis direction from the ridge portion 42 toward the auxiliary opening 28C. It can be said that the second extension portion 46 and the auxiliary opening 28C are spaced apart in the X-axis direction.

[0046] ​The drain electrode 34 includes a drain main body portion 34A provided within the drain opening 26B, and a drain extension portion 34B disposed on the peripheral edge of the second drain opening 30B in the second passivation layer 30. The drain extension portion 34B may include a drain end portion 34C located between the auxiliary opening 28C and the second drain opening 30B (first drain opening 28B). The drain end portion 34C may be disposed closer to the first drain opening 28B and the second drain opening 30B than to the auxiliary opening 28C. In the X-axis direction, the distance L43 between the drain end portion 34C and the drain opening 26B (first drain opening 28B, second drain opening 30B) may be smaller than the distance L44 between the drain end portion 34C and the end portion 28CB of the auxiliary opening 28C closer to the drain electrode 34. In a plan view, the drain extension portion 34B does not overlap with the first portion 52 of the auxiliary layer 50. In a plan view, the drain end portion 34C of the drain electrode 34 is separated from the first portion 52 of the auxiliary layer 50 in the X-axis direction.

[0047] In one example, the distance L11 between the second extending portion 46 and the auxiliary opening 28C in the X-axis direction may be longer than the distance L12 between the auxiliary opening 28C and the first drain opening 28B in the X-axis direction. It can be said that the auxiliary opening 28C is disposed closer to the first drain opening 28B between the second extending portion 46 and the first drain opening 28B.

[0048] In one example, the distance L11 between the second extending portion 46 and the auxiliary opening 28C in the X-axis direction may be shorter than the distance L13 between the first extending portion 44 and the first source opening 28A in the X-axis direction. It can be said that the gate layer 22 is disposed closer to the first source opening 28A between the first source opening 28A and the auxiliary opening 28C.

[0049] In one example, the nitride semiconductor device 10 may include a field plate electrode 32C formed on the passivation layer 26. The plate end portion 32D of the field plate electrode 32C may be disposed between the gate layer 22 and the auxiliary opening 28C in a plan view. The plate end portion 32D may be disposed closer to the auxiliary opening 28C in a plan view. In the X-axis direction, the distance L41 between the plate end portion 32D and the end portion 46B of the second extending portion 46 of the gate layer 22 may be greater than the distance L42 between the plate end portion 32D and the end portion 28CA of the auxiliary opening 28C closer to the gate layer 22. In a plan view, the field plate electrode 32C does not overlap with the first portion 52 of the auxiliary layer 50. In a plan view, the plate end portion 32D of the field plate electrode 32C is separated from the first portion 52 of the auxiliary layer 50 in the X-axis direction.

[0050] The length L21 of the auxiliary opening 28C in the X-axis direction is longer than the length L32 of the second extending portion 46 in the X-axis direction. The length L21 of the auxiliary opening 28C may be five times or more the length L32 of the second extending portion 46. The length L21 of the auxiliary opening 28C in the X-axis direction may be greater than half of the distance L23 between the second extending portion 46 and the first drain opening 28B in the X-axis direction. The length L21 of the auxiliary opening 28C may be 1000 nm or more. The maximum value of the length L21 of the auxiliary opening 28C may be set according to the electrical characteristics of the nitride semiconductor device 10, for example, the breakdown voltage.

[0051] (Planar layout of nitride semiconductor device) Next, with reference to FIG. 1, an example of the planar layout of the nitride semiconductor device 10 will be described. In FIG. 1, the gate electrode 24, the source electrode 32, the drain electrode 34, and the field plate electrode 32C are drawn with broken lines. Also, for the passivation layer 26, the source opening 26A and the drain opening 26B are drawn with solid lines, and the other portions are shown transparently.

[0052] As shown in FIG. 1, the nitride semiconductor device 10 includes a plurality of transistor elements each having an HEMT structure of the nitride semiconductor device 10 in an element region. Note that FIG. 1 shows only a plurality of transistor elements arranged in the X-axis direction. The transistor elements may be arranged side by side in both the X-axis direction and the Y-axis direction.

[0053] The drain electrode 34 is provided for each transistor element. The drain electrode 34 extends in the Y-axis direction in a plan view. The source electrode 32 is provided so as to surround each drain electrode 34 in a plan view, for example. In the example shown in FIG. 1, the source electrode 32 is continuously formed in the X-axis direction across a plurality of transistor elements adjacent in the X-axis direction, but may be separated into a plurality of parts in the X-axis direction.

[0054] The gate layer 22 and the gate electrode 24 are provided for each transistor element. Each gate layer 22 and each gate electrode 24 are formed in an annular shape so as to surround one of the drain electrodes 34 in a plan view.

[0055] The auxiliary layer 50 and the auxiliary opening 28C are arranged between the drain opening 26B and the gate layer 22 in the X-axis direction. In FIG. 1, the auxiliary opening 28C of the first passivation layer 28 is shown by a broken line. The auxiliary opening 28C extends in the Y-axis direction. In one example, the length L22 of the auxiliary opening 28C in the Y-axis direction may be equal to the length of the drain opening 26B in the Y-axis direction. The length L22 of the auxiliary opening 28C may be larger than the length of the drain opening 26B.

[0056] The nitride semiconductor device 10 may include a gate wiring 72, a source wiring 74, and a drain wiring 76. In FIG. 1, the gate wiring 72, the source wiring 74, and the drain wiring 76 are depicted by a dashed line. The gate wiring 72, the source wiring 74, and the drain wiring 76 are located above the source electrode 32 and the drain electrode 34 in the Z-axis direction. The gate wiring 72, the source wiring 74, and the drain wiring 76 extend in the X-axis direction. The gate wiring 72, the source wiring 74, and the drain wiring 76 are arranged to be separated from each other in the Y-axis direction.

[0057] The gate wiring 72 may be arranged at a position different from the drain electrode 34, the source opening 26A, and the drain opening 26B in the Y-axis direction. The gate wiring 72 may be electrically connected to the gate electrode 24 by a via wiring 73. The source wiring 74 and the drain wiring 76 may be arranged at positions overlapping with the drain electrode 34, the source opening 26A, and the drain opening 26B in a plan view in the Y-axis direction. The source wiring 74 may be electrically connected to the source electrode 32 by a via wiring 75. The drain wiring 76 may be electrically connected to the drain electrode 34 by a via wiring 77. In FIG. 1, the via wirings 73, 75, and 77 are depicted by a broken line. The planar layout of the nitride semiconductor device 10 is not limited to the example shown in FIG. 1. Any other planar layout can be applied to the nitride semiconductor device 10.

[0058] (Comparative Example) Here, a comparative example of the nitride semiconductor device 10 of the embodiment will be described. FIG. 6 is a schematic cross-sectional view showing a nitride semiconductor device 10X of a comparative example. The structure of FIG. 6 is shown as a comparative example with the structure of FIG. 2. For the nitride semiconductor device 10X of the comparative example, the same reference numerals are given to the components similar to those of the nitride semiconductor device 10 of the embodiment.

[0059] The nitride semiconductor device 10X of the comparative example includes an electron supply layer 18, a gate layer 22X, and a passivation layer 26X that covers the gate electrode 24. The passivation layer 26X of the comparative example has a single-layer structure. The gate layer 22X has a rectangular or trapezoidal shape in a cross section along the XZ plane of FIG. 6, and does not have the first extending portion 44 and the second extending portion 46 shown in FIG. 2. The thickness T31X of the gate layer 22X is larger than the thickness T31 of the ridge portion 42 of the embodiment.

[0060] (Operation of the Embodiment) The operation of the nitride semiconductor device 10 of the embodiment will be described. As shown in FIG. 4, in the nitride semiconductor device 10 of the embodiment, a voltage V1 of a power supply E1 is applied between the source electrode 32 and the drain electrode 34 via an electron load L as an example. The voltage V1 of the power supply E1 is 48V in one example. When a gate voltage Vg is applied to the gate electrode 24, the nitride semiconductor device 10 is turned on. In FIG. 4, the power supply E2 is equivalently shown as a source of the gate voltage Vg when the nitride semiconductor device 10 is turned on. The gate voltage Vg can be supplied as a pulse signal for switching the nitride semiconductor device 10 at high speed in one example.

[0061] The nitride semiconductor device 10 of the embodiment includes an electron supply layer 18 and an auxiliary layer 50 in contact with the electron supply layer 18. The electron supply layer 18 and the auxiliary layer 50 are composed of a nitride semiconductor having a larger bandgap than the electron traveling layer. Among the auxiliary layer 50, the first portion 52 of the auxiliary layer 50 in contact with the electron supply layer 18 substantially increases the thickness of the electron supply layer 18 on the electron traveling layer 16. Therefore, the first portion 52 of the auxiliary layer 50 increases the density (sheet carrier density) of the 2DEG20A generated in the region overlapping the first portion 52 in the electron traveling layer 16. Thereby, the gate-drain resistance can be reduced. Therefore, the on-resistance of the nitride semiconductor device 10 can be reduced.

[0062] In the nitride semiconductor device 10X of the comparative example shown in FIG. 6, for example, by increasing the thickness of the electron supply layer 18X, the density of the 2DEG 20 generated in the electron traveling layer 16 can be increased. However, in the nitride semiconductor device 10X of the comparative example, since the electron supply layer 18X also becomes thick directly under the gate layer 22, there is a trade-off that the gate threshold value decreases due to the increasing 2DEG 20. On the other hand, in the nitride semiconductor device 10 of the embodiment, the thickness of the electron supply layer 18 is substantially increased between the gate layer 22 and the drain electrode 34. Therefore, since the density of the 2DEG 20 in the electron traveling layer 16 directly under the gate layer 22 does not increase, normally-off can be surely realized.

[0063] In the nitride semiconductor device 10 of the embodiment, the gate layer 22 includes a ridge portion 42, a first extending portion 44 and a second extending portion 46 that extend from the ridge portion 42 and are thinner than the ridge portion 42. In the nitride semiconductor device 10 of the embodiment, the first extending portion 44 and the second extending portion 46 can suppress the electric field concentration to the corner portion where the electric field is the largest at the bottom of the ridge portion 42. Therefore, the band bending of the electron supply layer 18 at the corner portion at the bottom of the ridge portion 42 can be suppressed, and the increase in the gate leakage current can be suppressed. For this reason, in the gate layer 22 thinner than the gate layer 22X that does not include an extending portion, like the nitride semiconductor device 10 of the comparative example, the same level of gate breakdown voltage can be ensured.

[0064] When the gate-source voltage Vgs exceeds the positive threshold voltage by the gate voltage Vg applied to the gate electrode 24, a channel 20C by the 2DEG 20 is formed in the region of the electron traveling layer 16 directly under the ridge portion 42 of the gate layer 22. The thin gate layer 22 increases the ratio of the gate voltage Vg applied to the electron supply layer 18. Thereby, the density of the 2DEG 20 in the channel 20C increases. For this reason, the channel resistance of the nitride semiconductor device 10 can be reduced. Therefore, the on-resistance of the nitride semiconductor device 10 can be further reduced. That is, the nitride semiconductor device 10 of the embodiment can reduce the on-resistance while ensuring the gate breakdown voltage.

[0065] The gate layer 22 contains acceptor-type impurities. The average concentration of acceptor-type impurities in the first extending portion 44 and the second extending portion 46 is lower than the average concentration of acceptor-type impurities in the ridge portion 42. Thereby, the 2DEG 20 directly below the first extending portion 44 and the second extending portion 46 can be increased, and the on-resistance of the nitride semiconductor device 10 can be reduced.

[0066] FIG. 5 shows a zero-bias state in which a voltage equal to the voltage of the source electrode 32 is applied to the gate electrode 24. A voltage V1 (for example, 48 V) of the power supply E1 is applied between the source electrode 32 and the drain electrode 34. In FIG. 5, a region A1 indicated by a one-dot chain line indicates a region where the density of the 2DEG 20A (see FIG. 4) is high due to the auxiliary layer 50. Further, in FIG. 5, a range A2 indicated by an arrow indicates a location where the voltage drops.

[0067] In the state shown in FIG. 5, the field plate electrode 32C extends a depletion layer in the region directly below the field plate electrode 32C, and plays a role of relaxing the electric field concentration near the end of the gate electrode 24 and near the end of the gate layer 22.

[0068] In the state shown in FIG. 5, electric field concentration occurs in a portion 18A of the electron supply layer 18 directly below the plate end 32D of the field plate electrode 32C. When the auxiliary layer 50 is formed on the portion 18A of the electron supply layer 18, the electric field strength in this portion 18A increases, and there is a risk that the breakdown voltage between the drain and the gate decreases. For this reason, the electron supply layer 18 directly below the plate end 32D of the field plate electrode 32C is covered with the first passivation layer 28. That is, an end 28CA of the auxiliary opening 28C of the first passivation layer 28 closer to the gate layer 22 is located closer to the drain electrode 34 than the plate end 32D of the field plate electrode 32C. Thereby, the electric field concentration of the electron supply layer 18 by the field plate electrode 32C can be suppressed, and the decrease in the breakdown voltage between the drain and the gate can be suppressed.

[0069] Similarly, electric field concentration occurs in the portion 18B of the electron supply layer 18 directly below the drain end 34C of the drain electrode 34. Therefore, the portion of the electron supply layer 18 directly below the drain end 34C of the drain electrode 34 is covered with the first passivation layer 28. That is, the end 28CB of the auxiliary opening 28C of the first passivation layer 28 closer to the drain electrode 34 is located closer to the gate layer 22 than the drain end 34C of the drain electrode 34. Thereby, the electric field concentration of the electron supply layer 18 by the drain electrode 34 can be suppressed, and the decrease in the breakdown voltage between the drain and the gate can be suppressed.

[0070] The electron supply layer 18 is composed of Al α Ga (1-α) N (0.1 < α < 1). The auxiliary layer 50 is composed of Al β Ga (1-β) N (0.1 < β < 1). Therefore, the thickness of the AlGaN layer on the electron traveling layer 16 can be increased. Thereby, the density of the 2DEG 20 directly below the auxiliary layer 50 can be increased, and the on-resistance of the nitride semiconductor device 10 can be reduced.

[0071] By adjusting the Al composition ratio α of the AlGaN constituting the electron supply layer 18 and the Al composition ratio β of the AlGaN constituting the auxiliary layer 50, the Al composition of the AlGaN layer on the electron traveling layer 16 can be increased. Thereby, the density of the 2DEG 20 directly below the auxiliary layer 50 can be increased, and the on-resistance of the nitride semiconductor device 10 can be reduced.

[0072] (Method for manufacturing a nitride semiconductor device) With reference to FIGS. 7 to 19, an exemplary manufacturing method of the nitride semiconductor device 10 will be described. In FIGS. 7 to 19, the same components as those in FIG. 2 are denoted by the same reference numerals.

[0073] As shown in FIG. 7, the method for manufacturing a nitride semiconductor device 10 includes sequentially forming a buffer layer 14, an electron transport layer 16, an electron supply layer 18, and a nitride semiconductor layer 82 on a semiconductor substrate 12. The semiconductor substrate 12 is, for example, a Si substrate. The nitride semiconductor layer 82 is, for example, a gallium nitride (GaN) layer. The buffer layer 14, the electron transport layer 16, the electron supply layer 18, and the nitride semiconductor layer 82 can be epitaxially grown, for example, using a metal organic chemical vapor deposition (MOCVD) method.

[0074] The buffer layer 14 may be a multilayer buffer layer. In the multilayer buffer layer, an AlN layer (first buffer layer) is formed on the semiconductor substrate 12, and then a graded AlGaN layer (second buffer layer) is formed on the AlN layer. The graded AlGaN layer is formed, for example, by laminating three AlGaN layers having Al compositions of 75%, 50%, and 25% in order from the side closer to the AlN layer.

[0075] The electron transport layer 16 formed on the buffer layer 14 may be a GaN layer. The electron supply layer 18 formed on the electron transport layer 16 may be an AlGaN layer. Therefore, the electron supply layer 18 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16.

[0076] The nitride semiconductor layer 82 formed on the electron supply layer 18 may contain magnesium as an acceptor-type impurity. By doping magnesium during the growth of the nitride semiconductor layer 82 on the electron supply layer 18, a nitride semiconductor layer 82 containing acceptor-type impurities can be formed.

[0077] As shown in FIG. 8, the method for manufacturing a nitride semiconductor device 10 includes forming a first metal layer 84. In one example, the first metal layer 84 can be formed on the nitride semiconductor layer 82 by a sputtering method. The first metal layer 84 may be, for example, a TiN layer.

[0078] As shown in FIG. 9, the method of manufacturing the nitride semiconductor device 10 includes forming a gate electrode 24. In one example, the gate electrode 24 is formed by selectively removing the first metal layer 84 shown in FIG. 8 by lithography and etching.

[0079] As shown in FIGS. 10 and 11, the method of manufacturing the nitride semiconductor device 10 includes forming a gate layer 22. As shown in FIG. 2, the gate layer 22 includes a ridge portion 42, a first extending portion 44, and a second extending portion 46. Therefore, forming the gate layer 22 may include forming the ridge portion 42 shown in FIG. 10 and forming the first extending portion 44 and the second extending portion 46 shown in FIG. 11. As shown in FIG. 10, in one example, the ridge portion 42 is formed by selectively removing the nitride semiconductor layer 82 shown in FIG. 9 to a predetermined depth by lithography and etching. As shown in FIG. 11, the first extending portion 44 and the second extending portion 46 are formed by selectively removing the nitride semiconductor layer 82 shown in FIG. 10 by lithography and etching.

[0080] As shown in FIG. 12, the method of manufacturing the nitride semiconductor device 10 includes forming a first passivation layer 28. In one example, the first passivation layer 28 may be a SiN layer formed by a low-pressure chemical vapor deposition (LPCVD) method. The first passivation layer 28 is formed so as to cover the electron supply layer 18, the gate layer 22, and the gate electrode 24.

[0081] As shown in FIG. 13, the method of manufacturing the nitride semiconductor device 10 includes forming an auxiliary opening 28C in the first passivation layer 28. The auxiliary opening 28C is formed by selectively removing the first passivation layer 28 shown in FIG. 12 by lithography and etching. A part of the electron supply layer 18 is exposed by the auxiliary opening 28C.

[0082] As shown in FIG. 14, the method for manufacturing the nitride semiconductor device 10 includes forming a nitride semiconductor layer 86. In one example, the nitride semiconductor layer 86 can be epitaxially grown using the MOCVD method. The nitride semiconductor layer 86 is formed to cover a first passivation layer 28 and an electron supply layer 18 exposed by an auxiliary opening 28C of the first passivation layer 28. The nitride semiconductor layer 86 may be an AlGaN layer. In one example, the nitride semiconductor layer 86 may have the same configuration as the electron supply layer 18. Forming the nitride semiconductor layer 86, which is an AlGaN layer, in contact with the electron supply layer 18, which is also an AlGaN layer, can be referred to as AlGaN layer regrowth.

[0083] As shown in FIG. 15, the method for manufacturing the nitride semiconductor device 10 includes forming an auxiliary layer 50. In one example, the auxiliary layer 50 is formed by selectively removing the nitride semiconductor layer 86 shown in FIG. 14 by lithography and etching.

[0084] As shown in FIG. 16, the method for manufacturing the nitride semiconductor device 10 includes forming a second passivation layer 30. In one example, the second passivation layer 30 may be a SiN layer formed by low-pressure chemical vapor deposition (LPCVD). The second passivation layer 30 is formed to cover the first passivation layer 28 and the auxiliary layer 50.

[0085] As shown in FIG. 17, the method for manufacturing the nitride semiconductor device 10 includes forming a source opening 26A and a drain opening 26B in a passivation layer 26. In one example, the source opening 26A and the drain opening 26B are formed by selectively removing the passivation layer 26 by lithography and etching.

[0086] As shown in FIG. 18, the method for manufacturing the nitride semiconductor device 10 includes forming a third metal layer 88. In one example, the third metal layer 88 can be formed on the passivation layer 26 by a sputtering method. The third metal layer 88 is formed so as to fill the source opening 26A and the drain opening of the passivation layer 26. The third metal layer 88 may be, for example, a TiN layer.

[0087] As shown in FIG. 19, the method for manufacturing the nitride semiconductor device 10 includes forming a source electrode 32 and a drain electrode 34. In one example, it is formed by selectively removing the third metal layer 88 shown in FIG. 18 by lithography and etching. Through the above steps, the nitride semiconductor device 10 shown in FIG. 2 is obtained.

[0088] (Effects of the Embodiment) As described above, according to the present embodiment, the following effects are achieved. (1) The nitride semiconductor device 10 includes an electron traveling layer 16, an electron supply layer 18 composed of a nitride semiconductor having a larger bandgap than the electron traveling layer 16, a gate layer 22 composed of a nitride semiconductor containing acceptor-type impurities, a gate electrode 24 provided on the gate layer 22, a first source opening 28A and a first drain opening 28B that cover the electron supply layer 18, the gate layer 22, and the gate electrode 24 and are arranged with the gate layer 22 sandwiched therebetween in the X-axis direction, and a first passivation layer 28 including an auxiliary opening 28C arranged between the gate layer 22 and the first drain opening 28B, a source electrode 32 and a drain electrode 34 in contact with the electron supply layer 18, an auxiliary layer 50 in contact with the electron supply layer 18 exposed by the auxiliary opening 28C and composed of a nitride semiconductor having a larger bandgap than the electron traveling layer 16, and a second passivation layer 30 covering the auxiliary layer 50. The auxiliary layer 50 substantially increases the thickness of the electron supply layer 18 above the electron traveling layer 16. Therefore, the auxiliary layer 50 increases the density (sheet carrier density) of the 2DEG 20 generated in the electron traveling layer 16. Thereby, the gate-drain resistance can be reduced. Therefore, the on-resistance of the nitride semiconductor device 10 can be reduced.

[0089] (2) In the nitride semiconductor device 10 of the embodiment, the thickness of the electron supply layer 18 is substantially increased between the gate layer 22 and the drain electrode 34. Therefore, since the density of the 2DEG 20 in the electron traveling layer 16 directly under the gate layer 22 does not increase, it can be surely turned off.

[0090] (3) The gate layer 22 of the nitride semiconductor device 10 includes a ridge portion 42, a first extending portion 44 and a second extending portion 46 that extend from the ridge portion 42 and are thinner than the ridge portion 42. In the nitride semiconductor device 10 of the embodiment, the first extending portion 44 and the second extending portion 46 can suppress the electric field concentration at the corner where the electric field is the largest at the bottom of the ridge portion 42. Therefore, the band bending of the electron supply layer 18 at the corner of the bottom of the ridge portion 42 can be suppressed, and an increase in the gate leakage current can be suppressed. For this reason, in the gate layer 22 that is thinner than the gate layer 22X that does not include an extending portion, like the nitride semiconductor device 10 of the comparative example, the same level of gate breakdown voltage can be ensured.

[0091] (4) When the gate-source voltage Vgs exceeds a positive threshold voltage due to the gate voltage Vg applied to the gate electrode 24, a channel due to the 2DEG 20 is formed in the region of the electron traveling layer 16 directly under the ridge portion 42 of the gate layer 22. The thin gate layer 22 increases the ratio of the gate voltage Vg applied to the electron supply layer 18. Thereby, the density of the 2DEG 20 in the channel increases. For this reason, the channel resistance of the nitride semiconductor device 10 can be reduced. Therefore, the on-resistance of the nitride semiconductor device 10 can be further reduced. The nitride semiconductor device 10 of the embodiment can reduce the on-resistance while ensuring the gate breakdown voltage.

[0092] (5) The gate layer 22 contains acceptor-type impurities. The average concentration of the acceptor-type impurities in the first extending portion 44 and the second extending portion 46 is lower than the average concentration of the acceptor-type impurities in the ridge portion 42. Thereby, the 2DEG 20 directly under the first extending portion 44 and the second extending portion 46 can be increased, and the on-resistance of the nitride semiconductor device 10 can be reduced.

[0093] (6) The electron supply layer 18 directly under the plate end 32D of the field plate electrode 32C is covered with the first passivation layer 28. That is, the end 28CA of the auxiliary opening 28C of the first passivation layer 28 closer to the gate layer 22 is located closer to the drain electrode 34 than the plate end 32D of the field plate electrode 32C. Thereby, the electric field concentration of the electron supply layer 18 by the field plate electrode 32C can be suppressed, and the decrease in the breakdown voltage between the drain and the gate can be suppressed.

[0094] (7) The electron supply layer 18 directly under the drain end 34C of the drain electrode 34 is covered with the first passivation layer 28. That is, the end 28CB of the auxiliary opening 28C of the first passivation layer 28 closer to the drain electrode 34 is located closer to the gate layer 22 than the drain end 34C of the drain electrode 34. Thereby, the electric field concentration of the electron supply layer 18 by the drain electrode 34 can be suppressed, and the decrease in the breakdown voltage between the drain and the gate can be suppressed.

[0095] (8) The electron supply layer 18 is composed of Al α Ga (1-α) N (0.1 < α < 1). The auxiliary layer 50 is composed of Al β Ga (1-β) N (0.1 < β < 1). Therefore, the thickness of the AlGaN layer on the electron traveling layer 16 can be increased. Thereby, the density of the 2DEG 20 directly under the auxiliary layer 50 can be increased, and the on-resistance of the nitride semiconductor device 10 can be reduced.

[0096] (9) By adjusting the Al composition ratio α of the AlGaN constituting the electron supply layer 18 and the Al composition ratio β of the AlGaN constituting the auxiliary layer 50, the Al composition of the AlGaN layer on the electron traveling layer 16 can be increased. Thereby, the density of the 2DEG 20 directly under the auxiliary layer 50 can be increased, and the on-resistance of the nitride semiconductor device 10 can be reduced.

[0097] (Modified Example) The above-described embodiment can be modified as follows, for example. The above-described embodiment and each of the following modification examples can be combined with each other as long as no technical contradiction occurs. In the following modification examples, for parts common to the above-described embodiment, the same reference numerals as those in the above-described embodiment are given and the description thereof is omitted.

[0098] · The configuration of the nitride semiconductor device 10 in the embodiment may be appropriately changed. As shown in FIG. 20, the nitride semiconductor device 110 in the modification example may include a gate auxiliary layer 48. The gate auxiliary layer 48 may be formed of a nitride semiconductor having a larger bandgap than the gate layer 22. The gate auxiliary layer 48 is provided between the ridge portion 42 of the gate layer 22 and the gate electrode 24. In the example shown in FIG. 20, the gate auxiliary layer 48 may cover the entire upper surface of the ridge portion 42. The gate auxiliary layer 48 helps to deplete the 2DEG 20 directly under the gate layer 22. Thereby, the nitride semiconductor device 110 can be more surely turned off.

[0099] As shown in FIG. 21, the auxiliary layer 50 of the nitride semiconductor device 210 in the modification example may include an extending portion 56 that extends toward the source electrode 32 on the first passivation layer 28. The extending portion 56 of the auxiliary layer 50 covers the gate layer 22 and the gate electrode 24 in plan view. In the case of the auxiliary layer 50 that does not contain a donor-type impurity (for example, Si), the second portion 54 and the extending portion 56 on the first passivation layer 28 may function as an insulating layer. Therefore, the extending portion 56 contributes to increasing the film thickness of the portion of the passivation layer 26 that covers the gate layer 22 and the gate electrode 24.

[0100] As in the nitride semiconductor device 310 in the modification example shown in FIG. 22, the extending portion 56 of the auxiliary layer 50 may extend to the source electrode 32. · At least one of the first extending portion 44 and the second extending portion 46 may be omitted.

[0101] Like the nitride semiconductor device 410 of the modification example shown in FIG. 23, the electron supply layer 418 may include a source opening 418A and a drain opening 418B. The source main body portion 32A of the source electrode 32 is disposed in the source opening 26A of the passivation layer 26 and the source opening 418A of the electron supply layer 418. The source electrode 32 is in contact with the electron supply layer 418. Also, the source electrode 32 is in contact with the electron traveling layer 16. The drain main body portion 34A of the drain electrode 34 is disposed in the drain opening 26B of the passivation layer 26 and the drain opening 418B of the electron supply layer 418. The drain electrode 34 is in contact with the electron supply layer 418. Also, the drain electrode 34 is in contact with the electron traveling layer 16.

[0102] In the modification example shown in FIG. 23, the source opening 418A and the drain opening 418B of the electron supply layer 418 penetrate the electron supply layer 418. The source opening 418A may be formed as a recess such that the electron supply layer 418 is interposed between the source electrode 32 and the electron traveling layer 16. Also, for the modification example shown in FIG. 23, the electron traveling layer 16 includes a recess corresponding to the source opening 418A, and the source electrode 32 may enter the recess of the electron traveling layer 16. The drain opening 418B may be formed as a recess such that the electron supply layer 418 is interposed between the drain electrode 34 and the electron traveling layer 16. Also, for the modification example shown in FIG. 23, the electron traveling layer 16 includes a recess corresponding to the drain opening 418B, and the drain electrode 34 may enter the recess of the electron traveling layer 16.

[0103] As used in the present disclosure, the term "on" includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the expression "the first layer is formed on the second layer" is intended that in some embodiments the first layer may be in contact with the second layer and disposed directly on the second layer, while in other embodiments the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which another layer is formed between the first layer and the second layer.

[0104] The Z-axis direction used in the present disclosure does not necessarily have to be the vertical direction and does not have to exactly coincide with the vertical direction. Therefore, various structures according to the present disclosure (for example, the structure shown in FIG. 1) are not limited to the "upper" and "lower" in the Z-axis direction described in this specification being the "upper" and "lower" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0105] (Appendix) The technical idea that can be grasped from the present disclosure is described below. Note that, for the purpose of assisting understanding rather than for the intention of limitation, the constituent elements described in the appendix are assigned the reference signs of the corresponding constituent elements in the embodiments. The reference signs are shown as examples for assisting understanding, and the constituent elements described in each appendix should not be limited to the constituent elements indicated by the reference signs.

[0106] (Appendix 1) An electron transport layer (16) composed of a nitride semiconductor, An electron supply layer (18) provided on the electron transport layer (16) and composed of a nitride semiconductor having a larger bandgap than the electron transport layer (16), A gate layer (22) provided on the electron supply layer (18) and composed of a nitride semiconductor containing acceptor-type impurities, A gate electrode (24) provided on the gate layer (22), A first passivation layer (28) that covers the electron supply layer (18), the gate layer (22), and the gate electrode (24), and is arranged with a first source opening (28A) and a first drain opening (28B) arranged in a first direction (X) with the gate layer (22) sandwiched therebetween, and an auxiliary opening (28C) arranged between the gate layer (22) and the first drain opening (28B), A source electrode (32) in contact with the electron supply layer (18) exposed by the first source opening (28A), A drain electrode (34) in contact with the electron supply layer (18) exposed by the first drain opening (28B), An auxiliary layer (50) that is in contact with the electron supply layer (18) exposed by the auxiliary opening (28C) and is composed of a nitride semiconductor having a larger bandgap than the electron traveling layer (16); A second passivation layer (30) that covers the auxiliary layer (50); Including A nitride semiconductor device.

[0107] (Appendix 2) The second passivation layer (30) further covers the first passivation layer (28). The nitride semiconductor device according to Appendix 1.

[0108] (Appendix 3) The second passivation layer (30) A second source opening (30A) that communicates with the first source opening (28A); A second drain opening (30B) that communicates with the first drain opening (28B); Including The nitride semiconductor device according to Appendix 2.

[0109] (Appendix 4) The drain electrode (34) A drain main body portion (34A) that is disposed across both the first drain opening (28B) and the second drain opening (30B); A drain extension portion (34B) provided on the peripheral edge of the second drain opening (30B) in the second passivation layer (30); Including The drain extension portion (34B) includes a drain end portion (34C) on the auxiliary opening (28C) side, The drain end portion (34C) is disposed between the auxiliary opening (28C) and the first drain opening (28B) in a plan view. The nitride semiconductor device according to Appendix 3.

[0110] (Appendix 5) The drain end portion (34C) is disposed closer to the first drain opening (28B). The nitride semiconductor device according to Supplementary Note 4.

[0111] (Supplementary Note 6) It is provided on the second passivation layer (30) and includes a field plate electrode (32C) that at least partially extends in a region between the gate layer (22) and the drain electrode (34) in a plan view. The field plate electrode (32C) is electrically connected to the source electrode (32). The field plate electrode (32C) includes a plate end portion (32D) on the auxiliary opening (28C) side. The plate end portion (32D) is disposed between the gate layer (22) and the auxiliary opening (28C) in a plan view. The nitride semiconductor device according to any one of Supplementary Notes 2 to 5.

[0112] (Supplementary Note 7) The plate end portion (32D) is between the gate layer (22) and the auxiliary opening (28C) in a plan view and is disposed closer to the auxiliary opening (28C). The nitride semiconductor device according to Supplementary Note 6.

[0113] (Supplementary Note 8) The plate end portion (32D) is between the gate layer (22) and the auxiliary opening (28C) in a plan view and is disposed closer to the gate layer (22). The nitride semiconductor device according to Supplementary Note 6.

[0114] (Supplementary Note 9) The thickness of the auxiliary layer (50) is equal to or less than the thickness of the electron supply layer (18). The nitride semiconductor device according to any one of Supplementary Notes 1 to 8.

[0115] (Supplementary Note 10) The auxiliary layer (50) is disposed within a range between the gate layer (22) and the first drain opening (28B) in the first direction (X). The nitride semiconductor device according to any one of Appendices 1 to 9.

[0116] (Appendix 11) The auxiliary layer (50) contains donor-type impurities. The nitride semiconductor device according to any one of Appendices 1 to 10.

[0117] (Appendix 12) The electron supply layer (18) is composed of Al α Ga (1-α) N (0.1 < α < 1). The auxiliary layer (50) is composed of Al β Ga (1-β) N (0.1 < β < 1). The nitride semiconductor device according to any one of Appendices 1 to 11.

[0118] (Appendix 13) The Al composition ratio β of the auxiliary layer (50) is greater than the Al composition ratio α of the electron supply layer (18). The nitride semiconductor device according to Appendix 12.

[0119] (Appendix 14) The Al composition ratio β of the auxiliary layer (50) is the same as the Al composition ratio α of the electron supply layer (18). The nitride semiconductor device according to Appendix 12.

[0120] (Appendix 15) The Al composition ratio β of the auxiliary layer (50) is smaller than the Al composition ratio α of the electron supply layer (18). The nitride semiconductor device according to Appendix 12.

[0121] (Appendix 16) The first passivation layer (28) and the second passivation layer (30) are made of a material containing SiN. The nitride semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 13.

[0122] (Supplementary Note 17) The thickness of the first passivation layer (28) is greater than the thickness of the second passivation layer (30). The nitride semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 16.

[0123] (Supplementary Note 18) The thickness of the first passivation layer (28) is equal to the thickness of the second passivation layer (30). The nitride semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 16.

[0124] (Supplementary Note 19) The thickness of the first passivation layer (28) is smaller than the thickness of the second passivation layer (30). The nitride semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 16.

[0125] (Supplementary Note 20) The gate layer (22) A ridge portion (42) provided at a position overlapping with the gate electrode (24), A first extending portion (44) that is thinner than the ridge portion (42) and extends in the first direction (X) from the ridge portion (42) toward the first source opening (28A), A second extending portion (46) that is thinner than the ridge portion (42) and extends in the first direction (X) from the ridge portion (42) toward the auxiliary opening (28C), and includes The second extending portion (46) and the auxiliary opening (28C) are arranged to be separated in the first direction (X). The nitride semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 19.

[0126] (Supplementary Note 21) The length of the auxiliary opening (28C) in the first direction (X) is longer than the length of the second extending portion (46) in the first direction (X). The nitride semiconductor device described in Supplementary Note 20.

[0127] (Supplementary Note 22) The length of the second extending portion (46) is 100 nm or more and 600 nm or less. The nitride semiconductor device described in Supplementary Note 21.

[0128] (Supplementary Note 23) The thicknesses of the first extending portion (44) and the second extending portion (46) are greater than the thickness of the auxiliary layer (50). The nitride semiconductor device described in any one of Supplementary Notes 20 to 22.

[0129] (Supplementary Note 24) The thickness of the second extending portion (46) is 5 nm or more and 25 nm or less. The thickness of the auxiliary layer (50) is 5 nm or more and 10 nm or less. The nitride semiconductor device described in Supplementary Note 23.

[0130] (Supplementary Note 25) The thickness of the ridge portion (42) is less than 60 nm. The nitride semiconductor device described in any one of Supplementary Notes 20 to 24.

[0131] (Supplementary Note 26) The average concentration of acceptor impurities in the ridge portion (42) is higher than the average concentrations of acceptor impurities contained in the first extending portion (44) and the second extending portion (46). The nitride semiconductor device described in any one of Supplementary Notes 20 to 25.

[0132] (Supplementary Note 27) Including a gate auxiliary layer (48) provided between the ridge portion (42) and the gate electrode (24) and composed of a nitride semiconductor having a larger bandgap than the gate layer (22). The nitride semiconductor device described in any one of Supplementary Notes 20 to 26.

[0133] (Supplementary Note 28) The distance between the second extending portion (46) and the auxiliary opening (28C) in the first direction (X) is longer than the distance between the auxiliary opening (28C) and the first drain opening (28B) in the first direction (X). The nitride semiconductor device according to any one of Appendices 20 to 27.

[0134] [[ID=⑥]] (Appendix 29) The distance between the second extending portion (46) and the auxiliary opening (28C) in the first direction (X) is shorter than the distance between the first extending portion (44) and the first source opening (28A) in the first direction (X). The nitride semiconductor device according to any one of Appendices 20 to 27.

[0135] (Appendix 30) The length of the auxiliary opening (28C) in the first direction (X) is longer than half of the distance between the second extending portion (46) and the first drain opening (28B) in the first direction (X). The nitride semiconductor device according to any one of Appendices 20 to 27.

[0136] (Appendix 31) The auxiliary layer (50) extends toward the source electrode (32) along the upper surface of the first passivation layer (28). The nitride semiconductor device according to any one of Appendices 1 to 30.

[0137] (Appendix 32) The auxiliary layer (50) is connected to the source electrode (32). The nitride semiconductor device according to Appendix 31.

[0138] The above description is merely illustrative. Those skilled in the art can recognize that there are more possible combinations and substitutions other than the components and methods (manufacturing processes) listed for the purpose of explaining the technology of the present disclosure. The present disclosure is intended to encompass all alternatives, modifications, and changes within the scope of the present disclosure, including the scope of the claims.

Description of Symbols

[0139] 10, 110, 210, 310 Nitride semiconductor device 12 Semiconductor substrate 14 Buffer layer 16 Electron traveling layer 18 Electron supply layer 18A Portion 18B Portion 20 Two-dimensional electron gas 22 Gate layer 22A Upper surface 22B Lower surface 24 Gate electrode 26 Passivation layer 26A Source opening 26B Drain opening 28 First passivation layer 28A First source opening 28B First drain opening 28C Auxiliary opening 28CA End portion 28CB End portion 30 Second passivation layer 30A Second source opening 30B Second drain opening 32 Source electrode 32A Source main body portion 32B Source extending portion 32C Field plate electrode 32D Plate end portion 34 Drain electrode 34A Drain main body portion 34B Drain extending portion 34C Drain end portion 42 Ridge portion 42A Side surface 42B Side surface 44 First extending portion 46 Second extending portion 48 Gate auxiliary layer 50 Auxiliary layer 52 First portion 54 Second portion 56 Extension part 72 Gate wiring 73 Via wiring 74 Source wiring 75 Via wiring 76 Drain wiring 77 Via wiring α Al composition ratio β Al composition ratio

Claims

1. An electron transport layer composed of a nitride semiconductor, An electron supply layer provided on the electron transport layer and composed of a nitride semiconductor having a larger band gap than the electron transport layer, A gate layer provided on the electron supply layer and composed of a nitride semiconductor containing an acceptor-type impurity, A gate electrode provided on the gate layer, A first passivation layer that covers the electron supply layer, the gate layer, and the gate electrode, and includes a first source opening and a first drain opening disposed with the gate layer sandwiched therebetween in a first direction, and an auxiliary opening disposed between the gate layer and the first drain opening, A source electrode in contact with the electron supply layer exposed by the first source opening, A drain electrode in contact with the electron supply layer exposed by the first drain opening, An auxiliary layer in contact with the electron supply layer exposed by the auxiliary opening and composed of a nitride semiconductor having a larger band gap than the electron transport layer, A second passivation layer that covers the auxiliary layer, A nitride semiconductor device comprising the above.

2. The second passivation layer further covers the first passivation layer. The nitride semiconductor device according to Claim 1.

3. The second passivation layer, A second source opening communicating with the first source opening, A second drain opening communicating with the first drain opening, comprising, The nitride semiconductor device according to Claim 2.

4. The drain electrode, A drain main body portion disposed across both the first drain opening and the second drain opening, A drain extension portion provided on the peripheral edge of the second drain opening in the second passivation layer, comprising, The drain extension portion includes a drain end portion on the auxiliary opening side, The drain end portion is disposed between the auxiliary opening and the first drain opening in a plan view. The nitride semiconductor device according to Claim 3.

5. The drain end portion is disposed closer to the first drain opening. The nitride semiconductor device according to Claim 4.

6. Including a field plate electrode provided on the second passivation layer and at least partially extending in a region between the gate layer and the drain electrode in a plan view, The field plate electrode is electrically connected to the source electrode. The field plate electrode includes a plate end portion on the auxiliary opening side, The plate end portion is disposed between the gate layer and the auxiliary opening in a plan view, The nitride semiconductor device according to claim 2.

7. The plate end portion is between the gate layer and the auxiliary opening in a plan view and is disposed closer to the auxiliary opening, The nitride semiconductor device according to claim 6.

8. The plate end portion is between the gate layer and the auxiliary opening in a plan view and is disposed closer to the gate layer, The nitride semiconductor device according to claim 6.

9. The thickness of the auxiliary layer is equal to or less than the thickness of the electron supply layer, The nitride semiconductor device according to claim 1.

10. The auxiliary layer is disposed within a range between the gate layer and the first drain opening in the first direction, The nitride semiconductor device according to claim 1.

11. The auxiliary layer contains donor-type impurities, The nitride semiconductor device according to claim 1.

12. The electron supply layer is composed of Al with an Al composition ratio of α α Ga （１－α） N (0.1 < α < 1). The auxiliary layer is composed of Al with an Al composition ratio of β β Ga （１－β） N (0.1 < β < 1). The nitride semiconductor device according to claim 1.

13. The first passivation layer and the second passivation layer are made of a material containing SiN, The nitride semiconductor device according to claim 1.

14. The gate layer, A ridge portion provided at a position overlapping the gate electrode, A first extending portion thinner than the ridge portion, extending in the first direction from the ridge portion toward the first source opening, A second extending portion thinner than the ridge portion, extending in the first direction from the ridge portion toward the auxiliary opening, Including, The second extending portion and the auxiliary opening are spaced apart in the first direction, The nitride semiconductor device according to any one of claims 1 to 13.

15. The length of the auxiliary opening in the first direction is longer than the length of the second extending portion in the first direction, The nitride semiconductor device according to claim 14.

16. The length of the second extending portion is 100 nm or more and 600 nm or less, The nitride semiconductor device according to claim 15.

17. The thicknesses of the first extending portion and the second extending portion are greater than the thickness of the auxiliary layer, The nitride semiconductor device according to claim 14.

18. The thickness of the second extending portion is 5 nm or more and 25 nm or less, The thickness of the auxiliary layer is 5 nm or more and 10 nm or less, The nitride semiconductor device according to claim 17.

19. The thickness of the ridge portion is less than 60 nm. The nitride semiconductor device according to claim 14.

20. The average concentration of acceptor impurities in the ridge portion is higher than the average concentration of acceptor impurities contained in the first extending portion and the second extending portion. The nitride semiconductor device according to claim 14.

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