Electronic device

Abstract

To improve performance of an electronic device.SOLUTION: A substrate structure body (an electronic device) SUB1 includes: terminals TM1 formed in a wiring layer; an insulating layer 16 covering the wiring layer; and bump electrodes 30 electrically connected to the terminals TM1. The insulating layer 16 includes openings 16H1 that penetrate the insulating layer 16 in a thickness direction. The terminal has an exposed surface exposed from the insulating layer 16 at the opening 16H1. In a plan view in which the terminal is viewed from above, at least one of the insulating layer 16, the bump electrode 30, and the terminal has a shape that allows identification of presence or absence of the bump electrode 30.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to electronic devices. [Background technology]

[0002] There is an electronic device in which electronic components are mounted on a plurality of electrodes arranged on a substrate. For example, Japanese Patent Application Laid-Open No. 2021-15177 (Patent Document 1) describes an electronic device in which LED (Light Emitting Diode) elements are mounted on a plurality of electrodes arranged on a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-15177 Summary of the Invention [Problem to be solved by the invention]

[0004] In the case of electronic devices in which electronic components are mounted on terminals formed on a substrate, bump electrodes are formed on the terminals of the substrate to facilitate connection between the electrodes of the electronic components and the terminals on the substrate. From the viewpoint of improving the reliability of electronic devices, it is necessary that the bump electrodes are formed on the terminals as designed.

[0005] An object of the present invention is to provide a technique for improving the performance of electronic devices. [Means for solving the problem]

[0006] An electronic device according to one embodiment includes a substrate having a first surface and a second surface opposite to the first surface, a wiring layer disposed on the first surface of the substrate, a terminal formed on the wiring layer, a first insulating layer covering the wiring layer, and a bump electrode electrically connected to the terminal. The first insulating layer has a first opening penetrating the first insulating layer in the thickness direction. The terminal has an exposed surface exposed from the first insulating layer at the first opening. In a plan view of the terminal viewed from above, at least one of the first insulating layer, the bump electrode, and the terminal has a shape that allows the presence or absence of the bump electrode to be identified.

[0007] An electronic device according to another embodiment includes a substrate having a first surface and a second surface opposite to the first surface, a wiring layer disposed on the first surface of the substrate, a terminal formed on the wiring layer and made of a conductive material that is transparent to visible light, a first insulating layer covering the wiring layer, and a bump electrode electrically connected to the terminal. The first insulating layer has a first opening penetrating the first insulating layer in the thickness direction. The terminal has an exposed surface that is exposed from the first insulating layer at the first opening. A member located between the exposed surface of the terminal and the second surface of the substrate is made of a material that is transparent to visible light. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a configuration example of a micro LED display device that is an embodiment of an electronic device. [Figure 2] 2 is a circuit diagram showing an example of the configuration of a circuit around the pixel shown in FIG. 1. [Figure 3] 2 is an enlarged transparent plan view showing an example of a peripheral structure of LED elements arranged in each of a plurality of pixels of the display device shown in FIG. [Figure 4] FIG. 4 is an enlarged cross-sectional view taken along line AA in FIG. 3. [Figure 5] 4 is an enlarged plan view showing the upper surface of the substrate structure shown in FIG. 3 before the LED element is mounted thereon. [Figure 6]FIG. 6 is an enlarged plan view showing a modification of FIG. 5. [Figure 7] FIG. 7 is an enlarged plan view showing a study example for FIG. 6. [Figure 8] FIG. 6 is an enlarged cross-sectional view taken along line AA in FIG. 5. [Figure 9] FIG. 8 is an enlarged cross-sectional view taken along line BB in FIG. 7. [Figure 10] 1A to 1C are explanatory diagrams showing an example of a process flow of a method for manufacturing a display device, which is an embodiment of an electronic device. [Figure 11] 11 is an enlarged cross-sectional view showing a state in which a mask is formed on an exposed surface of the terminal in the mask formation step shown in FIG. 10. FIG. [Figure 12] 11 is an enlarged cross-sectional view showing a state in which a bump electrode is formed by plating in an opening formed in a mask in the plating step shown in FIG. 10. FIG. [Figure 13] 11 is an explanatory diagram showing an example of an inspection device that inspects the substrate structure in the bump electrode inspection step shown in FIG. 10. FIG. [Figure 14] FIG. 14 is an explanatory diagram showing an example of an image acquired by the inspection device shown in FIG. 13. [Figure 15] FIG. 6 is an enlarged plan view of a substrate structure which is a modified example of the substrate structure shown in FIG. [Figure 16] FIG. 16 is an enlarged cross-sectional view taken along line CC in FIG. [Figure 17] FIG. 17 is an enlarged cross-sectional view of a substrate structure which is a modified example of the substrate structure shown in FIG. [Figure 18] FIG. 17 is an enlarged cross-sectional view of a substrate structure which is another modified example of the substrate structure shown in FIG. [Figure 19] 6 is an enlarged plan view of a substrate structure which is another modified example of the substrate structure shown in FIG. 5. FIG. [Figure 20] FIG. 20 is an enlarged cross-sectional view taken along line DD in FIG. 19. [Figure 21] FIG. 14 is an explanatory diagram showing a modified example of FIG. 13. [Figure 22] 6 is an enlarged plan view of a substrate structure which is another modified example of the substrate structure shown in FIG. 5. FIG. [Figure 23] FIG. 23 is an enlarged cross-sectional view taken along line EE in FIG. 22. [Figure 24] FIG. 24 is an enlarged cross-sectional view showing a modification of FIG. 23. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those described above with reference to the previous drawings may be designated by the same or related reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In the following embodiments, a micro LED display device equipped with multiple micro LED elements and a bump electrode array device before the micro LED elements are mounted will be described as examples of electronic devices in which a bump electrode array for mounting multiple electronic components is arranged.

[0011] In this application, when describing the materials that make up a specific component, the expression "Component A is made of B" may be used. This means that "among the materials that make up component A, B is the material that is contained in the largest amount by weight." Therefore, component A may contain no impurities and may be made up purely of B, or it may contain materials other than B as impurities.

[0012] <Electronic equipment> First, a configuration example of a micro LED display device, which is one aspect of an electronic device according to the present embodiment, will be described. FIG. 1 is a plan view showing a configuration example of a display device according to one embodiment. In FIG. 1, the boundary between the display area DA and the peripheral area PFA, the control circuit 5, the drive circuit 6, and the plurality of pixels PIX are each indicated by a two-dot chain line. FIG. 2 is a circuit diagram showing a configuration example of a circuit around the pixel shown in FIG. 1. Note that the pixel circuit PC shown in FIG. 2 shows an example of an equivalent circuit corresponding to one pixel PIX shown in FIG. 1.

[0013] FIG. 1 shows the X direction and the Y direction. The X direction and the Y direction intersect with each other. In the example described below, the X direction is perpendicular to the Y direction. In the following description, the XY plane including the X direction and the Y direction will be described as a plane parallel to the display surface of the display device. In the following description, unless otherwise specified, the term "planar view" refers to the view of a plane parallel to the XY plane. Furthermore, as will be described later, the normal direction to the XY plane will be described as the "Z direction" or thickness direction. The X direction, the Y direction, and the Z direction intersect with each other, and more specifically, are directions perpendicular to each other.

[0014] In the explanation of this specification, it may be stated that "A" is "covered" by "B." "A is covered by B" means that at least a portion of A overlaps with B in a planar view seen from the above-mentioned XY plane. Furthermore, "A is covered by B" can also be rephrased as "at least a portion of A overlaps with B in the thickness direction (Z direction)" as described above.

[0015] 1, the display device DSP1 of this embodiment has a display area DA, a peripheral area PFA surrounding the periphery of the display area DA in a frame shape, and a plurality of pixels PIX arranged in a matrix within the display area DA. The display device DSP1 also has a substrate 10, a control circuit 5 formed on the substrate 10, and a drive circuit 6 formed on the substrate 10.

[0016] The control circuit 5 is a control circuit that controls the driving of the display function of the display device DSP1. For example, the control circuit 5 is a driver IC (Integrated Circuit) mounted on the substrate 10. In the example shown in FIG. 1, the control circuit 5 is arranged along one of the four short sides of the substrate 10. In the example of the present embodiment, the control circuit 5 includes a signal line drive circuit (video driver) that drives video signal lines VL (see FIG. 2) connected to multiple pixels PIX. However, the position and configuration of the control circuit 5 are not limited to the example shown in FIG. 1 and various modifications are possible. For example, in FIG. 1, a circuit board such as a flexible board may be connected to the position shown as the control circuit 5, and the driver IC may be mounted on the circuit board. In addition, for example, the signal line drive circuit that drives the video signal lines VL may be formed separately from the control circuit 5.

[0017] The drive circuit (scan driver) 6 is a circuit that drives the scan signal lines GLB, GLR, and GLS (see FIG. 2) of the multiple pixels PIX. The drive circuit 6 drives the multiple scan signal lines based on control signals from the control circuit 5. In the example shown in FIG. 1, the drive circuits 6 are arranged along each of two of the four long sides of the substrate 10. In the example shown in FIG. 1, the display area DA is arranged between the two drive circuits 6 in a plan view. However, the position and configuration of the drive circuit 6 are not limited to the example shown in FIG. 1, and various modifications are possible. For example, in FIG. 1, a circuit board such as a flexible board may be connected to the position shown as the control circuit 5, and the above-mentioned control circuit 5 and drive circuit 6 may be mounted on the circuit board.

[0018] Next, an example of the configuration of a pixel circuit PC that drives the pixel PIX shown in Fig. 1 will be described using Fig. 2. Note that Fig. 2 illustrates one pixel circuit PC that drives one pixel as a representative example. Each of the multiple pixels PIX shown in Fig. 1 has a circuit similar to the pixel circuit PC shown in Fig. 2. The pixel circuit PC is a voltage signal type circuit that controls the light emission state of an LED element (inorganic light emitting diode element, diode element) 20 in response to a video signal Vsg supplied from a control circuit 5 (see Fig. 1).

[0019] 2, the pixel PIX includes an LED element 20. The LED element 20 is the above-mentioned micro light-emitting diode. The LED element 20 has an anode electrode 20EA (see FIG. 3 described later) and a cathode electrode 20EC (see FIG. 3 described later).

[0020] The display device DSP1 has multiple types of wiring in the display area DA, including multiple scanning signal lines GLS, GLR, and GLB, multiple video signal lines VL, multiple power lines PL1, multiple power lines PL2, and multiple reset lines RSL.

[0021] The scanning signal lines GLS, GLR, and GLB extend in the X direction and are connected to the drive circuits 6. For example, as shown in FIG. 1 , among the pixels PIX arranged in the Y direction, the scanning signal lines GLS, GLR, and GLB for driving the even-numbered pixels PIX are connected to one drive circuit 6, and the scanning signal lines GLS, GLR, and GLB for driving the odd-numbered pixels PIX are connected to the other drive circuit 6. As another example, there is a case where any one of the scanning signal lines GLS, GLR, and GLB is connected to one drive circuit 6 and the remaining is connected to the other drive circuit 6, for example, all of the scanning signal lines GLS and GLR are connected to one drive circuit 6 and all of the scanning signal lines GLB are connected to the other drive circuit 6.

[0022] The video signal line VL, power supply lines PL1 and PL2, and reset line RSL extend in the Y direction. The video signal line VL is connected to a control circuit 5 (see FIG. 1). A video signal Vsg and an initialization signal are supplied to the video signal line VL from the control circuit 5. A high potential Pvdd is supplied to the power supply line PL1 from the control circuit 5. A low potential Pvss lower than the high potential Pvdd is supplied to the power supply line PL2 from the control circuit 5. A reset signal Vrs is supplied to the reset line RSL from the control circuit 5.

[0023] The control circuit 5 outputs a start pulse signal and a clock signal (not shown) to the drive circuit 6. The drive circuit 6 includes a plurality of shift register circuits, and sequentially transfers the start pulse signal to the next-stage shift register circuit in response to the clock signal, and sequentially supplies scanning signals to the scanning signal lines GLS, GLR, and GLB.

[0024] The pixel circuit PC controls the LED element 20 in response to a video signal Vsg supplied to a video signal line VL. To achieve this control, the pixel circuit PC in this embodiment includes a reset transistor (switching element) RST, a pixel selection transistor (switching element) SST, an output transistor (switching element) BCT, a drive transistor (switching element) DRT, a storage capacitor Cs, and an auxiliary capacitor Cad. The auxiliary capacitor Cad is an element provided to adjust the amount of light-emitting current, and may not be necessary in some cases.

[0025] The reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT are switching elements made up of thin film transistors (TFTs). The conductivity type of the thin film transistors is not particularly limited; for example, all of the transistors may be made up of N-channel TFTs, or at least one of them may be made up of a P-channel TFT.

[0026] In this embodiment, the reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT are formed in the same process and with the same layer structure, and have a bottom-gate structure using polycrystalline silicon for the semiconductor layer. As another example, the reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT may have a top-gate structure. Note that the semiconductor layer may be made of an oxide semiconductor, polycrystalline GaN semiconductor, or the like.

[0027] The reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT each have a source electrode, a drain electrode, and a gate electrode. The gate electrode of each transistor can be referred to as a control electrode. The source electrode and drain electrode of each transistor can also be referred to simply as electrodes.

[0028] The drive transistor DRT and the output transistor BCT are connected in series between the power supply line PL1 and the power supply line PL2 with the LED element 20. The high potential Pvdd supplied to the power supply line PL1 is set to, for example, 10 V, and the low potential Pvss supplied to the power supply line PL2 is set to, for example, 1.5 V.

[0029] The drain electrode of the output transistor BCT is connected to the power supply line PL1. The source electrode of the output transistor BCT is connected to the drain electrode of the drive transistor DRT. The gate electrode of the output transistor BCT is connected to the scanning signal line GLB. The output transistor BCT is turned on and off by a control signal Gsb provided to the scanning signal line GLB. Here, on represents a conductive state, and off represents a non-conductive state. The output transistor BCT controls the light-emitting time of the LED element 20 based on the control signal Gsb.

[0030] A source electrode of the drive transistor DRT is connected to one electrode (here, the anode electrode 20EA) of the LED element 20. The other electrode (here, the cathode electrode 20EC) of the LED element 20 is connected to the power supply line PL2. The drive transistor DRT outputs a drive current to the LED element 20 according to the video signal Vsg.

[0031] The source electrode of the pixel selection transistor SST is connected to the video signal line VL. The drain electrode of the pixel selection transistor SST is connected to the gate electrode of the drive transistor DRT. The gate electrode of the pixel selection transistor SST is connected to the scanning signal line GLS, which functions as a gate wiring for signal writing control. The pixel selection transistor SST is turned on and off by a control signal Gss supplied from the scanning signal line GLS, switching between connection and disconnection between the pixel circuit PC and the video signal line VL. In other words, when the pixel selection transistor SST is turned on, the video signal Vsg or initialization signal from the video signal line VL is supplied to the gate electrode of the drive transistor DRT.

[0032] The source electrode of the reset transistor RST is connected to the reset wiring RSL. The drain electrode of the reset transistor RST is connected to the source electrode of the drive transistor DRT and the anode of the LED element 20. The gate electrode of the reset transistor RST is connected to the scanning signal line GLR, which functions as a reset control gate wiring. The reset transistor RST is turned on and off by a control signal Grs supplied from the scanning signal line GLR. By switching the reset transistor RST on, the potentials of the source electrode of the drive transistor DRT and the anode of the LED element 20 can be reset by a reset signal Vrs on the reset wiring RSL. In other words, the reset wiring RSL is a wiring for resetting the voltage of the LED element 20.

[0033] The storage capacitor Cs is connected between the gate electrode and source electrode of the drive transistor DRT, and the auxiliary capacitor Cad is connected between the source electrode of the drive transistor DRT and the power supply line PL2.

[0034] The control signals Gss, Grs, and Gsb are sequentially supplied to the scanning signal lines GLS, GLR, and GLB of each line (a series of pixels PIX arranged in the X direction) by the drive circuit 6 based on the above-described start pulse signal and clock signal. Also, based on the signal supplied from the control circuit 5 shown in FIG. 2, the control circuit 5 sequentially supplies the video signal Vsg and the initialization signal to each video signal line VL. The charge held in the holding capacitor Cs is initialized with the supply of the initialization signal as the video signal Vsg is supplied.

[0035] In the configuration as described above, the pixel circuit PC is driven by the control signals Gss, Grs, and Gsb supplied to the scanning signal lines GLS, GLR, and GLB, and the LED element 20 emits light with a luminance corresponding to the video signal Vsg of the video signal line VL.

[0036] <Peripheral Structure of LED Element> Next, the peripheral structure of the LED element disposed in the pixel PIX shown in FIG. 1 will be described. FIG. 3 is a transmissive enlarged plan view showing an example of the peripheral structure of the LED element disposed in each of a plurality of pixels of the display device shown in FIG. 1. FIG. 4 is an enlarged cross-sectional view taken along the line A-A of FIG. 3.

[0037] In FIG. 3, the conductor pattern disposed in the wiring layer WL4 shown in FIG. 4 is indicated by a solid line. In FIG. 3, the outlines of the LED element 20 and the electrodes included in the LED element 20 are indicated by a two-dot chain line. Also, each of the pixels PIXA, PIXB, and PIXC shown in FIG. 3 has the same structure. For this reason, in FIG. 4, the structure of the pixel PIXA (see FIG. 3) is shown as a representative example, but the pixels PIXB and PIXC shown in FIG. 3 also have a similar cross-sectional structure.

[0038] In the following description, the terms "terminal TM1" and "terminal TM2" are used for explanation, but "terminal" means a conductor pattern including a terminal portion for electrically connecting an external device and can be read as "terminal pattern".

[0039] In addition, since the present embodiment describes a micro LED display device, in the following description, the unit area where the terminals TM1 and TM2 are arranged will be described using the term "pixel." When the technology described below is applied to an electronic device other than a display device, the term "pixel" can be read as "area."

[0040] Furthermore, the pixel circuit PC shown in Fig. 2 is a circuit corresponding to each of the pixels PIXA, PIXB, and PIXC shown in Fig. 3. Therefore, each of the pixels PIXA, PIXB, and PIXC shown in Fig. 3 includes the reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT described with reference to Fig. 2. Similarly, each of the pixels PIXA, PIXB, and PIXC shown in Fig. 3 includes the storage capacitor Cs and auxiliary capacitor Cad described with reference to Fig. 2.

[0041] 4, the display device DSP1 includes a substrate structure SUB1 and an LED element (inorganic light-emitting diode element) 20 mounted on the substrate structure SUB1. The substrate structure SUB1 of the display device DSP1 includes a plurality of insulating layers disposed between a plurality of wiring layers. The LED element 20 is mounted on a wiring layer WL4, which is disposed in the uppermost layer of the plurality of wiring layers.

[0042] The substrate structure SUB1 of the display device DSP1 has a substrate 10. The substrate 10 has a surface 10f and a surface 10b opposite to the surface 10f. A plurality of wiring layers and a plurality of insulating layers are stacked on the surface 10f of the substrate 10. The substrate 10 is, for example, a glass substrate made of glass. However, there are various variations in the material that constitutes the substrate 10; for example, a resin substrate made of resin may also be used.

[0043] The substrate structure SUB1 has transistors as switching elements. In Fig. 4, a drive transistor DRT is illustrated as an example of a switching element arranged on the substrate 10. However, the reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT described with reference to Fig. 2 are arranged on the substrate 10 (specifically, on the insulating layer 11). The reset transistor RST, pixel selection transistor SST, output transistor BCT, and drive transistor DRT shown in Fig. 2 each have a structure similar to that of the drive transistor DRT shown in Fig. 4, which will be described later.

[0044] As shown in Fig. 3, the display device DSP1 has a plurality of LED elements 20. Of the plurality of LED elements 20 that the display device has, Fig. 3 illustrates an LED element 20A, an LED element 20B arranged next to the LED element 20A, and an LED element 20C arranged next to the LED element 20B.

[0045] As shown in Fig. 4, the LED element 20 has a surface 20f and a surface 20b opposite to the surface 20f. The LED element 20 also has a plurality of electrodes (two in Fig. 3) arranged on the surface 20f. The plurality of electrodes included in the LED element 20 include an anode electrode 20EA and a cathode electrode 20EC. The anode electrode 20EA is electrically connected to a terminal TM1 via a bump electrode 31. The cathode electrode 20EC is electrically connected to a terminal TM2 via a bump electrode 32.

[0046] In this embodiment, an example of an LED element will be described in which an anode electrode 20EA and a cathode electrode 20EC are formed spaced apart on one surface 20f of the LED element 20. However, as a modification of this embodiment, one of the anode electrode 20EA and the cathode electrode 20EC may be formed on the surface 20f of the LED element 20, and the other of the anode electrode 20EA and the cathode electrode 20EC may be formed on the surface 20b opposite to the surface 20f. In this modification, one of the terminals TM1 and TM2 shown in FIG. 3 is formed on the substrate structure.

[0047] Of the conductor patterns included in the substrate structure SUB1, the terminals TM1 and TM2 are conductor patterns that include portions that function as "terminals" for electrically connecting the LED element 20 to the substrate structure SUB1. The terminals TM1 and TM2 are each disposed on the substrate 10.

[0048] The display device DSP1 displays an image by driving each of the plurality of LED elements 20 mounted on the substrate structure SUB1.

[0049] 4, the display device DSP1 includes a plurality of wiring layers, which are a wiring layer WL4, a wiring layer WL3, a wiring layer WL2, and a wiring layer WL1, stacked in this order from the wiring layer WL4 toward the substrate 10. The display device DSP1 also includes a plurality of insulating layers, which are insulating layers 11, 12, 13, 14, 15, and 16, stacked in this order from the top of the surface 10f of the substrate 10.

[0050] The insulating layer 11 is an underlying layer for the thin-film transistor, and is an inorganic insulating layer made of an inorganic material. The wiring layer WL1 is disposed on the insulating layer 11 and is covered with an insulating layer 12. The conductor pattern formed on the wiring layer WL1 includes the gate electrode EG shown in FIG. 4 and the scanning signal lines GLB, GLS, and GLR described with reference to FIG. 2. The insulating layer 12 is also an inorganic insulating layer made of an inorganic material. A portion of the insulating layer 12 disposed between the gate electrode EG of the transistor and the semiconductor layer 50 functions as a gate insulating film.

[0051] The drive transistor DRT including the gate electrode EG has a semiconductor layer 50, a gate electrode EG, a source electrode ES, and a drain electrode ED. In the example shown in FIG. 4, a thin-film transistor with a bottom-gate structure is shown as an example, but as mentioned above, a top-gate structure may also be used. The gate electrode EG is disposed on an insulating layer 11. The semiconductor layer 50 is disposed on an insulating layer 12. A portion of the semiconductor layer 50 corresponds to a source region, and a source electrode ES is connected to the source region. Another portion of the semiconductor layer 50 corresponds to a drain region, and a drain electrode ED is connected to the drain region. The region between the source region and the drain region functions as a channel region.

[0052] The wiring layer WL2 is disposed on the insulating layer 13 that covers the drive transistor DRT. The insulating layer 13 is an inorganic insulating layer made of an inorganic material. The conductor pattern formed on the wiring layer WL2 includes wiring connected to each of the multiple transistors. For example, as shown in FIG. 4, the wiring layer WL2 includes a wiring pattern MW1 connected to the source electrode ES of the drive transistor DRT. The conductor pattern formed on the wiring layer WL2 also includes the video signal line VL, power supply lines PL1 and PL2, and a reset line RSL shown in FIG. 2.

[0053] The wiring layer WL2 is electrically connected to the conductor pattern MP1 via a contact hole CH3 formed in the insulating layer 14, and includes a wiring pattern MW1 electrically connected to the electrode (source electrode ES) of the drive transistor DRT.

[0054] The insulating layer 14 covering the wiring layer WL2 and the insulating layer 15 stacked on the insulating layer 14 are both organic insulating films made of organic materials. The insulating layer 14 is an insulating layer disposed between the wiring layer WL2 and the wiring layer WL3. The insulating layer 15 is an insulating layer disposed between the wiring layer WL3 and the wiring layer WL4. As shown in FIG. 4, contact holes are used to electrically connect the wiring layer WL2 and the wiring layer WL3, and to electrically connect the wiring layer WL3 and the wiring layer WL4. Compared to inorganic insulating layers, organic insulating layers have superior filling characteristics for openings (e.g., contact holes). In other words, organic insulating layers can easily flatten their top surfaces even when there are openings in the underlying layer. For this reason, the insulating layers 14 and 15, in which numerous contact holes are formed, are each made of an organic material. An example of the organic material constituting the insulating layers 14 and 15 is acrylic resin.

[0055] 4 shows contact holes CH1, CH2, and CH3 among the many contact holes provided in the substrate structure SUB1. Contact hole CH1 is an opening that connects terminal TM1 to conductor pattern MP1 of wiring layer WL3. Contact hole CH2 is an opening that connects terminal TM2 to conductor pattern MP2 of wiring layer WL3. Contact hole CH3 is an opening that connects conductor pattern MP1 of wiring layer WL3 to wiring pattern MW1 of wiring layer WL2.

[0056] The wiring layer WL3 includes a conductor pattern MP1 electrically connected to the terminal TM1 through a contact hole CH1 formed in the insulating layer 15, and a conductor pattern MP2 made of the same metal as the conductor pattern MP1 and electrically connected to the terminal TM2 through a contact hole CH2 formed in the insulating layer 15.

[0057] The conductor pattern MP1 has a flat portion connected to the terminal TM1 at the bottom of the contact hole CH1 and a contact portion embedded in the contact hole CH3 and connected to the wiring layer WL2. As shown in Figure 3, the conductor pattern MP2 is a large-area pattern that extends across multiple pixels PIX.

[0058] 4 are made of, for example, the same metal material. In this embodiment, the conductor patterns MP1, MP2, terminals TM1, and TM2 are each a laminated film of a titanium layer made of titanium, an aluminum layer made of aluminum, and a titanium layer made of titanium.

[0059] The wiring layer WL4 is the uppermost wiring layer among the multiple wiring layers, and includes a terminal (conductor pattern) TM1 electrically connected to the anode electrode 20EA of the LED element 20A and a terminal (conductor pattern) TM2 electrically connected to the cathode electrode 20EC of the LED element 20A.

[0060] The wiring layer WL4 is covered with an insulating layer 16 made of an inorganic material. The insulating layer 16 is an inorganic insulating layer made of, for example, silicon nitride or silicon oxide. The terminals TM1 and TM2 are each covered with the insulating layer 16.

[0061] Specifically, the terminal TM1 has a terminal portion (which can also be called a flat portion) exposed from the insulating layer 16 at the opening 16H1 of the insulating layer 16, and a contact portion embedded in the contact hole CH1 and connected to the wiring layer WL3. The contact portion is covered by the insulating layer 16. Similarly, the terminal TM2 has a terminal portion exposed from the insulating layer 16 at the opening 16H2 of the insulating layer 16, and a contact portion embedded in the contact hole CH2 and connected to the wiring layer WL3. The contact portion is covered by the insulating layer 16. Each of the terminals TM1 and TM2 is an external terminal of the substrate structure SUB1.

[0062] An opening 16H1 is partially formed in the insulating layer 16. A terminal TM1 disposed on the wiring layer WL4 is connected to a bump electrode 31 through the opening 16H1 formed in the insulating layer 16. Similarly, a terminal TM2 disposed on the wiring layer WL4 is connected to a bump electrode 32 through an opening 16H2 formed in the insulating layer 16.

[0063] Bump electrode 31 is electrically connected to terminal TM1. Bump electrode 32 is electrically connected to terminal TM2. Furthermore, anode electrode 20EA of LED element 20A is electrically connected to terminal TM1 via bump electrode 31. Cathode electrode 20EC of LED element 20A is electrically connected to terminal TM2 via bump electrode 32. Each of bump electrode 31 and bump electrode 32 is made of, for example, tin.

[0064] <Details of terminals and bump electrodes> Next, the detailed structures of the terminals and bump electrodes shown in Figures 3 and 4 will be described. Figure 5 is an enlarged plan view showing the upper surface of the substrate structure shown in Figure 3 before the LED element is mounted. Figure 6 is an enlarged plan view showing a modified example of Figure 5. Figure 7 is an enlarged plan view showing an example of consideration of Figure 6. Figure 8 is an enlarged cross-sectional view taken along line AA in Figure 5. Figure 9 is an enlarged cross-sectional view taken along line BB in Figure 7.

[0065] 5 to 7, the plurality of bump electrodes 30 (the plurality of bump electrodes 31 and the plurality of bump electrodes 32) are formed on the exposed surface TMe of the terminal TM1 or the terminal TM2 by, for example, a plating method. The plurality of bump electrodes 30 are formed so as to be spaced apart from each other.

[0066] In plan view, the substrate structure SUB1 has a plurality of regions (pixels PIX), and each of the plurality of regions (pixels PIX) includes a terminal TM1 (and a terminal TM2) and a bump electrode 30.

[0067] 6 or 7, some of the bump electrodes 30 may not be formed due to defects during the manufacturing process, etc. In the example shown in FIGS. 6 and 7, among the multiple openings 16H1, no bump electrode 30 is formed in the opening 16H1 of pixel PIXB. In this case, even if the LED element 20B shown in FIG. 3 is mounted on pixel PIXB, the reliability of the electrical connection between the LED element 20 and terminal TM1 is low, and therefore pixel PIXB is likely not to operate as designed.

[0068] For this reason, as shown in Figures 6 and 7, when a pixel PIX is found in which a bump electrode 30 is not formed, it is necessary to take measures for that pixel PIX. Examples of such measures include the following methods. For example, when a pixel PIX in which a bump electrode 30 is not formed is found, the pixel can be repaired and a bump electrode 30 can be formed before mounting an LED element 20 (see Figure 3). In other words, a step of forming a bump electrode 30 is carried out for the pixel PIX in which a bump electrode 30 is not formed. In this case, although an additional manufacturing step is required, it is possible to ensure that each of the multiple pixels PIX operates normally, thereby improving the reliability of the display device.

[0069] Alternatively, when a pixel PIX is found that does not have a bump electrode 30 formed therein, the pixel is treated as a blank pixel without being equipped with an LED element 20 (see FIG. 3). In addition, in the case of a display device that is capable of performing color display using a set of multiple subpixels (for example, a set of red, green, and blue subpixels), when a subpixel that does not have a bump electrode 30 formed therein is found, the multiple subpixels including the found subpixel are treated as blank pixels without being equipped with an LED element 20.

[0070] When an LED element 20 (see FIG. 3) is mounted in a pixel PIX on which a bump electrode 30 is not formed, uncontrollable light emission may occur depending on the electrical connection state between the terminal and the LED element 20. When processing as a blank pixel, the displayed image may contain defective areas (e.g., black or white dots), but the impact on the quality of the displayed image is relatively small compared to when uncontrollable light emission occurs.

[0071] As described above, if a pixel PIX is generated in which some of the bump electrodes 30 are not formed due to a defect during the manufacturing process or the like, necessary measures can be taken by discovering this before mounting the LED element 20. However, according to the study of the present inventors, it has been found that depending on the shape of the bump electrode 30, it is difficult to determine whether or not the bump electrode 30 is present.

[0072] For example, when forming the bump electrode 30 by plating, as in the substrate structure SUB2 shown in Figures 7 and 9, if the insulating layer 16 itself is used as a mask, the bump electrode 30 is formed to cover the entire opening 16H2. On the other hand, as shown in Figure 9, if the contact state of the plating liquid is insufficient at the opening 16H1, the bump electrode 30 may not be formed on the opening 16H1, or the bump electrode 30 may not be thick enough. If the bump electrode 30 is extremely thin, it may be difficult to make it function as the bump electrode 30.

[0073] In the example shown in Figure 7, it is difficult to easily distinguish whether or not a bump electrode 30 is present in the multiple openings 16H1, 16H2 for the following reasons: The planar shapes of the exposed surface TMe and the bump electrode 30 are the same (square in the example shown in Figure 7). Furthermore, the terminal TM1 and the bump electrode 30 are each made of a metal material, so there is little difference in light reflectance. Furthermore, because the entire opening 16H1 or opening 16H2 is covered with the bump electrode 30, the outer edge of both the bump electrode 30 and the outer edges of the openings 16H1, 16H2 cannot be seen.

[0074] 7, each of the four corners of the bump electrode 30 is rounded, so strictly speaking, the planar shape of the bump electrode 30 and the planar shape of the exposed surface TMe are slightly different. However, because the difference is so slight, it is difficult to distinguish the presence or absence of the bump electrode 30 from the planar shape. In particular, in the step of determining the presence or absence of the bump electrode 30, when an image including a plurality of pixels PIX is acquired and the presence or absence of the bump electrode 30 is determined for the plurality of pixels PIX all at once, a clear difference is required in relation to the resolution of the acquired image in order to determine the presence or absence of the bump electrode 30.

[0075] For example, the planar shape of the exposed surface TMe shown in Fig. 7 is a square with a side length of about 10 µm. Therefore, if the resolution of the acquired image is, for example, about 1 to 2 [µm / pix], all that can be obtained is information that "multiple metal materials separated from each other are present in the insulating layer 16, and each of the multiple metal materials is square," making it difficult to identify the presence or absence of the bump electrode 30. Note that the above-mentioned unit of resolution is expressed as the length of one side of the subject included in one pixel when the shape of one pixel in the acquired image is square, in [µm / pix].

[0076] In the process of determining the presence or absence of bump electrodes 30, it is conceivable to increase the resolution of the captured image by reducing the range of each image capture. However, if the range of image capture is reduced, it will not be possible to determine the presence or absence of bump electrodes 30 for multiple pixels PIX at once. In this case, the process of determining the presence or absence of bump electrodes 30 will require an enormous amount of time, which is not practical. For this reason, in the case of the study example shown in FIG. 7, it can be said that it is practically difficult to identify the presence or absence of bump electrodes 30.

[0077] In the case of the substrate structure SUB1 of this embodiment shown in Figures 5, 6, and 8, the insulating layer 16 has an opening 16H1 (and opening 16H2) penetrating the insulating layer 16 in the thickness direction. The terminal TM1 has an exposed surface TMe exposed from the insulating layer 16 at the opening 16H1. In a plan view of the terminal TM1 (and terminal TM2) seen from above, the bump electrode 30 has a shape that makes it possible to distinguish the presence or absence of the bump electrode 30. The top surface SUBt of the substrate structure SUB1 shown in Figure 8 includes the top surface of the insulating layer 16 and the exposed surfaces TMe of the terminals TM1 and TM2.

[0078] Specifically, in a plan view, the area of the bump electrode 30 is smaller than the area of the exposed surface TMe, and the bump electrode 30 is formed on the exposed surface TMe in a state where the exposed surface TMe is visible.

[0079] 5 and 6, the bump electrode 30 has a rectangular shape, and the exposed surface TMe has a square shape.

[0080] As shown in Figures 5 and 6, when the planar shape of the bump electrode 30 and the planar shape of the exposed surface TMe are clearly different, the boundary between the bump electrode 30 and the terminal TM1 (or terminal TM2) can be identified even if the bump electrode 30 and the terminals TM1 and TM2 are each made of a metal material.

[0081] For example, the planar shape of the exposed surface TMe shown in Fig. 5 is a square with a side length of about 10 to 15 µm. On the other hand, the planar shape of the bump electrode 30 is a rectangle with a short side length of about 2 to 5 µm. In this case, if the resolution of the acquired image is, for example, about 1 to 2 µm / pix, it is possible to sufficiently identify the presence or absence of the bump electrode 30.

[0082] Furthermore, when acquiring an image including a plurality of pixels PIX (for example, several hundred to several tens of thousands of pixels PIX), it is possible to set the resolution of the acquired image to approximately 1 to 2 μm / pix. Therefore, in this embodiment, it is possible to collectively determine the presence or absence of bump electrodes 30 for a plurality of pixels PIX.

[0083] <Electronic Device Manufacturing Method> Next, a method for manufacturing a display device shown in FIG. 4 will be described as a method for manufacturing an electronic device according to this embodiment. FIG. 10 is an explanatory diagram showing an example of a process flow for a method for manufacturing a display device, which is one embodiment of an electronic device. As shown in FIG. 10, the method for manufacturing an electronic device according to this embodiment includes a substrate structure preparation step, a bump electrode formation step, and an electronic component mounting step. Note that the electronic component mounting step can be omitted if the substrate structure before the electronic components are mounted is shipped as a semi-finished product.

[0084] In the substrate structure preparation step, a substrate structure SUB1 shown in Fig. 8 is prepared. As shown in Fig. 10, the substrate structure preparation step includes a terminal formation step, an insulating layer formation step, an opening formation step, a bump electrode formation step, and a bump electrode inspection step. Note that, as indicated by the dotted line in Fig. 10, if a pixel in which the bump electrode is not correctly formed is found in the bump electrode inspection step, the substrate structure preparation step may include a bump electrode correction step.

[0085] Although not shown in FIG. 10, the substrate structure preparation step includes the following steps that are performed before the terminal formation step. That is, in the substrate structure preparation step, first, a substrate 10 made of glass or resin is prepared (substrate preparation step). The substrate structure preparation step includes a wiring layer lamination step in which the components shown in FIG. 2 or 4 are laminated on the substrate 10. In the wiring layer lamination step, an insulating layer 11, a wiring layer WL1, an insulating layer 12, a semiconductor element (for example, the drive transistor DRT shown in FIG. 4), an insulating layer 13, a wiring layer WL2, an insulating layer 14, a wiring layer WL3, and an insulating layer 15 are laminated in this order on the surface 10f of the substrate 10. A contact hole CH1 and a contact hole CH2 are formed in the insulating layer 15.

[0086] <Terminal formation process> In the terminal formation step shown in Fig. 10, terminals TM1 and TM2 are formed on the insulating layer 15 shown in Fig. 8. Prior to this step, contact holes CH1 and CH2 are formed in the insulating layer 15 in advance.

[0087] As described above, each of the terminals TM1 and TM2 is a laminated film of, for example, a titanium layer made of titanium, an aluminum layer made of aluminum, and a titanium layer made of titanium. Therefore, in the terminal formation process, the titanium layer, the aluminum layer, and the titanium layer are formed in this order. The titanium layer and the aluminum layer can be formed, for example, by sputtering. After the laminated film is formed, an etching process is performed using a mask (not shown), thereby patterning the terminals TM1 and TM2 as shown in FIGS. 5 and 8.

[0088] <Insulating layer formation process> Next, in the insulating layer forming step shown in FIG. 10, the insulating layer 16 is formed so as to entirely cover the terminals TM1 and TM2 shown in FIG.

[0089] As described above, insulating layer 16 is an inorganic insulating film such as silicon nitride. Therefore, the planarization characteristics of insulating layer 16 with respect to irregularities are lower than those of insulating layer 15, which is an organic insulating film. As a result, insulating layer 16 has an upper surface with irregularities that follow the irregularities of wiring layer WL4 formed on insulating layer 15.

[0090] <Opening formation process> Next, in the opening formation step shown in FIG. 10, openings 16H1 and 16H2 are formed in the insulating layer 16 as shown in FIG.

[0091] In the opening forming step, an opening 16H1 is formed to expose a portion of the terminal TM1 from the insulating layer 16. In the opening forming step, an opening 16H2 is formed to expose a portion of the terminal TM2 from the insulating layer 16.

[0092] The openings 16H1 and 16H2 are formed, for example, by the following method. First, a resist mask (not shown) is formed, and then openings are formed in the resist mask using photolithography at positions that overlap with the regions where the openings 16H1 and 16H2 are to be formed. Next, the insulating layer 16 that is exposed through the openings in the resist mask is removed by etching. This forms the openings 16H1 and 16H2. After that, the resist mask is removed, thereby obtaining the insulating layer 16 shown in FIG. 8.

[0093] <Bump electrode formation process> Next, in the bump electrode forming step shown in Fig. 10, bump electrodes 30 are formed on each of the terminals TM1 and TM2 shown in Fig. 8. In the example shown in Fig. 10, the bump electrode forming step includes a mask forming step and a plating step. Fig. 11 is an enlarged cross-sectional view showing a state in which a mask has been formed on the exposed surfaces of the terminals in the mask forming step shown in Fig. 10. Fig. 12 is an enlarged cross-sectional view showing a state in which bump electrodes are formed by plating in openings formed in the mask in the plating step shown in Fig. 10.

[0094] As shown in FIG. 11, in the mask formation step of the bump electrode formation process, a mask 30M is formed on the substrate 10 (see FIG. 8). In the present embodiment, the mask 30M is formed on the insulating layer 16 of the substrate structure SUB1. Furthermore, in the mask formation step, openings are formed at positions overlapping with the terminal TM1 and the terminal TM2, as shown in FIG. 11. A portion of the exposed surface TMe of the terminal TM1 and a portion of the exposed surface TMe of the terminal TM2 are exposed from the mask 30M at the openings in the mask 30M, respectively. The method of forming the openings in the mask 30M is the same as the method of forming the openings 16H1 and 16H2 described above.

[0095] 12, in the plating step of the bump electrode formation process, the bump electrode 30 is formed by plating. Examples of plating methods include electrolytic plating and electroless plating. When electrolytic plating or electroless plating is used, a plating film (a metal film formed by plating) is selectively formed on the exposed surface of the metal.

[0096] In this embodiment, the upper surface SUBt of the substrate structure SUB1 is covered with a mask 30M except for a portion of the exposed surface TMe of the terminal TM1 and a portion of the exposed surface TMe of the terminal TM2, as shown in Fig. 11. Therefore, in this step, the bump electrodes 30 are selectively formed in the openings of the mask 30M, as shown in Fig. 12.

[0097] Although not shown in Fig. 10, after the plating step, a mask removal step is performed in which the mask 30M shown in Fig. 12 is removed by, for example, etching. In this step, the mask 30M is entirely removed. As a result, as shown in Fig. 8, a bump electrode 30 is formed on each of the exposed surfaces TMe of the terminals TM1 and TM2, and a substrate structure SUB1 is obtained in which each of the exposed surfaces TMe of the terminals TM1 and TM2 is partially exposed from the bump electrode 30 and the insulating layer 16.

[0098] <Bump electrode inspection process> Next, in the bump electrode inspection process shown in Fig. 10, it is inspected whether or not bump electrodes 30 are formed on each of the plurality of terminals TM1 and the plurality of terminals TM2 shown in Fig. 5 and Fig. 6. Fig. 13 is an explanatory diagram showing an example of an inspection device that inspects the substrate structure in the bump electrode inspection process shown in Fig. 10. Fig. 14 is an explanatory diagram showing an example of an image acquired by the inspection device shown in Fig. 13.

[0099] 14 shows, as an example, a state in which terminals of 27 pixels are displayed in one image, but the number of pixels displayed in one image is not limited to 27. The number of pixels displayed in one image varies depending on the resolution specifications of camera 62 (see FIG. 13), but for example, terminals of several hundred to several tens of thousands of pixels may be displayed in one image. As already mentioned, the work efficiency of the bump electrode inspection process improves as the number of pixels displayed in one image increases within the range in which the presence or absence of bump electrodes can be identified.

[0100] In the bump electrode inspection process, the inspection is performed using, for example, an inspection device 60 shown in Fig. 13. The inspection device has a stage 61 capable of supporting the substrate structure SUB1, a camera 62 capable of photographing the upper surface SUBt of the substrate structure SUB1, and a display unit (monitor) 63 capable of displaying an image acquired by the camera 62. In the case of the inspection device 60, a display image 65 shown as an example in Fig. 14 is displayed on the display unit 63.

[0101] 13, the inspection device 60 has a judgment circuit 64 for judging whether or not a bump electrode is formed on each of the plurality of terminals, using image data acquired by the camera 62. In this case, the pass / fail judgment of the plurality of terminals is performed by the judgment circuit 64 of the inspection device 60, so the display unit 63 may not display the display image 65 shown in FIG. 14, and may simply display the pass / fail judgment result. However, it is preferable that the display image 65 be displayed on the display unit 63 so that the operator can easily check the pass / fail judgment result.

[0102] In the bump electrode inspection process, first, the substrate structure SUB1 is fixed on the stage 61. Next, the position of the camera 62 is moved along the XY plane and stopped on the upper surface SUBt of the substrate structure SUB1. Next, the camera 62 photographs a portion of the upper surface SUBt to acquire image data. The acquired image data is transmitted to an image processing circuit (not shown) and converted into image data. The image data is transmitted to the display unit 63, and the acquired display image 65 (see FIG. 14) is displayed on the display unit 63. The image data is also transmitted to a judgment circuit 64, which judges whether the display image 65 is good or bad.

[0103] The method for determining whether a product is good or bad is not particularly limited, but for example, the product can be determined by comparing it with image data of a good product previously acquired and determining whether any differences exceeding an allowable margin are detected. In the case of the display image 65 shown in Fig. 14, bump electrodes 30 are formed on each of the multiple terminals TM1 and TM2, but no bump electrode 30 is formed on the terminal shown as terminal TM3. Therefore, the display image 65 must be determined to be bad.

[0104] The resolution of the display image 65 is, for example, 2 μm / pix or less. As described above, the planar shape of the exposed surface TMe shown in FIGS. 5 and 6 is a square with a side length of about 10 to 15 μm. On the other hand, the planar shape of the bump electrode 30 is a rectangle with a short side length of about 2 to 5 μm. Therefore, in the display image 65 shown in FIG. 14, it can be identified that the bump electrode 30 is not formed on the terminal TM3. That is, in this embodiment, the presence or absence of the bump electrode 30 can be determined collectively for multiple pixels PIX (see FIG. 5).

[0105] <Bump electrode repair process> Next, in the bump electrode repair process shown in FIG. 10, a bump electrode 30 is newly formed on a terminal on which no bump electrode 30 has been formed, such as the terminal TM3 shown in the display image 65 shown in FIG.

[0106] In this step, for example, the bump electrodes 30 are formed by a processing step similar to the bump electrode formation step already described. However, the bump electrodes 30 (see FIG. 12) already formed on the substrate structure SUB1 (see FIG. 11) are covered with a mask 30M (see FIG. 11), and openings are selectively formed in the mask 30M at positions overlapping with the terminals TM3 shown in FIG.

[0107] This step is omitted when a pixel including a terminal TM3 on which no bump electrode 30 is formed is treated as a blank pixel as described above. In this case, the coordinates of the terminal TM3 are stored, and no electronic component is mounted on the terminal TM3 in the electronic component mounting step described later.

[0108] There are cases where the substrate structure SUB1 (see FIG. 4) before electronic components are mounted is shipped as a semi-finished product. In this case, the electronic component mounting process shown in FIG. 10 is omitted, and the substrate structure SUB1 shown in FIG. 6 undergoes the necessary inspection and packaging before being prepared for shipment. That is, the substrate structure SUB1 is obtained as an electronic device after being brought into the state shown in FIG. 5 through the bump electrode inspection process (or bump electrode correction process) shown in FIG. 10.

[0109] Next, in the electronic component mounting process shown in FIG. 10, after the bump electrode formation process, bump electrodes 31 and 32 are electrically connected to electronic components (LED elements 20 in the example of FIG. 4) as shown in FIG. 4. In this process, bump electrodes 31 and 32 are softened by, for example, laser irradiation. As a result, bump electrode 31 is connected to the anode electrode 20EA of LED element 20, and bump electrode 32 is connected to the cathode electrode 20EC of the LED element. Note that, prior to this process, a solder film may be formed in advance on each of the anode electrode 20EA and cathode electrode 20EC of LED element 20 shown in FIG. 4. In this case, bump electrodes 31 and 32 made of solder can be easily integrated with the solder film formed on the electrodes.

[0110] <Modification of the method for identifying the presence or absence of bump electrodes> Next, modified examples of the method for identifying the presence or absence of bump electrodes will be described. In the modified examples described below, modified examples of the substrate structure SUB1 described using Figures 5, 6, and 8 will be described as examples of electronic devices. In each of the modified substrate structures described below, when the LED element 20 shown in Figure 4 is mounted on the bump electrodes 30, a display device, which is an electronic device, is obtained.

[0111] 5, 6, and 7, a method for identifying the presence or absence of a bump electrode based on the difference between the planar shape of the bump electrode 30 and the planar shape of the exposed surface TMe of the terminal has been described. In FIGS. 5 and 6, an example in which the planar shape of the exposed surface TMe is square and the planar shape of the bump electrode 30 is rectangular has been described as an example of the planar shape. Although not shown, a modified example may be where the planar shape of the exposed surface TMe is rectangular and the planar shape of the bump electrode 30 is square. There are also various modified examples of the planar shapes of the bump electrode 30 and the exposed surface TMe of the terminal.

[0112] However, if the planar shapes of the bump electrode 30 and the exposed surface TMe of the terminal become complicated, it may become difficult to stably form the opening in the bump electrode 30 or the insulating layer 16 in relation to processing accuracy. In this regard, an embodiment in which one of the planar shapes of the bump electrode 30 and the exposed surface TMe is square and the other is rectangular is preferable in terms of ease of processing.

[0113] <Modification 1 of exposed terminal surface> Next, as a modified example of the method for identifying the presence or absence of bump electrodes, a method for identifying the presence or absence of bump electrodes by devising the shape of the exposed surface of the terminal will be described. Fig. 15 is an enlarged plan view of a substrate structure which is a modified example of Fig. 5. Fig. 16 is an enlarged cross-sectional view taken along line CC in Fig. 15.

[0114] 15 and 16 differs from the substrate structure SUB1 shown in FIGS. 5 and 8 in the following respects. That is, the terminal TM1 (and the terminal TM2) of the substrate structure SUB3 has a recess TMH1 formed in the exposed surface TMe. The bump electrode 30 is formed so as to cover the entire recess TMH1.

[0115] In this modified example, the recess TMH1 formed on the exposed surface TMe can be used as a mark for identifying the presence or absence of the bump electrode 30. If the bump electrode 30 is formed normally, the recess TMH1 will not be recognized in the bump electrode inspection process shown in Fig. 10. Therefore, if the recess TMH1 shown in Fig. 15 is recognized in the display image 65 (see Fig. 14) acquired in the bump electrode inspection process, it can be determined that the bump electrode 30 is not formed on the terminal.

[0116] As explained with reference to Figures 13 and 14, from the viewpoint of simultaneously inspecting multiple pixels, it is preferable that the size of the recess TMH1 shown in Figure 15 be within a square area with a side length of about 2 to 4 µm. For example, in the example shown in Figure 15, the planar shape of the exposed surface TMe is a square with a side length of about 10 µm. In contrast, the diameter of a recess having a circular planar shape is preferably about 2 to 4 µm.

[0117] Incidentally, there are various modified methods for forming the recess TMH1, but in the present embodiment, as shown in FIG. 16, a recess 15H1 is formed in the insulating layer 15, which is the underlying layer of the terminal TM1 (and the terminal TM2), and the recess TMH1 is formed following the recess 15H1.

[0118] 16 can be expressed as follows. That is, the wiring layer WL4 on which the terminal TM1 (and the terminal TM2) are formed is formed on an insulating layer 15 which is formed on the substrate 10 (see FIG. 8). The insulating layer 15 has a recess 15H1 formed at a position overlapping with the opening 16H1 (and the opening 16H2). The recess TMH1 of the terminal TM1 (and the recess TMH1 of the terminal TM2) is formed on the recess 15H1 of the insulating layer 15.

[0119] As described above, the terminals TM1 and TM2 are formed by, for example, a sputtering method. In this case, if the recess 15H1 is formed on the upper surface of the base layer (i.e., the upper surface 15t of the insulating layer 15), the recess TMH1 that follows the recess 15H1 is formed in the metal film deposited by the sputtering method. Therefore, in this modified example, a step of forming the recess 15H1 on the upper surface 15t of the insulating layer 15 is required before forming the wiring layer WL4, but no additional step is required in the step of forming the wiring layer WL4 (in other words, the step of forming the terminal TM1).

[0120] In addition, the substrate structure SUB3 shown in Figures 15 and 16 has an advantage over the substrate structure SUB4 shown in Figure 17 and the substrate structure SUB5 shown in Figure 18, which will be described next, in that the film thickness of the terminal TM1 (and terminal TM2) can be made constant.

[0121] In this modification, the recess TMH1 is used as an identification mark for identifying the presence or absence of the bump electrode 30, so there are no particular limitations on the shape of the bump electrode 30. For this reason, as shown in Fig. 16, the bump electrode 32 is formed so as to cover the entire opening 16H2.

[0122] <Modification 2 of exposed surface of terminal> Next, a description will be given of modifications of the recessed portion TMH1 described with reference to Fig. 15 and Fig. 16. Fig. 17 is an enlarged sectional view of a substrate structure which is a modification of Fig. 16. Fig. 18 is an enlarged sectional view of a substrate structure which is another modification of Fig. 16.

[0123] 15 and 16, an embodiment has been described in which a recess TMH1 is formed in the wiring layer WL4 by forming a recess 15H1 in the insulating layer 15, which is the base layer. Each of the substrate structure SUB4 shown in Fig. 17 and the substrate structure SUB5 shown in Fig. 18 differs from the substrate structure SUB3 shown in Fig. 16 in that the recess 15H1 (see Fig. 16) is not formed in the insulating layer 15, but the recess TMH2 or the recess TMH3 is formed directly in the terminal TM1 (and the terminal TM2).

[0124] In the case of the substrate structure SUB4 shown in FIG. 17, the terminal TM1 (and terminal TM2) has a surface (back surface) TMb located on the opposite side to the exposed surface TMe. The surface of the terminal TM1 (and terminal TM2) is flat compared to the exposed surface. In the case of the substrate structure SUB4, the recess TMH2 formed in a part of the exposed surface TMe has a bottom surface TMHb located between the top surface TMt and surface TMb of the terminal TM1 (or terminal TM2). In other words, in the case of the substrate structure SUB4, the recess TMH2 formed in a part of the exposed surface TMe does not penetrate the terminal TM1 (or terminal TM2) in the thickness direction.

[0125] On the other hand, in the case of the substrate structure SUB5 shown in FIG. 18, the recessed portion TMH3 is a through-hole that penetrates the terminal TM1 (or the terminal TM2) in the thickness direction.

[0126] The recesses TMH2 shown in Fig. 17 and the recesses TMH3 shown in Fig. 18 are formed so that the terminals TM1 and TM2 are directly subjected to an etching process. Therefore, the shapes of the opening ends of the recesses TMH2 and TMH3 tend to be more acute than the shape of the opening end of the recess TMH1 shown in Fig. 16. Therefore, in terms of ease of recognition in the bump electrode inspection process shown in Fig. 10, the recesses TMH2 shown in Fig. 17 or the recesses TMH3 shown in Fig. 18 are superior to the recesses TMH1 shown in Fig. 16.

[0127] Incidentally, the recessed portion TMH3 shown in Fig. 18 can be formed at the same time as an etching process for patterning the metal film on the wiring layer WL4, for example, to form the terminals TM1 and TM2 shown by dotted lines in Fig. 15. This is preferable because it does not require the addition of a new process for forming the recessed portion TMH3.

[0128] On the other hand, in the case of the recess TMH2 shown in FIG. 17, in order to form the bottom surface TMHb, it is necessary to stop etching midway for the recess TMH2 or to reduce the etching rate for the recess TMH2.

[0129] In each of the substrate structure SUB4 shown in Fig. 17 and the substrate structure SUB5 shown in Fig. 18, the bump electrode 32 is formed so as to cover the entire opening 16H2, similarly to the substrate structure SUB3 shown in Fig. 16.

[0130] <Modification of the insulating layer around the exposed surface of the terminal> Next, as a modified example of the method for identifying the presence or absence of bump electrodes, a method for identifying the presence or absence of bump electrodes by devising the shape of the insulating layer arranged around the exposed surface of the terminal will be described. Fig. 19 is an enlarged plan view of a substrate structure which is another modified example of Fig. 5. Fig. 20 is an enlarged cross-sectional view taken along line DD in Fig. 19.

[0131] In the case of the substrate structure SUB6 shown in FIGS. 19 and 20, marks are formed in the insulating layer 16 around the openings 16H1 and 16H2, making it possible to identify whether or not there are bump electrodes.

[0132] Specifically, the insulating layer 16 of the substrate structure SUB6 has a recess 16H3 formed outside the opening 16H1 (and outside the opening 16H2). The bump electrode 30 is formed so as to cover a part of the recess 16H3.

[0133] In the case of the substrate structure SUB6, the insulating layer 16 has a recess 16H4 located on the opposite side of the opening 16H1 (or opening 16H2) from the recess 16H3. The bump electrode 30 is formed so as to cover a portion of the recess 16H3 and the recess 16H4.

[0134] 19 and 20, for example, even in an embodiment in which the recess 16H3 is not formed or an embodiment in which the recess 16H4 is not formed, it is possible to distinguish the presence or absence of the bump electrode 30. However, from the viewpoint of ensuring reliable distinction, it is particularly preferable that the recess 16H3 and the recess 16H4 are arranged on opposite sides of the exposed surface TMe, as shown in FIGS.

[0135] In the case of this modified example, if the bump electrode 30 is normally formed, the recesses 16H3 and 16H4 shown in Fig. 19 are recognized as being partially missing in the bump electrode inspection process shown in Fig. 10. Alternatively, as a modified example, if the recesses 16H3 and 16H4 shown in Fig. 19 are entirely covered by the bump electrode 30, the recesses 16H3 and 16H4 shown in Fig. 19 are not recognized in the bump electrode inspection process. Therefore, if the entire recess 16H3 or the entire recess 16H4 shown in Fig. 19 is recognized in the display image 65 (see Fig. 14) acquired in the bump electrode inspection process, it can be determined that the bump electrode 30 is not correctly formed on the terminal.

[0136] Furthermore, as in the previously described embodiments, in this modified example, from the viewpoint of simultaneously inspecting multiple pixels, it is preferable that the resolution be identifiable with, for example, about 1 to 2 μm / pix. Therefore, it is preferable that the size of each of the recesses 16H3 and 16H4 shown in FIG. 19 be within a square area with a side length of about 2 μm to 4 μm. For example, in the example shown in FIG. 15, the planar shape of the exposed surface TMe is a square with a side length of about 10 μm. In contrast, it is preferable that the diameter of a recess having a circular planar shape be about 2 μm to 4 μm.

[0137] 20, each of the recesses 16H3 and 16H4 does not penetrate the insulating layer 16 in the thickness direction. Therefore, the terminal TM1 (and the terminal TM2) is not exposed from the insulating layer 16 at the position overlapping with the recess 16H3 or the recess 16H4.

[0138] If the terminal TM1 is exposed from the insulating layer 16 at a position overlapping with the recess 16H3 or the recess 16H4, the bump electrode 30 is also formed on the exposed portion, increasing the area of the bump electrode 30. If the arrangement pitch of the multiple terminals TM1 and TM2 is small and the surface area of the bump electrode 30 increases, there is a concern that adjacent bump electrodes 30 may short-circuit. Therefore, as shown in FIG. 20 , it is preferable that the terminal TM1 (and terminal TM2) is not exposed from the insulating layer 16 at a position overlapping with the recess 16H3 or the recess 16H4.

[0139] 19, there is an embodiment in which the entire recesses 16H3 and 16H4 are covered with the bump electrode 30. However, similarly to the above, from the viewpoint of preventing the plane area of the bump electrode 30 from becoming extremely large, it is preferable that each of the recesses 16H3 and 16H4 is partially covered with the bump electrode 30 and the other partially exposed from the bump electrode 30, as shown in FIG.

[0140] <Another modified example of the method for identifying the presence or absence of a bump electrode> Next, as another modified example of the method for identifying the presence or absence of bump electrodes, a method for identifying the presence or absence of bump electrodes while irradiating light from the back surface of the substrate structure will be described. Fig. 21 is an explanatory diagram showing a modified example of Fig. 13. Fig. 22 is an enlarged plan view of a substrate structure which is another modified example of Fig. 5. Fig. 23 is an enlarged cross-sectional view taken along line E-E in Fig. 22.

[0141] In this modified example, in the bump electrode process shown in Figure 10, as shown schematically in Figure 23, light 66L1 is irradiated from the surface 10b of the substrate 10, and the presence or absence of light 66L2 leaking from the upper surface SUBt of the substrate structure SUB7 is recognized to determine the presence or absence of the bump electrode 30.

[0142] The bump electrode inspection process of this modified example is performed by, for example, an inspection apparatus 60A shown in Fig. 21. The inspection apparatus 60A is similar to the inspection apparatus 60 described with reference to Fig. 13, except that a light source 66 is disposed between the surface 10b of the substrate structure SUB7 and the stage 61. The light source 66 is an optical device capable of irradiating light toward the surface 10b of the substrate structure SUB7.

[0143] The position of the light source 66 is not limited to between the surface 10b and the stage 61, as long as it is possible to irradiate light toward the surface 10b of the substrate structure SUB7.

[0144] The structure of substrate structure SUB7 is similar to the structure of substrate structure SUB5 described with reference to Fig. 18. That is, as shown in Fig. 23, substrate structure SUB7 has a substrate 10 having a surface 10f and a surface 10b opposite to surface 10f, a wiring layer WL4 disposed on surface 10f of the substrate 10, a terminal TM2 (and terminal TM1) formed on the wiring layer WL4, an insulating layer 16 covering terminal TM2, and a bump electrode 30 electrically connected to terminal TM2.

[0145] The insulating layer 16 has an opening 16H2 (and an opening 16H1) penetrating the insulating layer 16 in the thickness direction (Z direction). The terminal TM2 has an exposed surface TMe exposed from the insulating layer 16 at the opening 16H2. The terminal TM1 has an exposed surface TMe exposed from the insulating layer 16 at the opening 16H1. The members between the exposed surface TMe of the terminal TM2 and the surface 10b of the substrate are arranged in such a way that when light 66L1 is irradiated from the surface 10b of the substrate 10 toward the exposed surface TMe, the light can be irradiated onto the bump electrode from the opening.

[0146] In the case of the substrate structure SUB7, the terminal TM1 (and terminal TM2) is formed on the exposed surface TMe and has a recess TMH3 penetrating the terminal TM1 (or terminal TM2) in the thickness direction. The bump electrode 30 is formed so as to cover the entire recess TMH3. Each of the insulating layers 11, 12, 13, 14, and 15 shown in FIG. 23 is made of a light-transmitting material. On the other hand, the insulating layer 16 is made of a light-shielding material. Note that if the insulating layer 16 is made of a light-transmitting material, it is necessary to form a light-shielding film (not shown) between the insulating layer 16 and the insulating layer 15 or on the insulating layer 16.

[0147] In the case of the substrate structure SUB7, if the bump electrodes 30 are correctly formed, the light 66L2 is not detected. On the other hand, if the bump electrodes 30 are not formed, as in the case of the terminal TM1 in Fig. 23, the light 66L2 leaks onto the upper surface SUBt through the recess TMH3. Therefore, in the bump electrode inspection process, the presence or absence of the bump electrodes 30 can be determined by detecting the leaking light.

[0148] 23, the material constituting the elements such as the drive transistor DRT may not be light-transmitting. Even if the steel members of the elements formed on the substrate 10 are made of a light-shielding material, their area is not large. Therefore, if each of the insulating layers 11, 12, 13, 14, and 15, which are large-area members, is light-transmitting, light 66L1 incident from the surface 10b will travel around the light-shielding elements and reach the top surface SUBt.

[0149] Fig. 24 is an enlarged cross-sectional view showing a modification of Fig. 23. Substrate structure SUB8 shown in Fig. 24 differs from substrate structure SUB7 shown in Fig. 23 in that the recess TMH3 shown in Fig. 23 is not formed and that each of the terminals TM1 and TM2 is optically transparent.

[0150] The terminals TM1 and TM2 of the substrate structure SUB8 are each made of an electrode material known as a "transparent electrode." A representative example of a transparent electrode is ITO (Indium Tin Oxide). However, the light-transmitting material is not limited to ITO, and various modifications can be applied.

[0151] In the case of the substrate structure SUB8, as shown in FIG. 24, the light 66L2 passes through the terminal TM1, and therefore the openings 16H1 and 16H2 themselves function as marks for identifying the presence or absence of the bump electrodes 30.

[0152] In the case of the substrate structure SUB7 shown in Fig. 23 and the substrate structure SUB8 shown in Fig. 24, the presence or absence of bump electrodes 30 is determined by detecting light 66L2, and therefore the detection sensitivity is higher than in the embodiments described with reference to Figs. 5 to 20. Therefore, the range of the area that can be determined in one go can be made larger than in the case where determination is made using the display image 65 shown in Fig. 14, for example. In this case, the efficiency of the bump electrode inspection process can be improved.

[0153] In the case of the substrate structure SUB7 shown in FIG. 23 and the substrate structure SUB8 shown in FIG. 24, similarly to the substrate structures shown in FIGS. 6 to 18, the bump electrode 30 is formed so as to cover the entire opening 16H2.

[0154] In the case of the substrate structure SUB7 shown in Figure 23 and the substrate structure SUB8 shown in Figure 24, similar to the substrate structure SUB1 shown in Figures 5 and 6, in a planar view, the substrate structure SUB7 (and the substrate structure SUB8) has a plurality of pixels (regions) PIX (see Figure 5), and each of the plurality of pixels (regions) PIX has a terminal TM2 and a bump electrode 30.

[0155] Although the embodiment and representative modifications have been described above, the above-described technology can be applied to various modifications other than the modifications exemplified. For example, the above-described modifications may be combined with each other.

[0156] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the present invention. For example, to the above-described embodiments, a person skilled in the art may appropriately add, delete, or modify components, or add, omit, or change conditions of steps, and these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention. [Industrial Applicability]

[0157] The present invention can be used in electronic devices such as display devices. [Explanation of symbols]

[0158] 5 Control circuit 6 Drive circuit 10 Substrate 10b,10f,20b,20f,TMb surface 11,12,13,14,15,16 Insulating layer 15H1, 16H3, 16H4, TMH1, TMH2, TMH3 recess 15t,SUBt top surface 16H1,16H2 opening 20, 20A, 20B, 20C LED elements (light-emitting elements, electronic components) 20EA anode electrode 20EC cathode electrode 30, 31, 32 Bump electrodes 30M Mask 50 Semiconductor layer 60,60A Inspection Equipment 61 Stages 62 Camera 63 Display unit (monitor) 64 Judgment circuit 65 display images 66 Light source 66L1,66L2 light BCT output transistor (switching element) Cad auxiliary capacity CH1, CH2, CH3 contact holes Cs retention capacity DA display area DRT drive transistor (switching element) DSP1 display device ED drain electrode EG gate electrode ES source electrode GLB,GLR,GLS scanning signal lines Grs, Gsb, Gss control signals MW1 wiring pattern MP1, MP2 conductor patterns PC pixel circuit PFA surrounding area PIX, PIXA, PIXB, PIXC pixels PL1,PL2 power line Pvdd high potential Pvss low potential RSL Reset wiring RST Reset transistor (switching element) SST Pixel selection transistor (switching element) SUB1,SUB2,SUB3,SUB4,SUB5,SUB6,SUB7,SUB8 Substrate structure (electronic device) TM1, TM2, TM3 terminals (conductor patterns) TMe exposed surface TMHb bottom VL video signal line Vrs Reset signal Vsg video signal WL1, WL2, WL3, WL4 wiring layers

Claims

1. a substrate having a first surface and a second surface opposite the first surface; a wiring layer disposed on the first surface of the substrate; a terminal formed on the wiring layer; a first insulating layer covering the wiring layer; a bump electrode electrically connected to the terminal; and the first insulating layer has a first opening penetrating the first insulating layer in a thickness direction; the terminal has an exposed surface exposed from the first insulating layer in the first opening; In a plan view of the terminal seen from above, at least one of the first insulating layer, the bump electrode, and the terminal has a shape that allows the presence or absence of the bump electrode to be identified.

2. In claim 1, In the electronic device, the area of the bump electrode is smaller than the area of the exposed surface in the plan view, and the bump electrode is formed on the exposed surface in a state where the exposed surface is visible.

3. In claim 2, In the plan view, the planar shape of the bump electrode and the planar shape of the exposed surface are different from each other.

4. In claim 1, the terminal includes a first recess formed in the exposed surface; The bump electrode is formed so as to cover the entire first recess.

5. In claim 4, the wiring layer is formed on a second insulating layer formed on the substrate, the second insulating layer includes a second recess formed at a position overlapping the first opening, The first recess of the terminal is formed on the second recess of the second insulating layer.

6. In claim 4, the terminal has a third surface opposite the exposed surface; The third surface of the terminal is flat compared to the exposed surface.

7. In claim 4, The electronic device, wherein the first recess is a through hole that penetrates the terminal in a thickness direction.

8. In any one of claims 5 to 7, The bump electrode is formed so as to cover the entire first opening.

9. In claim 1, the first insulating layer has a third recess formed outside the first opening, The bump electrode is formed so as to cover the third recess.

10. In claim 9, the first insulating layer has a fourth recess located on the opposite side of the first opening from the third recess; The bump electrode is formed so as to cover the third recess and the fourth recess.

11. In claim 1, In a plan view, the electronic device has a plurality of regions, Each of the plurality of regions includes the terminal and the bump electrode.

12. a substrate having a first surface and a second surface opposite the first surface; a wiring layer disposed on the first surface of the substrate; a terminal formed on the wiring layer; a first insulating layer covering the wiring layer; a bump electrode electrically connected to the terminal; and the first insulating layer has a first opening penetrating the first insulating layer in a thickness direction; the terminal has an exposed surface exposed from the first insulating layer in the first opening; An electronic device, wherein a member between the exposed surface of the terminal and the second surface of the substrate is positioned in a state where, when light is irradiated from the second surface of the substrate toward the exposed surface, the light can be irradiated onto the bump electrode from the first opening.

13. In claim 12, The terminal includes a first recess formed on the exposed surface and penetrating the terminal in a thickness direction; The bump electrode is formed so as to cover the entire first recess.

14. In claim 12, The electronic device, wherein the terminals are made of a light-transmitting conductive material.

15. In claim 12, The bump electrode is formed so as to cover the entire first opening.

16. In claim 12, In a plan view, the electronic device has a plurality of regions, Each of the plurality of regions includes the terminal and the bump electrode.

Images