Power semiconductor element

Abstract

To provide a power semiconductor element with improved electric characteristics.SOLUTION: A power semiconductor element 100d includes: a substrate containing SiC of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a source region of the first conductivity type on the well region; a gate electrode 130C penetrating the source region and the well region and disposed in a gate trench extending in a Y direction that is parallel to an upper surface of the substrate; a gate pad 170 electrically connected to the gate electrode; a gate bus line 180 electrically connecting the gate pad and the gate electrode and including a region extending in an X direction that intersects with the Y direction; and a drain electrode on a lower surface of the substrate. At least one of the gate electrode and the gate bus line has a cross-sectional area that changes gradually in an extending direction.SELECTED DRAWING: Figure 6a

Description

[Technical Field]

[0001] The present invention relates to power semiconductor devices. [Background technology]

[0002] Power semiconductor devices are semiconductor devices that operate in high voltage and high current environments and are used in fields that require high power switching, such as power conversion, power converters, and inverters. Power semiconductor devices are basically required to withstand high voltages, and recently, high-speed switching operations have also become necessary. As a result, research is being conducted into power semiconductor devices using SiC, which has superior withstand voltage characteristics compared to silicon (Si). Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical problems that the technical idea of ​​the present invention aims to solve is to provide a power semiconductor device with improved electrical characteristics. [Means for solving the problem]

[0004] a gate electrode disposed in a gate trench extending in a first direction parallel to an upper surface of the substrate, the gate pad electrically connected to the gate electrode; a gate bus (BUS) line connecting the gate pad and the gate electrode, the gate bus (BUS) line including a first region extending from the gate pad in the first direction and a second region extending from the first region in a second direction intersecting the first direction and connected to an end of the gate electrode; and a drain electrode on a lower surface of the substrate, the second region having a first cross-sectional area at a first portion spaced a first distance from the gate pad, and a second cross-sectional area greater than the first cross-sectional area at a second portion spaced a second distance from the gate pad that is longer than the first distance.

[0005] a gate electrode disposed in a gate trench extending in a first direction parallel to an upper surface of the substrate, the gate electrode penetrating the source region and the well region; a gate pad electrically connected to the gate electrode; a gate bus line connecting the gate pad and the gate electrode and including a region extending in a second direction intersecting the first direction; and a drain electrode on a lower surface of the substrate, wherein at least one of the gate electrode and the gate bus line has a cross-sectional area that gradually changes in one direction that is the extension direction.

[0006] a gate electrode extending on the drift layer in a first direction parallel to an upper surface of the substrate; a gate pad electrically connected to the gate electrode; and a gate bus line connecting the gate pad and the gate electrode and including a region extending in a second direction intersecting the first direction, wherein at least one of the gate electrode and the gate bus line has a first cross-sectional area in a first portion having a first electrical path from the gate pad, and a second cross-sectional area larger than the first cross-sectional area in a second portion having a second electrical path longer than the first electrical path. [Effects of the Invention]

[0007] By optimizing the shape of the gate bus line and / or gate electrode in consideration of the electrical path from the gate pad, it is possible to provide a power semiconductor device with improved electrical characteristics.

[0008] The various beneficial advantages and effects of the present invention are not limited to the above, but will be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic plan view of a power semiconductor device according to an exemplary embodiment; [Figure 2a] 1 is a schematic cross-sectional view of a power semiconductor device according to an exemplary embodiment; [Figure 2b] 1 is a schematic cross-sectional view of a power semiconductor device according to an exemplary embodiment; [Figure 2c] 1 is a schematic cross-sectional view of a power semiconductor device according to an exemplary embodiment; [Figure 3] 1 is a cross-sectional view illustrating a power semiconductor device according to an exemplary embodiment. [Figure 4] 1 is a plan view illustrating a power semiconductor device according to an exemplary embodiment. [Figure 5] 1 is a plan view illustrating a power semiconductor device according to an exemplary embodiment. [Figure 6a] 1 is a plan view illustrating a power semiconductor device according to an exemplary embodiment. [Figure 6b] 1 is a plan view illustrating a power semiconductor device according to an exemplary embodiment. [Figure 7a] 1 is a schematic plan view of a power semiconductor device according to an exemplary embodiment; [Figure 7b] 1 is a schematic cross-sectional view of a power semiconductor device according to an exemplary embodiment; [Figure 8] 1 is a cross-sectional view illustrating a power semiconductor device according to an exemplary embodiment. [Figure 9a] 1A to 1C are diagrams illustrating a method for manufacturing a power semiconductor device according to an exemplary embodiment in order of steps; [Figure 9b] 1A to 1C are diagrams illustrating a method for manufacturing a power semiconductor device according to an exemplary embodiment in order of steps; [Figure 9c] 1A to 1C are diagrams illustrating a method for manufacturing a power semiconductor device according to an exemplary embodiment in order of steps; [Figure 9d] 1A to 1C are diagrams illustrating a method for manufacturing a power semiconductor device according to an exemplary embodiment in order of steps; [Figure 9e] 1A to 1C are diagrams illustrating a method for manufacturing a power semiconductor device according to an exemplary embodiment in order of steps; [Figure 9f] 1A to 1C are diagrams illustrating a method for manufacturing a power semiconductor device according to an exemplary embodiment in order of steps; DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. In the following, terms such as "top," "upper portion," "upper surface," "bottom," "lower portion," "lower surface," and "side surface" can be understood to be referred to with reference to the drawings unless otherwise specified.

[0011] FIG. 1 is a schematic plan view of a power semiconductor device according to an exemplary embodiment.

[0012] 2a to 2c are schematic cross-sectional views of a power semiconductor device according to an exemplary embodiment, where Fig. 2a shows a cross-section along section line I-I' in Fig. 1, Fig. 2b shows a cross-section along section line II-II' in Fig. 1, and Fig. 2c shows a cross-section along section line III-III' in Fig. 1.

[0013] 1 to 2c, a power semiconductor device 100 may include a substrate 101, a drift layer 102 on the substrate 101, a well region 105 on the drift layer 102, a source region 107 and a well contact region 109 on the well region 105, a gate insulating layer 120 disposed in a gate trench GT penetrating the source region 107 and the well region 105, a gate electrode 130 disposed on the gate insulating layer 120 in the gate trench GT, a gate pad 170 electrically connected to the gate electrode 130, a gate bus (BUS) line 180 connecting the gate electrode 130 and the gate pad 170 and having a cross-sectional area that changes in the extension direction, a first dielectric layer 140 covering the gate electrode 130, a source electrode 150 on the first dielectric layer 140, a second dielectric layer 145 covering the gate bus line 180, a bus metal layer 190 on the gate bus line 180, and a drain electrode 160 on a lower surface of the substrate 101.

[0014] The substrate 101 may have a top surface extending in the X and Y directions. The substrate 101 may include a semiconductor material, such as SiC. However, in some embodiments, the substrate 101 may include a Group IV semiconductor material, such as Si or Ge, or a compound semiconductor material, such as SiGe, GaAs, InAs, or InP.

[0015] The substrate 101 may be a bulk wafer or an epitaxial layer. The substrate 101 may include first conductivity type impurities, thereby having the first conductivity type. In some embodiments, the first conductivity type may be, for example, N-type, and the first conductivity type impurities may be N-type impurities such as nitrogen (N) and / or phosphorus (P). In some embodiments, the first conductivity type may be, for example, P-type, and the first conductivity type impurities may be P-type impurities such as aluminum (Al).

[0016] The drift layer 102 may be disposed on the substrate 101. The drift layer 102 may include a semiconductor material, such as SiC. The drift layer 102 may be an epitaxial layer grown on the substrate 101. The drift layer 102 may include first conductivity type impurities, thereby having the first conductivity type. The concentration of the first conductivity type impurities in the drift layer 102 may be lower than the concentration of the first conductivity type impurities in the substrate 101. In an embodiment, the first conductivity type impurities in the substrate 101 and the first conductivity type impurities in the drift layer 102 may include the same or different elements.

[0017] The well regions 105 may be disposed at a predetermined depth from the upper surface of the drift layer 102 and may be spaced apart from each other in a horizontal direction, e.g., the X direction, by the gate trenches GT. The well regions 105 may include a semiconductor material, e.g., SiC. The well regions 105 may be regions having a second conductivity type and may include second conductivity type impurities. The second conductivity type may be, e.g., P type, and the second conductivity type impurities may be P type impurities such as aluminum (Al). In some embodiments, the well regions 105 may include multiple regions having different doping concentrations.

[0018] The source region 107 may be disposed at a predetermined depth from the top surface of the well region 105. The source region 107 may include a semiconductor material, for example, SiC. The source region 107 may be a region having the first conductivity type and may include the above-described first conductivity type impurities. The concentration of the first conductivity type impurities in the source region 107 may be higher than the concentration of the first conductivity type impurities in the drift layer 102, but is not limited thereto.

[0019] The well contact region 109 may be disposed on the well region 105 on one side of at least a portion of the source region 107. The well contact region 109 may be disposed between the well region 105 and the source electrode 150, allowing a voltage from the source electrode 150 to be applied to the well region 105. The well contact region 109 may include a semiconductor material, for example, SiC. The well contact region 109 may be a region having the second conductivity type and may include the above-described second conductivity type impurities. The concentration of the second conductivity type impurities in the well contact region 109 may be higher than the concentration of the second conductivity type impurities in the well region 105.

[0020] The gate trenches GT may extend from the upper surface of the source region 107, penetrating the source region 107 and the well region 105, into the drift layer 102. The gate trenches GT may be spaced apart from each other in the X direction. At least a portion of the gate trenches GT may also extend beneath the gate bus line 180. At least a portion of the gate trenches GT may also extend beneath the gate pad 170. The gate trenches GT may completely penetrate the well region 105, and a lower end of the gate trench GT may be located within the drift layer 102. However, the length by which the gate trenches GT extend into the drift layer 102 may vary depending on the embodiment. A gate insulating layer 120 and a gate electrode 130 may be disposed within the gate trench GT.

[0021] The gate insulating layer 120 may be disposed in each gate trench GT. The gate insulating layer 120 may extend along the bottom surface and sidewall of the gate trench GT and cover the side surface and bottom surface of the gate electrode 130. The gate insulating layer 120 may be disposed between the source region 107, the well region 105, and the drift layer 102 and the gate electrode 130.

[0022] The gate insulating layer 120 may include an oxide, a nitride, or a high-k material. The high-k material may refer to a dielectric material having a higher dielectric constant than silicon dioxide (SiO2). Examples of the high-k material include aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ) and praseodymium oxide (Pr2O3).

[0023] The gate insulating layer 120 may have a non-uniform thickness. As shown in FIG. 2a, the gate insulating layer 120 may have a first thickness T1 on the bottom surface of the gate trench GT and a second thickness T2 on the sidewalls of the gate trench GT that is thinner than the first thickness T1. However, in some embodiments, the gate insulating layer 120 may have a constant thickness.

[0024] The gate electrodes 130 may be disposed in the gate trenches GT, extend in the Y direction, and be spaced apart from each other in the X direction. The gate electrodes 130 may be disposed on the gate insulating layer 120 in the gate trenches GT. The gate electrodes 130 may overlap the drift layer 102, the well region 105, and the source region 107 in a horizontal direction, for example, in the X direction. The lower surfaces of the gate electrodes 130 may be located in the drift layer 102. In some embodiments, the lower surfaces of the gate electrodes 130 may be located in the well region 105. The lower surfaces of the gate electrodes 130 may be located at the same level as or lower than the lower surface of the well region 105, and the upper surfaces of the gate electrodes 130 may be located at the same level as or lower than the upper surfaces of the source regions 107. However, in some embodiments, the upper surfaces of the gate electrodes 130 may be located at a higher level than the upper surfaces of the source regions 107. Some of the gate electrodes 130 may be disposed to overlap the gate pad 170 and the gate bus line 180 in the Z direction.

[0025] The gate electrode 130 may include a conductive material, such as a semiconductor material such as doped polycrystalline silicon, or a metal material. The metal material may be at least one of titanium nitride (TiN), titanium (Ti), titanium carbide (TiC), tantalum nitride (TaN), tungsten nitride (WN), aluminum (Al), tungsten (W), and molybdenum (Mo). Depending on the embodiment, the gate electrode 130 may be formed of two or more layers.

[0026] The gate pad 170 and the gate bus line 180 are electrically connected to the gate electrode 130 and may be a gate wiring structure for connecting the gate electrode 130 to the outside.

[0027] The gate pad 170 may be disposed on one side of the gate electrode 130 and electrically connected to the gate electrode 130 via a gate bus line 180. The gate pad 170 may be electrically connected to another pad metal layer disposed thereon and may receive an electrical signal through the pad metal layer. In some embodiments, a portion of the gate electrode 130 may extend below the gate pad 170 and be vertically connected to the gate pad 170. Depending on the embodiment, the gate pad 170 may have a rectangular, circular, elliptical, or other shape in a plan view.

[0028] A plurality of gate bus lines 180, for example, two, may be arranged and may be connected to one end and the other end of the gate electrode 130, respectively. The gate bus lines 180 may be arranged symmetrically in the Y direction with respect to the gate pad 170.

[0029] The gate bus line 180 may include a first region 182 and a second region 184. The first region 182 may be connected to the gate pad 170 and may extend in the Y direction from the gate pad 170. The second region 184 may be a region extending from an end of the first region 182 in a direction intersecting the extension direction of the gate electrode 130, for example, in the vertical X direction. The gate bus line 180 may be disposed on at least one gate electrode 130, as shown in FIG. 2b. The gate bus line 180 may penetrate the first dielectric layer 140 in at least one region to be vertically connected to the underlying gate electrode 130.

[0030] The cross-sectional area of ​​each of the first region 182 and the second region 184 may increase as the electrical path from the gate pad 170 becomes longer. Unless otherwise specified, "cross-sectional area" herein refers to the area of ​​a cross section perpendicular to the extension direction. The cross-sectional area of ​​each of the first region 182 and the second region 184 may increase, for example, the width, as it becomes farther from the gate pad 170. The width of each of the first region 182 and the second region 184 may gradually increase in the extension direction. In this embodiment, the width of the first region 182 and the second region 184 may increase continuously or linearly. However, in some embodiments, the width of the first region 182 and the second region 184 may increase discontinuously or nonlinearly. The first region 182 and the second region 184 may have sloping sides in a plan view such that the width increases as it becomes farther from the gate pad 170.

[0031] The cross-sectional area of ​​the first region 182 may increase as it moves away from the gate pad 170 in the Y direction. The cross-sectional area of ​​the second region 184 may increase as it moves away from the first region 182. The first region 182 may have a first width W1 at a first portion separated by a first distance from the gate pad 170 and a second width W2 larger than the first width W1 at a second portion separated by a second distance longer than the first distance. The first region 182 may have a substantially constant thickness, such that the first portion may have a first cross-sectional area AR1 and the second portion may have a second cross-sectional area AR2 larger than the first cross-sectional area AR1. The second region 184 may have a third width W3 at a third portion separated by a third distance from the gate pad 170 and a fourth width W4 larger than the third width W3 at a fourth portion separated by a fourth distance longer than the third distance. The second region 184 may have a substantially constant thickness, such that the third region has a third cross-sectional area and the fourth region has a fourth cross-sectional area that is larger than the third cross-sectional area. The relative sizes of the first width W1 and the second width W2 and the third width W3 and the fourth width W4 may vary in various embodiments.

[0032] Due to the shapes of the first region 182 and the second region 184, the gate bus line 180 may have a relatively high resistance in regions adjacent to the gate pad 170, e.g., the first and third portions, and a relatively low resistance in regions away from the gate pad 170, e.g., the second and fourth portions. This improves the uniformity of the voltage drop in the power semiconductor device 100 by preventing a relatively large voltage drop from occurring in regions far from the gate pad 170. As a result, the uniformity of the voltage applied to the gate electrode 130 via the gate pad 170 in the power semiconductor device 100 is improved.

[0033] The gate pad 170 and the gate bus line 180 may include a conductive material, such as a metal material. The gate pad 170 and the gate bus line 180 may include the same or a different material as the gate electrode 130. The gate pad 170 and the gate bus line 180 may include at least one of titanium nitride (TiN), titanium (Ti), titanium carbide (TiC), tantalum nitride (TaN), tungsten nitride (WN), aluminum (Al), tungsten (W), and molybdenum (Mo).

[0034] The first dielectric layer 140 may cover the gate electrode 130 and may be disposed to expose a portion of each of the source region 107 and the well contact region 109. The first dielectric layer 140 may expose a portion of the gate electrode 130 under the gate bus line 180. The second dielectric layer 145 may cover the gate bus line 180 and expose a portion of the gate bus line 180. Depending on the embodiment, the second dielectric layer 145 may also extend over the source electrode 150.

[0035] The first dielectric layer 140 and the second dielectric layer 145 may each comprise an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, at least one of the first dielectric layer 140 and the second dielectric layer 145 may comprise a high-k material.

[0036] The source electrode 150 may be disposed on the first dielectric layer 140 and electrically connected to the source region 107 and the well contact region 109. The source electrode 150 may include at least one of a metal material, such as nickel (Ni), aluminum (Al), titanium (Ti), silver (Ag), vanadium (V), tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), and ruthenium (Ru). The source electrode 150 may include a metal-semiconductor compound layer disposed at an interface in contact with the source region 107 and the well contact region 109. The metal-semiconductor compound layer may include a metal element and a semiconductor element, such as at least one of TiSi, CoSi, MoSi, LaSi, NiSi, TaSi, or WSi.

[0037] The bus metal layer 190 may be disposed on the gate bus line 180 and the second dielectric layer 145, and may be connected to the gate bus line 180 exposed from the second dielectric layer 145. The bus metal layer 190 may be disposed in the same or similar shape as the gate bus line 180 in a plan view. However, in some embodiments, the bus metal layer 190 may have a certain width in a plan view. Another pad metal layer may also be disposed on the gate pad 170, and the pad metal layer may be, for example, a region to be wire-bonded within a package or module. However, in some embodiments, the bus metal layer 190 and the pad metal layer may be omitted.

[0038] The bus metal layer 190 may include a metallic material, such as at least one of copper (Cu), aluminum (Al), silver (Ag), nickel (Ni), titanium (Ti), vanadium (V), tungsten (W), cobalt (Co), molybdenum (Mo), and ruthenium (Ru).

[0039] The drain electrode 160 may be disposed on the lower surface of the substrate 101 and electrically connected to the substrate 101. The drain electrode 160 may include at least one of a metal material, such as nickel (Ni), aluminum (Al), titanium (Ti), silver (Ag), vanadium (V), and tungsten (W). In some embodiments, the drain electrode 160, like the source electrode 150, may include a metal-semiconductor compound layer.

[0040] Although the power semiconductor device 100 has been described as being in the form of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the shape of the gate bus line 180 of the embodiment may also be applied to a super junction MOSFET, a double trench MOSFET, an IGBT (Insulated Gate Bipolar Transistor), etc. For example, when the power semiconductor device is an IGBT, the substrate 101 may have the second conductivity type.

[0041] In the following description of the embodiment, the same description as that given above with reference to FIGS. 1 to 2c will be omitted.

[0042] 3 is a cross-sectional view of a power semiconductor device according to an exemplary embodiment, showing the area corresponding to FIG.

[0043] 3, in the power semiconductor device 100a, the gate bus line 180 may be disposed in a connection trench CT. The connection trench CT may extend from the upper surface of the source region 107 through the source region 107 and the well region 105 into the drift layer 102. The connection trench CT may be formed together with the gate trench GT of FIG. 2a and may be located at the same level as the gate trench GT.

[0044] A gate insulating layer 120 is disposed in the connection trench CT, and a gate bus line 180 may be disposed on the gate insulating layer 120. However, the gate insulating layer 120 in the connection trench CT is merely a layer formed together with the gate insulating layer 120 in the gate trench GT, and may not substantially function as a gate insulating layer of the transistor. Therefore, the gate insulating layer 120 in the connection trench CT may also be referred to as a trench insulating layer. The upper surface of the gate bus line 180 may be located at substantially the same level as the upper surface of the gate electrode 130, the upper surface of the source region 107, and the top surface of the drift layer 102. Similarly, a gate pad 170 (see FIG. 1 ) may also be disposed in the connection trench CT.

[0045] The first dielectric layer 140 may be disposed on the gate bus line 180. The bus metal layer 190 may be connected to the gate bus line 180 on and through the first dielectric layer 140.

[0046] FIG. 4 is a plan view illustrating a power semiconductor device according to an exemplary embodiment.

[0047] 4, in the power semiconductor device 100b, the shape of a first region 182 of a gate bus line 180b differs from the embodiment of FIGS. 1 to 2c. The first region 182 may have a substantially constant first width W1' in the Y direction. The second region 184 may have a shape whose width increases with increasing distance from the gate pad 170 in the X direction. The second region 184 may have a third width W3' at a portion spaced a relatively short distance from the gate pad 170 and a fourth width W4' larger than the third width W3' at a portion spaced a relatively long distance from the gate pad 170.

[0048] FIG. 5 is a plan view illustrating a power semiconductor device according to an exemplary embodiment.

[0049] 5, in a power semiconductor device 100c, the shapes of a gate electrode 130c and a gate bus line 180c are different from those in the embodiment of Figures 1 to 2c. In this embodiment, the gate bus line 180c may include a first region 182 and a second region 184 extending from the gate pad 170 with a constant width.

[0050] The gate electrode 130c may have a cross-sectional area that increases and then decreases as it extends from the first end to the second end along the Y direction. The cross-sectional area and width of the gate electrode 130c may gradually increase and then decrease in the Y direction. In this embodiment, the thickness of the gate electrode 130c may be substantially constant in the Y direction. The cross-sectional area and width of the gate electrode 130c may vary continuously or linearly in the Y direction. However, in some embodiments, the cross-sectional area and width of the gate electrode 130c may vary discontinuously or nonlinearly.

[0051] The gate electrode 130c may have a fifth width W5 at a portion adjacent to an end connected to the second region 184 of the gate bus line 180c, and a sixth width W6 at the center in the Y direction that is larger than the fifth width W5. The relative sizes of the fifth width W5 and the sixth width W6 may vary depending on the embodiment. A portion of the gate electrode 130c may have a relatively small width at an end connected to the second region 184 of the gate bus line 180c and an end connected to the gate pad 170, and a relatively large width at the center in the Y direction. The gate electrode 130c may have a symmetrical shape with respect to the center in the Y direction.

[0052] Due to this shape, the gate electrode 130c can have high resistance in a region where the electrical path from the gate pad 170 is relatively short, for example, the end connected to the second region 184, and low resistance in a region where the electrical path from the gate pad 170 is relatively long, for example, the center of the gate electrode 130c along the Y direction. This improves the phenomenon of a relatively large voltage drop occurring in a region far from the gate pad 170 in the power semiconductor device 100c, and improves the uniformity of the voltage drop.

[0053] 6a and 6b are plan views illustrating a power semiconductor device according to an exemplary embodiment.

[0054] 6a, in a power semiconductor device 100d, the first region 182 and the second region 184 of each of the gate bus lines 180 may have a shape in which the width increases with increasing distance from the gate pad 170, and the gate electrode 130c may have a shape in which the width increases toward the center in the Y direction. The description above with reference to FIGS. 1 to 2c can be similarly applied to the gate bus lines 180, and the description above with reference to FIG. 5 can be similarly applied to the gate electrode 130c.

[0055] 6b, in the power semiconductor device 100e, the second regions 184 of the gate bus lines 180b may have a shape in which their width increases with increasing distance from the gate pad 170, and the gate electrodes 130c may have a shape in which their width increases toward the center in the Y direction. The description above with reference to FIG. 4 can be similarly applied to the gate bus lines 180b, and the description above with reference to FIG. 5 can be similarly applied to the gate electrodes 130c.

[0056] In some embodiments, the shape of the gate electrode 130c in the embodiment of FIG. 5 can also be applied to the embodiment of FIG.

[0057] 7a and 7b are a schematic plan view and a schematic cross-sectional view of a power semiconductor device according to an exemplary embodiment, with Fig. 7b showing a cross section along section line IV-IV' in Fig. 7a.

[0058] 7a and 7b, in the power semiconductor device 100f, the shape of the gate electrode 130f is different from that of the embodiment of FIG. 5. The gate electrode 130f may have a cross-sectional area that increases and then decreases as it extends from a first end to a second end along the Y direction. The depth or thickness of the gate electrode 130f in the Z direction within the gate trench GT may gradually increase and then decrease. The depth of the gate electrode 130f in the Z direction may change discontinuously, for example, in a step-like manner.

[0059] The gate electrode 130f may have a first depth D1 from the top surface adjacent to an end connected to the second region 184 of the gate bus line 180c and a second depth D2 deeper than the first depth D1 at the center along the Y direction. The second depth D2 may be the maximum depth of the gate electrode 130f. The relative magnitudes of the first depth D1 and the second depth D2 and the number of depths of the gate electrode 130f may vary in various embodiments. At least a portion of the gate electrode 130f may have a relatively small depth at an end connected to the second region 184 of the gate bus line 180c and an end connected to the gate pad 170, and a relatively large depth at the center along the Y direction. In this embodiment, the width of the gate electrode 130f may be substantially constant in the Y direction. The gate electrode 130f may have a symmetrical shape with respect to the center along the Y direction.

[0060] The gate electrode 130f has such a shape that it improves the uniformity of the voltage drop by improving the phenomenon of a relatively large voltage drop occurring in the region far from the gate pad 170, as described above with reference to Figure 5. The shape of the gate electrode 130f can also be applied to the embodiments of Figures 1 to 6b.

[0061] 8 is a cross-sectional view of a power semiconductor device according to an exemplary embodiment, showing the area corresponding to FIG.

[0062] 8, in a power semiconductor device 100g, the shape of a gate electrode 130g is different from that of the embodiment of FIG. 7b. In this embodiment, the gate electrode 130g may be disposed on the drift layer 102, rather than being disposed in a gate trench GT (see FIG. 7b) extending into the drift layer 102. A gate insulating layer 120 may be disposed on the drift layer 102, below the gate electrode 130g.

[0063] The gate electrode 130g may have a cross-sectional area that increases and then decreases as it extends from a first end to a second end along the Y direction. The gate electrode 130g may have a thickness that gradually increases and then decreases in the Z direction. The thickness of the gate electrode 130g in the Z direction may vary discontinuously, for example, in a stepwise manner.

[0064] The gate electrode 130g may have a third thickness T3 from the top surface adjacent to an end connected to the second region 184 of the gate bus line 180c, and a fourth thickness T4 thicker than the third thickness T3 at the center along the Y direction. The fourth thickness T4 may be the maximum thickness of the gate electrode 130g. The relative magnitudes of the third thickness T3 and the fourth thickness T4 and the number of thicknesses of the gate electrode 130g may vary in various embodiments. At least a portion of the gate electrode 130g may have a relatively small thickness at an end connected to the second region 184 of the gate bus line 180c and an end connected to the gate pad 170, and a relatively large thickness at the center along the Y direction. In this embodiment, the width of the gate electrode 130g may be substantially constant in the Y direction. The gate electrode 130g may have a symmetrical shape with respect to the center along the Y direction. This shape of the gate electrode 130g may also be applied to the embodiments of FIGS. 1 to 6b.

[0065] 9a to 9f are diagrams sequentially illustrating a method for manufacturing a power semiconductor device according to an exemplary embodiment. In Fig. 9a to 9f, one embodiment of a method for manufacturing the power semiconductor device of Fig. 1 to Fig. 2c is described, and regions corresponding to Fig. 2a and Fig. 2b are also shown.

[0066] Referring to FIG. 9a, a drift layer 102 may be formed on a substrate 101, and a well region 105, a source region 107, and a well contact region 109 may be formed thereon.

[0067] For example, a SiC wafer can be provided as the substrate 101. The drift layer 102 can be formed by epitaxial growth on the substrate 101. The drift layer 102 can be formed so as to contain first conductivity type impurities.

[0068] The well region 105, the source region 107, and the well contact region 109 can be sequentially formed in the drift layer 102 by an ion implantation process. Second conductivity type impurities can be implanted into the well region 105 and the well contact region 109, and first conductivity type impurities can be implanted into the source region 107. After the ion implantation process, an annealing process can be performed at a high temperature, for example, at a temperature of about 1600°C to about 1800°C.

[0069] In some embodiments, at least one of the well region 105, the source region 107, and the well contact region 109 may not be formed in the region on the right side corresponding to Figure 2b. Alternatively, in some embodiments, at least one of the well region 105, the source region 107, and the well contact region 109 may be formed in the region corresponding to Figure 2b as well, and then removed in a subsequent process.

[0070] Referring to FIG. 9b, a gate trench GT may be formed.

[0071] The gate trench GT can be formed by using another mask layer to partially remove the source region 107, the well region 105, and the drift layer 102. The drift layer 102 can be exposed from the bottom surface of the gate trench GT.

[0072] Referring to FIG. 9c, a gate insulating layer 120 and a gate electrode 130 may be formed.

[0073] The gate insulating layer 120 may be formed by forming an insulating layer to fill the gate trench GT and then partially removing the insulating layer. Alternatively, the gate insulating layer 120 may be formed by first forming a uniform first insulating layer using an oxidation process, such as a thermal oxidation process, and then forming a second insulating layer on the first insulating layer using a spin-on glass (SOG) process or a high-temperature oxide (HTO) process. The gate insulating layer 120 may be formed thicker on the bottom of the gate trench GT than on the sidewalls of the gate trench GT. Next, a conductive material may be deposited to form a gate electrode 130 in the gate trench GT.

[0074] Referring to Figure 9d, a first dielectric layer 140 may be formed.

[0075] The first dielectric layer 140 may be formed by depositing it over the entire top surface of the structure being fabricated and then removing it by an etching process to expose a portion of each of the source region 107 and the well contact region 109. In the region on the right, corresponding to FIG. 2b, the first dielectric layer 140 may be formed to expose a portion of the gate electrode 130. In some embodiments, removing the first dielectric layer 140 to expose a portion of the gate electrode 130 may be performed in a subsequent step.

[0076] Referring to FIG. 9 e , a source electrode 150 may be formed on the first dielectric layer 140 .

[0077] The source electrode 150 can be formed, for example, by depositing a conductive material over the entire top surface of the structure being fabricated and then removing some of it using an etching process. In the region on the right, corresponding to Figure 2b, the source electrode 150 can be completely removed.

[0078] Referring to FIG. 9f, the gate bus line 180 can be formed.

[0079] A gate bus line 180 is formed on the first dielectric layer 140 and can be connected to the underlying gate electrode 130 through an open area of ​​the first dielectric layer 140. In this step, a gate pad 170 (see FIG. 1) can also be formed together with the gate bus line 180.

[0080] 2a to 2c, a second dielectric layer 145 may be formed on the gate bus line 180, a bus metal layer 190 connected to the gate bus line 180 may be formed on the second dielectric layer 145, and a drain electrode 160 may be formed on the lower surface of the substrate 101. In some embodiments, the drain electrode 160 may be formed in a separate process step. This allows the power semiconductor device 100 of FIGS. 1 to 2c to be manufactured.

[0081] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the appended claims. Therefore, various substitutions, modifications, and changes can be made by a person skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and these also fall within the scope of the present invention. [Explanation of symbols]

[0082] 101 Substrate 102 Drift Layer 105 well area 107 Source Area 109 well contact area 120 Gate insulating layer 130 gate electrode 140 First dielectric layer 150 Source Electrode 160 drain electrode 170 Gate Pad 180 Gate Bus Line 182 1st area 184 Second area 190 Bus Metal Layer

Claims

1. a substrate including SiC of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a source region of the first conductivity type on the well region; a gate electrode disposed in a gate trench extending in a first direction parallel to an upper surface of the substrate, the gate trench penetrating the source region and the well region; a gate pad electrically connected to the gate electrode; a gate bus (BUS) line connecting the gate pad and the gate electrode, the gate bus (BUS) line including a first region extending from the gate pad in the first direction and a second region extending from the first region in a second direction intersecting the first direction and connected to an end of the gate electrode; a drain electrode on the lower surface of the substrate; the second region has a first cross-sectional area at a first portion spaced a first distance from the gate pad, and a second cross-sectional area larger than the first cross-sectional area at a second portion spaced a second distance from the gate pad that is longer than the first distance.

2. 2. The power semiconductor device of claim 1, wherein the second region has a first width at the first portion and a second width at the second portion that is greater than the first width.

3. The power semiconductor device according to claim 1 , wherein the second region has a width that gradually increases with increasing distance from the first region.

4. 2. The power semiconductor device of claim 1, wherein the first region has a third width at a portion spaced a third distance from the gate pad, and a fourth width greater than the third width at a portion spaced a fourth distance from the gate pad that is longer than the third distance.

5. 2. The power semiconductor device according to claim 1, wherein at least one of the gate electrodes has a third cross-sectional area at a portion spaced a fifth distance from the gate bus line, and a fourth cross-sectional area larger than the third cross-sectional area at a portion spaced a sixth distance from the gate bus line that is longer than the fifth distance.

6. a substrate including SiC of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a source region of the first conductivity type on the well region; a gate electrode disposed in a gate trench extending in a first direction parallel to an upper surface of the substrate, the gate trench penetrating the source region and the well region; a gate pad electrically connected to the gate electrode; a gate bus line connecting the gate pad and the gate electrode and including a region extending in a second direction intersecting the first direction; a drain electrode on the lower surface of the substrate; At least one of the gate electrode and the gate bus line has a cross-sectional area that gradually changes in one direction that is an extension direction.

7. 7. The power semiconductor device according to claim 6, wherein the gate bus line includes a region having a side surface that is inclined so that the width increases in the one direction in a plan view.

8. 7. The power semiconductor device according to claim 6, wherein the gate electrode has a first cross-sectional area at a portion spaced a first distance from the gate bus line, and a second cross-sectional area larger than the first cross-sectional area at a portion spaced a second distance from the gate bus line that is longer than the first distance.

9. a substrate including SiC of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a source region of the first conductivity type on the well region; a gate electrode extending in a first direction parallel to an upper surface of the substrate on the drift layer; a gate pad electrically connected to the gate electrode; a gate bus line connecting the gate pad and the gate electrode and including a region extending in a second direction intersecting the first direction; At least one of the gate electrode and the gate bus line has a first cross-sectional area at a first portion having a first electrical path from the gate pad, and a second cross-sectional area larger than the first cross-sectional area at a second portion having a second electrical path longer than the first electrical path.

10. 10. The power semiconductor device of claim 9, wherein the gate electrode has a first thickness at the first portion and a second thickness at the second portion that is thicker than the first thickness.

Images