Method for making material and semiconductor structure porous

Abstract

To provide a method for making a group III nitride material porous by using a few processing steps.SOLUTION: A method for making a III nitride material in a semiconductor structure porous is provided, and the semiconductor structure includes a subsurface structure of a first III nitride material having charge carrier density exceeding 5×1017 cm-3 under a surface layer of a second III nitride material having charge carrier density between 1×1014 cm-3 and 1×1017 cm-3. The method includes the steps of: exposing the surface structure to an electrolyte; and applying a potential difference between the first III nitride material and the electrolyte so as to make the subsurface structure porous by electrochemical etching, and on the other hand so as not to make the surface layer porous. Further, the semiconductor structure and its use are provided.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present invention relates to semiconductor materials, particularly III-nitride materials, methods for making semiconductor structures porous, uses of the semiconductor structures, and devices incorporating or attached to the semiconductor structures. The present invention may be particularly advantageous for the fabrication of porous semiconductor structures for use as distributed Bragg reflectors (DBRs) and substrates in the fabrication of semiconductor devices. [Background technology]

[0002] The class of semiconductor materials known as "III-nitride" materials includes gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), along with their ternary and quaternary alloys. III-nitride materials have not only achieved commercial success in solid-state lighting and power electronics, but also exhibit particular advantages for quantum light sources and light-matter interactions.

[0003] While various Group III nitride materials are of commercial interest, gallium nitride (GaN) is widely regarded as one of the most important emerging semiconductor materials and is of particular interest for several applications.

[0004] It is known that introducing pores into bulk GaN can greatly affect its material properties, such as its refractive index, without negatively affecting its electrical conductivity. Thus, the possibility of tailoring the optical properties of GaN by modifying its porosity makes porous GaN highly attractive for optoelectronic applications.

[0005] WO 2011 / 094391 A1 discloses the possibility of producing nanoporous GaN by electrochemical etching, in which the n-doped GaN is etched to create porosity by contacting the n-doped GaN with an electrolyte and applying an etching potential. WO 2011 / 094391 A1 (paragraph

[0031] ) describes two types of etching of GaN structures. In the first type, the surface of an exposed layer of n-doped GaN is etched in contact with the electrolyte to produce a porous layer. The etching proceeds perpendicular to the layer surface, referred to as vertical etching in WO 2011 / 094391 A1. In the second type of structure, a top layer of undoped GaN is formed on top of the n-doped GaN layer. Thus, the n-doped GaN forms a subsurface layer. The layer is then dry etched or cleaved to form trenches that expose the edges or sidewalls of the layer, allowing these edges to be exposed to the electrolyte. Etching then proceeds selectively from the exposed edges through the n-type layer, porosifying the doped subsurface layer but not the overlying undoped layer. In WO 2011 / 094391 A1, this is referred to as horizontal or lateral etching.

[0006] Electrochemical etching of n-type GaN is further described in various academic papers, all of which follow the teachings of WO2011 / 094391A1, which state that etching can be performed "vertically" to the exposed n-type GaN surface, or "horizontally" to the edge of an n-type GaN layer sandwiched between two layers of undoped GaN and / or an electrically insulating base layer.

[0007] Chen et al., Journal of Applied Physics, 112, 064303 (2012) describes the vertical etching of n-type GaN and the use of a 500 nm thick underlying undoped GaN layer as an "etch stop" to prevent further etching. Chen et al. further note that the vertical etching caused surface pits to form on the surface of the n-type GaN.

[0008] On the other hand, C. Zhang, et al., ACS Photonics 2015, 2, 980, discloses horizontal etching of a multilayer structure consisting of alternating layers of undoped GaN and n-type GaN. To enable horizontal etching, the multilayer sample was first lithographically patterned with trenches spaced 50 μm apart to expose the edges or sidewalls of the layers and allow for horizontal electrolyte transport into the n-type layer during porosification. An electrically insulating layer of SiO2 was also formed on top of the top undoped GaN layer as a protective layer.

[0009] Horizontal or lateral etching from the edge of a subsurface layer is limited by factors including the rate of diffusion of electrolyte into and out of the layer being etched, which implies a limit on the distance from the edge of the layer that can be etched, and therefore a limit on the width of the sample that can be made porous by horizontal etching (when etched from the opposite edge).

[0010] Prior art authors have addressed this sample-side limitation by dry-etching vertical trenches into the sample prior to etching, resulting in the edges of the sample layer being exposed at regular intervals. This allows the electrolyte to contact the layer edges and etch horizontally into the sample structure. Dry-etching trenches effectively divides each sample into multiple smaller samples, each extending between adjacent trenches. The distance between adjacent trenches is naturally limited to twice the distance that horizontal etching can penetrate into the layer (assuming the sample is etched horizontally from both sides). In C. Zhang, et al., for example, the sample width for horizontal etching is limited to a dimension of 50 μm between trenches.

[0011] This added processing step increases the cost of wafer processing and also limits the maximum size of the resulting porosified structure. The division of the semiconductor structure into small mesas by dry etching trenches can also make the resulting porosified structure unsuitable for use in the fabrication of certain semiconductor devices. Therefore, this technique can limit the feasibility of horizontal etching methods and the resulting structures for large-scale practical optoelectronic devices.

[0012] Furthermore, prior art horizontal etching methods involve applying a relatively thick dielectric layer to the top of the semiconductor structure prior to etching. This dielectric layer, often formed from silica (SiO), covers the surface layer and prevents the electrolyte from contacting the surface layer of the sample during etching. This layer acts as a mask to protect the surface layer from damage during the dry etching of the trench or during the horizontal etching process. The application and subsequent removal of this layer, if necessary, introduces additional processing steps and constrains material design. Summary of the Invention [Means for solving the problem]

[0013] The present invention relates to methods for making III-nitride materials and semiconductor structures porous, uses of the semiconductor structures and devices incorporating or having the semiconductor structures attached, as defined in the accompanying independent claims, to which reference should be made here. Preferred or advantageous features of the invention are set out in the dependent claims.

[0014] Our publication, Zhu, T. et al. Wafer-scale Fabrication of Non-polar Mesoporous GaN Distributed Bragg Reflectors via Electrochemical Porosification. Sci. Rep. 7, 45344; doi: 10.1038 / srep45344 (2017), is incorporated herein by reference in its entirety.

[0015] According to a first aspect of the present invention, there is provided a method for making a III-nitride material in a semiconductor structure porous. The semiconductor structure comprises a 1×10 14 cm -3 From 1×10 17 cm -3 5×10 17 cm -3 and a sub-surface structure of a first III-nitride material having a charge carrier density greater than 0. The method includes exposing the surface layer to an electrolyte and applying a potential difference between the sub-surface structure and the electrolyte such that the sub-surface structure is rendered porous by electrochemical etching while the surface layer is not rendered porous.

[0016] The method may alternatively be referred to as a method for subsurface porosification of III-nitride materials or a method for subsurface porosification of III-nitride materials. Because subsurface III-nitride materials can be selectively made porous depending on their charge carrier density, such a method may be a method for selectively making III-nitride materials porous.

[0017] The subsurface structures can be provided in any desired arrangement or pattern below the surface layer. Preferably, the subsurface structures form a sub-surface layer below the surface layer. It is particularly preferred that the subsurface structures form a continuous or uninterrupted sub-surface layer below the surface layer.

[0018] The subsurface structure may advantageously be made porosity by electrochemical etching through the surface layer, i.e. the method may be a through-layer porosity method.

[0019] Unlike in the prior art, the present method does not require the III-nitride material to be etched to be exposed to an electrolyte. In WO 2011 / 094391 A1, for example, both "horizontal" and "vertical" etching require that the edges or surfaces of the layer to be etched be exposed to the electrolyte. If the top surface of the n-doped GaN is exposed, "vertical" etching occurs downward into the layer. If only the sidewalls or edges of the n-doped layer are exposed to the electrolyte, "horizontal" etching occurs inward into these exposed edges.

[0020] This method is 1 × 10 14 cm -3 From 1×10 17 cm -3 Etching is enabled by exposing a surface layer of III-nitride material, which has a charge carrier density between 0.01 and 0.1, to the electrolyte. However, it is not necessary to expose the subsurface structure (the material to be etched) to the electrolyte.

[0021] The step of exposing the surface layer to the electrolyte may alternatively be described as contacting the surface layer with the electrolyte. Preferably, the upper, top, or outermost surface of the surface layer is exposed to the electrolyte. It is particularly preferred that only the surface layer is exposed to the electrolyte.

[0022] In the prior art, when a surface layer of nominally "undoped" GaN is masked by a layer of dielectric material such as SiO2, the top surface of the surface layer is not exposed to the electrolyte.

[0023] The surface layer may cover only the top surface of the subsurface structure. In other words, the subsurface structure may be located below or directly below the surface layer, or the surface layer may be located above the subsurface structure. The sidewalls or edges of the subsurface structure may be exposed, i.e., not covered by the surface layer.

[0024] Alternatively, the subsurface structure may be completely covered by the surface layer, i.e., both the top surface and sidewalls or edges of the subsurface structure may be covered by the surface layer. Thus, when the structure formed from the subsurface structure and the surface layer is completely immersed in an electrolyte, the surface layer may be the only material exposed to the electrolyte.

[0025] While the prior art discloses the use of undoped GaN as an "etch stop" to halt the progress of electrochemical etching, the present inventors have discovered that a surface layer of GaN or other III-nitride material, with a 1×10 14 cm -3 From 1×10 17 cm -3 It has been found that the use of a surface layer having a charge carrier density between 0.01 and 0.02 allows electrochemical etching through the surface layer of the second III-nitride material to occur. In other words, the subsurface structure can be made porous by etching through the surface layer without directly contacting the subsurface structure with an electrolyte and without etching the surface layer itself.

[0026] By controlling the charge carrier density of the surface layer as well as the charge carrier density of the subsurface structure, the inventors have discovered that the subsurface structure of a first III-nitride material can be rendered porous through the surface layer without the surface layer itself being rendered porous. It is particularly advantageous to be able to electrochemically etch the subsurface structure without damaging or roughening the surface layer during the etching process. Thus, the method of the present invention may advantageously enable selective porosity of a composite (e.g., multilayer) III-nitride structure without applying a protective conductive layer, e.g., of SiO2, over the surface layer. This may eliminate the need for the time-consuming and costly extra processing step of applying and subsequently removing a top protective layer, required by the prior art, before the porous structure can be used.

[0027] The surface layer should be at least 5×10 14 cm -3 , or 1×10 15 cm -3 , or 5 x 10 15 cm -3 and / or 7 x 10 charge carrier density 15 cm -3 , or 1×10 16 cm -3 , or 5 x 10 16 cm -3 , or 8 x 10 16 cm -3 The charge carrier density may be less than 1000 .mu.m.

[0028] The charge carrier density in the surface layer is 1×10 14 cm -3 If it is less than 0.15, the surface layer may be too electrically resistive to allow electrochemical etching through it, as there will not be enough charge carriers present to carry current to the subsurface structures to be porosified.

[0029] However, the charge carrier density in the surface layer is 1×10 17 cm -3, the surface layer may be sufficiently conductive that it becomes porous during the electrochemical process. Thus, the surface layer may become porous, "pitted" and / or roughened, which makes it unsuitable for further processing, e.g., further epitaxial overgrowth. This is because even if the surface layer is not intentionally doped, the impurity concentration in the surface layer may be too high and the surface layer may exceed 1×10 17 cm -3 This can occur when the charge carrier density exceeds

[0030] By controlling the charge carrier density of a layer and the contrast in charge carrier density between adjacent layers, it is possible to predetermine the layers that will be made porous by electrochemical etching.

[0031] The subsurface structure, when porous by electrochemical etching, is at least 5×10 17 cm -3 , or at least 1×10 18 cm -3 , or at least 5×10 18 cm -3 , or at least 1×10 19 cm -3 , or at least 5×10 19 cm -3 , or at least 1×10 20 cm -3 and / or 1 x 10 charge carrier density 21 cm -3 , or 5 x 10 21 cm -3 , or 1×10 22 cm -3 The charge carrier density may be less than 1000 .mu.m.

[0032] According to the method of the present invention, the inventors have 17 cm -3 Subsurface structures with charge carrier densities above 1 × 10 17 cm -3It has been found that layers having a charge carrier density of less than 1×10 are not porous. 17 cm -3 From 5 x 10 17 cm -3 While porosity can be achieved between 0.01 and 0.1, by using a charge carrier density outside this range, a contrast in electrical conductivity between the surface layer and the subsurface structure can be created, facilitating selective porosity of the subsurface structure.

[0033] To avoid damage to the "undoped" surface layer, prior art authors have found it necessary to apply a protective dielectric layer to the top surface of their samples.

[0034] Those skilled in the art will appreciate that the term "undoped" is relatively imprecise in semiconductor technology, as virtually all semiconductor materials contain inherent impurities that can be thought of as "dopant" atoms. Different methods of semiconductor growth can result in different levels of impurities and, therefore, different concentrations of inherent charge carriers. At high impurity levels, the resulting semiconductor material can have impurities as high as 1×10 even if the layer was not intentionally doped. 17 cm -3 The charge carrier density may be greater than .

[0035] Thus, the reason why prior art authors found it necessary to apply a protective dielectric layer to prevent unwanted etching of the surface layer is because that "undoped" surface layer is actually 1×10 17 cm -3 , resulting in the surface layer itself being etched or partially etched upon application of a potential difference. By applying a dielectric layer on top of the surface layer, the surface layer is protected from accidental etching, regardless of its charge carrier concentration.

[0036] The presence of an electrically insulating layer on the outer surface of the surface layer prevents electrical conduction through the surface layer to the underlying subsurface structure(s), thereby preventing electrochemical etching through the surface layer.

[0037] Coating the outer surface of the surface layer with a dielectric material, as done in the prior art, causes the etch to proceed horizontally into the exposed edges of the layer. The authors of the prior art found that by doing this, only the n-type doped GaN layer was made porous, while the "undoped" GaN layer was not made porous and acted as an "etch stop."

[0038] The present inventors hypothesize that in the prior art, horizontal etching proceeds preferentially into the exposed edges of "n-type" layers because these layers provide the path of lowest electrical resistance. Thus, the nominally "undoped" GaN layers of the prior art are in fact etched to a depth of 1×10 17 cm -3 Even if the "n-type" layers have a charge carrier density greater than 0.01, horizontal etching will proceed preferentially into the "n-type" layers as long as these layers have a higher charge carrier density, and therefore a higher electrical conductivity, than the "undoped" layers.

[0039] This "path of least resistance" behavior is not possible when the electrolyte is in contact with the exposed top surface of the surface layer. Therefore, the charge carrier concentration in the surface layer must be controlled so that etching through the surface layer can occur but does not cause damage to or porosity of the surface layer itself.

[0040] Thus, the method of the present invention advantageously provides a method for porosifying III-nitride materials using fewer processing steps than required by prior art methods, and the method can advantageously porosify large sample sizes without the need for pre-etching trenches.

[0041] The surface layer and subsurface structure preferably comprise a III-nitride material selected from the group consisting of GaN, AlGaN, InGaN, InAlN, and AlInGaN. The surface layer and subsurface structure may be formed from the same III-nitride material but with different charge carrier densities in each layer, or each layer may be formed from a different III-nitride material.

[0042] Suitable III-nitride materials can have, for example, any polar or non-polar crystal orientation. Suitable III-nitride materials can have any crystal structure, such as a wurtzite or cubic crystal structure, and any crystal orientation. For example, suitable III-nitride materials can include polar c-plane, non-polar a-plane, or even cubic III-nitride materials.

[0043] In a particularly preferred embodiment, the surface layer is 14 cm -3 From 1×10 17 cm -3 The subsurface structure consists of GaN with a charge carrier density between 5×10 17 cm -3 It consists of n-type doped GaN with a charge carrier density exceeding 1000 Å.

[0044] The subsurface structure preferably consists of an n-type doped III-nitride material, and it is particularly preferred that the subsurface structure is doped with silicon (Si), germanium (Ge) and / or oxygen (O).

[0045] The charge carrier density of a given layer can be readily measured by one skilled in the art, for example, by capacitance-voltage profiling or calibrated scanning capacitance microscopy. Depth profiling Hall effect techniques may also be suitable. Charge carrier density may alternatively be referred to as carrier density or carrier concentration. References to charge carrier density herein refer to charge carrier density at room temperature.

[0046] In a preferred embodiment, the subsurface structure comprises a planar subsurface layer of a first III-nitride material. The surface layer and the subsurface structure form a contiguous planar layer, with an upper surface of the subsurface layer contacting a lower surface of the surface layer, or they are separated by an intervening layer of III-nitride material. Preferably, the subsurface layer can be one of multiple subsurface layers formed from the same or different III-nitride materials.

[0047] The surface layer and subsurface structures may be formed by epitaxial growth, such as molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD) (also known as metalorganic vapor phase epitaxy (MOVPE)), hydride vapor phase epitaxy (HVPE), ammonothermal processes, or other conventional processes suitable for growing III-nitride materials with the required charge carrier concentrations.

[0048] The surface layer and subsurface structure(s) may be grown on an electrically insulating base layer or substrate. The base layer is preferably configured to form the bottom of the multi-layer structure, and the surface layer forms the top of the multi-layer structure, with the subsurface structure(s) disposed between the surface layer and the base layer. The electrically insulating base layer may preferably comprise sapphire, silicon, silicon carbide, LiAlO3, glass, or bulk GaN.

[0049] Electrochemical etching can be carried out in a variety of acidic or basic electrolytes. For example, suitable electrolytes include oxalic acid, KOH, NaOH, HF, HCl, and HNO3.

[0050] Preferably, the electrolyte should form a wetting or contact angle of 120° or greater with the exposed surface of the surface layer.

[0051] To electrochemically etch a sample, an electrochemical cell is arranged so that the sample itself acts as the anode and an inert electrode, such as a platinum foil electrode, acts as the cathode. The sample and platinum electrode are connected to a power source, and the sample is immersed or partially immersed in an electrolyte to complete the circuit.

[0052] In order to apply a potential difference between the sample electrolyte and the subsurface structure, the subsurface structure to be made porous must be electrically connected or in electrical contact with the terminals of a power source.

[0053] To perform electrochemical etching, a power supply is controlled to apply a potential difference (voltage) between the subsurface structure and the electrolyte, causing a current to flow through the electrolyte and the sample. The current flow through the sample is approximately 5×10 17 cm -3 This causes electrochemical etching of any subsurface structures with a charge carrier density above 0.1, resulting in increased porosity in these layers.

[0054] To selectively render the subsurface structure porous, the potential difference applied between the subsurface structure and the electrolyte is preferably at least 4 volts (v), or 6 V, or 8 V, or 10 V, or 15 V, and / or less than 20 V, or 25 V, or 30 V.

[0055] Electrochemical etching may be performed in a continuous or pulsed mode and may be controlled by controlling the voltage or current across the cell.

[0056] It is advantageous to be able to monitor the progress of the etching reaction by measuring the etching current during the reaction.

[0057] After etching, the samples were cleaned by rinsing with deionized water and drying with N to ensure complete dissolution of any remaining etching chemicals and products without affecting the porous structure of the subsurface structure.

[0058] Preferably, the charge carrier density in the subsurface structure is at least 5, or 10, or 100, or 1000, or 10,000, or 100,000, or 1,000,000 times higher than the charge carrier density in the surface layer. A large difference between the charge carrier densities of the different layers can be considered a large "contrast" in charge carrier densities, which can advantageously increase the selectivity of the etching process.

[0059] The threading dislocation density in both the surface layer and the subsurface structure is 1×10 4 cm -2 From 1×10 10 cm -2 It is particularly preferred that the threading dislocation density in both the surface layer and the subsurface structure is substantially equal in the surface layer and the subsurface structure. The threading dislocation density in both the surface layer and the subsurface structure is at least 1×10 4 cm -2 , 1×10 5 cm -2 , 1×10 6 cm -2 , 1×10 7 cm -2 Or 1 x 10 8 cm -2 and / or 1 x 10 9 cm -2 , or 1×10 10 cm -2Preferably, the dislocation density is less than 0.05. Typically, semiconductor material producers seek to minimize the threading dislocation density of their materials in an effort to improve material quality. However, in the present invention, a sufficient threading dislocation density between the surface layer and the subsurface layer may be necessary to allow electrochemical etching through the surface layer. This may be due to increased electrolyte or charge carrier transport to the subsurface layer.

[0060] The surface layer is preferably a continuous layer of III-nitride material, i.e., the surface layer is preferably substantially free of holes or large-scale defects.

[0061] In a preferred embodiment, the subsurface structure may also be a continuous subsurface layer of III-nitride material.

[0062] The thickness of the surface layer is preferably at least 1 nm, or 10 nm, or 100 nm, and / or less than 1 μm, or 5 μm, or 10 μm. In a preferred embodiment, the thickness of the surface layer is 50 nm.

[0063] The thickness of the subsurface structure or layer is preferably at least 1 nm, or 10 nm, or 100 nm, and / or less than 1 μm, or 5 μm, or 10 μm.

[0064] Particularly preferably, the outer surface of the continuous surface layer has a minimum lateral dimension of at least 300 μm, or at least 600 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0065] Particularly preferably, the subsurface structure is a continuous layer and has a minimum lateral dimension of at least 300 μm, or at least 600 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0066] The minimum lateral dimension of a layer refers to the lateral width of the layer at its narrowest point. The layers used in preferred embodiments of the present invention are relatively large and thin. As such, the lateral dimension of a layer should be understood to refer to the dimensions of the "top" and "bottom" surfaces of the layer, and the thickness of a layer refers to its "height," i.e., the distance between its top and bottom surfaces. Thus, the top surface of a sample is a square, and the minimum lateral dimension of the sample is the distance between the opposing edges of the square. In this context, the "bottom" surface should be understood to be the surface that is first formed during epitaxial growth of a layer on a substrate, and the "top" surface is the surface that is formed on the side of the layer opposite the "bottom" surface.

[0067] The method of the present invention advantageously allows for porosifying much larger semiconductor structures than are possible using prior art horizontal etching techniques. Because the method of the present invention results in electrochemical etching of subsurface structures through the surface layers rather than horizontally from the exposed edges of each individual layer, the effectiveness of the present invention is not limited by a maximum sample width.

[0068] Using this method, it is possible to uniformly porosify a continuous subsurface layer across an entire 2-inch semiconductor wafer without first forming regular trenches in the wafer to expose the layer edges. This is not possible using prior art etching methods because horizontal etching could not etch all the way to the center of such a large wafer. Horizontal etching would be limited to etching a distance of tens or hundreds of micrometers from the edge of the wafer. Furthermore, it is possible to uniformly porosify a continuous subsurface layer across an entire 2-inch semiconductor wafer without protecting the surface layer with an electrically insulating layer. This is not possible using prior art etching methods that require protection of the top surface.

[0069] The characteristics of prior art horizontal etching have been extensively studied and found to be rate-limited by etching from the sample edge. Limitations such as electrolyte and charge transport mean that beyond a certain sample width, horizontal etching cannot reach the center of the sample after any amount of time. Current concentration at the sample edge over an extended period of time can lead to non-uniform porosity throughout the layer, concentrating porosity at the sample edge and little porosity occurring in the sample center.

[0070] For these reasons, prior art authors have resorted to prepping samples with regularly spaced dry etching trenches across the entire sample to allow the electrolyte access to the sample edge every 50 μm or so, which allows the electrolyte access to exposed edges of subsurface layers and can result in horizontal etching.

[0071] The present inventors have circumvented these problems by etching through the surface layer, rather than just from the edge of the layer. This method advantageously allows porosity to develop uniformly throughout the subsurface layer, rather than from the edge. This can advantageously reduce the time required to etch the sample and increase the uniformity of the porosity compared to performing only horizontal etching.

[0072] Particularly advantageously, the method of the present invention does not require prior preparation of the sample by creating trenches in the layer, since access to the layer edges is not required. The present invention therefore requires fewer processing steps and allows for the porosification of large continuous semiconductor layers without the need to divide the layer with regular trenches.

[0073] Furthermore, because the method does not require access to the edge of the material to be etched, a variety of subsurface structures can be made porous. Unlike prior art, the subsurface structures do not need to extend to the edge of the sample or present a large surface area of ​​sidewalls for exposure to the electrolyte during the etching process. Therefore, a variety of patterns or structures of porous material can be formed as porous subsurface structures below the surface layer.

[0074] Preferably, the method can produce pores in the subsurface structure having an average pore size greater than 1 nm, or 2 nm, or 10 nm, or 20 nm, and / or an average pore size less than 50 nm, or 60 nm, or 70 nm.

[0075] The pore size and morphology of the subsurface structure, and the resulting percentage porosity, can be advantageously controlled by controlling the charge carrier concentration in the subsurface structure(s) and by controlling the potential difference applied between the electrolyte and the subsurface structure(s) during etching.

[0076] The method preferably can render the subsurface structure microporous, i.e., the subsurface structure has an average pore size of less than 2 nm. Alternatively, the method can render the subsurface structure mesoporous, i.e., the subsurface structure has an average pore size between 2 nm and 50 nm. Alternatively, the method can render the subsurface structure macroporous, i.e., the subsurface structure has an average pore size of greater than 50 nm.

[0077] In a preferred embodiment, the method can be used to porosify a plurality of subsurface structures. Thus, the method comprises applying a potential difference between the subsurface structure to be porosified and an electrolyte, the potential difference being 5×10 17 cm -3 Structures with charge carrier densities above 1 × 10 were made porous by electrochemical etching, while 14 cm -3From 1×10 17 cm -3 Structures with charge carrier densities between 0.1 and 0.2 are not porousified.

[0078] In a particularly preferred embodiment, the subsurface structure may be a subsurface layer, and the method may be used to porosify multiple subsurface layers. When the semiconductor structure includes multiple subsurface layers formed from III-nitride materials, the method includes applying a potential difference between the subsurface layer to be porosified and the electrolyte, and applying a potential difference of 5×10 17 cm -3 Layers with a charge carrier density of more than 1 × 10 are made porous by electrochemical etching, while 14 cm -3 From 1×10 17 cm -3 Layers having a charge carrier density between 0.1 and 0.25 are not porousified.

[0079] 5×10 17 cm -3 A layer having a charge carrier density above 0.1 can be made porous by electrochemical etching through the layer above it.

[0080] By controlling the charge carrier density in each layer, it is possible to control which subsurface layers are made porous by the electrochemical etching process. Thus, various multilayer structures can be grown to achieve different porosity characteristics in predetermined layers.

[0081] If the subsurface structure or layer is made porous by electrochemical etching, the charge carrier density is 5×10 17 cm -3 Above this threshold, the porosity of the resulting porous structure varies roughly with the charge carrier density of the original subsurface structure. Thus, 5×10 17 cm -3 If two subsurface structures are provided with charge carrier densities greater than , the subsurface structure with the higher charge carrier density will be rendered porous to a greater extent than the other subsurface structure, provided the same potential difference is applied to each.

[0082] In a preferred embodiment, the subsurface structure forms a plurality of subsurface layers arranged in a stack one above the other. The method of the present invention advantageously allows etching of the subsurface layers sequentially from the surface layer downwards, i.e., the subsurface layer closest to the surface layer is porosified first, followed by etching downwards through the subsurface structure. 17 cm -3 The process then proceeds to the next subsurface layer having a charge carrier density above 0.1, which in turn is made porous, and so on.

[0083] Particularly advantageously, this sequential etching can allow a user to control the porosity of a particular subsurface layer by controlling the potential difference between the electrolyte and the subsurface layer during electrochemical etching of that layer. Monitoring the etching current during etching advantageously allows a user to sequentially monitor the progress of etching through the multi-layer stack, thereby controlling the potential difference during electrochemical etching of a particular layer.

[0084] In a particularly preferred embodiment, the subsurface structure is a first subsurface layer and the semiconductor structure is a second subsurface layer of III-nitride material, 14 cm -3 From 1×10 17 cm -3 and a third subsurface layer of a III-nitride material, the second subsurface layer having a charge carrier density between 5×10 17 cm -3 and a third subsurface layer having a charge carrier density greater than 0.01, and the second subsurface layer is disposed between the first and third subsurface layers. The method includes the additional step of applying a potential difference between the third subsurface layer and an electrolyte, whereby the third subsurface layer is rendered porous by electrochemical etching, while the surface layer and second subsurface layer are not rendered porous.

[0085] In addition to porosifying the first subsurface layer, a third subsurface layer may be porosified by electrochemical etching through the surface layer, the first subsurface layer, and the second subsurface layer.

[0086] Therefore, the method of the present invention is suitable for the surface layer and the 1×10 14 cm -3 From 1×10 17 cm -3 , and the method allows selective subsurface porosity of a plurality of subsurface layers based on their charge carrier densities by etching through any subsurface layer having a charge carrier density between 1×10 and 1×10. 14 cm -3 From 1×10 17 cm -3 5 × 10 without damaging or roughening or making the layer porous. 17 cm -3 The subsurface layer can be made porous with a charge carrier density greater than .

[0087] Preferably, the root mean square roughness of the surface layer is not altered during electrochemical etching. Particularly preferably, the root mean square roughness of the outermost surface of the surface layer after etching is less than 10 nm, or less than 5 nm, or less than 2 nm, or less than 1 nm, or less than 0.5 nm over an area of ​​1 square micrometer. That is, the method of the present invention can produce an "epi-ready" surface, in which the root mean square roughness of the surface layer is sufficiently low so that further epitaxial growth can be performed on the surface layer without the need for intermediate processing steps.

[0088] In a preferred embodiment, the surface layer and subsurface layer(s) are provided as wafers having a diameter of 1 inch (2.54 cm), or 2 inches (5.08 cm), or 6 inches (15.24 cm), or 8 inches (20.36 cm).

[0089] This method is 1 × 10 14 cm -3 From 1×10 17 cm -3Since the present invention provides electrochemical etching through layers having charge carrier densities between 0.1 and 0.5, it is possible to etch regions of the subsurface structure or subsurface layer that are far from any sidewalls or edges of the semiconductor structure.

[0090] Thus, the method advantageously can etch regions of the subsurface structure at least 300 μm, or 500 μm, or 750 μm, or 1 mm, or 1 cm, or 5 cm from the nearest sidewall or edge of the semiconductor structure, which is not possible with horizontal etches, which are limited in how far they can be etched and can etch tens or even hundreds of micrometers from the layer edge.

[0091] The method is particularly preferably carried out without providing trenches in the surface layer and subsurface structures.

[0092] Preferably, the surface layer is not coated with an electrically insulating layer during electrochemical etching.

[0093] Preferably, the sample is not illuminated with UV illumination during electrochemical etching.

[0094] According to a second aspect of the present invention, there is provided a semiconductor structure formed by the method described above as the first aspect of the present invention.

[0095] According to a third aspect of the present invention, there is provided a porous subsurface structure of a first III-nitride material and a surface layer of a second III-nitride material, the porous subsurface structure comprising a 1×10 14 cm -3 From 1×10 17 cm -3 and a subsurface structure having a uniform porosity throughout the structure, wherein both the surface layer and the subsurface structure have a minimum lateral dimension greater than 550 μm.

[0096] According to a preferred embodiment, the semiconductor structure may be a multi-layer semiconductor structure.

[0097] As discussed above in connection with the first aspect of the present invention, prior art horizontal etching methods cannot porosify subsurface layers having minimum lateral dimensions longer than several hundred micrometers. In prepatterned structures with vertical trench cuts in a layer, the minimum lateral dimension of the sample may be the distance between adjacent trenches.

[0098] Furthermore, horizontal etching techniques may not produce porous subsurface layers with uniform porosity throughout the layer. Particularly when the minimum lateral dimension of the subsurface layer is relatively large, e.g., 250 μm, electrolyte limitations and / or limitations in edge-to-layer charge transport can create non-uniform porosity throughout the subsurface layer. In such horizontal etching techniques, exposure of the subsurface layer to electrolyte creates regions of high porosity at or near the exposed edges of the subsurface layer, with the porosity decreasing with distance from the edges of the subsurface layer. This effect is particularly pronounced in large structures, where electrolyte and / or charge transport problems become more pronounced away from the edges.

[0099] Preferably, the surface layer and the subsurface structure comprise a III-nitride material selected from the group consisting of GaN, AlGaN, InGaN, InAlN, and AlInGaN. The surface layer and the subsurface structure may be formed from the same or different III-nitride materials.

[0100] In a particularly preferred embodiment, the surface layer is 1×10 14 cm -3 From 1×10 17 cm -3 The subsurface structure is made of porous GaN.

[0101] In a preferred embodiment, the subsurface structure is a subsurface layer of a first III-nitride material. The surface layer and subsurface layer are adjacent layers, with the upper surface of the subsurface layer contacting the lower surface of the surface layer, or they are separated by an intervening layer of III-nitride material. Preferably, the subsurface layer can be one of multiple subsurface layers formed from III-nitride materials.

[0102] Preferably, the threading dislocation density in both the surface layer and the subsurface structure, or in the subsurface layer, is less than 1×10 4 cm -2 From 1×10 10 cm -2 The threading dislocation density in both the surface layer and the subsurface structure, or in the subsurface layer, is at least 1 × 10 4 cm -2 , 1×10 5 cm -2 , 1×10 6 cm -2 , 1×10 7 cm -2 Or 1 x 10 8 cm -2 and / or 1 x 10 9 cm -2 , or 1×10 10 cm -2 It is particularly preferred that it is less than 10 ...

[0103] The thickness of the surface layer is preferably at least 1 nm, or 10 nm, or 100 nm, and / or less than 1 μm, or 5 μm, or 10 μm.

[0104] The surface layer is preferably a continuous layer of a second III-nitride material.

[0105] The thickness of the subsurface structure or layer is preferably at least 1 nm, or 10 nm, or 100 nm, and / or less than 1 μm, or 5 μm, or 10 μm, or 100 μm.

[0106] Particularly preferably, the outer surface of the surface layer has a smallest lateral dimension of at least 600 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0107] It is particularly preferred that the subsurface structure is a continuous subsurface layer. The subsurface layer preferably has a minimum lateral dimension of at least 600 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0108] The surface layer may cover only the top surface of the subsurface structure. In other words, the subsurface structure may be located below or just below the surface layer, or the surface layer may be located above the subsurface structure. The sidewalls or edges of the subsurface structure may be exposed, i.e., not covered by the surface layer.

[0109] Alternatively, the sub-surface structure may be completely covered by the surface layer, i.e., both the top surface and the sidewalls or edges of the sub-surface structure may be covered by the surface layer.

[0110] Preferably, the porous subsurface structure has an average pore size of greater than 1 nm, or 2 nm, or 10 nm, or 20 nm, and / or an average pore size of less than 50 nm, or 60 nm, or 70 nm. The porous subsurface structure can be microporous, i.e., have an average pore size of less than 2 nm. Alternatively, the porous subsurface structure can be mesoporous, i.e., have an average pore size between 2 nm and 50 nm. Alternatively, the porous subsurface structure can be macroporous, i.e., have an average pore size of greater than 50 nm.

[0111] The semiconductor structure may include multiple stacked subsurface layers formed from III-nitride materials, where odd-numbered subsurface layers are porous with uniform porosity throughout the layer and even-numbered subsurface layers are non-porous, i.e., the subsurface layers may consist of multiple alternating porous / non-porous layers.

[0112] Particularly preferably, each of the odd-numbered subsurface layers may be porous and have the same porosity, while each of the even-numbered subsurface layers may be non-porous. The difference in porosity between adjacent layers leads to a difference in refractive index, such that the structure may act as a distributed Bragg reflector (DBR). By controlling the layer thickness and / or the porosity of the porous layers, the photonic stopband of the DBR can be tailored to reflect the desired wavelength of light. Particularly preferably, the thickness of each subsurface layer can be equal to one-quarter of the wavelength, or a multiple of one-quarter of the wavelength, to be reflected by the DBR.

[0113] The semiconductor structures of the present invention exhibit good electrical conductivity through the layers and offer the possibility to tune their spectral response by varying the thickness of the surface and subsurface layer(s). Thus, these structures may be usable as microcavity structures for electrically driven VCSELs and quantum light sources.

[0114] In a preferred embodiment, the at least two porous subsurface layers have different porosities.

[0115] It is particularly preferred that the semiconductor structure is not patterned with trenches, in other words the surface layer and subsurface structure(s) may be continuous or uninterrupted over their entire width.

[0116] Preferably, the upper, top, or outermost surface of the surface layer has a root-mean-square roughness of less than 10 nm, or less than 5 nm, or less than 2 nm, or less than 1 nm, or less than 0.5 nm over an area of ​​1 square micrometer. On the c-plane of GaN, for example, the root-mean-square roughness may be less than 1 nm over an area of ​​1 μm x 1 μm.

[0117] A low root-mean-square roughness is desirable to enable direct epitaxial overgrowth on semiconductor structures.

[0118] Preferably, additional III-nitride epitaxial layers and device structures can be directly deposited on the semiconductor structure after cleaning by techniques such as MBE, MOCVD, or HVPE. After this overgrowth, high-performance optical and electrical devices can be fabricated on the structure. Suitable devices include, for example, light-emitting diodes (LEDs), laser diodes (LDs), high electron mobility transistors (HEMTs), solar cells, and semiconductor-based sensor devices.

[0119] The top surface, outermost surface or upper surface of the surface layer is preferably not coated with an electrically insulating layer, in other words, the top surface of the surface layer may be exposed.

[0120] According to a fourth aspect of the present invention, there is provided a method for manufacturing a porous semiconductor device comprising: a porous subsurface structure of a first III-nitride material; and a surface layer of a second III-nitride material, the surface layer having a density of 1×10 14 cm -3 From 1×10 17 cm -3 and a surface layer covering the subsurface structure.

[0121] The surface layer preferably completely covers the subsurface structure. The subsurface structure may be completely covered by the surface layer, such that the top surface and all sidewalls or edges of the subsurface structure are covered by the surface layer.

[0122] The semiconductor structure may be a multi-layer semiconductor structure.

[0123] Using prior art etching methods that require an electrolyte to be in contact with the material to be etched, it would not be possible to form semiconductor devices in which the surface layer completely covers the subsurface structures.

[0124] The semiconductor structure is formed on an insulating base layer, e.g., a sapphire substrate, and the "bottom" or lower surface of the sub-surface structure (i.e., the surface facing away from the surface layer) is adjacent to either the base layer or a further sub-surface structure, and therefore the bottom surface of the sub-surface structure is not exposed to its surroundings.

[0125] Because no portion of the subsurface structure is exposed, it would not be possible to form such a semiconductor structure using prior art etching methods that require a portion of the material to be etched to be exposed to the electrolyte.

[0126] Preferably, the upper surface of the surface layer has a smallest lateral dimension of at least 1 μm, or 10 μm, or 50 μm, or 100 μm, or 500 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0127] Since the subsurface structure is completely covered by the surface layer, the lateral width of the subsurface structure will be smaller than the lateral width of the surface layer, but since the surface layer is extremely thin, the difference may be only a few nanometers or micrometers. Preferably, the subsurface structure is a continuous subsurface layer.

[0128] Particularly preferably, the subsurface structures have a minimum lateral dimension of at least 500 nm, 1 μm, 5 μm, 45 μm, 95 μm, or 1 mm, or at least 10 mm, or 5 cm, or 15 cm, or 20 cm.

[0129] In an exemplary preferred embodiment, a 20 μm×20 μm×20 μm cube of porous GaN is 1×10 14 cm -3 From 1×10 17 cm -3 The bottom surface of the cube is in contact with the sapphire substrate, while the other five faces of the cube are covered with a GaN surface layer, with a charge carrier density between 0.05 and 0.1.

[0130] Such a structure is 1×10 14 cm -3 From 1×10 17 cm -3 completely covered by a surface layer of GaN with a charge carrier density between 1 × 10 14 cm -3 A 20 μm×20 μm×20 μm cube of GaN having a charge carrier density greater than 100 μm can be formed according to the method of the present invention by etching the 20 μm×20 μm×20 μm cube of GaN. The method of the present invention allows the electrochemical etching to proceed through the surface layer of the III-nitride material to porosify the material inside the cube. This is not possible using prior art horizontal etching methods, because these methods require that the layer to be porosified be exposed to an electrolyte during etching.

[0131] Further features of the multilayer semiconductor structure according to the fourth aspect are as described above in relation to the third aspect of the invention.

[0132] According to a fifth aspect of the present invention there is provided the use of a multi-layer semiconductor structure as a substrate for the overgrowth of one or more semiconductor devices, the multi-layer semiconductor structure being as described in relation to the second, third or fourth aspect of the present invention above.

[0133] According to a sixth aspect of the present invention there is provided the use of a multilayer semiconductor structure as a distributed Bragg reflector (DBR), which may be as described in relation to the second, third or fourth aspects of the present invention above.

[0134] As described above, the method according to the first aspect of the present invention can be used to fabricate a multilayer semiconductor structure containing alternating layers of non-porous III-nitride material and porous III-nitride material. Differences in porosity between adjacent layers can lead to differences in refractive index, so that the structure can act as a distributed Bragg reflector (DBR). By controlling the layer thickness and the porosity of the porous layers, the photonic stop band of the DBR can be tuned to reflect a desired wavelength of light. Particularly preferably, the thickness of each subsurface layer can be equal to one-quarter of the wavelength, or a multiple of one-quarter of the wavelength, to be reflected by the DBR.

[0135] In particularly preferred embodiments, non-porous GaN / porous GaN DBRs can provide significant refractive index contrast, making them easy to fabricate without concerns about strain management, cracking, and dislocation generation, which are typical issues in DBR integration. For example, traditional fabrication of epitaxial III-nitride DBRs is extremely difficult in nonpolar orientations because there is no available lattice-matched counterpart to nonpolar GaN (c-plane GaN can be lattice-matched with low-index In0.18Al0.82N). However, the present invention can provide crack-free, high-reflectivity nonpolar III-nitride DBRs.

[0136] The multi-layer semiconductor structure of the present invention, when used as a DBR underneath a photonic device, can reflect downwardly directed light, thus significantly improving the light extraction efficiency of the photonic device.

[0137] According to a seventh aspect of the present invention there is provided a device incorporating or having attached a multi-layer semiconductor structure, which may be as described in relation to the second and third aspects of the present invention above.

[0138] Exemplary devices include vertical-cavity surface-emitting lasers (VCSELs) or other quantum light sources, where such multilayer structures may form microcavity structures. Additional devices that may incorporate such multilayer semiconductor structures include LEDs and micropillar cavity structures for single-photon sources.

[0139] According to an eighth aspect of the present invention, 1×10 14 cm -3 From 1×10 17 cm -3 5×10 below the surface layer of the second GaN material, which has a charge carrier density between 17 cm -3 A method is provided for porosifying GaN in a semiconductor structure including a subsurface structure formed from a first GaN material having a charge carrier density greater than 0. The method includes exposing the surface layer to an electrolyte and applying a potential difference between the subsurface structure and the electrolyte, such that the subsurface structure is porosified by electrochemical etching, while the surface layer is not porosified.

[0140] Further features of the method are as described above in relation to the first aspect of the invention. [Brief explanation of the drawings]

[0141] Specific embodiments of the present invention will now be described with reference to the drawings in which: [Figure 1] Figure 1 shows a schematic diagram of the electrochemical etching experimental setup. [Figure 2A] FIG. 2A shows a schematic diagram of a multi-layer semiconductor structure forming a distributed Bragg reflector (DBR), in accordance with an aspect of the present invention. [Figure 2B] FIG. 2B shows a cross-sectional scanning electron microscope (SEM) image of the multi-layer semiconductor structure of FIG. 2A. [Figure 3A]FIG. 3A shows a top-view Nomarski optical image of the etched sample of FIG. 2B. [Figure 3B] FIG. 3B shows an atomic force microscopy (AFM) image of the surface layer of the unetched area of ​​the sample shown in FIG. 2B. [Figure 3C] FIG. 3C shows an atomic force microscope (AFM) image of the surface layer of the etched area of ​​the sample shown in FIG. 2B. [Figure 4] FIG. 4 shows the measured reflectance spectrum of a GaN DBR structure according to a preferred embodiment of the present invention. [Figure 5A] FIG. 5A shows an AFM image of the top surface of an etched semiconductor wafer forming a DBR. [Figure 5B] FIG. 5B shows an AFM image of the top surface of an unetched GaN epitaxial layer. [Figure 6] FIG. 6 is a photograph of an etched 2-inch semiconductor wafer forming a DBR according to a preferred embodiment of the present invention. [Figure 7A] FIG. 7A shows photographs of various GaN DBR structures according to preferred embodiments of the present invention. [Figure 7B] FIG. 7B shows the measured reflectance spectrum of the DBR structure of FIG. 7A. [Figure 8A] FIG. 8A shows a schematic diagram of a GaN-based LED overgrown on a GaN DBR substrate according to a preferred embodiment of the present invention. [Figure 8B] FIG. 8B shows a cross-sectional SEM image of the overgrown LED structure of FIG. 8A. [Figure 8C] FIG. 8C shows a photograph of a GaN LED structure without the underlying porous GaN DBR. [Figure 8D] FIG. 8D shows a photograph of a GaN LED structure formed on top of a porous GaN DBR according to a preferred embodiment of the present invention. [Figure 8E] FIG. 8E shows the room temperature electroluminescence (EL) "internal quantum efficiency" (IQE) of LEDs with and without a porous GaN DBR as a pseudo-substrate. [Figure 9A] FIG. 9A shows a schematic diagram of a multi-layer semiconductor structure including several III-nitride materials, according to a preferred embodiment of the present invention. [Figure 9B] FIG. 9B shows an SEM image of the multi-layer semiconductor structure of FIG. 9A. [Figure 9C] FIG. 9C shows a magnified SEM image of the multilayer semiconductor structure of FIG. 9B. DETAILED DESCRIPTION OF THE INVENTION

[0142] Figure 1 shows a schematic diagram of an electrochemical (EC) experimental setup configuration that can be used in the method of the present invention. As shown in Figure 1, the experimental setup consists of a two-electrode electrochemical cell 100 with a sample 110 connected as the anode and a platinum foil 120 connected as the cathode. The platinum cathode and at least a portion of the surface layer of the sample are exposed to an electrolyte 130 by immersion in the electrolyte. A constant current DC power supply 140 is connected between the anode and cathode, and an ammeter 150 is used to monitor and record the etching current flowing through the circuit.

[0143] Unless otherwise noted, the EC etching experiments described herein were performed at room temperature using the semiconductor structure as the anode and platinum foil as the counter electrode (cathode). Oxalic acid with a concentration of 0.25 M was used as the electrolyte. The etching process was carried out in constant voltage mode controlled by a Keithley 2400 source meter. After etching, the samples were rinsed with deionized water and blown dry with N2.

[0144] As discussed above in the Summary of the Invention, those skilled in the art will understand that the term "undoped" is relatively imprecise in semiconductor technology. Virtually all semiconductor materials contain inherent impurities, which can be thought of as "dopant" atoms. Different methods of semiconductor growth can result in different levels of impurities and, therefore, different inherent charge carrier concentrations.

[0145] Thus, semiconductor materials referred to in the prior art as "undoped" may have high impurity levels, so that they have impurity levels of 1×10 17 cm -3 It is possible for the charge carrier density to exceed .

[0146] In recognition of this, the present inventors prefer to use the term "non-intentionally-doped" (NID) to refer to semiconductor materials that have been made without intentional doping. Impurity levels in semiconductor materials will naturally vary depending on factors including the method in which they are formed, the environment in which they are formed, and the purity of the reactants used to form the semiconductor material.

[0147] In this application, the term "unintentionally doped" (NID) refers to a 14 cm -3 From 1×10 17 cm -3 It should be understood to refer to a semiconductor material that has been carefully grown to be as pure as possible, and which has been measured to have a charge carrier density between 0.1 and 0.2.

[0148] 5×10 17 cm -3 Semiconductor materials that are intentionally doped with n-type dopants to obtain charge carrier densities above 0.1 are sometimes referred to as "n+" semiconductor materials.

[0149] Figure 2A shows a schematic diagram of the epitaxial nonpolar sample structure, consisting of alternating layers of non-intentionally doped GaN (NID-GaN) and heavily doped n-type GaN (n+-GaN). The NID-GaN layers are 1×10 17 cm -3 The n+-GaN layer has a charge carrier density of less than 2.3×10 19 cm -3 Each of the alternating n+-GaN / n+-GaN layers has a thickness of approximately 136 nm.

[0150] The sample includes a top surface layer of NID-GaN and 10 pairs of alternating NID-GaN / n+-GaN layers, which are formed on a sapphire substrate and underlying base layers of lightly doped n-type GaN (n-GaN) and NID-GaN. The n-GaN layer is 2 μm thick and is present due to the uniform distribution of anodization bias across the sample.

[0151] Samples were grown by metalorganic vapor phase epitaxy (MOVPE) on r-plane sapphire substrates in a 6 × 2 inch Thomas Swan close-coupled showerhead reactor. Trimethylgallium and ammonia were used as precursors, hydrogen as carrier gas, and silane for n-type doping. First, approximately 4 × 10 9 cm -2 and a nominal dislocation density of about 5 × 10 5 cm -1 We grew 4 μm-thick a-plane GaN pseudosubstrates with a basal-plane stacking fault density of 100 μm. Here, we used a single SiNx interlayer for defect reduction. We then grew another 500 nm undoped GaN layer, followed by 10 pairs of alternating n+-GaN and n+-GaN layers.

[0152] The sample in Figure 2A was electrically contacted by soldering an indium wire to the edge of the sample. A portion of the sample measuring approximately 1 cm x 1 cm was then immersed in the electrolyte. Using the experimental setup shown in Figure 1, the EC etching process was performed on the sample in constant voltage mode with a DC bias of 6 V and controlled by monitoring and recording the etching current signal at room temperature without UV illumination.

[0153] The EC porosification process begins with the oxidation of alternating n+-GaN layers by localized injection of holes upon application of a positive anodic bias, and localized dissolution of the oxide layers in an acid-based electrolyte leads to the formation of a mesoporous structure. The end of the anodization process is typically reached after approximately 30 minutes when the etching current drops to the baseline level, indicating that all of the n+-GaN layers have been etched and converted into mesoporous GaN layers.

[0154] The cross-sectional scanning electron microscope (SEM) image in Figure 2B shows the morphology of the porous DBR structure 200. The cross section in Figure 2B was taken from a post-etched cleaved edge, far removed from the original sample edge. This confirms that the porosification process proceeded quite uniformly across the entire sample area immersed in the etching solution. This also confirms that the morphology of the etched layer is indeed mesoporous, with an average pore size of approximately 30 nm. Figure 2B shows that the n+-GaN layers remain largely intact during the EC etching and are not themselves porosified. Only the n+-GaN layer is selectively etched and converted into a mesoporous layer of mesoporous GaN (MP-GaN).

[0155] The 1 cm × 1 cm sample is significantly larger than samples porosified by prior art horizontal etching, because the horizontal etch would not be able to penetrate horizontally to the center of such a large sample without regular trenches at the sample surface. Furthermore, the etching time of 30 minutes would be insufficient for the horizontal etch to proceed significantly into the bulk material of the sample. Thus, the porous cross section in Figure 2B, taken far from the sample edge, is evidence that the n+-GaN layer is etched through the surface layer of the N+-GaN, rather than horizontally from the sample edge.

[0156] Figure 3A shows a top-view Nomarski optical image of the etched sample, in which a boundary (indicated by the white arrow) corresponding to the location of the sample immersed in the EC etching solution can be seen. The optical contrast between regions with and without porous structures arises due to the altered refractive index of the porosified layer, leading to significantly higher reflectance in the etched regions. The sharp boundary between the etched and unetched regions provides evidence that etching through the surface layer is occurring, as uniform reflectance (and therefore porosity) is achieved far from the edge of the structure.

[0157] To assess possible etching damage to the top surface layer of the NID-GaN, atomic force microscopy (AFM) images were taken from the nonporous and porous regions and are shown in Figures 3B and 3C, respectively. Some dirt / small particles present in the porous region may be associated with EC etching products, etching chemicals, and / or contaminants in the sample cleaning process. Apart from these, no changes in the surface morphology were observed; the root-mean-square roughness (RRMS) of the top GaN surface was on the order of 1 nm measured over a 1 μm × 1 μm area, and was similar in both the etched and unetched regions. Therefore, it appears that subsurface EC porosification did not damage the surface of the GaN surface layer, and the RRMS of the post-etch sample was low enough to support further semiconductor overgrowth.

[0158] Such porous DBRs can therefore be used as bottom mirror templates for the regrowth of other heterostructures or for the deposition of high quality dielectric DBRs, for example, to form planar microcavities.

[0159] The porous DBR structure illustrated in Figures 2B-3C is formed purely by epitaxial growth of alternating n+-GaN / n+-GaN layers followed by EC porosification. By using the method of the present invention, there is no need to passivate the sample surface with SiO2 or to pattern the sample with regular trenches. Also, there is no need to use UV illumination.

[0160] The reflectance spectrum of the etched GaN / MP-GaN DBR was measured using a microreflectance setup with room light and normalized to a commercial silver mirror with a spot size of approximately 1 μm. Figure 4 shows the measured reflectance spectrum of the GaN / mesoporous-GaN DBR structure, with a peak reflectance centered at approximately 564 nm and a stop band with a full width at half maximum of 91 nm.

[0161] Peak reflectances greater than 96% have been achieved with nonpolar GaN / MP-GaN DBR structures, with remarkably large spectral widths greater than 80 nm. We note that the measured peak reflectance is slightly lower than the simulated value, which may be due to local inhomogeneities in the mesoporous GaN layer and etching paths through the layer, which lead to slight porosity in the NID-GaN. Nevertheless, to our knowledge, this is the highest reported peak reflectance from a nonpolar III-nitride DBR structure, and represents a more than two-fold increase in stop band width compared to previously reported structures. This is due to the fact that a significant refractive index contrast can be achieved using mesoporous GaN layers without introducing significant lattice mismatch (via crack formation and dislocation generation) that would lead to significant strain and degradation of structural quality. In contrast, the more common method for fabricating nitride DBRs, the use of Al-containing epitaxial layers on GaN, such as Al(Ga)N and InAlN, to achieve refractive index contrast, necessarily leads to the introduction of significant strain in at least one in-plane direction for nonpolar structures.

[0162] In another experiment, an equivalent DBR structure was epitaxially grown on a circular semiconductor wafer with a diameter of 2 inches (5.08 cm). A portion of the wafer was then immersed in an electrolyte and etched as described above in connection with Figures 1-2B. The etching time for a typical 2-inch wafer at 6 V was less than 6 hours.

[0163] Wafer-scale fabrication of mesoporous GaN DBRs has been found to correlate with threading dislocation density. The inventors believe that these threading dislocations act as etching paths through the layers, facilitating subsurface etching through the surface layer and downward through the multilayer structure. Only complete threading dislocations are expected to provide etching paths through the layers.

[0164] To achieve 2-inch wafer-scale formation of mesoporous GaN DBRs, the surface and subsurface layers must be at least 1×10 4 cm -2 It may be necessary to have a minimum threading dislocation density of 0.15 or less.

[0165] Due to the presence of threading dislocations, the EC process initiated from the top NID-GaN surface appears to proceed through the threading dislocation sites into the underlying multilayer structure. 17 cm -3 Upon reaching the subsurface layer with a charge carrier density above , the etching proceeds outward from the threading dislocations into the n+-GaN layer due to the conductivity selective nature of the EC process.

[0166] Figures 5A and 5B show AFM images of the top NID-GaN surface of the completed wafer-scale DBR sample and the standard as-grown GaN epitaxial layer. The surface morphology of the porous DBR is nearly identical to the as-grown GaN epitaxial layer. The surface roughness (root-mean-square roughness over a 5 μm × 5 μm scan) is very similar and can be maintained at approximately 0.4 nm.

[0167] Figure 6 is a photograph of an as-etched 2-inch semiconductor wafer 600 under room lighting, showing the reflection of a card with a printed logo. While the area near the wafer flat is clear and unetched, the strong reflection in the etched DBR area demonstrates the uniformity of the EC porosification process and the realization of a highly reflective nonpolar GaN / MP-GaN DBR at the wafer scale. Given that uniform porosification has occurred across the entire 2-inch wafer, it is again confirmed that, in addition to any lateral etching occurring at the wafer edge, the subsurface layer of n+-GaN is electrochemically etched downward through the surface layer of NID-GaN and all intermediate layers of NID-GaN.

[0168] Although the local refractive index of the NID-GaN layer can be modified by etching through the layer, the measured reflectivity values ​​are very close to the theoretical values, and the density of etching paths through such layers is sufficiently low (approximately 2 × 10 9 cm -2 ), the overall reflectivity at wafer scale (approximately 5 cm diameter) is expected to be only slightly affected.

[0169] Most materials are not affected by these considerations as they exhibit sufficient reflectivity to allow the fabrication of devices such as LEDs and micropillar cavity structures for single photon sources with reasonable yields.

[0170] Improved GaN pseudosubstrates with significantly lower densities of perfect dislocations still exhibit porosification, even when typical dislocation spacing is a few microns or larger, further reducing the effectiveness of vertical etching paths even though wafer-scale fabrication is still possible.

[0171] Tunability of the DBR can be easily achieved by varying the thickness of the NID-GaN and n+-GaN layers. Figures 7A and 7B show photographs and measured reflectance spectra of various GaN / porous GaN DBR structures under room lighting. By simply varying the thickness of the NID-GaN and n+-GaN epitaxial layers, a wide, tunable stop band with high reflectivity (>96%) across the entire visible spectrum is demonstrated. Due to the large refractive index contrast between the GaN and porous GaN layers, the stop band width remains extremely wide (>80 nm).

[0172] Particularly preferably, the porous GaN structures of the present invention may be usable as substrates or "pseudo-substrates" for further overgrowth or deposition of additional semiconductor materials. In other words, additional layers of III-nitride or other semiconductor materials can be advantageously deposited or overgrown on the porous semiconductor structures of the present invention to form various devices. The excellent reflective properties demonstrated by the above examples of DBRs make DBRs formed according to the present invention promising as pseudo-substrates for the overgrowth of optoelectronic devices such as LEDs, for example.

[0173] Particularly advantageously, the present method allows for the preparation of porosified semiconductor structures having "epi-ready" surfaces, i.e., porosified semiconductor structures having an upper surface with sufficiently low roughness that additional semiconductor layers can be epitaxially grown directly on the structure.

[0174] For example, porous GaN-based DBR pseudo-substrates according to embodiments of the present invention can be used for the fabrication of III-nitride LEDs, lasers, single photon sources, and for the formation of hybrid cavity structures and devices.

[0175] 8A shows a GaN-based LED structure 800 on a NID-GaN / MP-GaN DBR 850, as described above in connection with FIGS. 2-7. After formation of the DBR according to the above methods, additional semiconductor layers are epitaxially grown on the DBR according to known epitaxial techniques to form a light-emitting diode (LED). The DBR thus acts as a pseudo-substrate for the overgrowth of the LED.

[0176] The overgrown LED structure comprises a simple pin structure containing five periods of 2.5 nm InGaN quantum wells separated by 7.5 nm thick GaN barriers. The bottom of the active region is 3 × 10 18 cm -3The active region is covered at the top by a 500 nm thick layer of Si-doped n-type GaN with a charge carrier density of 1000 nm, and the top of the active region is covered by a 300 nm thick layer of Mg-doped p-type GaN.

[0177] Electrically implanted LED devices were fabricated using chlorine-based inductively coupled plasma etching to form the mesa: a Ti / Al / Ti / Au metal stack annealed in N2 served as the n-type contact, and a thin Ni / Au layer annealed in a N2 / O2 mixture served as a semitransparent current spreading layer on top of the p-type GaN layer and below the Ti / Au p-type contact.

[0178] 8B shows a cross-sectional SEM image of an LED structure 800 overgrown on a porous GaN DBR pseudo-substrate 850. The pore morphology of the DBR is preserved in the overgrowth process.

[0179] Figure 8C shows a photograph of a similar LED structure 860 without the underlying porous GaN DBR, while Figure 8D shows the same LED structure 800 formed on a porous GaN DBR 850 as described above. By comparison, the LED overgrown on the porous GaN DBR is significantly brighter than the LED without the GaN DBR as a pseudo-substrate. The intensity of the optical emission is found to be highly uniform across the device in Figure 8D, hindered only by dislocations and GaN material non-uniformities, which may be due to improper cleaning of the DBR before overgrowth.

[0180] Figure 8E shows the room-temperature electroluminescence (EL) "internal quantum efficiency" (IQE) as a function of current density for LEDs with and without a porous GaN DBR as a pseudo-substrate. The LED fabricated on a non-porous DBR exhibits a low IQE that decreases at low current densities, while the IQE of the LED / porous GaN DBR exhibits a significantly higher peak efficiency and begins to decrease at current densities more than an order of magnitude higher.

[0181] 9A is a schematic diagram of a multi-layer semiconductor structure forming a GaN HEMT transistor structure, according to a preferred embodiment of the present invention, which structure includes several III-nitride materials.

[0182] The structure shown in FIG. 9A was epitaxially grown by MOVPE on a 2-inch sapphire wafer 910 according to known methods. First, a 1×10 14 cm -3 From 1×10 17 cm -3 A layer of NiD-GaN with a charge carrier density between 5 × 10 and 5 × 10 was deposited on a sapphire substrate. 17 cm -3 A 5 μm thick layer B of GaN was deposited with a charge carrier density of more than 5×10 17 cm -3 A 250 nm thick layer C of GaN with a charge carrier density of more than 1 × 10. The charge carrier density of layer C was made higher than that of layer B by intentionally doping layer C to a higher degree. 14 cm -3 From 1×10 17 cm -3 A 500 nm thick layer D of NID-GaN, having a charge carrier density between 0.05 and 0.1, was deposited on top of layer C. A 1 nm thick layer E of NID-AlN was deposited on top of layer D, followed by a 25 nm thick layer F of NID-Al0.25GaN and a 2 nm thick surface layer G of NID-GaN.

[0183] Electrical contacts were made to the sides of the multilayer structure, and the wafer was immersed in an electrolyte and etched as described above in connection with FIG.

[0184] 9B and 9C are SEM images of a cross section of the wafer after etching. Taking the cross section far away from the edge of the wafer demonstrates that porosification occurs by etching through the surface layer, rather than by horizontal etching from the edge of the wafer. Due to the limitations of the prior art methods discussed above, horizontal etching of the entire 2-inch wafer is not possible.

[0185] As can be seen from Figures 9B and 9C, layers E, F, and G and NID-GaN layer D have a charge carrier density of 1 x 10 14 cm -3 From 1×10 17 cm -3 However, the lower GaN layer C is highly porous due to its high charge carrier density, and relatively large pores are distributed throughout the layer. GaN layer B was also 5×10 before etching. 17 cm -3 Layer B was porous because it had a charge carrier density greater than 1000 Å. However, the pores formed in Layer B were much smaller than those in Layer C. This is due to the lower charge carrier density of Layer B.

[0186] 9B shows that electrochemical etching has occurred through the unintentionally doped surface layer as well as the AlGaN and AlN NID layers. It is therefore clear that the method of the present invention can porosify multiple subsurface layers at various locations in a multilayer semiconductor structure, resulting in different porosities based on the initial charge carrier density of the III-nitride material.

Claims

1. 1. A semiconductor structure comprising: a porous subsurface structure of the first Group III nitride material; a non-porous surface layer of a second Group III nitride material, the surface layer having a thickness of 1×10 １４ cm －３ From 1 x 10 １７ cm －３ and a surface layer having a charge carrier density between Including, A semiconductor structure, wherein the subsurface structure has uniform porosity throughout the structure, the lateral width of the surface layer is greater than 550 μm at its narrowest point, and the lateral width of the subsurface structure is greater than 550 μm at its narrowest point.

2. 10. The structure of claim 1, wherein the lateral width of the surface layer at its narrowest point is at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

3. 3. The structure of claim 1 or 2, wherein the surface layer and subsurface structure comprise a Group III nitride material selected from the group consisting of GaN, AlGaN, InGaN, and AlInGaN.

4. The threading dislocation density in both the surface layer and the subsurface structure is at least 1×10 ４ cm －２ , 1×10 ５ cm －２ , 1×10 ６ cm －２ , 1×10 ７ cm －２ , or 1 x 10 ８ cm －２ and / or 1×10 ９ cm －２ , or 1 x 10 １０ cm －２ 4. The structure of claim 1, wherein the .lambda.

5. 5. The structure of claim 1, wherein the thickness of the surface layer is at least 1 nm, or 10 nm, or 100 nm, and / or less than 1 μm, or 5 μm, or 10 μm.

6. 6. The structure of any one of claims 1 to 5, wherein the porous subsurface structure has an average pore size of more than 1 nm, or 2 nm, or 10 nm, or 20 nm, and / or an average pore size of less than 50 nm, or 60 nm, or 70 nm.

7. 7. The structure of any of claims 1 to 6, comprising a plurality of subsurface layers formed from Group III-nitride materials in the form of a stack of layers, wherein the odd-numbered subsurface layers (counting away from the surface layers) are porous and have a uniform porosity throughout each layer, and the even-numbered subsurface layers are non-porous.

8. 8. The structure of claim 7, wherein each odd-numbered subsurface layer has the same porosity and each even-numbered layer is non-porous, such that the structure acts as a distributed Bragg reflector (DBR).

9. 9. The structure of claim 1, wherein the semiconductor structure is not patterned with trenches.

10. 10. The structure of any of claims 1 to 9, wherein the semiconductor structure is not pre-patterned with trenches separated by less than 1 cm, or 5 mm, or 1 mm, or 600 μm.

11. 11. The structure of any of claims 1 to 10, wherein the outermost surface of the surface layer has a root mean square roughness of less than 10 nm, or less than 5 nm, or less than 2 nm, or less than 1 nm, or less than 0.5 nm over an area greater than 1 square micrometer.

12. 12. The structure of claim 1, wherein the surface layer is not coated with an electrically insulating layer.

13. Use of a semiconductor structure according to any of claims 1 to 12 as a substrate for the overgrowth of one or more semiconductor devices.

14. 14. Use of the semiconductor structure according to claim 13, wherein the semiconductor device is a laser or an LED.

15. 15. Use of a semiconductor structure according to any of claims 13 or 14 as a mirror or a distributed Bragg reflector (DBR).

16. A device incorporating or having attached thereto a semiconductor structure according to any one of claims 1 to 12.

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