Semiconductor device

Abstract

To provide a semiconductor device 11 capable of reducing a parasitic capacitance without impairing various characteristics including an on-resistance value and a breakdown-voltage value.SOLUTION: A semiconductor device 11 includes: a field oxide film 57 electrically insulating between a semiconductor region including an n-type semiconductor layer 51, an n-type high-concentration semiconductor layer 53, a p-type semiconductor layer 55 and an n-type high-concentration semiconductor layer 54, and an electrode region including a drain electrode 69 and a source electrode 65; and a gate electrode 61 provided on a surface side of the field oxide film 57 so as to overlap a pn junction 56 consisting of a combination of the n-type high-concentration semiconductor layer 54 and the p-type semiconductor layer 55 and a combination of the n-type semiconductor layer 51 and the p-type semiconductor layer 55. A comb-shaped structure 63 is provided at an end, of the gate electrode 61, toward the drain electrode 69, in a first region 41 where the gate electrode 61 and the n-type semiconductor layer 51 overlap in a depth direction.SELECTED DRAWING: Figure 5A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses an invention of a semiconductor device related to a MOSFET (metal-oxide-semiconductor field-effect transistor).

[0003] The semiconductor device (MOSFET) disclosed in Patent Document 1 (see Abstract and FIG. 9) comprises a field oxide film selectively provided on the surface portion of a semiconductor region present on a semiconductor substrate, a p-type drain region provided near the field oxide film and having a p-type power supply region, a p-type source region provided near the field oxide film and having a p-type power supply region, and a gate electrode provided across the field oxide film and facing a well region, and carrier traps parasitically present inside the field oxide film from below the gate electrode to the source region, particularly near the interface with silicon, are terminated by ions.

[0004] According to the semiconductor device disclosed in Patent Document 1, in a Field-MOSFET in which a field oxide film is configured as a gate insulating film, it is possible to improve the phenomenon of a decrease in breakdown voltage at a high gate voltage slew rate and the phenomenon of NBTI (Negative Bias Temperature Instability) degradation caused by carrier trapping in the oxide film. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-165293 Summary of the Invention [Problem to be solved by the invention]

[0006] For example, in a semiconductor device (MOSFET) such as that shown in Patent Document 1, parasitic capacitances such as gate-drain parasitic capacitance and drain-source parasitic capacitance occur due to their structure. When such a semiconductor device is used as, for example, an analog switch (multiplexer / demultiplexer) for an ultrasound diagnostic device, the parasitic capacitances cause signal leakage. This leads to attenuation of ultrasound energy due to attenuation of signal energy transmitted from the signal source of the ultrasound diagnostic device to the ultrasound transducer, and to deterioration of the quality of tomographic images due to distortion of the ultrasound signal. As a result, there is a problem that the performance of the ultrasound diagnostic device is adversely affected.

[0007] The present invention has been made in view of the above circumstances, and has an object to provide a semiconductor device capable of reducing parasitic capacitance without impairing various characteristics including on-resistance and breakdown voltage. [Means for solving the problem]

[0008] In order to solve the above problems, the semiconductor device according to the present invention comprises: a first conductivity type semiconductor layer (51); a first conductivity type high concentration semiconductor layer (53) associated with a drain region formed on the surface side of the first conductivity type semiconductor layer (51); a second conductivity type semiconductor layer (55) associated with a source region formed on the surface side of the first conductivity type semiconductor layer (51) at a predetermined distance in the longitudinal direction from the first conductivity type high concentration semiconductor layer (53) associated with the drain region; a first conductivity type high concentration semiconductor layer (54) relating to the source region, which is provided so that a part of the first conductivity type high concentration semiconductor layer (54) is buried in the second conductivity type semiconductor layer (55) relating to the source region; a drain electrode (69) provided in contact with the front side surface of the first conductivity type high concentration semiconductor layer (53) relating to the drain region; a source electrode (65) provided in contact with the front and side surfaces of the first conductivity type high concentration semiconductor layer (54) and the second conductivity type semiconductor layer (55) relating to the source region; a field oxide film (57) provided to electrically insulate a semiconductor region including the first conductivity type semiconductor layer (51), the first conductivity type high concentration semiconductor layer (53) associated with the drain region, the second conductivity type semiconductor layer (55) associated with the source region, and the first conductivity type high concentration semiconductor layer (54) associated with the source region from one another, and an electrode region including the drain electrode (69) and the source electrode (65); a gate electrode (61) provided on the surface side of the field oxide film (57) so as to overlap the first conductivity type high concentration semiconductor layer (54) and the second conductivity type semiconductor layer (55) related to the source region, and a pn junction (56) formed by a combination of the first conductivity type semiconductor layer (51) and the second conductivity type semiconductor layer (55); an insulating layer (59) provided so as to surround each of the drain electrode (69), the source electrode (65), and the gate electrode (61), In a first region (41) where the gate electrode (61) and the first conductivity type semiconductor layer (51) overlap in the depth direction, a comb-shaped structure (63) is provided at an end of the gate electrode (61) facing the drain electrode (69). This is its most important feature.

[0009] According to the present invention, it is possible to provide a semiconductor device capable of reducing parasitic capacitance without impairing various characteristics including on-resistance and breakdown voltage. Problems, configurations, and effects other than those described above will be described in detail in the following embodiments. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a conceptual diagram showing an overview of an analog switch IC for an ultrasound diagnostic device. [Figure 2] FIG. 2 is a circuit diagram showing the internal configuration of an analog switch for one channel. [Figure 3] FIG. 2 is an equivalent circuit diagram of an analog switch in an off state. [Figure 4]FIG. 10 is a cross-sectional view schematically illustrating a general configuration of a semiconductor device according to a comparative example. [Figure 5A] 1 is a plan view showing an internal structure of a semiconductor device according to an embodiment of the present invention, focusing on a gate electrode and its surroundings; [Figure 5B] 1 is a plan view showing the internal structure of a semiconductor device according to an embodiment of the present invention, focusing on the periphery of a source electrode and a drain electrode; [Figure 6A] FIG. 6A is a cross-sectional view taken along line 6A-6A shown in FIG. 5A. [Figure 6B] FIG. 6B is a cross-sectional view taken along line 6B-6B shown in FIG. 5A. [Figure 6C] FIG. 6C is a cross-sectional view taken along line 6C-6C shown in FIG. 5B. DETAILED DESCRIPTION OF THE INVENTION

[0011] Semiconductor devices according to embodiments of the present invention will be described in detail with reference to the appropriate drawings.

[0012] In the description of the semiconductor device according to the embodiment of the present invention, components having the same or similar functions are denoted by common reference numerals, and redundant descriptions thereof will be omitted as a general rule. For the sake of convenience, the size and shape of components may be exaggerated or distorted to show a schematic representation.

[0013] In this specification, n + , n, n - , and p + , p, p - Each notation indicates the relative level of impurity concentration for each conductivity type. + has a relatively high n-type impurity concentration compared to n, - indicates that the n-type impurity concentration is relatively low compared to n. + has a relatively high p-type impurity concentration compared to p, - indicates that the p-type impurity concentration is relatively low compared to p. + type, n - The type is simply n-type and p + type, p -The type is sometimes abbreviated as simply p-type.

[0014] Furthermore, in this specification, for the convenience of expressing the positional relationship between a plurality of elements, the following terms are defined. That is, the side where the gate electrode 61, source electrode 65, and drain electrode 69 (see FIG. 4, for example) exist (upper side on the paper) is called the "front" and the opposite side (lower side on the paper) is called the "back". The relative direction between the front and back is called the “depth direction.” “Deep” means the state toward the back in the depth direction, and “depth” means the degree (distance) toward the back in the depth direction. The direction perpendicular to the depth direction and extending from left to right on the paper surface is called the "length direction." The direction perpendicular to the depth direction and perpendicular to the paper surface is called the "width direction."

[0015] Hereinafter, the semiconductor device 11 according to the embodiment of the present invention will be described by taking as an example an aspect in which the first conductivity type is n-type and the second conductivity type is p-type.

[0016] [Outline of Ultrasound Diagnostic Device 12 to which Semiconductor Device 11 According to an Embodiment of the Present Invention is Applied] First, an overview of an ultrasonic diagnostic device 12 to which a semiconductor device 10 according to a comparative example and a semiconductor device 11 according to an embodiment of the present invention (described in detail later) are applied will be described with reference to FIGS. Fig. 1 is a conceptual diagram showing an overview of an analog switch IC for an ultrasound diagnostic device 12. Fig. 2 is a circuit diagram showing the internal configuration of an analog switch for one channel. Fig. 3 is an equivalent circuit diagram of the analog switch in the off state.

[0017] As shown in FIG. 1, the ultrasound diagnostic device 12 transmits ultrasound waves while applying an ultrasound probe 109, which is made up of an array of ultrasound transducers 107, to a subject, and receives the reflected waves. The ultrasound diagnostic device 12 then performs appropriate image processing on the received reflected waves to obtain a tomographic image of the subject.

[0018] In the electronic scanning type ultrasonic diagnostic device 12, a high-voltage analog switch IC (multiplexer / demultiplexer) 101 is used to transmit a high-voltage, high-frequency pulse signal from a signal source 103 to each of a plurality of ultrasonic transducers 107 by sequentially switching a plurality of analog switches 105.

[0019] The analog switch IC 101 is configured by integrating multiple analog switches 105, which are turned on / off in response to external control signals, on a single chip. In the analog switch IC 101 for the ultrasound diagnostic device 12, multiple analog switches 105 are connected in parallel to one signal source 103, and one ultrasonic transducer 107 is connected to each of the multiple analog switches 105 in a one-to-one relationship.

[0020] Ultrasonic vibrator 107 converts a high voltage (for example, about ±100 V) and high frequency (for example, about 1 to 20 MHz) pulse signal from signal source 103 into vibration by the piezoelectric effect, thereby generating (oscillating) ultrasonic waves.

[0021] The analog switch IC101 for the ultrasonic diagnostic device 12 operates in accordance with an external control signal to turn on only the analog switch 105 connected to the ultrasonic transducer that is to be oscillated, while turning off the analog switch 105 connected to the ultrasonic transducer that is not to be oscillated. As a result, the analog switch IC 101 for the ultrasonic diagnostic device 12 plays a role in emitting ultrasonic waves by providing a pulse signal from the signal source 103 only to the ultrasonic transducer that is the oscillation target.

[0022] 2, the high-voltage analog switch 105 is configured to include an analog switch section 111, a level shift circuit 113, and a logic circuit 115. The analog switch section 111 is connected to a signal source 103 and an ultrasonic vibrator 107 via a pair of switch terminals 117 and 118, respectively. The level shift circuit 113 is connected to positive and negative DC power supplies 121 and 123 via a pair of power supply terminals 119 and 120, respectively. The logic circuit 115 is connected to a positive DC power supply 127 via a power supply terminal 125, and to an external control signal source (not shown) via an input terminal 129.

[0023] The analog switch section 111 is configured to include first and second N-channel MOSFETs 21 and 23 connected in series with a common source electrode, and a third N-channel MOSFET 25 having a drain electrode connected to the source electrodes of the first and second N-channel MOSFETs 21 and 23 and a source electrode connected to a negative DC power supply 123 via a power supply terminal 120.

[0024] The drain electrode of the first N-channel MOSFET 21 is connected to the signal source 103 via a switch terminal 117 , and the drain electrode of the second N-channel MOSFET 23 is connected to the ultrasonic transducer 107 via a switch terminal 118 . The gate electrodes of the first and second N-channel MOSFETs 21 and 23 are connected to the level shift circuit 113 via a common signal line 27, and the gate electrode of the third N-channel MOSFET 25 is connected to the level shift circuit 113 via a signal line 29.

[0025] When the analog switch 105 is in the on state, a positive DC voltage related to the positive DC power supply 121 is applied to the gate electrodes of the first and second N-channel MOSFETs 21 and 23 via a common signal line 27, a level shift circuit 113, etc., while a negative DC voltage related to the negative DC power supply 123 is applied to the gate electrode of the third N-channel MOSFET 25 via a signal line 29, a level shift circuit 113, etc.

[0026] At this time, the first and second N-channel MOSFETs 21 and 23 are turned on, while the third N-channel MOSFET 25 is turned off. This creates conduction between the pair of switch terminals 117 and 118 via the series-connected circuit of the first and second N-channel MOSFETs 21 and 23. As a result, the pulse signal from the signal source 103 is transmitted to the ultrasonic transducer 107 via the series-connected circuit.

[0027] When the analog switch 105 is in the off state, a negative DC voltage related to the negative DC power supply 123 is applied to the gate electrodes of the first and second N-channel MOSFETs 21 and 23 via a common signal line 27, a level shift circuit 113, etc., while a positive DC voltage related to the positive DC power supply 121 is applied to the gate electrode of the third N-channel MOSFET 25 via a signal line 29, a level shift circuit 113, etc.

[0028] At this time, the first and second N-channel MOSFETs 21 and 23 are turned off, while the third N-channel MOSFET 25 is turned on. Then, a negative DC voltage related to the negative DC power supply 123 is applied to the common source electrode of the first and second N-channel MOSFETs 21 and 23 via the third N-channel MOSFET 25 and the power supply terminal 120, respectively. This interrupts the series connection circuit of the first and second N-channel MOSFETs 21 and 23 interposed between the pair of switch terminals 117 and 118. As a result, in principle (as will be described next), the pulse signal from the signal source 103 is not transmitted to the ultrasonic transducer 107.

[0029] Here, the parasitic capacitance occurring in the analog switch section 111 when the analog switch 105 is in the OFF state will be considered.

[0030] As shown in FIG. 3 , when signal source 103 is connected to the drain terminal of first N-channel MOSFET 21 and ultrasonic vibrator 107 is connected to the drain terminal of second N-channel MOSFET 23, gate-drain parasitic capacitances 31 and 32 and drain-source parasitic capacitances 33 and 34 of first N-channel MOSFET 21 are generated between signal source 103 and power supply terminal 120 related to negative DC power supply 123.

[0031] When a pulse signal related to the signal source 103 is input to the analog switch 105 in the OFF state, a signal leaks to the power supply terminal 120 related to the negative DC power supply 123 via the gate-drain parasitic capacitance 31 of the first N-channel MOSFET 21, and to the power supply terminal 120 related to the negative DC power supply 123 via the drain-source parasitic capacitance 33 of the first N-channel MOSFET 21 and the third N-channel MOSFET 25 in the ON state (ON resistance 35).

[0032] Signal leakage from analog switch 105 in the off state causes attenuation of ultrasonic energy due to attenuation of signal energy transmitted from signal source 103 to ultrasonic transducer 107 of ultrasonic diagnostic device 12, and causes deterioration of the quality of tomographic images due to distortion of the ultrasonic signal, adversely affecting the performance of ultrasonic diagnostic device 12. Therefore, the smaller the parasitic capacitances 31, 32, 33, and 34 of first N-channel MOSFET 21, the better.

[0033] [Semiconductor device 10 according to comparative example] Next, in order to clarify the configuration and effects of the semiconductor device 11 according to the embodiment of the present invention, a semiconductor device 10 according to a comparative example will be described before describing the semiconductor device 11. 4 is a cross-sectional view schematically illustrating the configuration of a semiconductor device 10 according to a comparative example. The semiconductor device 10 according to the comparative example is an N-channel MOSFET, and when applied to an analog switch 105 for an ultrasound diagnostic device 12, first and second N-channel MOSFETs 21 and 23 correspond to the semiconductor device 10 according to the comparative example.

[0034] As shown in FIG. 4, a semiconductor device (N-channel MOSFET) 10 according to the comparative example includes a first conductivity type semiconductor layer (n-type semiconductor layer) 51, first conductivity type high concentration semiconductor layers (n-type high concentration semiconductor layers) 53 and 54 formed on the front and side surfaces of the n-type semiconductor layer 51, and a pair of second conductivity type semiconductor layers (p-type semiconductor layers) 55 formed on the front and side surfaces of the n-type semiconductor layer 51 and spaced a predetermined distance from the n-type high concentration semiconductor layer 53 in the longitudinal direction and sandwiching the n-type high concentration semiconductor layer 53 therebetween. The n-type high concentration semiconductor layer 54 is provided so that a part of it is buried in the p-type semiconductor layer 55 (details will be described later). The n-type high concentration semiconductor layers 53 and 54 have an impurity concentration of [n + ] is set. The p-type semiconductor layer 55 is not particularly limited, but may have an impurity concentration of [p + ] can also be set.

[0035] A drain electrode 69 is provided on the front surface of the heavily doped n-type semiconductor layer 53 so as to be in contact with the front surface of the heavily doped n-type semiconductor layer 53 .

[0036] The drain electrode 69 has a main body 70 that is approximately rectangular when viewed from the front on the paper, and a drain electrode field plate 71 that extends on both sides of the main body 70 in the longitudinal direction, and is formed into an approximately T-shape overall when viewed from the front.

[0037] The pair of drain electrode field plates 71 are each provided so as to extend longitudinally beyond the length of the n-type high concentration semiconductor layer 53 relative to the main body portion 70 associated with the drain electrode 69 (overlapping the n-type high concentration semiconductor layer 53).

[0038] A field oxide film 57 is provided at the junction between the main body 70 and the n-type heavily doped semiconductor layer 53, which is related to the drain electrode 69, so as to cover both sides of the junction, including the periphery, in the longitudinal direction. The field oxide film 57 has a predetermined thickness in the depth direction and extends along the longitudinal direction.

[0039] A source electrode 65 is provided on the front surface of each of the pair of second conductivity type semiconductor layers (p-type semiconductor layers) 55 so as to be in contact with a part of the front surface of the p-type semiconductor layer 55.

[0040] An insulating layer 59 made of an oxide film is provided to cover the opposite end of the p-type semiconductor layer 55 in the depth direction on the end opposite to the n-type heavily doped semiconductor layer 53. The insulating layer 59 is also provided to cover the electrode region including the gate electrode 61, the source electrode 65, and the drain electrode 69 of the semiconductor device (N-channel MOSFET) 10 according to the comparative example.

[0041] Here, the semiconductor device (N-channel MOSFET) 10 according to the comparative example employs a symmetrical structure in which a pair of source electrodes 65 are disposed on both sides of a drain electrode 69.

[0042] The source electrode 65 comprises a main body 66 that is approximately rectangular when viewed from the front on the paper, and a source electrode field plate 67 that extends on both sides of the main body 70 in the longitudinal direction, and is formed into an approximately T-shape overall when viewed from the front.

[0043] The source electrode field plates 67 are each provided so as to extend beyond the longitudinal size of the p-type semiconductor layer 55 relative to the main body 66 of the source electrode 65 (so as to overlap the p-type semiconductor layer 55).

[0044] A field oxide film 57 is provided at the junction between the main body 66 of the source electrode 65 and the p-type semiconductor layer 55 so as to cover both sides in the length direction, including the periphery. The field oxide film 57 has a predetermined thickness in the depth direction and is provided so as to extend along the length direction.

[0045] A pair of n-type high concentration semiconductor layers 54 is provided at both longitudinal ends of the rear surface of the main body 66 relating to the source electrode 65, with portions of the layers being in contact with the source electrode 65. The pair of n-type high concentration semiconductor layers 54 has a predetermined thickness in the depth direction and is provided so as to extend along the longitudinal direction. The pair of n-type high concentration semiconductor layers 54 is provided so that portions thereof are buried in the p-type semiconductor layer 55.

[0046] A pair of gate electrodes 61, each having an approximately rectangular shape in front view, are provided on both longitudinal sides of the main body 66 of the source electrode 65 at a predetermined distance from the main body 66 so as to contact the front side of the field oxide film 57.

[0047] The pair of gate electrodes 61 are provided so as to overlap the n-type high concentration semiconductor layer 54 and the p-type semiconductor layer 55, and the pn junction 56 formed by the combination of the n-type semiconductor layer 51 and the p-type semiconductor layer 55.

[0048] Of the pair of gate electrodes 61, the gate electrode 61 located on the drain electrode 69 side includes a gate electrode section field plate 63 extending toward the drain electrode 69. The gate electrode section field plate 63 is provided so as to extend in the longitudinal direction beyond the end of the p-type semiconductor layer 55 on the drain electrode 69 side (so as to overlap the p-type semiconductor layer 55).

[0049] An extension 68 is provided at the end of source electrode field plate 67 on the drain electrode 69 side. Extension 68 of source electrode field plate 67 is provided so as to extend in the length direction toward drain electrode 69 beyond the end of gate electrode 61 on the drain electrode 69 side (so as to overlap gate electrode 61).

[0050] In the semiconductor device (N-channel MOSFET) 10 according to the comparative example, a field oxide film 57 having a depth dimension (film thickness) larger than that of a normal gate oxide film is used as the gate oxide film in order to properly transmit and block high-voltage and high-frequency electrical signals.

[0051] Furthermore, in order to suppress a decrease in breakdown voltage due to electric field concentration at the interface between the pn junction 56 and the field oxide film 57 when a high voltage is applied to the drain electrode 69 in the off state, a field plate structure is adopted in which part of the source electrode 65 is extended toward the drain electrode 69 so as to overlap the gate electrode 61, and part of the drain electrode 69 is also extended toward the source electrode 65.

[0052] When the semiconductor device (N-channel MOSFET) 10 according to the comparative example is in an off state, the N-channel MOSFET 10 has gate-to-drain parasitic capacitances 81 (Cgd1), 83 (Cgd2), and drain-to-source parasitic capacitances 85 (Cds1), 87 (Cds2), 89 (Cds3), 91 (Cds4), 93 (Cds5), and 95 (Cds6).

[0053] The gate-drain parasitic capacitances 81 (Cgd1) and 83 (Cgd2) are generated by the field oxide film 57 interposed between the gate electrode 61 and the n-type semiconductor layer 51.

[0054] Drain-source parasitic capacitances 85 (Cds1) and 87 (Cds2) are generated by the pn junction 56 of the p-type semiconductor layer 55 and the n-type semiconductor layer 51.

[0055] The drain-source parasitic capacitances 89 (Cds3) and 91 (Cds4) are generated by the insulating layer 59 and the field oxide film 57 being interposed between the source electrode 65 and the n-type semiconductor layer 51.

[0056] The drain-source parasitic capacitances 93 (Cds5) and 95 (Cds6) are generated by the insulating layer 59 interposed between the source electrode 65 and the drain electrode 69.

[0057] The capacitance values ​​of the gate-drain parasitic capacitances 81 (Cgd1), 83 (Cgd2) and the drain-source parasitic capacitances 85 (Cds1), 87 (Cds2), 89 (Cds3), 91 (Cds4), 93 (Cds5), and 95 (Cds6) that occur in the N-channel MOSFET 10 are in a trade-off relationship with the on-resistance and breakdown voltage of the N-channel MOSFET 10.

[0058] If the element area of ​​the N-channel MOSFET 10 is reduced, the capacitance values ​​of the gate-drain parasitic capacitances 81 (Cgd1), 83 (Cgd2), and the drain-source parasitic capacitances 85 (Cds1), 87 (Cds2), 89 (Cds3), 91 (Cds4), 93 (Cds5), and 95 (Cds6) can be reduced.

[0059] However, reducing the element area of ​​the N-channel MOSFET 10 reduces the channel area when the N-channel MOSFET 10 is in the on state, resulting in an increase in the on-resistance value. When such an N-channel MOSFET 10 is applied to an analog switch 105 for an ultrasonic diagnostic device 12, an increase in the on-resistance value is synonymous with an increase in signal energy loss in the analog switch 105 that is turned on to oscillate ultrasonic waves, resulting in attenuation of ultrasonic energy.

[0060] Furthermore, if the longitudinal dimension of gate electrode portion field plate 63 were shortened (including removal of gate electrode portion field plate 63), the capacitance values ​​associated with gate-drain parasitic capacitances 81 (Cgd1) and 83 (Cgd2) could be reduced.

[0061] Furthermore, by shortening the length of extension 68 of source electrode field plate 67 (including removing extension 68) or by shortening the length of drain electrode field plate 71 (including removing drain electrode field plate 71), the capacitance values ​​of drain-source parasitic capacitances 89 (Cds3), 91 (Cds4), 93 (Cds5), and 95 (Cds6) can be appropriately reduced.

[0062] However, shortening the length of gate electrode field plate 63, the length of extension 68 related to source electrode field plate 67, or the length of drain electrode field plate 71 results in a decrease in breakdown voltage due to electric field concentration at the interface between pn junction 56 and field oxide film 57 when a high voltage is applied to drain electrode 69 of N-channel MOSFET 10 while N-channel MOSFET 10 is in the off state.

[0063] Therefore, in the semiconductor device (N-channel MOSFET) 10 according to the comparative example, it is difficult to reduce the parasitic capacitance without affecting the on-resistance value and the breakdown voltage. As a result, the parasitic capacitance causes attenuation of ultrasonic energy in ultrasonic diagnostic equipment and degradation of the quality of tomographic images.

[0064] The present invention has been made in view of the above circumstances, and has an object to provide a semiconductor device capable of reducing parasitic capacitance without impairing various characteristics including on-resistance and breakdown voltage.

[0065] [Semiconductor device 11 according to an embodiment of the present invention] Next, the configuration and effects of the semiconductor device 11 according to the embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 5A is a plan view showing the internal structure of a semiconductor device 11 according to an embodiment of the present invention, focusing on the area around a gate electrode 61. FIG. 5B is a plan view showing the internal structure of a semiconductor device 11 according to an embodiment of the present invention, focusing on the area around a source electrode 65 and a drain electrode 69. FIG. 6A is a cross-sectional view taken along line 6A-6A in FIG. 5A. FIG. 6B is a cross-sectional view taken along line 6B-6B in FIG. 5A. FIG. 6C is a cross-sectional view taken along line 6C-6C in FIG. 5B.

[0066] The semiconductor device 11 according to the embodiment of the present invention is an N-channel MOSFET, and when applied to the analog switch 105 for the ultrasound diagnostic device 12, the first and second N-channel MOSFETs 21 and 23 correspond to the semiconductor device 11 according to the embodiment of the present invention.

[0067] 5A, 5B, 6A, and 6B, similar to the semiconductor device 10 according to the comparative example, the semiconductor device (N-channel MOSFET) 11 according to the embodiment of the present invention includes a first conductivity-type semiconductor layer (n-type semiconductor layer) 51, first conductivity-type heavily doped semiconductor layers (n-type heavily doped semiconductor layers) 53 and 54 formed on the front and side surfaces of the n-type semiconductor layer 51, and a pair of second conductivity-type semiconductor layers (p-type semiconductor layers) 55 formed on the front and side surfaces of the n-type semiconductor layer 51 so as to sandwich the n-type heavily doped semiconductor layer 53 and be spaced a predetermined distance apart in the longitudinal direction from the n-type heavily doped semiconductor layer 53. The n-type heavily doped semiconductor layer 54 is provided so as to be buried in the p-type semiconductor layer 55. The n-type high concentration semiconductor layers 53 and 54 have an impurity concentration of [n + ] is set. The p-type semiconductor layer 55 is not particularly limited, but may have an impurity concentration of [p + ] is set.

[0068] When the semiconductor device (N-channel MOSFET) 11 according to the embodiment of the present invention is in an off state, the N-channel MOSFET 11 has gate-drain parasitic capacitances 81 (Cgd1), 83 (Cgd2), and drain-source parasitic capacitances 85 (Cds1), 87 (Cds2), 89 (Cds3), 91 (Cds4), 93 (Cds5), and 95 (Cds6), similar to the N-channel MOSFET 10 according to the comparative example.

[0069] The gate-drain parasitic capacitances 81 (Cgd1) and 83 (Cgd2) are generated by the field oxide film 57 interposed between the gate electrode 61 and the n-type semiconductor layer 51.

[0070] Drain-source parasitic capacitances 85 (Cds1) and 87 (Cds2) are generated by the pn junction 56 of the p-type semiconductor layer 55 and the n-type semiconductor layer 51.

[0071] The drain-source parasitic capacitances 89 (Cds3) and 91 (Cds4) are generated by the insulating layer 59 and the field oxide film 57 being interposed between the source electrode 65 and the n-type semiconductor layer 51.

[0072] The drain-source parasitic capacitances 93 (Cds5) and 95 (Cds6) are generated by the insulating layer 59 interposed between the source electrode 65 and the drain electrode 69.

[0073] As shown in FIGS. 5A, 6A, and 6B, in the semiconductor device (N-channel MOSFET) 11 according to the embodiment of the present invention, as a planar structure around the gate electrode 61, in the first region 41 (see FIG. 5A) where the gate electrode 61 and the n-type semiconductor layer 51 overlap in the depth direction, a comb-shaped structure portion 63 is provided at the end of the gate electrode 61 facing the drain electrode 69.

[0074] Specifically, for the gate electrode 61 provided immediately adjacent to and on both sides of the drain electrode 69, portions 61a having a gate electrode portion field plate (comb-shaped structure portion related to the gate electrode 61) 63 and portions 61b not having a gate electrode portion field plate 63 are alternately provided across the width at the end facing the drain electrode 69, thereby forming the comb-shaped structure portion 63 related to the gate electrode 61.

[0075] In the gate electrode 61, a portion 61a having the gate electrode portion field plate 63 and a portion 61b not having the gate electrode portion field plate 63 are set to have approximately the same dimensions in the width direction (see FIG. 5A). With this configuration, even if there is some variation in the width direction dimension of the comb-shaped structure of the gate electrode 61 during the manufacturing process, it is possible to expect the effect of suppressing deviations in parasitic capacitance between products.

[0076] As shown in FIGS. 5B, 6A, and 6B, in the semiconductor device (N-channel MOSFET) 11 according to the embodiment of the present invention, as a planar structure around the source electrode 65, a comb-shaped structure 68 is provided at the end of the source electrode 65 facing the drain electrode 69 in the second region 43 (see FIG. 5B) where the source electrode 65 and the n-type semiconductor layer 51 overlap in the depth direction.

[0077] Specifically, for the source electrode 65 provided on both sides of the drain electrode 69, portions 65a having extension portions (comb-shaped structure portions related to the source electrode 65) 68 related to the source electrode portion field plate 67 and portions 65b not having extension portions 68 related to the source electrode portion field plate are alternately provided across the width at the end facing the drain electrode 69, thereby forming comb-shaped structure portions 68 related to the source electrode 65.

[0078] Of the source electrode 65, the portion 65a having the extension portion 68 associated with the source electrode portion field plate 67 and the portion 65b not having the extension portion 68 associated with the source electrode portion field plate 67 are set to have approximately the same dimensions in the width direction (see FIG. 5B). With this configuration, even if there is some variation in the width direction dimension of the comb-shaped structure portion 68 related to the source electrode 65 during the manufacturing process, it is possible to expect the effect of suppressing deviations in parasitic capacitance between products.

[0079] As shown in FIGS. 5B, 6A, and 6B, in the semiconductor device (N-channel MOSFET) 11 according to the embodiment of the present invention, as a planar structure around the drain electrode 69, a comb-shaped structure portion 71 is provided at the end of the drain electrode 69 facing the source electrode 65 in the third region 45 (see FIG. 5B) where the drain electrode 69 and the n-type semiconductor layer 51 overlap in the depth direction.

[0080] Specifically, for the drain electrode 69, which is sandwiched between source electrodes 65 in the longitudinal direction, portions 69a having a drain electrode field plate (comb-shaped structure portion related to the drain electrode 69) 71 and portions 69b not having a drain electrode field plate 71 are alternately arranged across the width at the end facing the source electrode 65, thereby forming comb-shaped structure portion 71 related to the drain electrode 69.

[0081] In the drain electrode 69, a portion 69a having the drain electrode field plate 71 and a portion 69b not having the drain electrode field plate 71 are set to have approximately the same dimensions in the width direction (see FIG. 5B). With this configuration, even if there is some variation in the width direction dimension of the comb-shaped structure portion 71 related to the drain electrode 69 during the manufacturing process, it is possible to expect the effect of suppressing deviations in parasitic capacitance between products.

[0082] Comparing the comb-shaped structure 68 of the source electrode 65 and the comb-shaped structure 71 of the drain electrode 69 in the longitudinal direction, a portion 65a of the source electrode 65 having the source electrode field plate 68 and a portion 69b of the drain electrode 69 not having the drain electrode field plate 71 are arranged to face each other along the longitudinal direction.

[0083] Furthermore, when comparing the comb-shaped structure 68 associated with the source electrode 65 and the comb-shaped structure 71 associated with the drain electrode 69 in the longitudinal direction, a portion 65b of the source electrode 65 that does not have a source electrode field plate 68 and a portion 69a of the drain electrode 69 that has a drain electrode field plate 71 are arranged to face each other along the longitudinal direction.

[0084] In short, when comparing the comb-shaped structure 68 associated with the source electrode 65 and the comb-shaped structure 71 associated with the drain electrode 69 in the longitudinal direction, the opposing distance in the longitudinal direction between the source electrode 65 and the drain electrode 69 in the embodiment of the present invention is set to be longer than the opposing distance in the longitudinal direction between the source electrode 65 and the drain electrode 69 in the comparative example.

[0085] With this configuration, the capacitance values ​​(Cds5·Cds6) of the drain-source parasitic capacitances 93·95 according to the embodiment of the present invention can be made smaller than the capacitance values ​​(Cds5·Cds6) of the drain-source parasitic capacitances 93·95 according to the comparative example, because the capacitance value of the capacitor (parasitic capacitance) and the electrode distance (facing distance) are inversely proportional to each other.

[0086] As shown in Figures 5B and 6C, for the comb-shaped structure portion 68 related to the source electrode 65, if the depth direction distance between the source electrode 65 and the n-type semiconductor layer 51 (the value obtained by adding the thickness of the field oxide film 57 to the thickness of the insulating layer 59) is d [m] and the width direction spacing between the portions 65a having the source electrode field plates 68 is Dcb [m], then the width direction spacing Dcb [m] is set to less than 2*d [m] [Dcb<2*d].

[0087] With this configuration, the field plate structure associated with the source electrode 65 can be expected to have a high breakdown voltage.

[0088] When observing the cross-sectional view shown in FIG. 6A, since the drain electrode 69 does not have a drain electrode portion field plate 71, the opposing distance in the longitudinal direction between the source electrode 65 and the drain electrode 69 in the embodiment of the present invention is longer than the opposing distance in the longitudinal direction between the source electrode 65 and the drain electrode 69 in the comparative example by the amount by which the drain electrode 69 does not have the drain electrode portion field plate 71.

[0089] As a result, the capacitance values ​​(Cds5·Cds6) of the drain-source parasitic capacitances 93·95 in the embodiment of the present invention can be made smaller than the capacitance values ​​(Cds5·Cds6) of the drain-source parasitic capacitances 93·95 in the comparative example.

[0090] Observing the cross-sectional view shown in FIG. 6B, it is seen that gate electrode 61 does not have gate electrode field plate 63, and therefore gate-drain parasitic capacitances 81 (Cgd1) and 83 (Cgd2) generated by the presence of field oxide film 57 between gate electrode 61 and n-type semiconductor layer 51 do not substantially occur. Similarly, since the source electrode 65 does not have a source electrode field plate 68, the drain-source parasitic capacitances 89 (Cds3) and 91 (Cds4) that are generated by the insulating layer 59 and the field oxide film 57 being interposed between the source electrode 65 and the n-type semiconductor layer 51 are substantially not generated.

[0091] In summary, it can be seen that the parasitic capacitance value relating to the embodiment of the present invention can be made smaller than the parasitic capacitance value relating to the comparative example.

[0092] Therefore, the semiconductor device (N-channel MOSFET) 11 according to the embodiment of the present invention can reduce the parasitic capacitance while maintaining substantially the same breakdown voltage and on-resistance as the semiconductor device (N-channel MOSFET) 10 according to the comparative example. In other words, the parasitic capacitance can be reduced without impairing various characteristics including the on-resistance and breakdown voltage. As a result, the semiconductor device (N-channel MOSFET) 11 according to the embodiment of the present invention can suppress attenuation of ultrasonic energy and deterioration in the quality of tomographic images caused by parasitic capacitance when used in the ultrasonic diagnostic device 12.

[0093] [Configuration and Effects of the Semiconductor Device 11 According to the Present Invention] A semiconductor device (11) according to a first aspect includes: a first conductivity type semiconductor layer (51); a first conductivity type high concentration semiconductor layer (53) associated with a drain region formed on the surface side of the first conductivity type semiconductor layer (51); a second conductivity type semiconductor layer (55) associated with a source region formed on the surface side of the first conductivity type semiconductor layer (51) at a predetermined distance in the longitudinal direction from the first conductivity type high concentration semiconductor layer (53) associated with the drain region; a first conductivity type high concentration semiconductor layer (54) relating to the source region, which is provided so that a part of the first conductivity type high concentration semiconductor layer (54) is buried in the second conductivity type semiconductor layer (55) relating to the source region; a drain electrode (69) provided in contact with the front side surface of the first conductivity type high concentration semiconductor layer (53) relating to the drain region; a source electrode (65) provided in contact with the front and side surfaces of the first conductivity type high concentration semiconductor layer (54) and the second conductivity type semiconductor layer (55) relating to the source region; a field oxide film (57) provided to electrically insulate a semiconductor region including the first conductivity type semiconductor layer (51), the first conductivity type high concentration semiconductor layer (53) associated with the drain region, the second conductivity type semiconductor layer (55) associated with the source region, and the first conductivity type high concentration semiconductor layer (54) associated with the source region from one another, and an electrode region including the drain electrode (69) and the source electrode (65); a gate electrode (61) provided on the surface side of the field oxide film (57) so as to overlap a pn junction (56) formed by a combination of a first conductivity type high concentration semiconductor layer (54) and a second conductivity type semiconductor layer (55) related to the source region, and the first conductivity type semiconductor layer (51) and the second conductivity type semiconductor layer (55); an insulating layer (59) provided so as to surround each of the drain electrode (69), the source electrode (65), and the gate electrode (61), In a first region (41) where the gate electrode (61) and the first conductivity type semiconductor layer (51) overlap in the depth direction, a comb-shaped structure (63) is provided at an end of the gate electrode (61) facing the drain electrode (69). The semiconductor device is characterized by the above.

[0094] The semiconductor device 11 according to the first aspect relates to a semiconductor device (N-channel MOSFET) 11 according to an embodiment of the present invention, and is configured in consideration of capturing both N-channel MOSFETs and P-channel MOSFETs within the technical scope of the present invention, as well as capturing a unit structure having one gate electrode 61, one source electrode 65, and one drain electrode 69 in an electrode region.

[0095] According to the semiconductor device 11 of the first aspect, in the first region (41) where the gate electrode (61) and the first conductivity type semiconductor layer (51) overlap in the depth direction, a comb-shaped structure (63) is provided at the end of the gate electrode (61) facing the drain electrode (69). This can be expected to have the effect of reducing, for example, the capacitance values ​​(Cgd1·Cgd2) associated with the gate-drain parasitic capacitances 81·83 generated by the field oxide film 57 interposed between the gate electrode 61 and the n-type semiconductor layer 51, without impairing various characteristics including the on-resistance value and the breakdown voltage value.

[0096] A semiconductor device 11 according to a second aspect is the semiconductor device 11 according to the first aspect, The gate electrode (61) includes a gate electrode field plate (63) at a part thereof, the gate electrode field plate (63) extending toward the drain electrode (69), The comb-shaped structure (63) may be configured by alternately providing portions (61a) having the gate electrode portion field plate (63) and portions (61b) not having the gate electrode portion field plate (63) across the width at the end of the gate electrode (61) facing the drain electrode (69).

[0097] According to the semiconductor device 11 according to the second aspect, the configuration of the comb-shaped structure portion (63) associated with the gate electrode (61) is clarified, and therefore, in addition to the effects of the semiconductor device 11 according to the first aspect, an effect of ensuring the feasibility requirements of the present invention can be expected.

[0098] A semiconductor device 11 according to a third aspect is the semiconductor device 11 according to the second aspect, A configuration may be adopted in which the portion (61a) of the gate electrode (61) having the gate electrode portion field plate (63) and the portion (61b) not having the gate electrode portion field plate (63) are set to approximately the same dimensions in the width direction.

[0099] According to the semiconductor device 11 of the third aspect, in addition to the effects of the semiconductor device 11 of the second aspect, even if some variation occurs in the width direction dimension of the comb-shaped structure portion 63 associated with the gate electrode 61 during the manufacturing process, it is possible to expect the effect of suppressing deviation in parasitic capacitance between products.

[0100] A semiconductor device 11 according to a fourth aspect comprises: a first conductivity type semiconductor layer (51); a first conductivity type high concentration semiconductor layer (53) associated with a drain region formed on the surface side of the first conductivity type semiconductor layer (51); a second conductivity type semiconductor layer (55) associated with a source region formed on the surface side of the first conductivity type semiconductor layer (51) at a predetermined distance in the longitudinal direction from the first conductivity type high concentration semiconductor layer (53) associated with the drain region; a first conductivity type high concentration semiconductor layer (54) relating to the source region, which is provided so that a part of the first conductivity type high concentration semiconductor layer (54) is buried in the second conductivity type semiconductor layer (55) relating to the source region; a drain electrode (69) provided in contact with the front side surface of the first conductivity type high concentration semiconductor layer (53) relating to the drain region; a source electrode (65) provided in contact with the front and side surfaces of the first conductivity type high concentration semiconductor layer (54) and the second conductivity type semiconductor layer (55) relating to the source region; a field oxide film (57) provided to electrically insulate a semiconductor region including the first conductivity type semiconductor layer (51), the first conductivity type high concentration semiconductor layer (53) associated with the drain region, the second conductivity type semiconductor layer (55) associated with the source region, and the first conductivity type high concentration semiconductor layer (54) associated with the source region from one another, and an electrode region including the drain electrode (69) and the source electrode (65); a gate electrode (61) provided on the surface side of the field oxide film (57) so as to overlap the first conductivity type high concentration semiconductor layer (54) and the second conductivity type semiconductor layer (55) related to the source region, and a pn junction (56) formed by a combination of the first conductivity type semiconductor layer (51) and the second conductivity type semiconductor layer (55); an insulating layer (59) provided so as to surround each of the drain electrode (69), the source electrode (65), and the gate electrode (61), In a second region (43) where the source electrode (65) and the first conductivity type semiconductor layer (51) overlap in the depth direction, a comb-shaped structure (68) is provided at an end of the source electrode (65) facing the drain electrode (69). The semiconductor device is characterized by the above.

[0101] Like the semiconductor device 11 according to the first aspect, the semiconductor device 11 according to the fourth aspect relates to the semiconductor device (N-channel MOSFET) 11 according to an embodiment of the present invention, and is configured in consideration of capturing a P-channel MOSFET within the technical scope of the present invention, as well as capturing a unit structure having one gate electrode 61, one source electrode 65, and one drain electrode 69 in an electrode region.

[0102] According to the semiconductor device 11 in accordance with the fourth aspect, in the second region (43) where the source electrode (65) and the first conductivity type semiconductor layer (51) overlap in the depth direction, a comb-shaped structure (68) is provided at the end of the source electrode (65) facing the drain electrode (69). This can be expected to have the effect of reducing, for example, capacitance values ​​(Cds3·Cds4) associated with drain-source parasitic capacitances 89·91 generated by the insulating layer 59 and field oxide film 57 interposed between the source electrode 65 and the n-type semiconductor layer 51, without impairing various characteristics including the on-resistance value and the breakdown voltage value.

[0103] A semiconductor device 11 according to a fifth aspect is the semiconductor device 11 according to the fourth aspect, The source electrode (65) includes a source electrode field plate (68) at a part thereof, the source electrode field plate (68) extending toward the drain electrode (69), The comb-shaped structure (68) may be configured by alternately providing, across the width, a portion (65a) having an extension (68) associated with the source electrode field plate (67) and a portion (65b) not having the extension (68) associated with the source electrode field plate (67) at the end of the source electrode (65) facing the drain electrode (69).

[0104] According to the semiconductor device 11 in accordance with the fifth aspect, the configuration of the comb-shaped structure portion (68) relating to the source electrode (65) is clarified, and therefore, in addition to the effects of the semiconductor device 11 in accordance with the fourth aspect, an effect of ensuring the feasibility requirements of the present invention can be expected.

[0105] A semiconductor device 11 according to a sixth aspect is the semiconductor device 11 according to the fifth aspect, A configuration may be adopted in which a portion (65a) of the source electrode (65) having an extension portion (68) associated with the source electrode field plate (67) and a portion (65b) not having the extension portion (68) associated with the source electrode field plate (67) are set to approximately the same dimensions in the width direction.

[0106] According to the semiconductor device 11 in accordance with the sixth aspect, in addition to the effects of the semiconductor device 11 in accordance with the fifth aspect, even if some variation occurs in the width direction dimension of the comb-shaped structure portion 68 related to the source electrode 65 during the manufacturing process, it can be expected to have the effect of suppressing deviation in parasitic capacitance between products.

[0107] A semiconductor device 11 according to a seventh aspect is the semiconductor device 11 according to the sixth aspect, In a third region (45) where the drain electrode (69) and the first conductivity type semiconductor layer (51) overlap in the depth direction, a configuration may be adopted in which a comb-shaped structure (71) is provided at the end of the drain electrode (69) facing the source electrode (65).

[0108] According to the semiconductor device 11 of the seventh aspect, in the third region (45) where the drain electrode (69) and the first conductivity type semiconductor layer (51) overlap in the depth direction, a comb-shaped structure (71) is provided at the end of the drain electrode (69) facing the source electrode (65). Therefore, in addition to the effects of the semiconductor device 11 of the sixth aspect, it is possible to expect an effect of reducing the capacitance value related to the drain-source parasitic capacitances 93 (Cds5) and 95 (Cds6) generated by the insulating layer 59 being interposed between the source electrode 65 and the drain electrode 69, for example, without impairing various characteristics including the on-resistance value and the breakdown voltage value.

[0109] A semiconductor device 11 according to an eighth aspect is the semiconductor device 11 according to the seventh aspect, The drain electrode (69) includes a drain electrode field plate (71) at a part thereof, the field plate extending toward the source electrode (65), The comb-shaped structure (71) may be configured by alternately providing a portion (69a) having the drain electrode field plate (71) and a portion (69b) not having the drain electrode field plate (71) across the width of the end of the drain electrode (69) facing the source electrode (65).

[0110] According to the semiconductor device 11 of the eighth aspect, the configuration of the comb-shaped structure portion (71) relating to the drain electrode (69) is clarified, and therefore, in addition to the effects of the semiconductor device 11 of the seventh aspect, an effect of ensuring the feasibility of the present invention can be expected.

[0111] A semiconductor device 11 according to a ninth aspect is the semiconductor device 11 according to the eighth aspect, 9. The semiconductor device according to claim 8, A configuration may be adopted in which a portion (69a) of the drain electrode (69) having the drain electrode field plate (71) and a portion (69b) not having the drain electrode field plate (71) are set to approximately the same dimensions in the width direction.

[0112] According to the semiconductor device 11 of the ninth aspect, in addition to the advantageous effects of the semiconductor device 11 of the eighth aspect, even if some variation occurs in the width direction dimension of the comb-shaped structure portion 71 related to the drain electrode 69 during the manufacturing process, it is possible to expect an effect of suppressing deviation in parasitic capacitance between products.

[0113] A semiconductor device 11 according to a tenth aspect is the semiconductor device 11 according to the ninth aspect, When comparing the comb-shaped structure (68) of the source electrode (65) and the comb-shaped structure (71) of the drain electrode (69) in the length direction, a configuration may be adopted in which a portion (65a) of the source electrode (65) having the extension (68) of the source electrode field plate (67) and a portion (69b) of the drain electrode (69) not having the drain electrode field plate (71) are arranged to face each other, and a portion (65b) of the source electrode (65) not having the extension (68) of the source electrode field plate (67) and a portion (69a) of the drain electrode (69) having the drain electrode field plate (71) are arranged to face each other.

[0114] According to the semiconductor device 11 in accordance with the tenth aspect, the opposing distance in the longitudinal direction between the source electrode 65 and the drain electrode 69 is set to be relatively long, and therefore, in addition to the effects of the semiconductor device 11 in accordance with the ninth aspect, an effect of reducing the capacitance values ​​Cds5 and Cds6 associated with the drain-source parasitic capacitances 93 and 95 can be expected.

[0115] A semiconductor device 11 according to an eleventh aspect is the semiconductor device 11 according to any one of the fifth to tenth aspects, With regard to the comb-shaped structure portion (68) of the source electrode (65), if the depth direction distance between the source electrode (65) and the first conductivity type semiconductor layer (51) is d [m] and the width direction spacing between the portions (65a) having the extension portions (68) of the source electrode field plate (67) is Dcb [m], a configuration may be adopted in which the width direction spacing Dcb [m] is set to less than 2*d [m] [Dcb<2*d].

[0116] According to the semiconductor device 11 in accordance with the eleventh aspect, in addition to the effects of the semiconductor device 11 in accordance with any one of the fifth to tenth aspects, the effect of maintaining breakdown voltage due to the field plate structure associated with the source electrode 65 can be expected.

[0117] [Ultrasound diagnostic device 12] The semiconductor device 11 according to the eleventh aspect is an N-channel MOSFET, and the N-channel MOSFET may be applied to an analog switch (105) for an ultrasonic diagnostic device 12 (see FIG. 1). With this configuration, it is possible to obtain a high-performance ultrasonic diagnostic device 12 in which the attenuation of ultrasonic energy caused by the parasitic capacitance of the N-channel MOSFET and the deterioration of the quality of tomographic images are suppressed.

[0118] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments and modifications have been described to aid in understanding the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0119] In the description of the semiconductor device 11 according to the present invention, an example in which the first conductivity type is n-type and the second conductivity type is p-type has been given, but the present invention is not limited to this example. Semiconductor device 11 in which the first conductivity type is p-type and the second conductivity type is n-type is also included within the technical scope of the present invention.

[0120] Finally, in the embodiments and modifications of the present invention, the control lines and information lines shown are those that are considered necessary for explanation, and do not necessarily show all the control lines and information lines on the product. [Explanation of symbols]

[0121] 10 Semiconductor device according to comparative example (N-channel MOSFET) 11 Semiconductor device according to an embodiment of the present invention (N-channel MOSFET) 12 Ultrasound diagnostic equipment 41 First Area 43 Second Area 45 The Third Region 51 n-type semiconductor layer (first conductivity type semiconductor layer) 53 n-type heavily doped semiconductor layer (first conductive type heavily doped semiconductor layer related to the drain region) 54 n-type high concentration semiconductor layer (first conductivity type high concentration semiconductor layer related to the source region) 55 p-type semiconductor layer (second conductivity type semiconductor layer related to the source region) 56 pn junction 57 Field oxide 59 Insulating layer 61 gate electrode 63 Gate electrode field plate (comb-shaped structure related to the gate electrode) 65 Source electrode 67 Source electrode field plate 68 Extension portion relating to source electrode field plate (comb-shaped structure portion relating to source electrode) 69 Drain electrode 71 Drain electrode field plate (comb-shaped structure related to the drain electrode) 81 Gate-drain parasitic capacitance (Cgd1) 83 Gate-drain parasitic capacitance (Cgd2) 85 Drain-source parasitic capacitance (Cds1) 87 Drain-source parasitic capacitance (Cds2) 89 Drain-source parasitic capacitance (Cds3) 91 Drain-source parasitic capacitance (Cds4) 93 Drain-source parasitic capacitance (Cds5) 95 Drain-source parasitic capacitance (Cds6)

Claims

1. A first conductivity type semiconductor layer (51), a first conductivity type high concentration semiconductor layer (53) relating to a drain region formed on the surface side of the first conductivity type semiconductor layer (51); a second conductivity type semiconductor layer (55) associated with a source region formed on the surface side of the first conductivity type semiconductor layer (51) at a predetermined distance in the longitudinal direction from the first conductivity type high concentration semiconductor layer (53) associated with the drain region; a first conductivity type high concentration semiconductor layer (54) relating to the source region, which is provided so that a part of the first conductivity type high concentration semiconductor layer (54) is buried in the second conductivity type semiconductor layer (55) relating to the source region; a drain electrode (69) provided in contact with the front side surface of the first conductivity type high concentration semiconductor layer (53) relating to the drain region; a source electrode (65) provided in contact with the front and side surfaces of the first conductivity type high concentration semiconductor layer (54) and the second conductivity type semiconductor layer (55) relating to the source region; a field oxide film (57) provided to electrically insulate between a semiconductor region to which the first conductivity type semiconductor layer (51), the first conductivity type high concentration semiconductor layer (53) relating to the drain region, the second conductivity type semiconductor layer (55) relating to the source region, and the first conductivity type high concentration semiconductor layer (54) relating to the source region belong, and an electrode region to which the drain electrode (69) and the source electrode (65) belong; a gate electrode (61) provided on the surface side of the field oxide film (57) so as to overlap the first conductivity type high concentration semiconductor layer (54) and the second conductivity type semiconductor layer (55) relating to the source region, and a pn junction (56) formed by a combination of the first conductivity type semiconductor layer (51) and the second conductivity type semiconductor layer (55); an insulating layer (59) provided so as to surround each of the drain electrode (69), the source electrode (65), and the gate electrode (61), In a first region (41) where the gate electrode (61) and the first conductive type semiconductor layer (51) overlap in the depth direction, a comb-shaped structure (63) is provided at an end of the gate electrode (61) facing the drain electrode (69). A semiconductor device characterized by:

2. 2. The semiconductor device according to claim 1, The gate electrode (61) includes, as a part thereof, a gate electrode field plate (63) extending toward the drain electrode (69), The comb-shaped structure (63) is formed by alternately providing, in the width direction, a portion (61a) having the gate electrode field plate (63) and a portion (61b) not having the gate electrode field plate (63) at the end of the gate electrode (61) facing the drain electrode (69). A semiconductor device characterized by:

3. 3. The semiconductor device according to claim 2, Of the gate electrode (61), a portion (61a) having the gate electrode portion field plate (63) and a portion (61b) not having the gate electrode portion field plate (63) are set to have approximately the same dimensions in the width direction. A semiconductor device characterized by:

4. A first conductivity type semiconductor layer (51), a first conductivity type high concentration semiconductor layer (53) relating to a drain region formed on the surface side of the first conductivity type semiconductor layer (51); a second conductivity type semiconductor layer (55) associated with a source region formed on the surface side of the first conductivity type semiconductor layer (51) at a predetermined distance in the longitudinal direction from the first conductivity type high concentration semiconductor layer (53) associated with the drain region; a first conductivity type high concentration semiconductor layer (54) relating to the source region, which is provided so that a part of the first conductivity type high concentration semiconductor layer (54) is buried in the second conductivity type semiconductor layer (55) relating to the source region; a drain electrode (69) provided in contact with the front side surface of the first conductivity type high concentration semiconductor layer (53) relating to the drain region; a source electrode (65) provided in contact with the front and side surfaces of the first conductivity type high concentration semiconductor layer (54) and the second conductivity type semiconductor layer (55) relating to the source region; a field oxide film (57) provided to electrically insulate between a semiconductor region to which the first conductivity type semiconductor layer (51), the first conductivity type high concentration semiconductor layer (53) relating to the drain region, the second conductivity type semiconductor layer (55) relating to the source region, and the first conductivity type high concentration semiconductor layer (54) relating to the source region belong, and an electrode region to which the drain electrode (69) and the source electrode (65) belong; a gate electrode (61) provided on the surface side of the field oxide film (57) so as to overlap the first conductivity type high concentration semiconductor layer (54) and the second conductivity type semiconductor layer (55) relating to the source region, and a pn junction (56) formed by a combination of the first conductivity type semiconductor layer (51) and the second conductivity type semiconductor layer (55); an insulating layer (59) provided so as to surround each of the drain electrode (69), the source electrode (65), and the gate electrode (61), In a second region (43) where the source electrode (65) and the first conductive type semiconductor layer (51) overlap in the depth direction, a comb-shaped structure (68) is provided at an end of the source electrode (65) facing the drain electrode (69). A semiconductor device characterized by:

5. 5. The semiconductor device according to claim 4, The source electrode (65) includes a source electrode field plate (67) at a part thereof, the source electrode field plate (67) extending toward the drain electrode (69), The comb-shaped structure (68) is formed by alternately providing, across the width, a portion (65a) having an extension (68) associated with the source electrode field plate (67) and a portion (65b) not having the extension (68) associated with the source electrode field plate (67) at the end of the source electrode (65) facing the drain electrode (69). A semiconductor device characterized by:

6. 6. The semiconductor device according to claim 5, Of the source electrode (65), a portion (65a) having an extension (68) relating to the source electrode field plate (67) and a portion (65b) not having the extension (68) relating to the source electrode field plate (67) are set to have approximately the same dimensions in the width direction. A semiconductor device characterized by:

7. 7. The semiconductor device according to claim 6, In a third region (45) where the drain electrode (69) and the first conductive type semiconductor layer (51) overlap in the depth direction, a comb-shaped structure (71) is provided at an end of the drain electrode (69) facing the source electrode (65). A semiconductor device characterized by:

8. 8. The semiconductor device according to claim 7, The drain electrode (69) includes a drain electrode field plate (71) at a part thereof, the field plate extending toward the source electrode (65), The comb-shaped structure (71) is formed by alternately providing a portion (69a) having the drain electrode field plate (71) and a portion (69b) not having the drain electrode field plate (71) across the width of the end of the drain electrode (69) facing the source electrode (65). A semiconductor device characterized by:

9. 9. The semiconductor device according to claim 8, Of the drain electrode (69), a portion (69a) having the drain electrode field plate (71) and a portion (69b) not having the drain electrode field plate (71) are set to have approximately the same dimensions in the width direction. A semiconductor device characterized by:

10. 10. The semiconductor device according to claim 9, When the comb-shaped structure (68) of the source electrode (65) and the comb-shaped structure (71) of the drain electrode (69) are compared in the length direction, a portion (65a) of the source electrode (65) having an extension (68) of the source electrode field plate (67) and a portion (69b) of the drain electrode (69) not having the drain electrode field plate (71) are arranged to face each other, and the portion (65b) of the source electrode (65) not having the extension (68) of the source electrode field plate (67) and a portion (69a) of the drain electrode (69) having the drain electrode field plate (71) are arranged to face each other. A semiconductor device characterized by:

11. The semiconductor device according to any one of claims 5 to 10, With respect to the comb-shaped structure portion (68) of the source electrode (65), if the depth direction distance between the source electrode (65) and the first conductivity type semiconductor layer (51) is d [m] and the width direction distance between portions (65a) having extension portions (68) of the source electrode field plate (67) is D [m], the width direction distance D [m] is set to less than 2*d [m] [D < 2 * d]. A semiconductor device characterized by:

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