Storage device and method of manufacturing storage device

Abstract

To provide a storage device capable of operating at a high speed.SOLUTION: A storage device according to one embodiment includes a first substrate, a first transistor on the first substrate, a second substrate provided above the first transistor, an external connection terminal provided above the second substrate, a second transistor on the second substrate, a first conductor, a first separation structure, and a memory cell array. The first conductor penetrates the second substrate to electrically connect the first transistor and external connection terminal. The first separation structure is annular encircling the first conductor when viewed from a first direction, and penetrates the second substrate to separate the second substrate. The memory cell array is electrically connected to the first transistor and second transistor.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD Embodiments generally relate to memory devices and methods for manufacturing memory devices. [Background technology]

[0002] A memory device including memory cells arranged three-dimensionally is known. In order to achieve a large memory capacity, the memory device may have a structure in which structures including elements formed in separate processes on separate substrates are bonded together. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2006 / 0118965 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a storage device capable of operating at high speed. [Means for solving the problem]

[0005] According to one embodiment, a memory device includes a first substrate, a first transistor on the first substrate, a second substrate provided above the first transistor, an external connection terminal provided above the second substrate, a second transistor on the second substrate, a first conductor, a first isolation structure, and a memory cell array. The first conductor penetrates the second substrate and electrically connects the first transistor to the external connection terminal. The first isolation structure has an annular shape surrounding the first conductor when viewed from a first direction, penetrates the second substrate, and separates the second substrate. The memory cell array is electrically connected to the first transistor and the second transistor. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 shows an example of components of a storage device according to the first embodiment and connections between the components. [Figure 2] FIG. 2 shows the components and connections of one block of the storage device of the first embodiment. [Figure 3] FIG. 3 shows the appearance of the storage device of the first embodiment. [Figure 4] FIG. 4 shows an example of the structure of a part of the surface of the storage device of the first embodiment. [Figure 5] FIG. 5 shows an example of the cross-sectional structure of a part of the storage device of the first embodiment. [Figure 6] FIG. 6 shows an example of a cross section of a memory pillar of the storage device of the first embodiment. [Figure 7] FIG. 7 shows an example of the cross-sectional structure of a portion of the storage device of the first embodiment. [Figure 8] FIG. 8 is a plan view of a portion of the storage device of the first embodiment. [Figure 9] FIG. 9 shows an example of the flow of a method for manufacturing the storage device of the first embodiment. [Figure 10] FIG. 10 shows an example of a state during manufacture of a portion of a storage device of the first embodiment. [Figure 11] FIG. 11 shows an example of a state during manufacture of a part of a storage device of the first embodiment. [Figure 12] FIG. 12 shows an example of a state during manufacture of a portion of a storage device of the first embodiment. [Figure 13] FIG. 13 shows an example of a state during manufacture of a part of a storage device of the first embodiment. [Figure 14] FIG. 14 shows an example of a state during manufacture of a part of a storage device of the first embodiment. [Figure 15] FIG. 15 shows an example of a state during manufacture of a portion of a storage device of the first embodiment. [Figure 16] FIG. 16 is a plan view of a portion of the storage device of the first embodiment. [Figure 17] FIG. 17 is a plan view of a part of a storage device according to a first modified example of the first embodiment. [Figure 18]FIG. 18 shows an example of the cross-sectional structure of a part of a memory device according to a second modification of the first embodiment. [Figure 19] FIG. 19 shows an example of the cross-sectional structure of a part of a memory device according to a third modified example of the first embodiment. [Figure 20] FIG. 20 shows an example of the cross-sectional structure of a part of the memory device of the second embodiment. [Figure 21] FIG. 21 shows an example of a state during manufacture of a part of a storage device according to the second embodiment. [Figure 22] FIG. 22 shows an example of a state during manufacture of a portion of a storage device according to the second embodiment. [Figure 23] FIG. 23 shows an example of a state during manufacture of a portion of a storage device according to the second embodiment. [Figure 24] FIG. 24 shows an example of a state during manufacture of a portion of a storage device according to the second embodiment. [Figure 25] FIG. 25 shows an example of a state during manufacture of a portion of a storage device according to the second embodiment. [Figure 26] FIG. 26 shows an example of a state during the manufacture of a part of a storage device according to a modification of the second embodiment. [Figure 27] FIG. 27 shows an example of a state during the manufacture of a part of a storage device according to a modification of the second embodiment. [Figure 28] FIG. 28 shows an example of a state during manufacture of a part of a storage device according to a modification of the second embodiment. [Figure 29] FIG. 29 shows an example of a state during manufacture of a part of a storage device according to a modification of the second embodiment. [Figure 30] FIG. 30 shows an example of a state during manufacture of a part of a storage device according to a modification of the second embodiment. [Figure 31] FIG. 31 shows an example of a state during manufacture of a part of a storage device according to a modification of the second embodiment. [Figure 32] FIG. 32 shows an example of the cross-sectional structure of a part of the memory device of the third embodiment. [Figure 33] FIG. 33 shows an example of the cross-sectional structure of a part of the memory device of the third embodiment. [Figure 34] FIG. 34 shows an example of the cross-sectional structure of a part of the memory device of the fourth embodiment. [Figure 35] FIG. 35 shows an example of the cross-sectional structure of a part of the memory device of the fourth embodiment. [Figure 36] FIG. 36 shows an example of the cross-sectional structure of a part of a memory device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In order to distinguish between multiple components having substantially the same functions and configurations in a certain embodiment or different embodiments, additional numbers or letters may be added to the end of the reference numeral. Any description of one embodiment also applies to the description of another embodiment, unless explicitly or obviously excluded.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include portions in which the relationship and ratio of dimensions differ from one another.

[0009] Any steps in the method flows of the embodiments are not limited to the illustrated order and may occur in an order different from the illustrated order and / or in parallel with other steps unless otherwise indicated.

[0010] In this specification and claims, when a first element is "connected" to another second element, it includes the first element being connected to the second element directly or via an element that is always or selectively conductive.

[0011] Hereinafter, an XYZ Cartesian coordinate system will be used to describe the embodiments, where the x-axis extends in the X direction, the y-axis extends in the Y direction, and the z-axis extends in the Z direction.

[0012] 1. First embodiment 1.1.Configuration (Structure) FIG. 1 shows an example of components and connections of the components of a memory device according to the first embodiment. The memory device 1 is a device that stores data using memory cells. The memory device 1 operates based on a command CMD and address information ADD received from an external memory controller. The memory device 1 receives data DAT to be written and outputs data stored in the memory device 1.

[0013] The memory device 1 includes components such as a memory cell array 10, an input / output circuit 11, a logic controller 12, a register 13, a sequencer 14, a voltage generation circuit 15, a driver 16, a row decoder 17, a sense amplifier 18, a data register (data cache) 19, and multiple external connection terminals (pads) PD.

[0014] The memory cell array 10 is a set of arranged memory cells. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK. Each block BLK includes a plurality of memory cell transistors MT. In the area where the memory cell array 10 is provided, wiring such as word lines WL (not shown) and bit lines BL (not shown) are also arranged.

[0015] The input / output circuit 11 transmits and receives various signals to and from the outside of the storage device 1, for example, a memory controller. The input / output circuit 11 is connected to the external connection terminal PD. The input / output circuit 11 transmits and receives input / output signals DQ_0, DQ_1, DQ_2, DQ_3, DQ_4, DQ_5, DQ_6, and DQ_7 via the external connection terminals PD_D0, PD_D1, PD_D2, PD_D3, PD_D4, PD_D5, PD_D6, and PD_D7, respectively. The input / output circuit 11 transmits and receives signals DQS and DQS via the external connection terminal PD. The symbol "" indicates the inverse logic of a signal whose name is not accompanied by the symbol "" and indicates that the signal whose name is accompanied by the symbol "" is asserted when it is at a low ("L") level. The set of input / output signals DQ_0 to DQ_7 transmits a command (CMD), write data or read data (DAT), address information (ADD), and status (STA). The signals DQS and DQS indicate the timing of capturing the input / output signals DQ_0 to DQ_7.

[0016] The logic controller 12 transmits and receives signals to and from the outside of the memory device 1, for example, a memory controller. The logic controller 12 is connected to the external connection terminal PD, and transmits and receives signals CE, CLE, ALE, WE, RE, RE, WP, and RY / BY at the external connection terminal PD. The signal CE enables the memory device 1. The signal CLE notifies the memory device 1 to send a command via the input / output signal DQ. The signal ALE notifies the memory device 1 to send address information ADD via the input / output signal DQ. The signal WE instructs the memory device 1 to receive the input / output signal DQ. The signal RE instructs the memory device 1 to output the input / output signal DQ. The ready / busy signal RY / BY indicates whether the memory device 1 is ready or busy, and a low level indicates a busy state. When the memory device 1 is ready, it accepts commands, and when it is busy, it does not accept commands.

[0017] The register 13 is a circuit that holds commands CMD and address information ADD received by the memory device 1. The commands CMD instruct the sequencer 14 to perform various operations, including data read, data write, and data erase. The address information ADD includes, in one example, a block address, a page address, and a column address. The block address, page address, and column address specify a block BLK, a word line WL, and a bit line BL, respectively.

[0018] The sequencer 14 is a circuit that controls the overall operation of the memory device 1. Based on the command CMD received from the register 13, the sequencer 14 controls the voltage generation circuit 15, the row decoder 17, and the sense amplifier 18 to perform various operations including data read, data write, and data erase.

[0019] The voltage generating circuit 15 is a circuit that generates a plurality of voltages of different magnitudes. The voltage generating circuit 15 receives a power supply voltage from outside the storage device 1 and generates a plurality of voltages from the power supply voltage. The generated voltages are supplied to a driver 16.

[0020] The driver 16 is a circuit that applies various voltages required for the operation of the memory device 1 to several components. The driver 16 receives multiple voltages from the voltage generation circuit 15 and supplies the received voltages to the memory cell array 10, the row decoder 17, and the sense amplifier 18.

[0021] The row decoder 17 is a circuit for selecting a block BLK. The row decoder 17 transfers the voltage supplied from the driver 16 to one block BLK selected based on the block address received from the register 13.

[0022] The sense amplifier 18 is a circuit that determines the data stored in the memory cell array 10. The sense amplifier 18 senses the state of the memory cell transistor MT, and generates read data based on the sensed state, or transfers write data to the memory cell transistor MT.

[0023] The data register 19 is a circuit that holds data for input and output by the memory device 1. The data register 19 receives data DAT received by the memory device 1 and supplies data based on the received data DAT to the sense amplifier 18. The data register 19 receives data from the sense amplifier 18 and supplies data DAT based on the received data to the input / output circuit 11.

[0024] 1.1.1.Memory Cell Array 2 shows the components and connections of one block of the storage device of Embodiment 1. A plurality of blocks BLK, for example, all blocks BLK, include the components and connections shown in FIG.

[0025] One block BLK includes a plurality of string units SU. Figure 2 shows an example of five string units SU_0 to SU_4.

[0026] 2, m bit lines BL_0 to BL_m-1 are each connected to one NAND string NS from each of the string units SU_0 to SU_4 in each block BLK, where m is a positive integer.

[0027] Each NAND string NS includes one select gate transistor ST, n memory cell transistors MT (MT_0 to MT_n-1), and one select gate transistor DT (DT0, DT1, DT2, DT3, or DT4), where n is a positive integer. The memory cell transistor MT is an element that stores data in a non-volatile manner. The memory cell transistor MT includes a control gate electrode or gate electrode (word line WL) and a charge storage film insulated from the surroundings, and stores data in a non-volatile manner based on the charge in the charge storage film. Data is written to the memory cell transistor MT by injecting electrons into the charge storage film.

[0028] The select gate transistor ST, the memory cell transistors MT_0 to MT_n-1, and the select gate transistor DT are connected in series in this order between a source line SL and one bit line BL.

[0029] A plurality of NAND strings NS connected to different bit lines BL respectively constitute one string unit SU. In each string unit SU, the control gate electrodes of memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. A set of memory cell transistors MT sharing a word line WL in one string unit SU is called a cell unit CU.

[0030] The select gate transistors DT0 to DT4 belong to the string units SU_0 to SU_4, respectively. The select gate transistors DT2, DT3, and DT4 are omitted from FIG. 2. The gate of the select gate transistor DT0 of each of the multiple NAND strings NS in the string unit SU_0 is connected to a select gate line SGDL0. Similarly, the gates of the select gate transistors DT1, DT2, DT3, and DT4 of each of the multiple NAND strings NS in the string units SU_1, SU_2, SU_3, and SU_4 are connected to select gate lines SGDL1, SGDL2, SGDL3, and SGDL4, respectively.

[0031] The gate of the select gate transistor ST is connected to a select gate line SGSL.

[0032] 1.1.2. Storage Structure Figure 3 shows the external appearance of the storage device of the first embodiment. As shown in Figure 3, the storage device 1 includes a first structure 100, a second structure 200, and a third structure 300 that are aligned along the z-axis. The first structure 100, the second structure 200, and the third structure 300 extend along the xy plane and are aligned along the z-axis. The second structure 200 is located on the top surface of the first structure 100. The third structure 300 is located on the top surface of the second structure 200.

[0033] The first structure 100, the second structure 200, and the third structure 300 each include a plurality of semiconductors, a plurality of various conductors, and a plurality of insulators formed on a substrate using a substrate. The first structure 100, the second structure 200, and the third structure 300 each include a plurality of elements and wiring realized by the semiconductors, conductors, and insulators. The first structure 100, the second structure 200, and the third structure 300 each include an electrical circuit including elements and wiring. The elements and wiring in the first structure 100, the elements and wiring in the second structure 200, and the elements and wiring in the third structure 300 are electrically connected to each other.

[0034] The set of the first structure 100 and the second structure 200 includes an input / output circuit 11, a logic controller 12, a register 13, a sequencer 14, a voltage generation circuit 15, a driver 16, a row decoder 17, a sense amplifier 18, and a data register 19. The first structure 100 may include any of the input / output circuit 11, the logic controller 12, the register 13, the sequencer 14, the voltage generation circuit 15, the driver 16, the row decoder 17, the sense amplifier 18, and the data register 19. The second structure 200 may include any of the input / output circuit 11, the logic controller 12, the register 13, the sequencer 14, the voltage generation circuit 15, the driver 16, the row decoder 17, the sense amplifier 18, and the data register 19.

[0035] The third structure 300 includes a memory cell array 10 and a plurality of external connection terminals PD. The external connection terminals PD are exposed on the top surface of the third structure 300.

[0036] 4 shows an example of the structure of a surface of a part of the storage device of the first embodiment. FIG. 4 shows an exploded view of the structure of FIG.

[0037] 4, the first structure 100 includes a plurality of conductive bond terminals BD1. The bond terminals BD1 are exposed on the top surface of the first structure 100. The bond terminals BD1 are connected to elements in the first structure 100.

[0038] The second structure 200 includes a plurality of conductive junction terminals BD2L and a plurality of conductive junction terminals BD2U. The junction terminals BD2L are exposed on the bottom surface of the second structure 200. The junction terminals BD2L are connected to elements in the second structure 200. The junction terminals BD2L have the same layout as the junction terminals BD1 of the first structure 100. The junction terminals BD2L are arranged so that, when the first structure 100 and the second structure 200 are joined, each junction terminal BD2L contacts one of the junction terminals BD1 of the first structure 100 that corresponds to the junction terminal BD2L. A specific junction terminal BD2L and one of the junction terminals BD1 of the first structure 100 that corresponds to the specific junction terminal BD2L are elements that function as the same node in a circuit.

[0039] The bonding terminal BD2U is exposed on the upper surface of the second structure 200. The bonding terminal BD2U is connected to an element in the second structure 200.

[0040] The third structure 300 includes a plurality of conductive bond terminals BD3. The bond terminals BD3 are exposed on the bottom surface of the third structure 300. The bond terminals BD3 are connected to elements in the third structure 300. The bond terminals BD3 have the same layout as the bond terminals BD2U of the second structure 200. The bond terminals BD3 are arranged so that, when the second structure 200 and the third structure 300 are bonded together, each bond terminal BD3 contacts one of the bond terminals BD2U of the second structure 200 that corresponds to the particular bond terminal BD3. A particular bond terminal BD3 and one of the bond terminals BD2U of the second structure 200 that corresponds to the particular bond terminal BD3 are elements that function as the same node in a circuit.

[0041] 5 shows an example of a cross-sectional structure of a portion of the memory device of the first embodiment. As shown in FIG. 5, the memory device 1 includes a connection area PA. The connection area PA is an area where conductors electrically connected to the external connection terminals PD are located. The connection area PA extends along the x-axis, y-axis, and z-axis.

[0042] The first structure 100 further includes a substrate W1, an STI structure, a transistor Tr1, contacts CS1, C0, C1, C2, and C3, conductors L0, L1, and L2, and insulators 21 and 22. In the following description, a conductor also includes a semiconductor that is conductive due to containing impurities. In one example, the substrate W1 includes silicon. In one example, the contacts CS1, C0, C1, C2, and C3 and the conductors L0, L1, and L2 include copper or tungsten. In one example, the insulators 21 and 22 include silicon oxide.

[0043] The structure STI will be simply referred to as STI hereinafter. The STI extends in the substrate W1 along the z-axis from the top surface of the substrate W1. In one example, the STI includes silicon oxide.

[0044] Transistor Tr1 is located in a region above and near the top surface of substrate W1 and includes a gate insulator on the top surface of substrate W1, a gate electrode on the top surface of the gate insulator, and a pair of source / drain regions sandwiching a region below the gate electrode.

[0045] Each contact C0 has a lower surface in contact with the upper surface of the gate electrode of one transistor Tr1, and each contact CS1 has a lower surface in contact with one source / drain region.

[0046] Each conductor L0 is in contact with one contact C0 or CS1 on the bottom surface.

[0047] Each contact C1 is in contact at its lower surface with the upper surface of one of the conductors L0. Each of the contacts C1 in the connection area PA is in contact at its lower surface with the upper surface of one of the conductors L0.

[0048] The lower surface of each conductor L1 contacts the upper surface of one contact C1. The lower surface of one conductor L1 in the connection area PA contacts the upper surfaces of the plurality of contacts C1.

[0049] Each contact C2 has its lower surface in contact with the upper surface of one of the conductors L1. Each of the contacts C2 in the connection area PA has its lower surface in contact with the upper surface of one of the conductors L1.

[0050] The lower surface of each conductor L2 contacts the upper surface of one contact C2. The lower surface of one conductor L2 in the connection area PA contacts the upper surfaces of the plurality of contacts C2.

[0051] Each contact C3 has its lower surface in contact with the upper surface of one of the conductors L2. Each of the contacts C3 in the connection area PA has its lower surface in contact with the upper surface of one of the conductors L2.

[0052] The set of transistor Tr1, contacts CS1, C0, C1, C2, and C3, and conductors L0, L1, and L2 implements a circuit included in the first structure 100. Thus, the first structure 100 has transistor Tr1, contacts CS1, C0, C1, C2, and C3, and conductors L0, L1, and L2 in any shape and arrangement that implements the circuit included in the first structure 100.

[0053] The insulator 21 extends from the height of the upper surface of the substrate W1 to the height of the upper surface of the contact C3 and fills the regions of the first structure 100 that do not include components, i.e., the transistor Tr1, the contacts CS1, C0, C1, C2, and C3, and the conductors L0, L1, and L2.

[0054] The bottom surface of each bonding terminal BD1 contacts the top surface of one of the contacts C3. The insulator 22 fills in the region of the layer in which the bonding terminals BD1 are located, where the bonding terminals BD1 are not provided.

[0055] The second structure 200 further includes a substrate W2, an STI structure, a transistor Tr2, contacts CS2, CS5, C4, C5, C7, C8, C9, C10, and C3, conductors L3, L4, L5, and L6, and insulators 24, 25, 26, and 27. In one example, the substrate W2 includes silicon. In one example, the contacts CS2, CS5, C4, C5, C7, C8, C9, C10, and C3, and the conductors L3, L4, L5, and L6 include copper or tungsten. In one example, the insulators 24, 25, 26, and 27 include silicon dioxide.

[0056] Each bonding terminal BD2L is located on the bottom layer of the second structure 200. The insulator 24 fills in the region of the layer on which the bonding terminals BD2L are located, where the bonding terminals BD2L are not provided.

[0057] The lower surface of each contact C4 comes into contact with the upper surface of one bonding terminal BD2L.

[0058] The lower surface of each conductor L3 contacts the upper surface of one contact C4. The lower surface of one conductor L3 in the connection region PA contacts the upper surfaces of the plurality of contacts C4.

[0059] Each contact C5 has its lower surface in contact with the upper surface of one of the conductors L3. Each of the contacts C5 in the connection area PA has its lower surface in contact with the upper surface of one of the conductors L3.

[0060] The insulator 25 extends from the height of the upper surfaces of the bonding terminal BD2L and the insulator 24 to the height of the upper surface of the contact C5. The insulator 25 fills the region above the bonding terminal BD2L and the insulator 24 where the contacts C4 and C5 and the conductor L3 are not provided. In one example, the insulator 25 includes silicon oxide.

[0061] Substrate W2 is located on the upper surface of insulator 25. The STI penetrates substrate W2 across the upper and lower surfaces of substrate W2.

[0062] The vias TS penetrate the substrate W2 from the top surface to the bottom surface of the substrate W2. Each via TS contacts the top surface of one contact C5 at its bottom surface.

[0063] The insulators SP1 penetrate the substrate W2 across the upper and lower surfaces of the substrate W2. Each insulator SP1 covers the side surface of one via TS.

[0064] The isolation structure DS electrically separates an area of ​​the substrate W2 surrounded by the isolation structure DS from an area of ​​the substrate W2 outside the area surrounded by the isolation structure DS. The isolation structure DS surrounds multiple sets of vias TS and insulators SP1 in the connection area PA. The isolation structure DS penetrates the substrate W2 across the upper and lower surfaces of the substrate W2. The isolation structure DS includes an insulator, and in one example, includes silicon oxide.

[0065] Transistor Tr2 is located in a region above and near the top surface of substrate W2 and includes a gate insulator on the top surface of substrate W2, a gate electrode on the top surface of the gate insulator, and a pair of source / drain regions sandwiching a region below the gate electrode.

[0066] Each contact C7 contacts the upper surface of the gate electrode of one transistor Tr2 at its lower surface, each contact CS2 contacts the source / drain region at its lower surface, and each contact CS5 contacts the upper surface of one via TS at its lower surface.

[0067] The lower surface of each conductor L4 contacts the upper surface of one of the contacts C7, CS2, or CS5. The lower surface of one conductor L4 in the connection region PA contacts the upper surface of each of the multiple contacts CS5.

[0068] Each contact C8 has its lower surface in contact with the upper surface of one of the conductors L4. Each of the contacts C8 in the connection area PA has its lower surface in contact with the upper surface of one of the conductors L4.

[0069] The lower surface of each conductor L5 contacts the upper surface of one contact C8. The lower surface of one conductor L5 in the connection region PA contacts the upper surfaces of the plurality of contacts C8, respectively.

[0070] Each contact C9 has its lower surface in contact with the upper surface of one of the conductors L5. Each of the contacts C9 in the connection area PA has its lower surface in contact with the upper surface of one of the conductors L5.

[0071] The lower surface of each conductor L6 contacts the upper surface of one contact C9. The lower surface of one conductor L6 in the connection region PA contacts the upper surfaces of the plurality of contacts C9, respectively.

[0072] Each contact C10 has its lower surface in contact with the upper surface of one of the conductors L6. Each of the contacts C10 in the connection area PA has its lower surface in contact with the upper surface of one of the conductors L6.

[0073] The set of transistor Tr2, contacts CS2, CS5, C7, C8, C9, and C10, and conductors L4, L5, and L6 implements a circuit included in second structure 200. Thus, second structure 200 has transistor Tr2, transistor Tr2, contacts CS2, CS5, C7, C8, C9, and C10, and conductors L4, L5, and L6 in any shape and arrangement that implements the circuit included in second structure 200.

[0074] The insulator 26 extends from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10. The insulator 26 fills the region from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10 where no components are provided, i.e., the region where the transistor Tr2, the transistor Tr2, the contacts CS2, CS5, C7, C8, C9, and C10, and the conductors L4, L5, and L6 are not provided.

[0075] The bottom surface of each bonding terminal BD2U contacts the top surface of one of the contacts C10. The insulator 27 fills in the region of the layer in which the bonding terminals BD2U are located, where the bonding terminals BD2U are not provided.

[0076] The third structure 300 further includes contacts C11, C12, and C13, conductors L7, L8, 31, 33, 36, 38, insulators 29, 34, 35, 37, 40, 41, and memory pillar MP.

[0077] Each bonding terminal BD3 is located on the bottom layer of the third structure 300. The insulator 29 fills in the region of the layer on which the bonding terminals BD3 are located, where the bonding terminals BD3 are not provided.

[0078] The lower surface of each contact C11 comes into contact with the upper surface of one of the bonding terminals BD3.

[0079] The lower surface of each conductor L7 contacts the upper surface of one contact C11. The lower surface of one conductor L7 in the connection region PA contacts the upper surfaces of the plurality of contacts C11, respectively.

[0080] The lower surface of each contact C12 is in contact with the upper surface of one of the conductors L7. The lower surfaces of the contacts C12 in the connection area PA are in contact with the upper surface of one of the conductors L7.

[0081] The lower surface of each conductor L8 contacts the upper surface of one contact C12. The lower surface of one conductor L8 in the connection region PA contacts the upper surfaces of the plurality of contacts C12, respectively.

[0082] The conductor 31 is located above the conductor L8. The conductor 31 has a plate-like shape along the xy plane. The conductor 31 functions as at least a part of the select gate line SGDL. The lower surface of the conductor 31 is exposed at the end and has a terrace.

[0083] The insulator 32 is located on the upper surface of the conductor 31. The insulator 32 has a plate shape along the xy plane.

[0084] The conductors 33 and insulators 34 are alternately stacked one by one on the upper surface of the insulator 32. The conductors 33 and insulators 34 have a plate-like shape along the xy plane. Each conductor 33 functions as at least a part of a word line WL. FIG. 5 shows an example where n, that is, the number of memory cell transistors MT, is 8. The conductors 33 function as at least a part of word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7, in order from the bottom up. The lower surface of each conductor 33 is exposed at the edge and has a terrace.

[0085] An insulator 35 is located on top of the top conductor 33 .

[0086] The conductor 36 is located on the upper surface of the insulator 35. The conductor 36 functions as at least a part of the select gate line SGSL.

[0087] Insulator 37 is located on the upper surface of conductor 36. Conductor 38 is located on the upper surface of insulator 37. The lower surface of conductor 38 is exposed at the end and has a terrace.

[0088] The memory pillar MP extends along the z-axis and penetrates a set of conductors 31, 33, and 36 and insulators 32, 34, 35, and 37. Each memory pillar MP includes an insulator CI, a semiconductor SM, and a stack SS. The semiconductor SM covers the side surface of the insulator CI. The stack SS covers the side surface of the semiconductor SM. The stack SS has an opening at the top end of the memory pillar MP. A portion of the semiconductor SM is located in the opening and contacts the conductor 38 on the top surface.

[0089] The upper portion of the memory pillar MP may be located in the conductor 38, the stacked body SS may have an opening at the portion facing the conductor 38, and part of the semiconductor SM may be located in the opening.

[0090] 6 shows an example of a cross-sectional structure along the xy plane of a memory pillar of the memory device according to the first embodiment. As shown in FIG. 6, in one example, the stacked body SS includes a tunnel insulator TI, a charge storage film CA, and a block insulator BI.

[0091] A tunnel insulator TI surrounds the side of the semiconductor SM. A charge storage film CA surrounds the side of the tunnel insulator TI. A block insulator BI surrounds the side of the charge storage film CA. A conductor 31, 33, or 36 surrounds the side of the block insulator BI.

[0092] The semiconductor SM functions as a channel (current path) for the memory cell transistor MT and the select gate transistors DT and ST. The tunnel insulator TI and the block insulator BI each contain, for example, silicon oxide. The charge storage film CA stores charges. The charge storage film CA contains, for example, silicon nitride.

[0093] Returning to FIG. 5, the portion of each memory pillar MP that faces the conductor 31 functions as one select gate transistor DT. The portion of each memory pillar MP that faces the conductor 33 functions as one memory cell transistor MT. The portion of each memory pillar MP that faces the conductor 36 functions as one select gate transistor ST. The lower surface of the semiconductor SM is exposed at the lower surface of each memory pillar MP. The lower surface of the semiconductor SM is exposed at the upper surface of each memory pillar MP.

[0094] Each contact C13 contacts the upper surface of one conductor L8 at its lower surface. The contacts C13 in the connection region PA contact the upper surface of one conductor L8 at their respective lower surfaces. Some of the contacts C13 each contact the lower surface of the semiconductor SM of one memory pillar MP at their upper surface. Some of the contacts C13 each contact the lower surface of the terrace portion of one of the conductors 31, 33, and 37 at their upper surface.

[0095] The insulator 40 extends from the height of the upper surface of the insulator 29 to the height of the upper surface of the conductor 38. The insulator 40 fills the area of ​​the third structure 300 where no components are provided, i.e., contacts C11, C12, and C13, conductors L7, L8, 31, 33, 36, and 38, insulators 40, 32, 34, 35, and 37, and memory pillar MP are provided.

[0096] The insulator 41 is located on the upper surfaces of the conductor 38 and the insulator 40. The insulator 41 has an opening OG in the connection region PA. The opening OG extends from the upper surface to the lower surface of the insulator 41. The opening OG reaches the plurality of contacts C13 in the connection region PA. The opening OG has an external connection terminal PD1 therein. In one example, the external connection terminal PD is any one of external connection terminals PD_D0, PD_D1, PD_D2, PD_D3, PD_D4, PD_D5, PD_D6, and PD_D7 that transmit and receive input / output signals DQ. The external connection terminal PD is in contact at its lower surface with the upper surfaces of the plurality of contacts C13.

[0097] In the third structure 300, the portion from the layer of the insulator 29 and the bonding terminal BD3 to the layer of the conductor 38 may be referred to as a first portion 300a of the third structure 300 hereinafter.

[0098] 1.1.3. Structure of the Connection Area 7 shows an example of the cross-sectional structure of a portion of the memory device of the first embodiment. Fig. 7 shows an enlarged view of the region where the vias TS are provided in the substrate W2 in Fig. 5 (i.e., the connection region PA) and the regions above and below it.

[0099] 7, the conductor L3 and the contact C5 have an inverse tapered shape. A component having an inverse tapered shape means that a certain length (or width) of the component along the xy plane increases from the top end to the bottom end of the component. That is, the length (or width) of the top end of the component along a certain imaginary straight line is greater than the length (or width) of the bottom end of the component along the same imaginary straight line.

[0100] The isolation structure DS has an inverted tapered shape. As will be described later with reference to Fig. 8, the isolation structure DS extends along the xy plane. The length of the isolation structure DS in a direction (X direction or Y direction) intersecting the direction in which the isolation structure DS extends increases from the upper end to the lower end.

[0101] The via TS has a tapered shape. A certain component has a tapered shape when a certain length (or width) of the component along the xy plane decreases from the top end to the bottom end of the component. In other words, the length (or width) of the top end of the component along a certain imaginary straight line is smaller than the length (or width) of the bottom end of the component along the same imaginary straight line.

[0102] The contact CS5 and the conductor L4 have a tapered shape.

[0103] Fig. 8 is a plan view of a portion of the memory device of Embodiment 1. Fig. 8 shows the structure of the region of the substrate W2 where the vias TS are provided (that is, the connection region PA) as viewed from the Z direction.

[0104] As described above with reference to Figure 6 and shown in Figure 8, a plurality of sets of vias TS and insulators SP1 are provided, which exemplarily show the sets arranged in a matrix of five rows along the x-axis and five columns along the y-axis.

[0105] The isolation structure DS surrounds the pair of vias TS and insulators SP1 along the xy plane. The isolation structure DS has a linear shape and extends continuously along the xy plane. Due to this structure of the isolation structure DS, the isolation structure DS electrically separates the portion of the substrate W2 surrounded by the separation structure (i.e., the inner portion) from the portion of the substrate W2 outside the separation structure. The width of the isolation structure DS, i.e., the length (or width) along an imaginary line intersecting the extension direction of the separation structure, is large enough to sufficiently suppress the capacitance (electrostatic capacitance) between the inner and outer regions of the isolation structure DS. The larger the width, the more the capacitance is suppressed, but this leads to an increase in the area of ​​the memory device 1. Therefore, the isolation structure DS has a width determined based on the capacitance suppression by the isolation structure DS and the allowable area of ​​the separation structure WS.

[0106] 1.2. Manufacturing method 9 shows an example of a flow of the manufacturing method of the memory device of the first embodiment. As shown in FIG. 9, the first structure 100, a structure including a part of the second structure 200, and a first portion 300a of the third structure 300 are formed (step ST1). The first structure 100, the structure including a part of the second structure 200, and the first portion 300a of the third structure 300 are formed by separate processes.

[0107] In one example, the first structure 100 is formed by forming components located further in the Z direction than the substrate W1 on the substrate W1 in order in the Z direction.

[0108] The structure including a portion of the second structure 200 includes the structure from the substrate W2 to the bonding terminal BD2L and the insulator 24. In one example, the structure including a portion of the second structure 200 is formed by the following method. First, the substrate W2 is prepared in a state in which it is inverted with respect to the xy plane from the orientation shown in FIG. 5, i.e., with the top side shown in FIG. 5 facing downward. Next, the structure from the substrate W2 to the bonding terminal BD2L and the insulator 24 is formed on the top surface (the bottom surface in FIG. 5) of the substrate W2.

[0109] In one example, the first portion 300a of the third structure 300 is formed by the following method. First, a substrate W3 (not shown) is prepared. Next, a structure is formed on the upper surface of the substrate W3 that is inverted with respect to the xy plane from the orientation of the first portion 300a shown in FIG. 5, i.e., a structure with the top side of the structure shown in FIG. 5 facing downward. In one example, the portion of the structure closer to the substrate W3 is formed first.

[0110] The first structure 100 and a structure including a portion of the second structure 200 are bonded (or pasted together) (step ST2). The bonding is performed such that the bonding terminal BD1 of the first structure 100 and the bonding terminal BD2L of the structure including a portion of the second structure 200 are in contact with each other, with the structure including a portion of the second structure 200 inverted with respect to the xy plane.

[0111] The remaining portion of the second structure 200 is formed (step ST3). The method of forming the remaining portion of the second structure 200 will be described in detail later. The formation includes forming the bonding terminal BD2U of the second structure 200.

[0112] The second structure 200 and the first portion 300a of the third structure 300 are bonded (or pasted together) (step ST4). The bonding is performed such that the bonding terminal BD2U of the second structure 200 and the bonding terminal BD3 of the first portion 300a of the third structure 300 are in contact with each other, with the first portion 300a of the third structure 300 inverted with respect to the xy plane.

[0113] The substrate W3 on which the third structure 300 has been formed is removed (step ST5). An example of the removal includes CMP (Chemical Mechanical Polishing). The substrate W3 may be left without being removed, but only thinned.

[0114] The remaining portions of the third structure 300 are formed (step ST4), resulting in the structure shown in FIG.

[0115] 1.2.1. Method of Manufacturing the Second Structure 10 to 15 show an example of a state during the manufacture of a part of the memory device of the first embodiment. 10 to 15 show an example of a state during the manufacture of the second structure 200.

[0116] FIG. 10 shows a process performed as part of step ST1 of the flow of FIG. 9. As shown in FIG. 10, a substrate W2 is prepared in a state inverted with respect to the xy plane from the orientation shown in FIG. 5, i.e., with the top side facing downward as shown in FIG. 5. STI and isolation structures DS are formed in a region including the upper surface (i.e., the lower surface in FIG. 5) of the substrate W2. In one example, the STI and isolation structures DS are formed by a common process. That is, a trench is formed in a region including the upper surface of the substrate W2 by a combination of a lithography process and anisotropic etching. An example of an etching method includes RIE (Reactive Ion Etching). The trench is then filled with the material of the STI and isolation structures DS. Due to the use of anisotropic etching, the STI and isolation structures DS have a tapered shape.

[0117] Above the substrate W2, a structure from the upper surface of the substrate W2 to the layer of the bonding terminal BD2L and the insulator 24, that is, contacts C5 and C4, conductor L3, bonding terminal BD2L, and insulators 25 and 24, is formed.

[0118] 11 to 15 show processes performed as part of step ST3 of the flow of FIG. 9. As shown in FIG. 11, the structure formed by the processes up to this point, i.e., the structure including part of the second structure 200, is inverted with respect to the xy plane. As a result, the isolation structure DS has an inverted tapered shape. Next, the substrate W2 is thinned by partially removing the top surface (the surface opposite to the side where the insulator 25 is located). An example of a removal method includes CMP (Chemical Mechanical Polishing). The removal is performed until the STI and the isolation structure DS are exposed.

[0119] As shown in FIG. 12, a transistor Tr2 is formed.

[0120] As shown in FIG. 13, openings OP1 are formed by partially removing the substrate W2. Each opening OP1 is formed in an area where a pair of vias TS and insulators SP1 are to be formed. Each opening OP1 reaches from the upper surface to the lower surface of the substrate W2. Each opening OP1 exposes the upper surface of each contact C5 and a portion of the upper surface of the insulator 25. An example of a method for forming the openings OP1 includes a combination of a lithography process and an anisotropic etching process such as RIE. The openings OP1 have a tapered shape due to the use of anisotropic etching.

[0121] 14, an insulator SP1 is formed on the side surface of the opening OP1, i.e., on the portion of the surface of the substrate W2 exposed by the opening OP1. Specifically, first, the insulator SP1 is deposited over the side surface and bottom surface of the opening OP1, i.e., over the surface of the substrate W2 and the portion of the surface of the insulator 25 exposed in the opening OP1, as well as over the upper surface of the contact C5. An example of the deposition method includes CVD (Chemical Vapor Deposition). Next, the portion of the insulator SP1 on the bottom surface of the opening OP1 is removed by a combination of a lithography process and anisotropic etching such as RIE.

[0122] 15, the remaining portion of the opening OP1 is filled with the via TS. Based on the shape of the opening OP1, each pair of the via TS and the insulator SP1 has a tapered shape.

[0123] 5, the remaining portion of the second structure 200, that is, the structure from the substrate W to the bonding terminal BD2U and the layer of the insulator 27, is formed. In this way, the second structure 200 is obtained.

[0124] 1.3.Advantages (Effects) According to the first embodiment, as described below, a storage device capable of operating at high speed can be provided.

[0125] To increase the capacity of a memory device, the memory device may include multiple joined structures, such as a first structure 100, a second structure 200, and a third structure 300. In such structures, to electrically connect components in the separate structures, one of the structures must include a via, such as a via TS, penetrating the substrate. These vias form parasitic capacitance with the substrate surrounding the via. Parasitic capacitance reduces the speed of signals passing through the via. The demand for high-speed operation of memory devices, particularly the requirements for input / output signals, increases, resulting in a significant impact of parasitic capacitance. Without the isolation structures DS of the first embodiment, each via TS would have parasitic capacitance formed with the rest of the substrate W2. Furthermore, because the insulator SP1 is thin, the parasitic capacitance of each via TS is large. While the parasitic capacitance can be reduced by thickening the insulator SP1 around the via TS, the area of ​​the insulator SP1 must be significantly increased to achieve sufficient parasitic capacitance reduction. Increasing the thickness of the insulator SP1 may also require increasing the spacing between the vias TS.

[0126] According to the first embodiment, an isolation structure DS is provided to surround a plurality of vias TS connected in parallel. Therefore, the region inside the isolation structure DS (i.e., the region where the vias TS are located) and the region outside the isolation structure DS on the substrate W2 are electrically isolated. This isolates the capacitance formed by the region outside the isolation structure DS from the inner region. This reduces the parasitic capacitance of the vias TS. This makes it possible to provide a memory device 1 that can operate at high speed.

[0127] Furthermore, according to the first embodiment, the isolation structure DS surrounds multiple vias TS. Therefore, by newly providing one isolation structure DS, the parasitic capacitance of multiple vias TS can be reduced. Therefore, by providing a wide isolation structure DS, the parasitic capacitance can be significantly reduced while suppressing an increase in area due to the provision of the new isolation structure DS.

[0128] 1.4. Variations 1.4.1. First Variant 16 and 17 are plan views of a portion of a memory device according to a first modified example of the first embodiment. Each of the figures shows the structure of the region of the substrate W2 where the vias TS are provided (i.e., the connection region PA) as viewed from the Z direction.

[0129] 16 and 17, the isolation structures DS may be arranged in multiple layers. That is, in the example of Fig. 16, an isolation structure DS2 is further provided, and the isolation structure DS2 surrounds the isolation structure DS2 along the xy plane. In the example of Fig. 17, one isolation structure DS2 surrounds multiple isolation structures DS along the xy plane. Also, in the example of Fig. 17, some pairs of vias TS and insulators SP1 are not surrounded by an isolation structure DS, but are surrounded by one isolation structure DS2.

[0130] 1.4.2. Second Variant The orientations of the first structure 100, the second structure 200, and the third structure 300 are not limited to those shown in FIGS. 3 and 5, and may be any orientation.

[0131] 18 shows an example of a cross-sectional structure of a portion of a memory device according to a second modification of the first embodiment. As shown in FIG. 18, the second structure 200 has an orientation opposite to that shown in FIG. 5 with respect to the xy plane. That is, each conductor L4 contacts the upper surface of one contact C5 at its lower surface. One conductor L4 in the connection region PA contacts the upper surfaces of the multiple contacts C5 at its lower surface.

[0132] Each contact C6 has its lower surface in contact with the upper surface of one of the conductors L4. Each of the contacts C6 in the connection area PA has its lower surface in contact with the upper surface of one of the conductors L4.

[0133] The lower surface of each conductor L5 contacts the upper surface of one contact C6. The lower surface of one conductor L5 in the connection region PA contacts the upper surfaces of the plurality of contacts C6, respectively.

[0134] Each contact CS2 contacts the upper surface of one of the conductors L5 at its lower surface. Each contact CS5 contacts the upper surface of one of the conductors L5 at its lower surface. Each of the multiple contacts CS5 in the connection area PA contacts the upper surface of one of the conductors L4 at its lower surface.

[0135] Substrate W2 is located in a layer above the layer of contacts CS2 and CS5.

[0136] Transistor Tr2 is located in a region below and near the bottom surface of substrate W2. Transistor Tr2 includes a gate insulator on the bottom surface of substrate W2, a gate electrode on the bottom surface of the gate insulator, and a pair of source / drain regions sandwiching a region above the gate electrode. Each gate electrode contacts the top surface of one contact C7 at its bottom surface. Each source / drain region contacts the top surface of one contact CS2 at its bottom surface.

[0137] The bottom surface of each via TS is in contact with the top surface of one contact CS5.

[0138] The insulator 25 extends from the height of the upper surface of the junction terminal BD2L and the upper surface of the insulator 24 to the height of the upper surface of the contact C8. The insulator 25 fills in the region above the junction terminal BD2L and the insulator 24, in a region where the contacts C4, C5, C6, C7, CS2, and CS5, the conductors L3, L4, and L5, and the transistor Tr2 are not provided.

[0139] The bottom surface of each contact C9 is in contact with the top surface of one via TS.

[0140] The lower surface of each conductor L6 contacts the upper surface of one contact C9. The lower surface of one conductor L6 in the connection region PA contacts the upper surfaces of the plurality of contacts C9, respectively.

[0141] Each contact C10 has its lower surface in contact with the upper surface of one of the conductors L6. Each of the contacts C10 in the connection area PA has its lower surface in contact with the upper surface of one of the conductors L6.

[0142] The insulator 26 extends from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10. The insulator 26 fills the region from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10 where no components are provided, i.e., the region where the contacts C9 and C10 and the conductor L6 are not provided.

[0143] The lower surface of each bonding terminal BD2U contacts the upper surface of one contact C10.

[0144] 1.4.3. Third Variant The arrangement of the first structure 100, the second structure 200, and the third structure 300 is not limited to that shown in FIGS. 3 and 5, and may be any arrangement.

[0145] 19 shows an example of the cross-sectional structure of a portion of a memory device according to a third modification of the first embodiment. As shown in Fig. 19, a third structure 300 is located on the upper surface of the first structure 100, and a second structure 200 is located on the upper surface of the third structure 300. The second structure 200 has the same orientation as the second structure 200 in the second modification.

[0146] The third structure 300 includes a bonding terminal BD3L instead of the bonding terminal BD3, and further includes a bonding terminal BD3U instead of the external connection terminal PD. The third structure 300 further includes a contact C15, a conductor L10, and an insulator 45.

[0147] The lower surface of each contact C11 comes into contact with the upper surface of one of the bonding terminals BD3L.

[0148] The upper surfaces of the plurality of contacts C13 in the connection area PA contact the lower surface of one conductor L8 instead of the external connection terminal PD.

[0149] The lower surface of the contact C15 contacts the upper surface of one of the conductors L10. The lower surfaces of the plurality of contacts C15 in the connection area PA contact one of the conductors L10.

[0150] The upper surface of each contact C15 comes into contact with the lower surface of one of the joining terminals BD3U.

[0151] The insulator 45 fills in the region of the layer in which the bonding terminal BD3U is located, where the bonding terminal BD3U is not provided.

[0152] The upper surface of each bonding terminal BD3U contacts the lower surface of one bonding terminal BD2L.

[0153] The second structure 200 further includes external connection terminals PD and an insulator 41. The lower surface of each external connection terminal PD is in contact with the upper surface of each of the plurality of contacts C10.

[0154] 2. Second embodiment Fig. 20 shows an example of a cross-sectional structure of a portion of the second embodiment, which shows the same area as Fig. 7 of the first embodiment.

[0155] As shown in FIG. 20 , each isolation structure DS includes a first portion DSA and a second portion DSB. The first portion DSA occupies a lower portion including a lower surface of the isolation structure DS. The second portion DSB is located on an upper surface of the first portion DSA. The second portion DSB occupies a portion including an upper surface of the isolation structure DS. The first portion DSA has an inverted tapered shape. The second portion DSB has a tapered shape. In one example, the first portion DSA and the second portion DSB include silicon oxide.

[0156] The overall flow of the manufacturing method for the memory device structure of the second embodiment is the same as the flow of the first embodiment shown in FIG.

[0157] 21 to 25 sequentially show an example of a state during the manufacture of a part of a memory device according to the second embodiment. 21 to 25 sequentially show an example of a state during the manufacture of a second structure 200. Differences from the first embodiment will be described below.

[0158] 21 shows a process performed as part of step ST1 of the flow of FIG. 9. In the process shown in FIG. 21, a first portion DSA of the isolation structure DS is formed in the connection region PA, instead of the isolation structure DS in the process shown in FIG. 5. An example of a formation method includes, similar to the formation of STI, forming a trench by a combination of a lithography process and anisotropic etching, and filling the trench with a material for the first portion DSA. Due to the use of anisotropic etching, the first portion DSA of the isolation structure DS has a tapered shape.

[0159] 22 to 25 show processes performed as part of step ST3 of the flow in FIG. 9. As shown in FIG. 22, the structure formed by the processes up to this point, i.e., the structure including part of the second structure 200, is inverted with respect to the xy plane and bonded to the first structure 100. As a result, the first portion DSAS of the isolation structure DS has an inverted tapered shape. Next, the transistor Tr2 is formed.

[0160] The via TS and the insulator SP1 are formed as shown in Fig. 23. The method for forming the via TS and the insulator SP1 is the same as the method described above with reference to Figs. 13 to 15 in the first embodiment.

[0161] As shown in FIG. 24, openings OP2 are formed by partially removing the substrate W2. Each opening OP2 is formed in a region where the second portion DSB of the isolation structure DS is to be formed. Each opening OP2 reaches from the upper surface of the substrate W2 to the upper surface of the first portion DSA of the isolation structure DS. An example of a method for forming the openings OP2 includes a combination of a lithography process and anisotropic etching such as RIE. The openings OP2 have a tapered shape due to the use of anisotropic etching.

[0162] 25, the opening OP2 is filled with the material of the second portion DSB of the isolation structure DS, thereby completing the isolation structure DS.

[0163] The subsequent steps are the same as those in the first embodiment.

[0164] The step described above with reference to Figure 24 may be performed before the step described above with reference to Figure 23, i.e., opening OP2 is formed, followed by via TS and insulator SP1.

[0165] The isolation structure DS may include only the second portion DSB. Fig. 26 shows an example of the cross-sectional structure of a portion of a memory device according to a modified example of the second embodiment. Fig. 26 shows the same area as Fig. 20 and Fig. 7 of the first embodiment. As shown in Fig. 26, the isolation structure DS includes the second portion DSB that extends from the upper surface to the lower surface of the substrate W2.

[0166] The structure of FIG. 26 can be formed by the following manufacturing process. FIGS. 27 to 31 sequentially show an example of a state during the manufacture of a portion of a memory device according to a modification of the second embodiment. FIGS. 27 to 31 sequentially show an example of a state during the manufacture of a second structure 200 according to the modification. Differences from the first embodiment will be described below.

[0167] Fig. 27 shows a process performed as part of step ST1 in the flow of Fig. 9. In the process shown in Fig. 27, the isolation structure DS is not formed in the connection region PA. It is a structure that includes a part of the second structure 200.

[0168] 28 to 31 show processes performed as part of step ST3 of the flow in Fig. 9. As shown in Fig. 28, the structure formed by the processes up to this point, i.e., the structure including part of the second structure 200, is inverted with respect to the xy plane and bonded to the first structure 100. Next, the transistor Tr2 is formed.

[0169] The via TS and the insulator SP1 are formed as shown in Fig. 29. The method for forming the via TS and the insulator SP1 is the same as the method described above with reference to Figs. 13 to 15 in the first embodiment.

[0170] As shown in FIG. 30, openings OP3 are formed by partially removing the substrate W2. Each opening OP3 is formed in a region where the second portion DSB of the isolation structure DS is to be formed. Each opening OP3 reaches from the upper surface to the lower surface of the substrate W2. An example of a method for forming the openings OP3 includes a combination of a lithography process and anisotropic etching such as RIE. The openings OP3 have a tapered shape due to the use of anisotropic etching.

[0171] 31, the opening OP3 is filled with the material of the second portion DSB of the isolation structure DS, thereby completing the isolation structure DS.

[0172] The subsequent steps are the same as those in the first embodiment.

[0173] The step described above with reference to Figure 30 may be performed before the step described above with reference to Figure 29. That is, the opening OP3 is formed, followed by the via TS and the insulator SP1.

[0174] The first, second, or third modified example of the first embodiment may be applied to the second embodiment.

[0175] 25, the opening OP2 may be filled by forming an insulator 26. In this case, the second portion DSB of the isolation structure DS includes the same material as the insulator 26.

[0176] The insulator SP1 and the second portion DSB may be formed in a common step. That is, after the step described above with reference to Fig. 25, in the step of forming the openings for the via TS and the insulator SP1, the opening OP2 is also formed. In the subsequent step for forming the insulator SP1, the opening OP2 is filled.

[0177] The second embodiment also provides the same advantages as the first embodiment.

[0178] 3. Third embodiment The third embodiment is based on the second embodiment, but differs from the second embodiment in the structure of the second portion DSB of the separation structure DS.

[0179] Fig. 32 shows an example of a cross section of a portion of the third embodiment, which shows the same area as Fig. 7 of the first embodiment.

[0180] 32, the second portion DSB includes a conductor DSB1 and an insulator DSB2. The conductor DSB1 extends along the z-axis and occupies an area including the center of the second portion DSB2. In one example, the conductor DSB12 includes the same material as the via TS. The insulator DSB2 covers the side surface of the conductor DSB1.

[0181] 32 can be formed by a common process for forming the pair of vias TS and insulators SP1. That is, in the process described above with reference to FIG. 23 of the second embodiment, the opening OP2 described above with reference to FIG. 24 of the second embodiment is formed before filling the material for the vias TS and insulators SP1. The formation of the opening OP2 may be performed by a separate process from the formation of the openings for the pair of vias TS and insulators SP1, or may be performed by a common process. Thereafter, the insulator DSB2 is formed by a process common to the process for forming insulators SP1, and the conductor DSB1 is formed by a process common to the process for forming vias TS.

[0182] 33, the isolation structure DS includes a second portion DSB extending from the upper surface to the lower surface of the substrate W2, and the second portion DSB includes a conductor DSB1 and an insulator DSB2.

[0183] The first, second, or third modified example of the first embodiment may be applied to the third embodiment.

[0184] The third embodiment also provides the same advantages as the first embodiment.

[0185] 4. Fourth embodiment Figures 34 and 35 show an example of a cross-sectional structure of a portion of the fourth embodiment, which shows the same region as Figure 7 of the first embodiment.

[0186] 34, the isolation structure DS is made of a diffusion region of p-type impurities. The substrate W2 contains n-type impurities. Examples of p-type impurities include boron (B). Examples of n-type impurities include arsenic (As).

[0187] As shown in FIG. 35, the isolation structure DS may be made of an n-type impurity diffusion region, and the substrate W2 may contain p-type impurities.

[0188] In one example, the isolation structure DS can be formed by ion implantation before the formation of the contact C5 in the step described above with reference to FIG. 10 of the first embodiment.

[0189] The first, second, or third modified example of the first embodiment may be applied to the fourth embodiment.

[0190] The fourth embodiment also provides the same advantages as the first embodiment.

[0191] 5. Other Modifications The storage device 1 may further include one or more fourth structures similar to the second structure 200.

[0192] The structure of the via TS and the insulator SP1 is not limited to the structure shown in FIG. 7 and may have the structure shown in FIG. 36. That is, the upper portions of the via TS and the insulator SP1 protrude from the upper surface of the substrate W2. Such a structure results, for example, from the following process. That is, in the process shown in FIG. 13, a mask is formed on the upper surface of the substrate W2, and an opening OP is formed using this mask by the lithography process and anisotropic etching described above with reference to FIG. 13. Next, the via TS and the insulator SP1 are formed while the mask remains, and then the mask is removed. As a result, the via TS and the insulator SP1 protrude from the upper surface of the substrate W2 by the thickness of the area where the mask was present. The structure shown in FIG. 36 shows an example based on FIG. 7 regarding the basic form of the first embodiment. However, the structure shown in FIG. 36 can also be applied to the modified example of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment.

[0193] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0194] 1...memory device, 10...memory cell array, 11...input / output circuit, 12...logic controller, 13...register, 14...sequencer, 15...voltage generation circuit, 16...driver, 17...row decoder, 18...sense amplifier, 19...data register, PD...external connection terminal, W2...substrate, TS...via, SP1, 25, 26...insulator, DS...isolation structure, L3, L4...conductor, C5, CS5...contact

Claims

1. a first substrate; a first transistor on the first substrate; a second substrate provided above the first transistor; an external connection terminal provided above the second substrate; a second transistor on the second substrate; a first conductor that penetrates the second substrate and electrically connects the first transistor and the external connection terminal; a first isolation structure that is annular and surrounds the first conductor when viewed from a first direction, penetrates the second substrate, and isolates the second substrate; a memory cell array electrically connected to the first transistor and the second transistor; A storage device comprising:

2. the first isolation structure includes a first insulator penetrating the second substrate in the first direction; The storage device according to claim 1 .

3. the second substrate includes a first surface and a second surface that are aligned and opposed to each other in the first direction, a length of the first insulator along a second direction intersecting with a direction in which the first insulator extends increases from a side of the first surface of the second substrate toward a side of the second surface of the second substrate; The storage device according to claim 2 .

4. a second insulator disposed in the second substrate and surrounding the second transistor; a length of the second insulator along the second direction increases from the first surface side of the second substrate toward the second surface side of the second substrate; The storage device according to claim 3 .

5. a length of the first conductor along the second direction decreases from the first surface side of the second substrate toward the second surface side of the second substrate; The storage device according to claim 4.

6. The first isolation structure is a third insulator; and a fourth insulator provided on the side of the third insulator in the first direction; Including, The storage device according to claim 1 .

7. the second substrate includes a first surface and a second surface that are aligned and opposed to each other in the first direction, a length of the third insulator along a second direction intersecting a direction in which the third insulator extends increases from a side of the first surface of the second substrate toward a side of the second surface of the second substrate; a length of the fourth insulator along the second direction decreases from a side of the first surface of the second substrate toward a side of the second surface of the second substrate; The storage device according to claim 6.

8. a second insulator disposed in the second substrate and surrounding the second transistor; a length of the second insulator along the second direction increases from the first surface side of the second substrate toward the second surface side of the second substrate; The storage device according to claim 7.

9. a length of the first conductor along the second direction decreases from the first surface side of the second substrate toward the second surface side of the second substrate; The storage device according to claim 8.

10. the first isolation structure further includes a second conductor; the third insulator surrounds the second conductor; The storage device according to claim 6.

11. the second substrate includes a first surface and a second surface that are aligned and opposed to each other in the first direction, a length of the second conductor along a second direction intersecting with a direction in which the second conductor extends decreases from a side of the first surface of the second substrate toward a side of the second surface of the second substrate; The storage device of claim 10.

12. a second insulator disposed in the second substrate and surrounding the second transistor; a length of the second insulator along the second direction increases from the first surface side of the second substrate toward the second surface side of the second substrate; The storage device of claim 11.

13. a length of the first conductor along the second direction decreases from the first surface side of the second substrate toward the second surface side of the second substrate; The storage device of claim 12.

14. the second substrate contains impurities of a first conductivity type; the first isolation structure contains impurities of a second conductivity type different from the first conductivity type; The storage device according to claim 1 .

15. further comprising a second isolation structure surrounding the first isolation structure when viewed from the first direction; The storage device according to any one of claims 1 to 14.

16. a first structure including a first terminal; a second structure that is in contact with the first structure on a side of the first structure in the first direction, that includes a second terminal that is in contact with the first terminal, and that includes a third terminal that is electrically connected to the second terminal; a third structure including a fourth terminal that is in contact with the second structure on a side of the second structure in the first direction, that is in contact with the third terminal, and that is electrically connected to the external connection terminal; Further provided with The storage device according to any one of claims 1 to 14.

17. the first transistor is electrically connected to the external connection terminal through the second substrate; The storage device according to any one of claims 1 to 14.

18. forming a first structure including a first substrate, a first transistor on the first substrate, and a first conductor in contact with the first substrate, the first structure including forming a first annular isolation structure in the first substrate surrounding a first region of the first substrate; bonding a second structure including a second substrate and a second transistor on the second substrate to the first structure; forming a second conductor in the first region, the second conductor penetrating the first substrate and contacting the first conductor; forming a third structure including a memory cell array electrically connected to the first transistor and the second transistor, and an external connection terminal electrically connected to the second conductor; A method for manufacturing a storage device comprising:

19. forming the first isolation structure includes forming a first insulator in an opening extending from a first surface of the first substrate; The method for manufacturing the storage device according to claim 18.

20. after the bonding of the second structure and the first structure, forming a second isolation structure in the first substrate, the second isolation structure extending from a surface opposite to the first surface and contacting the first isolation structure; The method for manufacturing the storage device according to claim 19.

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