Electro-optical device and electronic apparatus

Abstract

To provide an electro-optical device that can improve its properties to block light incident on a semiconductor layer, and an electronic apparatus.SOLUTION: An electro-optical device comprises: a substrate; transistors each including a gate electrode, and a semiconductor layer arranged between the substrate and the gate electrode; scan lines each arranged in a first direction with respect to the gate electrode, and electrically connected to the gate electrode; a first light blocking part arranged in the first direction with respect to the semiconductor layer, and overlapping the semiconductor layer in plan view seen from the first direction; and a second light blocking part arranged in a second direction opposite to the first direction with respect to the semiconductor layer, and overlapping the semiconductor layer in the plan view. The electric potential of the first light blocking part and the electric potential of the second light blocking part are different from each other. The first light blocking part has side-face light blocking parts that are provided on both sides in a width direction of the semiconductor layer, and extend in the second direction from a first insulating layer between the scan line and the gate electrode, to the same layer as the second light blocking part or beyond the second light blocking part.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] BACKGROUND ART Electronic devices such as projectors use electro-optical devices such as liquid crystal display devices that can change optical characteristics for each pixel. A known example of such an electro-optical device is the display device described in Patent Document 1.

[0003] The display device described in Patent Document 1 includes a thin film transistor (TFT) including a semiconductor film and a gate electrode disposed above the semiconductor film, and a scanning line disposed above the gate electrode. The gate electrode and the scanning line are electrically connected via a contact hole. In this display device, the scanning line disposed above the semiconductor film is used as a light-shielding layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-7806 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in conventional devices, the scanning lines provided on the upper layer of the semiconductor film are used as a light-shielding layer, but this alone does not provide sufficient light-shielding properties for the semiconductor film, which is a problem. [Means for solving the problem]

[0006] One aspect of the electro-optical device of the present invention comprises a substrate, a transistor including a gate electrode arranged in a first direction relative to the substrate, and a semiconductor layer arranged between the substrate and the gate electrode, a scanning line arranged in the first direction relative to the gate electrode and electrically connected to the gate electrode, a first light-shielding portion arranged in the first direction relative to the semiconductor layer and overlapping with the semiconductor layer in a planar view seen from the first direction, and a second light-shielding portion arranged in a second direction opposite to the first direction relative to the semiconductor layer and overlapping with the semiconductor layer in the planar view, wherein the potential of the first light-shielding portion and the potential of the second light-shielding portion are different from each other, and the first light-shielding portion is provided on both sides of the semiconductor layer in the width direction, and has side light-shielding portions that extend from a first insulating layer between the scanning line and the gate electrode in the second direction, either in the same layer as the second light-shielding portion or further than the second light-shielding portion.

[0007] An electronic device according to an aspect of the present invention includes an electro-optical device and a control unit that controls the operation of the electro-optical device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of an electro-optical device according to an embodiment. [Figure 2] 2 is a cross-sectional view of the electro-optical device shown in FIG. 1 taken along the line AA. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the element substrate of FIG. [Figure 4] 3 is a plan view showing a part of the element substrate in the display region of FIG. 2. FIG. [Figure 5] 5 is a cross-sectional view taken along the line A1-A1 in FIG. 4. [Figure 6] 5 is a cross-sectional view taken along the line A2-A2 in FIG. 4. [Figure 7] FIG. 6 is a plan view showing the transistor in FIG. 5. [Figure 8] FIG. 6 is a plan view of the second light-shielding part shown in FIG. 5. [Figure 9] 6 is a plan view of the first light-shielding portion and the second light-shielding portion shown in FIG. 5. FIG. [Figure 10] 6 is a plan view of the first light-shielding portion and the second light-shielding portion shown in FIG. 5. FIG. [Figure 11] 11 is a cross-sectional view taken along the line A3-A3 in FIG. 10. [Figure 12] 11 is a cross-sectional view taken along line A4-A4 in FIG. 10. [Figure 13] 5A and 5B are cross-sectional views illustrating a method for manufacturing the first recessed portion. [Figure 14] FIG. 10 is a plan view illustrating a method for manufacturing the first recessed portion. [Figure 15] FIG. 10 is a cross-sectional view illustrating a method for manufacturing the second recessed portion. [Figure 16] FIG. 10 is a plan view illustrating a method for manufacturing the second recessed portion. [Figure 17] FIG. 10 is a plan view illustrating a method for manufacturing the third recessed portion. [Figure 18] 10A to 10C are diagrams illustrating a method for manufacturing the first light-shielding portion. [Figure 19] FIG. 10 is a cross-sectional view showing a second light-shielding portion in a second embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a second light-shielding portion in a second embodiment. [Figure 21] FIG. 20 is a plan view showing the second light-shielding part shown in FIG. [Figure 22] 20 is a diagram showing the planar arrangement of the second light-shielding portion and the first light-shielding portion 6 shown in FIG. 19. FIG. [Figure 23] FIG. 11 is a cross-sectional view showing a fourth light-shielding part in the third embodiment. [Figure 24] FIG. 11 is a cross-sectional view showing a fourth light-shielding part in the third embodiment. [Figure 25] FIG. 24 is a plan view showing the fourth light-shielding part shown in FIG. 23. [Figure 26] FIG. 1 is a perspective view showing a personal computer as an example of an electronic device. [Figure 27] FIG. 1 is a plan view showing a smartphone as an example of an electronic device. [Figure 28] FIG. 1 is a schematic diagram illustrating a projector as an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the dimensions and scale of each part in the drawings may differ from the actual dimensions and some parts are shown schematically to facilitate understanding. Furthermore, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited thereto.

[0010] 1. Electro-optical devices 1A.Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to an embodiment. FIG. 2 is a cross-sectional view of the electro-optical device 100 taken along line AA in FIG. 1. The opposing substrate 3 is not shown in FIG. 1. For ease of explanation, the following description will appropriately use the mutually perpendicular X, Y, and Z axes. A direction along the X axis will be referred to as the X1 direction, and a direction opposite to the X1 direction will be referred to as the X2 direction. Similarly, a direction along the Y axis will be referred to as the Y1 direction, and a direction opposite to the Y1 direction will be referred to as the Y2 direction. A direction along the Z axis will be referred to as the Z1 direction, and a direction opposite to the Z1 direction will be referred to as the Z2 direction. The Z1 direction corresponds to the "first direction," and the Z2 direction corresponds to the "second direction." The Y1 direction or the Y2 direction corresponds to the "third direction."

[0011] Furthermore, in this specification, "element β on element α" means that element β is located above element α. Therefore, "element β on element α" includes not only the case where element β is in direct contact with element α, but also the case where element α and element β are spaced apart. Furthermore, "electrical connection" between element α and element β includes not only a configuration in which element α and element β are electrically connected by direct bonding, but also a configuration in which element α and element β are indirectly electrically connected via another conductor.

[0012] The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device that employs an active matrix driving method. The electro-optical device 100 includes an element substrate 2, a counter substrate 3, a frame-shaped sealing member 4, and a liquid crystal layer 5. As shown in FIG. 2, the element substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in this order in the Z1 direction. Note that a view from the Z1 direction or the Z2 direction in which these elements overlap is referred to as a "plan view." Furthermore, although the shape of the electro-optical device 100 shown in FIG. 1 is rectangular in plan view, it may also be a polygon other than a rectangle or a circle.

[0013] The element substrate 2 shown in FIG. 2 includes a first substrate 21 having light-transmitting properties, a laminate 22 having light-transmitting properties, a plurality of pixel electrodes 25 having light-transmitting properties, and a first alignment film 29 having light-transmitting properties. The first substrate 21 corresponds to a "substrate." The first substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 are laminated in this order in the Z1 direction. "Light-transmitting" refers to transparency to visible light, preferably a visible light transmittance of 50% or more. As will be described in detail later, the element substrate 2 also includes a first light-shielding portion 6, a second light-shielding portion 210, and a fourth light-shielding portion 7 having light-shielding properties, as shown in FIGS. 5 and 6. "Light-shielding" refers to a property of blocking visible light, preferably a visible light transmittance of less than 50%, more preferably 10% or less.

[0014] The first substrate 21 is a flat plate having translucent and insulating properties, and is formed of, for example, a glass substrate or a quartz substrate. The laminate 22 includes a plurality of insulating films having translucent properties. The laminate 22 is also provided with various wirings and the like. The pixel electrodes 25 are used to apply an electric field to the liquid crystal layer 5. The pixel electrodes 25 include, for example, a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide), or FTO (fluorine-doped tin oxide). Although not shown, the element substrate 2 has a plurality of dummy pixel electrodes surrounding the plurality of pixel electrodes 25 in a planar view. The first alignment film 29 is also translucent and insulating. The first alignment film 29 aligns liquid crystal molecules in the liquid crystal layer 5. The first alignment film 29 is disposed so as to cover the plurality of pixel electrodes 25. The first alignment film 29 is made of, for example, polyimide, silicon oxide, or the like.

[0015] The counter substrate 3 is disposed opposite the element substrate 2. The counter substrate 3 has a light-transmitting second substrate 31, a light-transmitting inorganic insulating layer 32, a light-transmitting common electrode 33, and a light-transmitting second alignment film 34. Although not shown, the counter substrate 3 also has a light-shielding partition surrounding the plurality of pixel electrodes 25 in a plan view.

[0016] The second substrate 31, inorganic insulating layer 32, common electrode 33, and second alignment film 34 are stacked in this order in the Z2 direction. The second substrate 31 is a flat plate having translucent and insulating properties, such as a glass substrate or a quartz substrate. The inorganic insulating layer 32 is also translucent and insulating, and is formed of an inorganic material containing silicon, such as silicon oxide. The common electrode 33 is a counter electrode disposed across the liquid crystal layer 5 from the plurality of pixel electrodes 25. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 is translucent and conductive. The common electrode 33 includes a transparent conductive material, such as ITO, IZO, or FTO. The second alignment film 34 is translucent and insulating. The second alignment film 34 aligns the liquid crystal molecules in the liquid crystal layer 5. The second alignment film 34 is made of a material such as polyimide or silicon oxide.

[0017] The sealing member 4 is disposed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive containing various curable resins such as epoxy resin. The sealing member 4 may also contain a gap material made of an inorganic material such as glass.

[0018] The liquid crystal layer 5 is disposed within the region surrounded by the element substrate 2, the counter substrate 3, and the sealing member 4. The liquid crystal layer 5 is an electro-optical layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules with positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the voltage applied to the liquid crystal layer 5.

[0019] As shown in FIG. 1, a plurality of scanning line driving circuits 11, a signal line driving circuit 12, and a plurality of external terminals 13 are arranged on the element substrate 2. Some of the plurality of external terminals 13 are connected to wiring (not shown) drawn from the scanning line driving circuit 11 or the signal line driving circuit 12. The plurality of external terminals 13 also includes a terminal to which a constant potential Vcom is applied. This terminal is electrically connected to a common electrode 33 of the counter substrate 3 via wiring and a conductive material (not shown). Therefore, the constant potential Vcom is supplied to the common electrode 33.

[0020] The electro-optical device 100 has a display area A10 that displays an image and a peripheral area A20 located outside the display area A10 in a planar view. A plurality of pixels P are arranged in a matrix in the display area A10. A plurality of pixel electrodes 25 are arranged in a one-to-one correspondence with the plurality of pixels P. The aforementioned common electrode 33 is provided in common to the plurality of pixels P. The peripheral area A20 surrounds the display area A10 in a planar view. A scanning line driving circuit 11 and a signal line driving circuit 12 are arranged in the peripheral area A20.

[0021] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in Fig. 2, an image is displayed by modulating light LL after it is incident on the counter substrate 3 and before it is emitted from the element substrate 2. Note that an image may also be displayed by modulating light that has entered the element substrate 2 and before it is emitted from the counter substrate 3.

[0022] The electro-optical device 100 is also applied to display devices that perform color display, such as personal computers and smartphones, which will be described later. When applied to such display devices, a color filter is appropriately used for the electro-optical device 100. The electro-optical device 100 is also applied to, for example, a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light valve. In this case, the color filter is omitted from the electro-optical device 100.

[0023] 1B. Electrical configuration of element substrate 2 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 of FIG. 1. As shown in FIG. 3, the element substrate 2 has a plurality of transistors 23, n scanning lines 241, m signal lines 242, and n constant potential lines 243. n and m are each an integer of 2 or greater. A transistor 23 is disposed at each intersection of the n scanning lines 241 and the m signal lines 242. Each transistor 23 is, for example, a TFT (Thin Film Transistor) that functions as a switching element. Each transistor 23 includes a gate, a source, and a drain.

[0024] Each of the n scanning lines 241 extends in the X1 direction, and the n scanning lines 241 are arranged at equal intervals in the Y1 direction. Each of the n scanning lines 241 is electrically connected to the gates of the corresponding plurality of transistors 23. The n scanning lines 241 are electrically connected to the scanning line driving circuit 11 shown in FIG. 1. Scanning signals G1, G2, ..., and Gn are supplied line-sequentially to the 1st to nth scanning lines 241 from the scanning line driving circuit 11.

[0025] 3, each of the m signal lines 242 extends in the Y1 direction, and the m signal lines 242 are arranged at equal intervals in the X1 direction. Each of the m signal lines 242 is electrically connected to the sources of the corresponding plurality of transistors 23. The m signal lines 242 are electrically connected to the signal line drive circuit 12 shown in FIG. 1. Image signals S1, S2, ..., and Sm are supplied in parallel to the 1 to m signal lines 242 from the signal line drive circuit 12.

[0026] 3 are electrically insulated from one another and arranged in a grid pattern in plan view. An area surrounded by two adjacent scanning lines 241 and two adjacent signal lines 242 corresponds to a pixel P. A transistor 23, a pixel electrode 25, and a capacitance element 24 are provided for each pixel P. The pixel electrodes 25 are provided in a one-to-one correspondence with the transistors 23. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.

[0027] Each of the n constant potential lines 243 extends in the X1 direction and is arranged at equal intervals in the Y2 direction. The n constant potential lines 243 are electrically insulated from the n scanning lines 241 and the m signal lines 242 and are spaced apart from them. A constant potential Vcom is applied to each of the n constant potential lines 243. Each of the n constant potential lines 243 is electrically connected to one of two electrodes of a corresponding capacitance element 24. Each capacitance element 24 is a storage capacitor for storing the potential of the pixel electrode 25. The capacitance elements 24 are provided in a one-to-one correspondence with the transistors 23. The other of the two electrodes of each capacitance element 24 is electrically connected to the corresponding pixel electrode 25. Therefore, a constant potential Vcom is applied to one electrode of the capacitance element 24, and the other electrode is electrically connected to the drain of the transistor 23.

[0028] When the scanning signals G1, G2, ..., and Gn become active in sequence and n scanning lines 241 are selected in sequence, the transistor 23 connected to the selected scanning line 241 is turned on. Then, image signals S1, S2, ..., and Sm having a magnitude corresponding to the gradation to be displayed are received by the pixel P corresponding to the selected scanning line 241 via m signal lines 242 and applied to the pixel electrode 25. This applies a voltage corresponding to the gradation to be displayed to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in FIG. 2, and the orientation of the liquid crystal molecules changes in response to the applied voltage. The applied voltage is maintained by the capacitive element 24. This change in the orientation of the liquid crystal molecules modulates light, enabling gradation display.

[0029] 1C. Structure of a portion of the element substrate 2 FIG. 4 shows a portion of the element substrate 2 in the display region A10 of FIG. 2. As shown in FIG. 4, the display region A10 has a plurality of opening regions A11 and a light-shielding region A12. The opening regions A11 are arranged in a matrix in a plan view. The light-shielding region A12 has a frame shape in a plan view and is located between the opening regions A11. Each opening region A11 is an area where a pixel electrode 25 is arranged and is a light-transmitting area. Meanwhile, a transistor 23 is arranged in the light-shielding region A12. Although not shown in FIG. 4, the light-shielding region A12 is also provided with various wirings such as the scanning line 241, the signal line 242, and the constant potential line 243 shown in FIG. 3, as well as a capacitance element 24.

[0030] FIG. 5 is a cross-sectional view taken along line A1-A1 in FIG. 4. FIG. 6 is a cross-sectional view taken along line A2-A2 in FIG. 4. As shown in FIGS. 5 and 6, the element substrate 2 includes a first substrate 21, which is a "substrate," and a laminate 22. The laminate 22 includes multiple insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229. The insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229 are stacked in this order on the first substrate 21. The insulating layers 221 to 229 are translucent and insulating. Each of the insulating layers 221 to 229 is made of an inorganic material containing silicon, such as silicon oxide or silicon oxynitride. The insulating layer 221 corresponds to a "second insulating layer," and the insulating layers 223 and 224 form the first insulating layer 201.

[0031] The laminate 22 is provided with a transistor 23, a scanning line 241, a signal line 242, a first light-shielding portion 6, and a fourth light-shielding portion 7. The laminate 22 is also provided with relay electrodes 244, 245, 246, 247, 248, and 249. The first substrate 21 is also provided with a second light-shielding portion 210.

[0032] As described above, the first substrate 21 is made of, for example, a glass substrate or a quartz substrate. The first substrate 21 has a recess H1. The recess H1 is a depression formed in the first substrate 21, and is formed for each transistor 23. The recess H1 is formed along the Y1 direction, which is the extension direction of a semiconductor layer 231 described below.

[0033] A second light-shielding portion 210 is disposed within the recess H1. The second light-shielding portion 210 is formed, for example, by a damascene method. The second light-shielding portion 210 is provided to prevent light from entering a semiconductor layer 231 of the transistor 23. The first substrate 21 does not necessarily have to have the recess H1. In this case, the second light-shielding portion 210 is disposed on a flat surface of the first substrate 21 facing the Z1 direction. The second light-shielding portion 210 overlaps the semiconductor layer 231 of the transistor 23 (described later) in a planar view and is disposed between the first substrate 21 and the semiconductor layer 231. The second light-shielding portion 210 functions as a back-surface light-shielding portion disposed below the semiconductor layer 231.

[0034] The transistor 23 is disposed on the insulating layer 221. The transistor 23 has a semiconductor layer 231, a gate electrode 232, and a gate insulating film 233. The semiconductor layer 231 is disposed on the insulating layer 221, which corresponds to the "second insulating layer." The insulating layer 221 is a layer between the semiconductor layer 231 and the second light-shielding portion 210. The gate electrode 232 is disposed on the insulating layer 222. The gate insulating film 233 is interposed between the gate electrode 232 and the semiconductor layer 231. A region of the insulating layer 222 that corresponds to the gate electrode 232 in a plan view corresponds to the gate insulating film 233.

[0035] 7 is a plan view of the transistor 23 in FIG. 5. The transistor 23 shown in FIG. 7 has an LDD (Lightly Doped Drain) structure. The semiconductor layer 231 extends in the Y1 direction. The width direction of the semiconductor layer 231 is along the X-axis. The semiconductor layer 231 is disposed between the first substrate 21 and the gate electrode 232. The semiconductor layer 231 has a drain region 231a, a source region 231b, a channel region 231c, a low-concentration drain region 231d, and a low-concentration source region 231e. The channel region 231c is located between the drain region 231a and the source region 231b. The low-concentration drain region 231d is located between the channel region 231c and the drain region 231a. The low-concentration source region 231e is located between the channel region 231c and the source region 231b. The semiconductor layer 231 is formed of, for example, polysilicon. The regions other than the channel region 231c are doped with impurities that increase conductivity. The impurity concentration in the lightly doped drain region 231d is lower than the impurity concentration in the drain region 231a. The impurity concentration in the lightly doped source region 231e is lower than the impurity concentration in the source region 231b. Note that, for example, the transistor 23 does not need to have an LDD structure, and the lightly doped source region 231e and the lightly doped drain region 231d may be omitted.

[0036] The gate electrode 232 is formed, for example, by doping polysilicon with impurities that increase conductivity. The gate electrode 232 may also be formed using a conductive material such as a metal, a metal oxide, or a metal compound. In plan view, the gate electrode 232 overlaps the channel region 231c of the semiconductor layer 231. The gate insulating film 233 is made of a silicon oxide film formed, for example, by thermal oxidation or a CVD (chemical vapor deposition) method.

[0037] As shown in FIG. 5, the first light-shielding portion 6 is disposed in the insulating layer 222. The first light-shielding portion 6 is formed, for example, by a damascene method. The first light-shielding portion 6 is disposed in a through-hole formed in the insulating layers 221 to 223. The through-hole includes a first recess R1, a second recess R2, and a third recess R3. The first light-shielding portion 6 is directly connected to the drain region 231a of the semiconductor layer 231. Therefore, the first light-shielding portion 6 is at the pixel potential.

[0038] 5, the first light-shielding portion 6 includes a first portion 61, a second portion 62, and a third portion 63. The first portion 61 is disposed in the first recess R1. The second portion 62 is disposed in the second recess R2. The third portion 63 is disposed in the third recess R3. The first light-shielding portion 6 functions as an upper light-shielding portion disposed in a layer above the semiconductor layer 231.

[0039] As described above, in the element substrate 2, the second light-shielding portion 210 is provided below the semiconductor layer 231, and the first light-shielding portion 6 is disposed above the semiconductor layer 231. This makes it possible to improve the light-shielding properties compared to conventional methods.

[0040] 5, a relay electrode 244 is disposed on the insulating layer 223. The relay electrode 244 is electrically connected to the source region 231b of the semiconductor layer 231 via a contact 271. For example, the contact 271 is a contact plug that fills a hole that penetrates the insulating layers 222 and 223. The relay electrode 244 and the contact 271 may be integrally formed using the same material, or may be formed using different materials.

[0041] 5, a scanning line 241, a relay electrode 245, and a relay electrode 246 are disposed on an insulating layer 224. The scanning line 241 is electrically connected to a gate electrode 232 via a fourth light-shielding portion 7. The relay electrode 245 is electrically connected to a first light-shielding portion 6 via a contact 272 that penetrates the insulating layer 224. The relay electrode 246 is electrically connected to the relay electrode 244 via a contact 273 that penetrates the insulating layer 224. A first insulating layer 201 constituted by insulating layers 224 and 223 is present between the scanning line 241 and the gate electrode 232.

[0042] As shown in FIG. 6, the fourth light-shielding portion 7 is disposed on the insulating layers 221 to 224. The fourth light-shielding portion 7 is formed, for example, by using a damascene method. The fourth light-shielding portion 7 is directly connected to the scanning line 241 and the gate electrode 232. Therefore, the fourth light-shielding portion 7 is at the gate potential.

[0043] The fourth light-shielding portion 7 includes two fourth portions 71 and a fifth portion 72. The two fourth portions 71 are spaced apart from each other and extend from the scanning line 241 to the second light-shielding portion 210, and are connected thereto. Therefore, the second light-shielding portion 210 has the same potential as the gate electrode 232 and functions as a back gate. Each of the two fourth portions 71 is located outside the first portion 61 in the direction along the X-axis. The fifth portion 72 is located between the two fourth portions 71 and is connected to the scanning line 241.

[0044] Relay electrodes 247 and 248 are disposed on insulating layer 225. Relay electrode 247 is electrically connected to relay electrode 246 via contact 275 that penetrates insulating layer 225. Relay electrode 248 is electrically connected to relay electrode 245 via contact 274 that penetrates insulating layer 225.

[0045] The signal line 242 is disposed on the insulating layer 226. The signal line 242 is electrically connected to the relay electrode 247 via a contact 276 that penetrates the insulating layer 226. Therefore, the signal line 242 is electrically connected to the source region 231b via the contact 276, the relay electrode 247, the contact 275, the relay electrode 246, the contact 273, the relay electrode 244, and the contact 271.

[0046] 6, a relay electrode 249 is disposed on the insulating layer 226. The relay electrode 249 is electrically connected to the relay electrode 248 via a contact 277 that penetrates the insulating layer.

[0047] The capacitor 24 is disposed on the insulating layer 227. The capacitor 24 has a pair of electrodes 2401 and 2402 and a dielectric layer 2403. The electrode 2401 is disposed on the insulating layer 227. The electrode 2402 is disposed on the insulating layer 228. The dielectric layer 2403 is disposed between the electrodes 2401 and 2402. The dielectric layer 2403 contains, for example, HfO2 or Al2O3. The electrode 2401 also serves as the constant potential line 243 in FIG. 2. As shown in FIG. 6, the electrode 2402 is electrically connected to the relay electrode 249 via a contact 278 that penetrates the insulating layers 227 and 228. Therefore, as shown in FIG. 5 or 6, the electrode 2402 is electrically connected to the drain region 231a via the contact 278, the relay electrode 249, the contact 277, the relay electrode 248, the contact 274, the relay electrode 245, the contact 272 and the first light-shielding portion 6.

[0048] 5, the pixel electrode 25 is disposed on the insulating layer 229. The pixel electrode 25 is electrically connected to the electrode 2402 via a contact 279 that penetrates the insulating layer 229.

[0049] Each of the aforementioned scan line 241, signal line 242, electrode 2401, electrode 2402, and relay electrodes 244, 245, 246, 247, 248, and 249 includes, for example, a metal such as tungsten (W), titanium (Ti), chromium (Cr), iron, or aluminum (Al), a metal nitride, or a metal silicide. These may be single layers or multilayers. For example, they may be formed of a multilayer structure of an aluminum film and a titanium nitride film.

[0050] Each of the contacts 271 to 279 includes, for example, a metal such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), or aluminum (Al), a metal nitride, or a metal silicide. Each of the contacts 271 to 279 may be a single layer or a multilayer. Each of the contacts 271 to 279 may be formed integrally with or separately from the electrode or wiring to which it is connected.

[0051] 5 and 6 is an example. For example, the element substrate 2 may include a capacitive element other than the capacitive element 24. Although the scanning line 241, the signal line 242, and the capacitive element 24 are arranged in this order in the Z1 direction, they do not have to be arranged side by side.

[0052] 1D. First light-shielding portion 6, fourth light-shielding portion 7, and second light-shielding portion 210 FIG. 8 is a plan view of the second light-shielding portion 210 shown in FIG. 8 is elongated in plan view, with its longitudinal direction aligned with the Y-axis, which is the direction in which the scanning lines 241 extend. The second light-shielding portion 210 includes a wide portion 211, a first narrow portion 212, and a second narrow portion 213. The wide portion 211 is located between the first narrow portion 212 and the second narrow portion 213, and has a width, which is the length along the X-axis, greater than those of the first narrow portion 212 and the second narrow portion 213. The first narrow portion 212 extends from the wide portion 211 in the Y1 direction. The second narrow portion 213 extends from the wide portion 211 in the Y2 direction.

[0053] 7 and 8, the wide portion 211 overlaps the gate electrode 232 in a plan view. The first narrow portion 212 overlaps the source region 231b in a plan view. The second narrow portion 213 overlaps the drain region 231a in a plan view.

[0054] 9 and 10 are plan views of the first light-shielding portion 6 and the fourth light-shielding portion 7, respectively. In Fig. 10, for ease of understanding, the first portion 61 is hatched, the second portion 62 is meshed, and the third portion 63 is dotted. Furthermore, the fourth portion 71 is hatched, and the fifth portion 72 is dotted.

[0055] 9, the first light-shielding portion 6 and the fourth light-shielding portion 7 overlap the second light-shielding portion 210 in a plan view. The first light-shielding portion 6 and the fourth light-shielding portion 7 are spaced apart from each other. The fourth light-shielding portion 7 is located outside the first light-shielding portion 6 in a plan view. The first light-shielding portion 6 overlaps the drain region 231a and the low-concentration drain region 231d of the semiconductor layer 231 in a plan view. Furthermore, the fourth light-shielding portion 7 overlaps the gate electrode 232 and the channel region 231c of the semiconductor layer 231 in a plan view.

[0056] As described above, the first light-shielding portion 6 has the first portion 61, the second portion 62, and the third portion 63. Specifically, the first portion 61 includes a drain connection portion 611 and two side surface light-shielding portions 612. The first portion 61 is provided to surround the low-concentration drain region 231d, which is located between the drain region 231a and the channel region 231c in a planar view. The drain connection portion 611 is a portion that overlaps with the drain region 231a in a planar view and is directly connected to the drain region 231a. The drain connection portion 611 is located further in the Y2 direction than the second portion 62 and extends along the X-axis. The drain connection portion 611 also overlaps with the second light-shielding portion 210 in a planar view. Each side surface light-shielding portion 612 does not overlap with the semiconductor layer 231 in a planar view. Furthermore, each side surface light-shielding portion 612 does not overlap with the second light-shielding portion 210 in a planar view. Each side surface light shielding portion 612 is located further in the X1 direction or X2 direction than the second portion 62 and the third portion 63 in plan view, and extends substantially along the Y axis.

[0057] The second portion 62 is located further in the Y2 direction than the third portion 63 in a planar view. The second portion 62 overlaps the lightly doped drain region 231d in a planar view. The lightly doped drain region 231d is the region of the semiconductor layer 231 in which light leakage is most likely to occur. Therefore, by having the second portion 62 overlap the lightly doped drain region 231d in a planar view, the first light-shielding portion 6 can effectively suppress light from entering the lightly doped drain region 231d. This makes it possible to effectively suppress light leakage.

[0058] As described above, in this embodiment, the transistor 23 has an LDD structure. However, the low-concentration source region 231e and the low-concentration drain region 231d may be omitted. In this case, it is preferable that the second portion 62 overlaps the junction between the drain region 231a and the source region 231b in a planar view. This junction is a region where light leakage is likely to occur. Therefore, by having the second portion 62 overlap the junction in a planar view, the first light-shielding portion 6 can effectively suppress light from entering the junction. This allows light leakage to be effectively suppressed.

[0059] Moreover, the third portion 63 overlaps the gate electrode 232 in a planar view. Therefore, compared to a case where the third portion 63 does not overlap the gate electrode 232 in a planar view, it is possible to suppress light from entering the semiconductor layer 231, particularly the lightly doped drain region 231d.

[0060] 9, each fourth portion 71 includes a portion extending along the Y-axis and a portion extending along the X-axis in a planar view. The fifth portion 72 extends along the X-axis and is located between the two fourth portions 71 in a planar view. As shown in FIGS. 9 and 10, the fifth portion 72 overlaps the gate electrode 232 in a planar view. Each of the two fourth portions 71 is located outward in the direction along the X-axis of the first portion 61 in a planar view and does not overlap the gate electrode 232 in a planar view.

[0061] The fourth light-shielding portion 7 and the first portion 61 surround the lightly doped drain region 231d in plan view, which effectively prevents light from entering the lightly doped drain region 231d from a direction along the XY plane.

[0062] Furthermore, the fourth light-shielding portion 7 is positioned further outward on the X-axis than the first light-shielding portion 6. Therefore, compared to when the fourth light-shielding portion 7 is positioned further inward on the X-axis than the first light-shielding portion 6, the influence of the fourth light-shielding portion 7, which is the gate potential, on the lightly doped drain region 231d can be suppressed. This can suppress an increase in off-leakage current. This can suppress a deterioration in display quality due to the occurrence of black spots, etc. The off-leakage current is a leakage current that flows when the transistor 23 is turned off.

[0063] Furthermore, as described above, the potential of the first light-shielding portion 6 and the potential of the second light-shielding portion 210 are different from each other. By making them different from each other, the potential of the first light-shielding portion 6 and the potential of the second light-shielding portion 210 can be set independently. This makes it possible to reduce adverse electrical effects of the first light-shielding portion 6 and the second light-shielding portion 210 on the semiconductor layer 231.

[0064] Specifically, the first portion 61 of the first light-shielding portion 6 is directly connected to the drain region 231a and electrically connected to the drain region 231a. The second light-shielding portion 210 is electrically connected to the gate electrode 232 and overlaps the semiconductor layer 231 in a planar view. Since the first light-shielding portion 6 is electrically connected to the drain region 231a, electrical problems are unlikely to occur even if the first light-shielding portion 6 is placed close to the drain region 231a. Therefore, the first light-shielding portion 6 can be placed close to the low-concentration drain region 231d. Therefore, although the second portion 62 and the third portion 63 are spaced apart from the semiconductor layer 231, they can be easily placed close to the semiconductor layer 231. Since the first light-shielding portion 6 can be placed close to the semiconductor layer 231, the light-shielding effect of the first light-shielding portion 6 can be improved compared to conventional techniques. Meanwhile, since the second light-shielding portion 210 is electrically connected to the gate electrode 232, the second light-shielding portion 210 can be used as a back gate.

[0065] Furthermore, the first light-shielding portion 6 is a pixel potential, not a gate potential. Therefore, even if the first light-shielding portion 6 is disposed close to the semiconductor layer 231, it is possible to prevent the influence of the gate potential from reaching the semiconductor layer 231. Specifically, it is possible to prevent an increase in off-leak current caused by the gate potential approaching a region other than the channel region 231c of the semiconductor layer 231. This makes it possible to prevent a deterioration in display quality due to the occurrence of black spots, etc.

[0066] Examples of materials for the first light-shielding portion 6, the second light-shielding portion 210, and the fourth light-shielding portion 7 include metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), metal nitrides, and metal silicides. Among these, the first light-shielding portion 6 and the fourth light-shielding portion 7 preferably contain tungsten. Among various metals, tungsten has excellent heat resistance and is less susceptible to a decrease in optical density (OD) value, even during heat treatment during manufacturing. Therefore, when the first light-shielding portion 6, the second light-shielding portion 210, and the fourth light-shielding portion 7 contain tungsten, the first light-shielding portion 6, the second light-shielding portion 210, and the fourth light-shielding portion 7 can effectively prevent light from entering the semiconductor layer 231. Furthermore, the materials for the first light-shielding portion 6, the second light-shielding portion 210, and the fourth light-shielding portion 7 may be the same or different from each other.

[0067] Fig. 11 is a cross-sectional view taken along the line A3-A3 in Fig. 9. Fig. 12 is a cross-sectional view taken along the line A4-A4 in Fig. 9.

[0068] As shown in FIGS. 11 and 12 , the two side surface light shielding portions 612 of the first portion 61 are disposed on the outer side of the semiconductor layer 231 in the X-axis direction. That is, the two side surface light shielding portions 612 are disposed on both sides of the semiconductor layer 231 in the width direction. Therefore, the two side surface light shielding portions 612 can suppress light incident on the semiconductor layer 231 in the X1 and X2 directions. The side surface light shielding portions 612 are disposed so as to extend in the direction along the Z-axis across the first substrate 21 and the insulating layers 221, 222, and 223. In other words, the side surface light shielding portion 612 extends in the Z2 direction from the first insulating layer 201 to reach the first substrate 21, and protrudes into the first substrate 21. The side surface light shielding portion 612 protrudes in the Z2 direction further than the second light shielding portion 210.

[0069] 5, 11, or 12, each side surface light-shielding portion 612 of the first portion 61 extends in the Z2 direction from the first insulating layer 201, which is a layer between the scanning line 241 and the gate electrode 232, further than the second light-shielding portion 210. Since the first portion 61 extends in the Z2 direction further than the second light-shielding portion 210, it is possible to reduce the risk of light penetrating into the semiconductor layer 231 from between the first light-shielding portion 61 and the second light-shielding portion 210, compared to when the first portion 61 is positioned in the Z2 direction, for example. Therefore, it is possible to maintain a more consistent light-shielding performance than before, thereby stabilizing the quality of the electro-optical device 100.

[0070] In addition, in a plurality of electro-optical devices 100, it is possible to suppress variations in the light resistance of the semiconductor layer 231 caused by variations in the processing of the side surface light shielding portion 612. Specifically, when the end portion of the side surface light shielding portion 612 in the Z2 direction is located in a layer above the second light shielding portion 210, variations occur in the distance between the side surface light shielding portion 612 and the second light shielding portion 210 for each pixel P due to manufacturing errors or the like. On the other hand, in the present embodiment, each side surface light shielding portion 612 extends from the first insulating layer 201 in the Z2 direction beyond the second light shielding portion 210. Therefore, even if variations occur in the position of the end portion of the side surface light shielding portion 612 in the Z2 direction for each pixel P, it is possible to reduce variations in the light resistance of the semiconductor layer 231. Therefore, it is possible to suppress a decrease in yield. And since a constant light shielding shape can be maintained as compared with the prior art, the quality of the electro-optical device 100 can be stabilized.

[0071] Note that each side surface light shielding portion 612 of the first portion 61 extends from the first insulating layer 201 in the Z2 direction beyond the second light shielding portion 210, but the first portion 61 only needs to extend at least from the first insulating layer 201 to the same layer as the second light shielding portion 210. By the first portion 61 extending at least to the same layer, it is possible to suppress the possibility that light enters the semiconductor layer 231 from between the first light shielding portion 6 and the second light shielding portion 210.

[0072] Also, as shown in FIG. 5, the drain connection portion 611 of the first portion 61 extends from the first insulating layer 201 to the drain region 231a. The second portion 62 is provided between the semiconductor layer 231 and the insulating layer 225 in which the scanning line 241 is provided. The third portion 63 is provided between the gate electrode 232 and the insulating layer 225.

[0073] And the length L3 in the Z2 direction of the third portion 63, the length L2 in the Z2 direction of the second portion 62, and the length L1 in the Z2 direction of the first portion 61 increase in this order. The length L1 is the longest. Therefore, the lengths L1, L2, and L3 satisfy the relationship L3 < L2 < L1. Note that each of the lengths L1, L2, and L3 is the maximum length. Therefore, the length L1 is the length of the side surface light shielding portion 612.

[0074] According to the configuration of the first light-shielding portion 6 in which the lengths L1, L2, and L3 satisfy the relationship L3 < L2 < L1, the first light-shielding portion 6 can be disposed near the semiconductor layer 231. Therefore, the incidence of light on the semiconductor layer 231 can be suppressed more effectively than in the prior art. Thus, it is possible to suppress the operation of the transistor 23 from becoming unstable. As a result, it is possible to suppress the occurrence of display defects such as luminance unevenness. Therefore, it is possible to suppress a decrease in display quality.

[0075] In addition, no other wiring and electrodes are interposed between the first light-shielding portion 6 and the semiconductor layer 231. Therefore, the first light-shielding portion 6 can be brought close to the semiconductor layer 231. Thus, the incidence of light in the Z1 direction on the semiconductor layer 231 by the first light-shielding portion 6 can be suppressed as compared with the case where wiring and electrodes are interposed between the first light-shielding portion 6 and the semiconductor layer 231.

[0076] In addition, the upper surfaces of the first portion 61, the second portion 62, and the third portion 63 are flush. Therefore, the distance D1 between the first portion 61 and the semiconductor layer 231, the distance D2 between the second portion 62 and the semiconductor layer 231, and the distance D3 between the third portion 63 and the semiconductor layer 231 increase in this order. The distance D3 is the longest. Therefore, the lengths D1, D2, and D3 satisfy the relationship D1 < D2 < D3. Note that the length D3 is 0 (zero). For this reason, the second portion 62 is closer to the semiconductor layer 231 in the direction along the Z axis than the third portion 63. By having the first light-shielding portion 6 include the second portion 62, the first light-shielding portion 6 can be brought closer to the semiconductor layer 231. Thus, the incidence of light on the semiconductor layer 231 can be exerted more effectively.

[0077] In particular, the surface of the second portion 62 facing the semiconductor layer 231 is preferably located between the surface of the gate electrode 232 facing the semiconductor layer 231 and the surface of the gate electrode 232 facing the scanning line 241 in the Z-axis direction. By locating the surface of the second portion 62 facing the semiconductor layer 231 in such a position, the distance between the second portion 62 and the semiconductor layer 231 can be made very short. Furthermore, by overlapping the second portion 62 with the low-concentration drain region 231d in a planar view, the second portion 62 can be made very close to the low-concentration drain region 231d. In other words, the distance between the second portion 62 and the low-concentration drain region 231d can be made much shorter than in the past. This makes it possible to suppress light from entering the semiconductor layer 231, particularly the low-concentration drain region 231d, along the Z1 direction. Suppressing the incidence of light along the Z1 direction is particularly effective in a configuration in which light is incident from the opposing substrate 3, as in this embodiment.

[0078] 11, each side surface light-shielding portion 612 extends in the Z2 direction from the first insulating layer 201 beyond the second light-shielding portion 210, and therefore the semiconductor layer 231 is surrounded by the first light-shielding portion 612 and the second light-shielding portion 210 when viewed in the Y1 direction. This makes it possible to suppress light from entering the semiconductor layer 231 from any angle when viewed in the Y1 direction.

[0079] Furthermore, as described above, the side surface light shielding portion 612 and the second light shielding portion 210 do not overlap in a planar view. Therefore, the side surface light shielding portion 612, which has a different potential from the second light shielding portion 210, can be made to extend further in the Z2 direction than the second light shielding portion 210. Therefore, when viewed in the Y1 direction, the semiconductor layer 231 can be surrounded by the first light shielding portion 612 and the second light shielding portion 210. Therefore, the incidence of light on the semiconductor layer 231 can be particularly effectively suppressed.

[0080] For example, the third recess R3 may be omitted, and in this case, the third portion 63 may be omitted.

[0081] 1E. Manufacturing method of first light-shielding portion 6 The above-mentioned first light-shielding portion 6 is manufactured, for example, by the following method: Note that the manufacturing method of the first light-shielding portion 6 is not limited to the following method.

[0082] Fig. 13 is a cross-sectional view illustrating a method for manufacturing the first recess R1. Fig. 14 is a plan view illustrating a method for manufacturing the first recess R1. As shown in Figs. 13 and 14, after forming the insulating layer 223, the first recess R1 penetrating the first substrate 21 and the insulating layers 221-223 is formed by etching. For example, if the first substrate 21 and the insulating layers 221-223 are made of an inorganic material containing silicon, a fluorine-based etching agent is used to etch away part of the insulating layers 221-223.

[0083] Fig. 15 is a cross-sectional view illustrating a method for manufacturing the second recess R2. Fig. 16 is a plan view illustrating the method for manufacturing the second recess R2. Next, as shown in Figs. 15 and 16, the second recess R2 is formed in the insulating layer 223 by etching. As described above, for example, if the insulating layer 223 is made of an inorganic material containing silicon, a portion of the insulating layer 223 is removed by etching using a fluorine-based etching agent.

[0084] 17 is a cross-sectional view illustrating a method for manufacturing the third recess R3. Next, as shown in FIG. 17, the third recess R3 is formed in the insulating layer 223 by etching. As described above, for example, if the insulating layer 223 is made of an inorganic material containing silicon, a portion of the insulating layer 223 is removed by etching using a fluorine-based etching agent.

[0085] The order of manufacturing the first recess R1, the second recess R2, and the third recess R3 is not limited to the above order. For example, the first recess R1, the second recess R2, and the third recess R3 may be partially formed at the same time.

[0086] Fig. 18 is a diagram for explaining a manufacturing method of the first light-shielding portion 6. As shown in Fig. 18, the first recess R1, the second recess R2, and the third recess R3 are filled with a conductive material such as tungsten, thereby forming the first light-shielding portion 6.

[0087] 2. Second embodiment In the second embodiment exemplified below, for elements whose actions or functions are similar to those of the first embodiment, the symbols used in the description of the first embodiment will be used and detailed descriptions of each will be omitted as appropriate.

[0088] Fig. 19 and Fig. 20 are cross-sectional views showing the second light-shielding part 210A in the second embodiment. Fig. 21 is a plan view showing the second light-shielding part 210A shown in Fig. 19. Fig. 22 is a diagram showing the planar arrangement of the second light-shielding part 210A and the first light-shielding part 6 shown in Fig. 19.

[0089] 19 to 21 does not overlap, in plan view, with any part of the semiconductor layer 231. Specifically, the second light-shielding portion 210A overlaps, in plan view, with the source region 231b, the channel region 231c, the low-concentration drain region 231d, and the low-concentration source region 231e, but does not overlap with the drain region 231a.

[0090] 22, the second light-shielding portion 210A does not overlap the first light-shielding portion 6 in plan view. This makes it easier to extend the first light-shielding portion 6, which has a different potential from the second light-shielding portion 210A, in the Z2 direction from the first insulating layer 201 beyond the second light-shielding portion 210 without contacting the second light-shielding portion 210A. Furthermore, because the second light-shielding portion 210A and the side light-shielding portion 612 do not overlap in plan view, the risk of the second light-shielding portion 210A and the side light-shielding portion 612 coming into contact with each other due to manufacturing errors can be reduced compared to the first embodiment.

[0091] Furthermore, as described above, since the second light-shielding portion 210A does not overlap with the drain region 231a, it is possible to suppress an increase in off-leak current caused by the second light-shielding portion 210A, which is the gate potential, approaching the drain region 231a. This makes it easier to bring the second light-shielding portion 210A close to the semiconductor layer 231. This makes it possible to effectively suppress light from entering the semiconductor layer 231 from the back surface.

[0092] From this viewpoint, it is preferable that the second light-shielding portion 210A does not overlap with the low-concentration drain region 231d in a planar view. However, when considering the viewpoint of suppressing the incidence of light on the semiconductor layer 231 by increasing the planar overlap between the semiconductor layer 231 and the second light-shielding portion 210A, rather than the viewpoint of bringing the second light-shielding portion 210A closer to the semiconductor layer 231, it is preferable that the second light-shielding portion 210A overlaps with the low-concentration drain region 231d in a planar view.

[0093] 3. Third embodiment In the third embodiment exemplified below, for elements whose actions or functions are similar to those of the first embodiment, the symbols used in the description of the first embodiment will be used and detailed descriptions of each will be omitted as appropriate.

[0094] 23 and 24 are cross-sectional views showing the third light-shielding portion 250 in the third embodiment. FIG. 25 is a plan view showing the third light-shielding portion 250 shown in FIG.

[0095] 23 and 24, in this embodiment, a third light-shielding portion 250 is provided on the first substrate 21. The third light-shielding portion 250 is spaced apart from the second light-shielding portion 210 and is disposed in a layer below the second light-shielding portion 210.

[0096] The third light-shielding portion 250 is provided in a recess H2 of the first substrate 21. The recess H2 is a depression formed in the first substrate 21, and is formed for each transistor 23. The recess H2 is formed along the Y1 direction, which is the extension direction of the semiconductor layer 231. The third light-shielding portion 250 is disposed in the recess H2. The third light-shielding portion 250 is formed using, for example, a damascene method. Note that if the recess H2 is not provided in the first substrate 21, the third light-shielding portion 250 is disposed on a flat surface of the first substrate 21 facing the Z1 direction. The third light-shielding portion 250 overlaps the semiconductor layer 231 in a planar view and is disposed between the first substrate 21 and the semiconductor layer 231. The third light-shielding portion 250, together with the second light-shielding portion 210, functions as a back-surface light-shielding portion disposed below the semiconductor layer 231.

[0097] The third light-shielding portion 250 includes, for example, a metal such as tungsten, titanium, chromium, iron, or aluminum, a metal nitride, or a metal silicide.

[0098] In this embodiment, the second light-shielding portion 210 is disposed on an insulating layer 219 provided on the first substrate 21. The insulating layer 219 is formed of an inorganic material containing silicon, such as silicon oxide, and is the same material as the insulating layer 221, for example.

[0099] In this embodiment, the first light-shielding portion 6 extends from the insulating layer 223 to the third light-shielding portion 250. The first light-shielding portion 6 is in contact with the third light-shielding portion 250. Therefore, the third light-shielding portion 250 has the same potential as the first light-shielding portion 6, specifically, the pixel potential.

[0100] 25 , the third light-shielding portion 250 has an elongated shape in a plan view, with its longitudinal direction along the Y-axis, which is the direction in which the scanning lines 241 extend. The third light-shielding portion 250 includes a wide portion 251, a first narrow portion 252, and a second narrow portion 253. The wide portion 251 is located between the first narrow portion 252 and the second narrow portion 253, and has a width, which is the length along the X-axis, wider than the first narrow portion 252 and the second narrow portion 253. The first narrow portion 252 extends from the wide portion 251 in the Y1 direction. The second narrow portion 253 extends from the wide portion 251 in the Y2 direction.

[0101] Although not shown in detail, the wide portion 251 is in contact with the side surface light shielding portion 612 of the first light shielding portion 6. Furthermore, the third light shielding portion 250 overlaps with the side surface light shielding portion 612 in a plan view, but the second light shielding portion 210 does not overlap with the side surface light shielding portion 612 in a plan view. Therefore, the plane area of ​​the third light shielding portion 250 is larger than the plane area of ​​the second light shielding portion 210 by the plane area of ​​the side surface light shielding portion 612.

[0102] As described above, in this embodiment, the third light-shielding portion 250 is provided between the first substrate 21 and the second light-shielding portion 210. The side surface light-shielding portion 612 is directly connected to the third light-shielding portion 250. By providing the third light-shielding portion 250, it is possible to block light that may enter the semiconductor layer 231 from between the second light-shielding portion 210 and the side surface light-shielding portion 612.

[0103] Furthermore, it is preferable that the length along the Z axis of the second light-shielding portion 210, i.e., the thickness D21, is thicker than the thickness D25 of the third light-shielding portion 250. The second light-shielding portion 210 is closer to the semiconductor layer 231 than the third light-shielding portion 250. For this reason, when the thickness D21 is thicker than the thickness D25, the effect of suppressing light from entering the semiconductor layer 231 can be improved compared to when the thickness D21 is thinner.

[0104] The thickness D21 may be equal to or less than the thickness D25.

[0105] 4. Variations The above-described exemplary embodiments may be modified in various ways. Specific modifications that may be applied to the above-described embodiments are exemplified below. Two or more aspects arbitrarily selected from the following examples may be combined as appropriate to the extent that they are not mutually inconsistent.

[0106] In the above description, the fourth light-shielding portion 7 is connected to the second light-shielding portion 210, but it does not have to be connected. Also, the fourth light-shielding portion 7 may be omitted.

[0107] In the above-described embodiments, the electro-optical device 100 is an active matrix type, but the driving method of the electro-optical device 100 is not limited to this, and may be, for example, a passive matrix type.

[0108] The driving method of the "electro-optical device" is not limited to the vertical electric field method, but may be a horizontal electric field method. The horizontal electric field method may be, for example, an in-plane switching (IPS) mode. The vertical electric field method may be, for example, a twisted nematic (TN) mode, a vertical alignment (VA) mode, a PVA mode, or an optically compensated bend (OCB) mode.

[0109] 5.Electronic equipment The electro-optical device 100 can be used in various electronic devices.

[0110] 26 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 has an electro-optical device 100 that displays various images, a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0111] 27 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 has an operation button 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to an operation of the operation button 3001. The control unit 3002 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0112] FIG. 28 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-plate projector. The electro-optical device 1r is an electro-optical device 100 corresponding to the red display color, the electro-optical device 1g is an electro-optical device 100 corresponding to the green display color, and the electro-optical device 1b is an electro-optical device 100 corresponding to the blue display color. In other words, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0113] The illumination optical system 4001 supplies a red component r of light emitted from an illumination device 4002, which is a light source, to an electro-optical device 1r, a green component g to an electro-optical device 1g, and a blue component b to an electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 in accordance with a display image. The projection optical system 4003 combines the light emitted from the electro-optical devices 1r, 1g, and 1b and projects the combined light onto a projection surface 4004.

[0114] The above electronic devices include the electro-optical device 100 and the control unit 2003, 3002, or 4005. The electro-optical device 100 has excellent light-blocking properties due to the first light-blocking portion 6 of the semiconductor layer 231, which prevents the operation of the transistor 23 from becoming unstable. This reduces the risk of display defects. Therefore, the inclusion of the electro-optical device 100 can improve the display quality of the personal computer 2000, smartphone 3000, or projection display device 4000.

[0115] Electronic devices to which the electro-optical device of the present invention can be applied are not limited to the devices exemplified above, and examples thereof include PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, videophones, and POS (Point of Sale) terminals. Furthermore, examples of electronic devices to which the present invention can be applied include printers, scanners, copiers, video players, and devices equipped with touch panels.

[0116] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the above-described embodiments. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-described embodiments, and any configuration can be added.

[0117] In the above description, a liquid crystal display device has been described as an example of the electro-optical device of the present invention, but the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to an image sensor, etc. [Explanation of symbols]

[0118] 2...element substrate, 5...liquid crystal layer, 6...first light-shielding portion, 7...fourth light-shielding portion, 21...first substrate, 23...transistor, 25...pixel electrode, 61...first portion, 62...second portion, 63...third portion, 100...electro-optical device, 201...first insulating layer, 210...second light-shielding portion, 220...first insulating layer, 221...insulating layer (second insulating layer), 231...semiconductor layer, 231a...drain region, 231b...source region, 231c...channel region, 231d...lightly doped drain region, 231e...lightly doped source region, 232...gate electrode, 233...gate insulating film, 241...scanning line, 250...third light-shielding portion, 611...drain connection portion, 612...side light-shielding portion, D21...thickness, D25...thickness.

Claims

1. A substrate; a transistor including a gate electrode disposed in a first direction relative to the substrate, and a semiconductor layer disposed between the substrate and the gate electrode; a scanning line disposed in the first direction relative to the gate electrode and electrically connected to the gate electrode; a first light-shielding portion that is disposed in the first direction with respect to the semiconductor layer and overlaps with the semiconductor layer in a plan view seen from the first direction; a second light-shielding portion that is arranged in a second direction opposite to the first direction with respect to the semiconductor layer and overlaps with the semiconductor layer in the plan view, the potential of the first light-shielding portion and the potential of the second light-shielding portion are different from each other, the first light-shielding portion is provided on both sides of the semiconductor layer in a width direction, and has a side light-shielding portion that is in the same layer as the second light-shielding portion or extends further in the second direction than the second light-shielding portion from a first insulating layer between the scanning line and the gate electrode; Electro-optical device characterized by:

2. the first light-shielding portion has a first portion including the side light-shielding portion, a second portion, and a third portion; the second portion is provided between the semiconductor layer and a layer on which the scanning line is provided, the third portion is provided between the gate electrode and a layer in which the scanning line is provided, a length of the third portion in the second direction, a length of the second portion in the second direction, and a length of the first portion in the second direction increase in this order, and the length of the first portion in the second direction is the longest; The electro-optical device according to claim 1 .

3. the semiconductor layer includes a drain region, a source region, and a channel region provided between the drain region and the source region; the first light-shielding portion is electrically connected to the drain region, and the first light-shielding portion has a drain connection portion that overlaps the drain region in the plan view; the second light-shielding portion is electrically connected to the gate electrode; The electro-optical device according to claim 1 .

4. the semiconductor layer extends in a third direction intersecting the first direction, the semiconductor layer is surrounded by the first light-shielding portion and the second light-shielding portion when viewed in the first direction; The electro-optical device according to claim 1 .

5. the side light-shielding portion and the second light-shielding portion do not overlap in the plan view; The electro-optical device according to claim 1 .

6. the semiconductor layer includes a drain region, a source region, and a channel region provided between the drain region and the source region; the first light-shielding portion includes a first portion having the side light-shielding portion and a drain connection portion that is electrically connected to the drain region and overlaps with the drain region in the plan view, the first portion and the second light-shielding portion do not overlap in the plan view; The electro-optical device according to claim 1 .

7. the second light-shielding portion does not overlap the drain region in the plan view; 7. The electro-optical device according to claim 6.

8. the first portion is provided to surround the gap between the drain region and the channel region in the plan view; 7. The electro-optical device according to claim 6.

9. a third light-shielding portion disposed between the substrate and the second light-shielding portion; the side surface light-shielding portion is connected to the third light-shielding portion, The electro-optical device according to claim 1 .

10. The thickness of the second light-shielding portion is greater than the thickness of the third light-shielding portion. The electro-optical device according to claim 9 .

11. the side surface light-shielding portion protrudes in the second direction further than the second light-shielding portion; The electro-optical device according to claim 1 .

12. The electro-optical device according to claim 1 , and a control unit that controls the operation of the electro-optical device.

Images