Signal output circuit

Abstract

To improve the symmetry between a pair of signals when transmitting signals differentially.SOLUTION: A high-side output circuit (110) includes a parallel circuit of a plurality of high-side transistors (MH) provided between a first DC wiring (WVCC) and a first output terminal (HH). The low-side output circuit (120) includes a parallel circuit of a plurality of low-side transistors (ML) provided between a second DC wiring (WGND) and a second output terminal (LL). The gate voltage adjustment circuit (160) adjusts a specific gate voltage (VGL) for setting each low-side transistor to an ON state on the basis of the intermediate voltage between a first DC voltage and a second DC voltage.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a signal output circuit. [Background technology]

[0002] Signal transmission circuits are used in CAN (Controller Area Network) and other networks. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-19219

[0004] [overview] When transmitting signals differentially, it is required to have good symmetry between the pair of signals.

[0005] A signal output circuit according to one aspect of the present disclosure includes a high-side output circuit having a first DC wiring configured to apply a predetermined first DC voltage, a first signal terminal, and a first parallel circuit of a plurality of high-side transistors provided between the first DC wiring and the first signal terminal; a low-side output circuit having a second DC wiring configured to apply a second DC voltage lower than the first DC voltage, a second signal terminal, and a second parallel circuit of a plurality of low-side transistors provided between the second DC wiring and the second signal terminal; and a low-side output circuit configured to individually set the plurality of high-side transistors to on or off, and a control circuit configured to generate a first output signal at the first signal terminal by controlling the current between the first DC wiring and the first signal terminal through one parallel circuit, and to individually set the plurality of low-side transistors to on or off, and to generate a second output signal at the second signal terminal by controlling the current between the second DC wiring and the second signal terminal through the second parallel circuit; and a gate voltage adjustment circuit configured to adjust a specific gate voltage for setting each low-side transistor to on based on an intermediate voltage between the first DC voltage and the second DC voltage. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a configuration diagram of an ECU according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a configuration diagram of an ECU system having two ECUs according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic diagram showing the internal configuration of a transceiver in a transmitting ECU and a transceiver in a receiving ECU 1 according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a timing chart showing the relationship between a number of signals according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is an explanatory diagram of the relationship between paired signals and skew according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a circuit diagram of a transmission circuit according to a reference example. [Figure 7] FIG. 7 is a circuit diagram of a transmission circuit according to a first example of an embodiment of the present disclosure. [Figure 8] FIG. 8 is a circuit diagram of a high-side output circuit according to a first example of an embodiment of the present disclosure. [Figure 9] FIG. 9 is a state transition diagram of one unit circuit in a high-side output circuit according to a first example of an embodiment of the present disclosure. [Figure 10] FIG. 10 is a circuit diagram of a low-side output circuit according to a first example of an embodiment of the present disclosure. [Figure 11] FIG. 11 is a state transition diagram of one unit circuit in a low-side output circuit according to a first example of an embodiment of the present disclosure. [Figure 12] FIG. 12 is an operation flowchart of a transmission circuit according to a first example belonging to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram showing the electrical characteristics of a high-side transistor and the electrical characteristics of a low-side transistor according to a first example belonging to an embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and redundant descriptions of identical parts will be omitted as a general rule. For the sake of brevity, this specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and may omit or abbreviate the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs. For example, a high-side transistor referred to by "MH" (see FIG. 7) may be written as a high-side transistor MH or abbreviated as a transistor MH, but these terms all refer to the same thing.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as a ground voltage. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0009] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any signal that functions as a voltage signal, an increase or decrease in the signal's potential means an increase or decrease in the signal's potential. The same applies to other similar expressions. For any given signal or voltage, a signal or voltage at a high level strictly means that the signal or voltage level is at a high level, and a signal or voltage at a low level strictly means that the signal or voltage level is at a low level.

[0010] For any transistor configured as a FET (field effect transistor) exemplified by a MOSFET, the on-state refers to a state where the drain and source of the transistor are conducting, and the off-state refers to a state where the drain and source of the transistor are non-conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source.

[0011] In any transistor configured as a MOSFET, the gate-source voltage refers to the potential of the gate as seen from the potential of the source, and the drain-source voltage refers to the potential of the drain as seen from the potential of the source.

[0012] Any switch can be composed of one or more FETs (field effect transistors). When a certain switch is in the on-state, the two ends of the switch are conducting, while when a certain switch is in the off-state, the two ends of the switch are non-conducting. Hereinafter, for any transistor or switch, the on-state and off-state may also be simply expressed as on and off.

[0013] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.

[0014] When any two voltages to be compared are v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0015] FIG. 1 shows the configuration of an ECU 1 according to an embodiment of the present disclosure. ECU is an abbreviation for "Electronic Control Unit." The ECU 1 is mounted on a vehicle such as an automobile. The ECU 1 is a unit that controls, for example, various components mounted on the vehicle (such as an engine, a motor, a transmission, a brake, a power steering, and a power window). Hereinafter, the vehicle shown in this embodiment refers to a vehicle on which the ECU 1 is mounted.

[0016] The ECU 1 includes a transceiver 10, an MPU (Micro Processing Unit) 20, a regulator 30, and a termination resistor R TM , a reverse current prevention diode 41, and capacitors 42 and 43. The ECU 1 is also provided with terminals TP, TN, TH, and TL as terminals for connection to an external circuit of the ECU 1. An input voltage VPW is supplied to the terminal TP from outside the ECU 1. The input voltage VPW is a positive DC voltage. The terminal TN is connected to ground.

[0017] The input voltage VPW supplied to the terminal TP is supplied to the regulator 30 through the backflow prevention diode 41, and the regulator 30 outputs the voltage (VPW-Vf 41 ) is converted to DC / DC to generate the power supply voltage VCC, which is a positive DC voltage. 41 represents the forward voltage of the blocking diode 41. Therefore, the voltage (VPW-Vf 41 ) is the forward voltage Vf from the input voltage VPW 41 The power supply voltage VCC has a predetermined positive DC voltage value (for example, 5 V). Here, the power supply voltage VCC is a voltage (VPW-Vf 41 ), and therefore, regulator 30 operates at a voltage lower than the voltage supplied to it (VPW-Vf 41 The regulator 30 generates the power supply voltage VCC by stepping down the voltage (VPW-Vf 41 ) to generate the power supply voltage VCC.

[0018] Specifically, the terminal TP is connected to the anode of a reverse current prevention diode 41, and the cathode of the reverse current prevention diode 41 is connected to a first end of a capacitor 42. A second end of the capacitor 42 is connected to the terminal TN. The regulator 30 is connected to the first and second ends of the capacitor 42. A voltage (VPW-Vf 41 ) is applied to the regulator 30. 41 ) is subjected to DC / DC conversion to generate a power supply voltage VCC. In the ECU 1, a capacitor 43 is provided between a line to which the power supply voltage VCC is applied and a terminal TN.

[0019] The transceiver 10 is an electronic component (semiconductor device) formed by encapsulating a semiconductor integrated circuit in a resin housing (package), and each circuit constituting the transceiver 10 is integrated using semiconductors. The housing of the electronic component serving as the transceiver 10 has multiple external terminals exposed from the housing to the outside of the transceiver 10. As some of the multiple external terminals provided on the transceiver 10, FIG. 1 shows a power supply terminal IN, a ground terminal GND, a high-side signal terminal HH, a low-side signal terminal LL, a receive data output terminal RXD, and a transmit data input terminal TXD. Other external terminals may also be provided on the transceiver 10.

[0020] In the ECU1, a power supply voltage VCC is supplied to a power supply terminal IN. A ground terminal GND is connected to a terminal TN and is therefore connected to ground. A signal terminal HH is connected to a terminal TH via a signal wiring 44 in the ECU1, and a signal terminal LL is connected to a terminal TL via a signal wiring 45 in the ECU1. A termination resistor R TM is provided between the signal wirings 44 and 45. That is, the termination resistor R TM The first end of the resistor R is connected to the signal wiring 44 (and therefore to the terminals HH and TH). TM The second end of each of the terminals RXD and TXD is connected to the signal wiring 45 (and therefore to the terminals LL and TL).

[0021] The MPU 20 is connected to a wiring to which a power supply voltage VCC is applied and to a terminal TN, and is driven based on the power supply voltage VCC with respect to the ground voltage. The MPU 20 is an arbitrary processing unit such as a microcomputer. The MPU 20 in one ECU 1 can communicate bidirectionally with the MPU 20 in another ECU 1 using the transceiver 10.

[0022] FIG. 2 shows the configuration of an ECU system having two ECUs 1 according to this embodiment. While an ECU system may have three or more ECUs 1, we focus here on two ECUs 1. The ECU system is provided with cables 2 to 5. Cable 2 is connected to terminal TP of each ECU 1 and transmits an input voltage VPW. Cable 3 is connected to terminal TN of each ECU 1 and is also connected to ground. Cable 4 is connected to terminal TH of each ECU 1, and cable 5 is connected to terminal TL of each ECU 1. Although not clear from FIG. 2, cables 4 and 5 form a twisted pair cable. A voltage source VS is connected to the ECU system. The negative output terminal of the voltage source VS is connected to cable 3 and ground, and the positive output terminal of the voltage source VS is connected to cable 2. The voltage source VS outputs an input voltage VPW to each ECU 1 from its positive output terminal, with the potential of the negative output terminal as the reference. Therefore, the input voltage VPW is applied to cable 2. The voltage source VS is a battery installed in a vehicle in which the ECU system is installed. Alternatively, a power supply circuit that generates the input voltage VPW by power conversion of the output voltage of a battery mounted on the vehicle may be the voltage source VS. Alternatively, the voltage source VS may be any DC voltage source.

[0023] Of the two ECUs 1, one ECU 1 functions as a transmitting ECU, and the other ECU 1 functions as a receiving ECU. A signal is transmitted from the transmitting ECU to the receiving ECU. The communication between the two ECUs 1 (communication between the two transceivers 10) is serial and half-duplex. Therefore, an ECU 1 that functions as a transmitting ECU at one timing may function as a receiving ECU at another timing. An in-vehicle network is formed in the vehicle, and bidirectional communication between ECUs 1 is realized through the in-vehicle network. Here, the in-vehicle network is assumed to be a network that follows the CAN (Controller Area Network) communication protocol. In this case, each termination resistor R TM has a resistance value of 120 Ω (ohms). Cables 4 and 5 correspond to the main bus in the CAN. When three or more ECUs 1 are provided in the ECU system, a sub-bus (not shown) is connected to cables 4 and 5, and a termination resistor R TM An ECU 1 other than the two ECUs 1 provided with the sub-bus is connected to the sub-bus.

[0024] FIG. 2 shows a state in which the ECU1 shown on the left functions as a transmitting ECU, and the ECU1 shown on the right functions as a receiving ECU. In the transmitting ECU1, the MPU 20 supplies a transmitting data signal S_T to the transmitting data input terminal TXD of the transceiver 10. The transmitting data signal S_T is a binary signal having a high level or a low level. In the transmitting data signal S_T, a value of "1" is assigned to either the high level or the low level, and a value of "0" is assigned to the other. In the transmitting data signal S_T, the high level has the level of the power supply voltage VCC, and the low level has the level of the ground voltage (i.e., a level of 0 V). In the transmitting ECU1, the transmitting data signal S_T is transmitted between the MPU 20 and the transceiver 10 using a single-ended transmission method.

[0025] The transceiver 10 in the transmitting ECU 1 converts the transmission data signal S_T into a differential signal S_DIF and transmits the differential signal S_DIF to the transceiver 10 in the receiving ECU 1. In the transmitting ECU 1, the transceiver 10 generates the differential signal S_DIF between terminals HH and LL. The differential signal S_DIF propagates through cables 4 and 5 and is applied between terminals HH and LL of the transceiver 10 in the receiving ECU 1. The differential signal S_DIF is transmitted between the transceiver 10 in the transmitting ECU 1 and the transceiver 10 in the receiving ECU 1 using a differential transmission method.

[0026] In the receiving ECU 1, the transceiver 10 converts the differential signal S_DIF received at terminals HH and LL into a received data signal S_R and outputs the received data signal S_R from the received data output terminal RXD to the MPU 20. The received data signal S_R, like the transmitted data signal S_T, is a binary signal having a high level or a low level. In the received data signal S_R, a value of "1" is assigned to either the high level or the low level, and a value of "0" is assigned to the other. In the received data signal S_R, the high level has the level of the power supply voltage VCC, and the low level has the level of the ground voltage (i.e., 0 V). In the receiving ECU 1, the transmission method of the received data signal S_R between the transceiver 10 and the MPU 20 is single-ended transmission.

[0027] 3 shows the schematic internal configuration of the transceiver 10 in the transmitting ECU 1 and the schematic internal configuration of the transceiver 10 in the receiving ECU 1. Each transceiver 10 includes a transmitting circuit 11 and a receiving circuit 12. In the transceiver 10 in the transmitting ECU 1, the transmitting circuit 11 generates a differential signal S_DIF between terminals HH and LL based on a transmit data signal S_T supplied to a transmit data input terminal TXD. In the transceiver 10 in the receiving ECU 1, the receiving circuit 12 converts the differential signal S_DIF received at terminals HH and LL into a receive data signal S_R and outputs the receive data signal S_R from a receive data output terminal RXD.

[0028] FIG. 4 is a timing chart showing the relationship between the transmit data signal S_T, differential signal S_DIF, and receive data signal S_R. The differential signal S_DIF is composed of a high-side signal SH and a low-side signal SL. The high-side signal SH is a signal generated by the transceiver 10 of the transmitting ECU 1 at the signal terminal HH (first output signal from the signal terminal HH) and applied to the cable 4. The low-side signal SL is a signal generated by the transceiver 10 of the transmitting ECU 1 at the signal terminal LL (second output signal from the signal terminal LL) and applied to the cable 5. The signal value of the differential signal S_DIF is the potential difference (SH-SL). The potential difference (SH-SL) is the potential of the high-side signal SH relative to the potential of the low-side signal SL, and is called the differential mode component DIF (i.e., "DIF = SH-SL"). On the other hand, the average signal of the high-side signal SH and the low-side signal SL has a potential "(SH+SL) / 2" and is called the common mode component COM (ie, "COM=(SH+SL) / 2").

[0029] Just before time t1, the transmit data signal S_T and the receive data signal S_R are at a low level. Just before time t1, the high-side signal SH has a voltage VM1, and the low-side signal SL has a voltage VM2. Although the voltages VM1 and VM2 basically coincide with the intermediate voltage (VCC / 2), the voltages VM1 and VM2 may differ slightly from each other. In FIG. 4, for convenience of illustration, the levels of the voltages VM1 and VM2 are slightly shifted up and down. The intermediate voltage (VCC / 2) is the intermediate voltage between the power supply voltage VCC and the ground voltage (i.e., the average voltage between the power supply voltage VCC and the ground voltage).

[0030] At time t1, the level of the transmission data signal S_T is switched to a high level. In response to the signal S_T being switched to a high level, the transmission circuit 11 in the transmitting ECU 1 gradually increases the level of the high-side signal SH from the level of voltage VM1 toward the level of voltage VH, and gradually decreases the level of the low-side signal SL from the level of voltage VM2 toward the level of voltage VL. Although the voltage VH may coincide with the power supply voltage VCC, depending on the internal configuration of the transmission circuit 11 and the termination resistor RTM is somewhat lower than the power supply voltage VCC depending on the value. The voltage VL may coincide with the ground voltage, but depending on the internal configuration of the transmission circuit 11 and the value of the termination resistance R TM is somewhat higher than the ground voltage. In any case, “VM1 < VH”, “VL < VM2” and “VL < VH” hold. After time t1 and until immediately before time t2, the level of the high-side signal SH continues to rise, and at time t2, when the level of the high-side signal SH reaches the level of the voltage VH, the rise in the level of the high-side signal SH ends. After time t1 and until immediately before time t2, the level of the low-side signal SL continues to decrease, and at time t2, when the level of the low-side signal SL reaches the level of the voltage VL, the decrease in the level of the low-side signal SL ends.

[0031] At time t3 after time t2, the level of the transmission data signal S_T switches from the high level to the low level. In response to the switching of the signal S_T to the low level, the transmission circuit 11 in the transmission-side ECU1 gradually decreases the level of the high-side signal SH from the level of the voltage VH toward the level of the voltage VM1, and gradually increases the level of the low-side signal SL from the level of the voltage VL toward the level of the voltage VM2. After time t3 and until immediately before time t4, the decrease in the level of the high-side signal SH continues, and at time t4, when the level of the high-side signal SH reaches the level of the voltage VM1, the decrease in the level of the high-side signal SH ends. After time t3 and until immediately before time t4, the increase in the level of the low-side signal SL continues, and at time t4, when the level of the low-side signal SL reaches the level of the voltage VM2, the increase in the level of the low-side signal SL ends. Thereafter, each time the level of the transmission data signal S_T switches from the low level to the high level, the same operation as between times t1 and t2 is performed, and each time the level of the transmission data signal S_T switches from the high level to the low level, the same operation as between times t3 and t4 is performed.

[0032] The receiving circuit 12 of the receiving-side ECU1 uses the differential mode component DIF as a predetermined threshold voltage V THH and V THLThe received data signal S_R is generated by comparing it with the threshold voltage V THH and V THL is greater than the differential voltage (VM1-VM2) between the voltages VM1 and VM2 and less than the differential voltage (VH-VL) between the voltages VH and VL. THL <V THH " holds true.

[0033] Immediately before time t1, the differential mode component DIF is equal to the differential voltage (VM1-VM2). <V THL When the condition "VM1-VM2" is satisfied, the level of the received data signal S_R is set to a low level. <V THL ", the level of the received data signal S_R is low immediately before time t1. Between times t1 and t2, the component DIF rises, and in the process of rising, "DIF <V THH " to "DIF≧V THH When the level of the received data signal S_R is changed from low to high, the receiving circuit 12 of the receiving ECU 1 changes the level of the received data signal S_R from low to high. THL The level of the received data signal S_R is maintained at a high level until the condition "V THL <DIF”から“V THL ≧DIF”, the receiving circuit 12 of the receiving ECU 1 switches the level of the receiving data signal S_R from high to low, and then, when “DIF≧V THH The level of the received data signal S_R is maintained at a low level until the condition "is met." is satisfied.

[0034] FIG. 4 shows the relationship between various signals when the symmetry between the signals SH and SL is ideal. When the symmetry between the signals SH and SL is ideal, the amplitude of the high-side signal SH and the amplitude of the low-side signal SL are equal, and the timing of the changes in the high-side signal SH and the low-side signal SL coincide, as well as the slope of their changes. As a result, when the symmetry between the signals SH and SL is ideal, the common-mode component COM remains constant, as shown in FIG. 4. If the amplitudes of the high-side signal and the low-side signal SL differ, or if the timing of the changes in the high-side signal SH and the low-side signal SL differ, or if the slopes of their changes differ, fluctuations will occur in the common-mode component COM. Fluctuations in the common-mode component COM can generate common-mode noise, which can adversely affect the noise characteristics of the system.

[0035] 5, assuming that the skew (time difference) between the first and second voltage signals having AC components is constant, the voltage difference between the first and second voltage signals is larger for high-frequency components than for low-frequency components. Therefore, in order to suppress common-mode noise due to skew, it is important to make the waveforms of the high-side signal SH and the low-side signal SL smooth and with few high-frequency components.

[0036] <<Reference example>> 6 shows the main components of a transmitter circuit 11ref according to a reference example. The transmitter circuit 11ref includes a high-side output circuit 910, a low-side output circuit 920, a high-side protection circuit 930, and a low-side protection circuit 940. The high-side output circuit 910 includes a plurality of unit circuits 911 (30 unit circuits 911 in this example), a current limiting transistor 914, and a pull-up resistor 915. The low-side output circuit 920 includes a plurality of unit circuits 921 (30 unit circuits 921 in this example), a current limiting transistor 924, and a pull-down resistor 925. Each unit circuit 911 is composed of a series circuit of a high-side transistor 912 and a resistor 913, and each unit circuit 921 is composed of a series circuit of a low-side transistor 922 and a resistor 923.

[0037] A current limiting transistor 914 is connected to a wiring to which a power supply voltage VCC is applied, and a plurality of unit circuits 911 are provided between the current limiting transistor 914 and a node 916. Although not clear from FIG. 6 , the plurality of unit circuits 911 are connected in parallel with one another. A high-side protection circuit 930 is provided between the node 916 and a signal terminal HH. The high-side protection circuit 930 is composed of a series circuit of a high-voltage protection transistor 931 and a backflow prevention diode 932, and protects the high-side output circuit 910 (particularly the high-side transistor 912) from abnormal voltages that may be applied to the signal terminal HH.

[0038] A current limiting transistor 924 is connected to a wiring to which a ground voltage is applied, and a plurality of unit circuits 921 are provided between the current limiting transistor 924 and a node 926. Although not clear from FIG. 6 , the plurality of unit circuits 921 are connected in parallel with one another. A low-side protection circuit 940 is provided between the node 926 and a signal terminal LL. The low-side protection circuit 940 is composed of a series circuit of a high-voltage protection transistor 941 and a backflow prevention diode 942, and protects the low-side output circuit 920 (particularly the low-side transistor 922) from abnormal voltages that may be applied to the signal terminal LL.

[0039] Protection transistors 931 and 941 are normally fixed in the on state. The gates of current limiting transistors 914 and 924 are biased at appropriate voltages. Note that pull-up resistor 915 has a resistance value that is sufficiently larger than that of each resistor 913, so the effect of pull-up resistor 915 on the output resistance value of high-side output circuit 910 is negligible. Similarly, pull-down resistor 925 has a resistance value that is sufficiently larger than that of each resistor 923, so the effect of pull-down resistor 925 on the output resistance value of low-side output circuit 920 is negligible.

[0040] The operation of the transmission circuit 11ref will be described with reference to the timing chart of FIG. 4. Just before time t1, all of the transistors 912 and 922 are off. Between times t1 and t2, the multiple transistors 912 in the multiple unit circuits 911 are sequentially switched on one by one, and the multiple transistors 922 in the multiple unit circuits 921 are sequentially switched on one by one. At time t2, all of the transistors 912 and 922 are on. Thereafter, between times t3 and t4, the multiple transistors 912 in the multiple unit circuits 911 are sequentially switched off one by one, and the multiple transistors 922 in the multiple unit circuits 921 are sequentially switched off one by one. At time t4, all of the transistors 912 and 922 are off. Through this operation, a smoothly changing, well-symmetrical differential signal S_DIF can be obtained, as shown in FIG. 4.

[0041] In the transmission circuit 11ref, the output resistance value of the high-side output circuit 910 is determined by the total number of transistors 912 that are turned on, and decreases as this total number increases. Similarly, the output resistance value of the low-side output circuit 920 is determined by the total number of transistors 922 that are turned on, and decreases as this total number increases.

[0042] The magnitude of the output current from the high-side output circuit 910 to the signal terminal HH is determined depending on the output resistance value of the high-side output circuit 910. For this reason, an excessively large output current may occur if the signal terminal HH is short-circuited to ground, for example. Therefore, a current-limiting transistor 914 is provided to set an upper limit on the output current of the high-side output circuit 910. For example, the current-limiting transistor 914 and another transistor (not shown) form a current mirror circuit, and the current determined by this current mirror circuit becomes the upper limit on the output current of the high-side output circuit 910. The same applies to the low-side output circuit 920.

[0043] In the transmitter circuit 11ref, the output resistance of each output circuit (910, 920) is determined by the resistors (913, 923), making it easy to generate a differential signal S_DIF with good symmetry. However, because many components are stacked vertically (for example, in the high-side output circuit 910, components 914, 912, and 913 are stacked vertically), the number of components is large. Furthermore, because the output resistance of each output circuit (910, 920) is determined by the resistors (913, 923), the on-resistance of the transistors (912, 922) must be sufficiently small compared to the resistors (913, 923). Reducing the on-resistance of the transistors (912, 922) requires increasing the size of the transistors (912, 922), resulting in increased circuit area and cost. Additionally, increasing the size of the transistors (912, 922) increases switching noise associated with the switching of the transistors (912, 922).

[0044] Below, several examples will be described that take these circumstances into consideration. The matters described above in this embodiment (excluding matters related to the Reference Example) apply to each of the following examples unless otherwise specified and unless there is a contradiction. If there are any matters in each example that contradict the matters described above, the description in that example may take precedence. Furthermore, unless there is a contradiction, matters described in any of the following examples can also be applied to any of the other examples (i.e., any two or more of the multiple examples can be combined).

[0045] <<First Example>> A first embodiment will be described. FIG. 7 is a configuration diagram of a transmission circuit 11 according to the first embodiment. The transmission circuit 11 includes a high-side output circuit 110, a low-side output circuit 120, a high-side protection circuit 130, a low-side protection circuit 140, a control circuit 150, and a gate voltage adjustment circuit 160. The transmission circuit 11 also includes a power supply wiring W to which a power supply voltage VCC is applied. VCC and ground wiring W to which ground voltage is applied GND The power supply voltage VCC and the ground voltage are examples of the first DC voltage and the second DC voltage. VCC and ground wiring W GNDare examples of the first DC wiring and the second DC wiring. The intermediate voltage (VCC / 2) is an intermediate voltage between the first DC voltage and the second DC voltage (i.e., the average voltage of the first DC voltage and the second DC voltage). It can be said that the power supply voltage VCC corresponds to the positive power supply voltage and the ground voltage corresponds to the negative power supply voltage, so the intermediate voltage (VCC / 2) corresponds to an intermediate voltage between the positive power supply voltage and the negative power supply voltage (i.e., the average voltage of the positive power supply voltage and the negative power supply voltage).

[0046] The high-side output circuit 110 includes a plurality of unit circuits 111 and a pull-up resistor 112. A high-side signal SH generated at a signal terminal HH corresponds to the output signal (first output signal) of the high-side output circuit 110. The plurality of unit circuits 111 have the same configuration, and each unit circuit 111 includes a high-side transistor MH, which is an output transistor on the high side, and a selector SEL_H, which is a high-side selector. The high-side transistor MH is configured by a P-channel MOSFET. The plurality of high-side transistors MH in the plurality of unit circuits 111 are connected in parallel with each other. The source of each high-side transistor MH is connected to a power supply wiring W VCC and receives the power supply voltage VCC. The drain of each high-side transistor MH is connected to a node 113. A first end of the pull-up resistor 112 is connected to the power supply wiring W VCC , and the second end of the pull-up resistor 112 is connected to a node 113. In each unit circuit 111, under the control of the control circuit 150, the selector SEL_H selects a connection destination of the gate of the corresponding high-side transistor MH to a gate wiring W (described later). GH Or power wiring W VCC Switch to.

[0047] The high-side protection circuit 130 has a series circuit of a protection transistor 131 and a backflow prevention diode 132, and is inserted between the high-side output circuit 110 and the signal terminal HH. The protection transistor 131 is configured with a P-channel MOSFET. The anode of the backflow prevention diode 132 is connected to the node 113, and the cathode of the backflow prevention diode 132 is connected to the source of the protection transistor 131. The drain of the protection transistor 131 is connected to the signal terminal HH. The gate of the protection transistor 131 is connected to the control circuit 150, and the protection transistor 131 is set on or off by a driver in the control circuit 150.

[0048] The low-side output circuit 120 includes a plurality of unit circuits 121 and a pull-down resistor 122. A low-side signal SL generated at a signal terminal LL corresponds to the output signal (second output signal) of the low-side output circuit 120. The plurality of unit circuits 121 have the same configuration, and each unit circuit 121 includes a low-side transistor ML, which is an output transistor on the low side, and a selector SEL_L, which is a low-side selector. The low-side transistor ML is configured by an N-channel MOSFET. The plurality of low-side transistors ML in the plurality of unit circuits 121 are connected in parallel with each other. The source of each low-side transistor ML is connected to a ground wiring W GND and receives the ground voltage. The drain of each low-side transistor ML is connected to node 123. The first end of the pull-down resistor 122 is connected to the ground wiring W GND , and the second end of the pull-down resistor 122 is connected to a node 123. In each unit circuit 121, under the control of the control circuit 150, the selector SEL_L selects the connection destination of the gate of the corresponding low-side transistor ML to a gate wiring W (described later). GL Or ground wiring W GND Switch to.

[0049] The low-side protection circuit 140 has a series circuit of a protection transistor 141 and a backflow prevention diode 142, and is inserted between the low-side output circuit 120 and the signal terminal LL. The protection transistor 141 is configured with an N-channel MOSFET. The anode of the backflow prevention diode 142 is connected to the signal terminal LL, and the cathode of the backflow prevention diode 142 is connected to the drain of the protection transistor 141. The source of the protection transistor 141 is connected to node 123. The gate of the protection transistor 141 is connected to the control circuit 150, and the protection transistor 141 is set on or off by a driver in the control circuit 150.

[0050] When one or more high-side transistors MH are in an on-state in the high-side output circuit 110, a signal current IH is generated. VCC The signal current IL flows from the signal terminal LL to the ground wiring W via the high-side transistor MH in the ON state and the high-side protection circuit 130. When one or more low-side transistors ML in the low-side output circuit 120 are in the ON state, a signal current IL is generated. The signal current IL flows from the signal terminal LL to the ground wiring W via the low-side protection circuit 140 and the low-side transistor ML in the ON state. GND In FIG. 7, resistor RL represents a load resistor connected in series between signal terminals HH and LL. The load resistor RL is connected to the termination resistor R TH and the termination resistor R of the receiving ECU1 TH This corresponds to a parallel circuit with (see Figure 2).

[0051] The pull-up resistor 112 is a resistor that keeps the voltage of the node 113 at the power supply voltage VCC when all the transistors MH are off. The value of the pull-up resistor 112 is sufficiently larger than the on-resistance of each transistor MH, and the output resistance of the high-side output circuit 110 when one or more transistors MH are on can be considered independent of the value of the pull-up resistor 112. The pull-up resistor 112 can also be omitted. Similarly, the pull-down resistor 122 is a resistor that keeps the voltage of the node 123 at the ground voltage when all the transistors ML are off. The value of the pull-down resistor 122 is sufficiently larger than the on-resistance of each transistor ML, and the output resistance of the low-side output circuit 120 when one or more transistors ML are on can be considered independent of the value of the pull-down resistor 122. The pull-down resistor 122 can also be omitted. In the following, the presence of the pull-up resistor 112 and the pull-down resistor 122 will be ignored unless otherwise necessary.

[0052] The high-side transistor MH is a low-voltage element, while the protection transistor 131 is a high-voltage element. The high-side protection circuit 130 protects each high-side transistor MH from a first abnormal voltage when a first abnormal voltage outside a predetermined first allowable voltage range is applied to the signal terminal HH. The first allowable voltage range is a voltage range that depends on the power supply voltage VCC and the ground voltage, e.g., a voltage range below the power supply voltage VCC and above the ground voltage. The first abnormal voltage is, for example, a negative voltage. Depending on the magnitude of the negative voltage, the difference between the power supply voltage VCC and the negative voltage may exceed the withstand voltage of the drain-source voltage of the high-side transistor MH. By providing the protection transistor 131, even in an abnormal state in which a negative voltage is applied to the signal terminal HH, a relatively large voltage based on the negative voltage is applied between the drain and source of the protection transistor 131, and a voltage exceeding the withstand voltage of the high-side transistor MH is not applied between the drain and source of the high-side transistor MH. The first abnormal voltage may also be a voltage higher than the power supply voltage VCC. When a first abnormal voltage higher than the power supply voltage VCC is applied to the signal terminal HH, the backflow prevention diode 132 blocks a reverse current from the signal terminal HH toward the high-side transistor MH.

[0053] The low-side transistor ML is a low-voltage element, while the protection transistor 141 is a high-voltage element. The low-side protection circuit 140 protects each low-side transistor ML from a second abnormal voltage that deviates from a predetermined second allowable voltage range when the signal terminal LL is applied with a second abnormal voltage. The second allowable voltage range is a voltage range that depends on the power supply voltage VCC and the ground voltage, e.g., a voltage range below the power supply voltage VCC and above the ground voltage. The second abnormal voltage is, for example, a voltage higher than the power supply voltage VCC. In this case, depending on the second abnormal voltage, the difference voltage between the ground voltage and the second abnormal voltage higher than the power supply voltage VCC may exceed the withstand voltage of the drain-source voltage of the low-side transistor ML. By providing the protection transistor 141, even in an abnormal state in which a second abnormal voltage higher than the power supply voltage VCC is applied to the signal terminal LL, a relatively large voltage based on the second abnormal voltage is applied between the drain and source of the protection transistor 141, and a voltage exceeding the withstand voltage of the low-side transistor ML is not applied between the drain and source of the low-side transistor ML. The second abnormal voltage may also be a negative voltage. When a negative voltage is applied to the signal terminal LL as the second abnormal voltage, the backflow prevention diode 142 blocks a reverse current from the low-side transistor ML toward the signal terminal LL.

[0054] A low-voltage element refers to a MOSFET that has a relatively low withstand voltage against the voltage between the drain and source compared to a high-voltage element. A high-voltage element refers to a MOSFET that has a relatively high withstand voltage against the voltage between the drain and source compared to a low-voltage element. In other words, a low-voltage element has a withstand voltage against the voltage between the drain and source that is higher than the first voltage V XL In the high-voltage element, the withstand voltage for the voltage between the drain and source is the second voltage V XH Then, the second voltage V XH is the first voltage V XLThe protection transistors 131 and 141 may be configured by a double-diffused metal-oxide-semiconductor field-effect transistor (DMOSFET), which is a type of MOSFET. In the following, unless otherwise specified, it is assumed that the first abnormal voltage is not applied to the signal terminal HH and the second abnormal voltage is not applied to the signal terminal LL.

[0055] Based on a transmission data signal S_T (see also FIGS. 3 and 4), the control circuit 150 individually controls the state of the selector SEL_H of each unit circuit 111 and also individually controls the state of the selector SEL_L of each unit circuit 121. In each unit circuit 111, the high-side transistor MH is set on or off by controlling the state of the selector SEL_H, and in each unit circuit 121, the low-side transistor ML is set on or off by controlling the state of the selector SEL_L.

[0056] The control circuit 150 also controls the on / off states of the protection transistors 131 and 141. Except in special cases, such as when the transceiver 10 is set to a power-down mode, both protection transistors 131 and 141 are fixed to an on state. In this embodiment, unless otherwise noted, it is assumed that the transceiver 10 is set to a normal mode. When the transceiver 10 is set to the normal mode, the control circuit 150 fixes both protection transistors 131 and 141 to an on state and causes the output circuits 110 and 120 to generate a differential signal S_DIF in accordance with the timing chart shown in FIG. 4 in response to the transmit data signal S_T. That is, the control circuit 150 fixes the protection transistors 131 and 141 to an on state at least during the period (including the period between times t1 and t4) during which the high-side transistors MH are turned on or off to generate a high-side signal SH at the signal terminal HH and the low-side transistors ML are turned on or off to generate a low-side signal SL at the signal terminal LL. It is assumed that the electrical characteristics of the protection transistors 131 and 141 are matched so that the on-resistances of the protection transistors 131 and 141 are equal to each other. It is also assumed that the electrical characteristics of the backflow prevention diodes 132 and 142 are matched so that the forward voltages of the backflow prevention diodes 132 and 142 are equal to each other when "IH=IL".

[0057] The gate voltage adjustment circuit 160 includes transistors 161, 164, and 167 to 169, resistors 162 and 163, an operational amplifier 165, a current source 166, and an intermediate voltage generation circuit 170. The transistors 161 and 169 are configured as P-channel MOSFETs, and the transistors 164, 167, and 168 are configured as N-channel MOSFETs.

[0058] The current source 166 is the power supply wiring W VCC and a reference current I, which is a constant current based on the power supply voltage VCC, connected to the drain of the transistor 167. REF Generates a reference current I REFflows between the drain and source of the transistor 167 as the drain current of the transistor 167. The gate of the transistor 167 is connected to the drain of the transistor 167 and the gate of the transistor 168. The sources of the transistors 167 and 168 are connected to the ground wiring W GND The drain of the transistor 168 is connected to the drain and gate of the transistor 169 and the gate of the transistor 161. The sources of the transistors 161 and 169 are connected to the power supply wiring W VCC The wiring to which the gates of the transistors 161 and 169 are connected is particularly referred to as the gate wiring W GH The gate wiring W GH The voltage at the gate voltage V GH It is called.

[0059] The drain of the transistor 161 is connected to the drain of the transistor 164 via two series resistors. The two series resistors are resistors 162 and 163. The resistors 162 and 163 are configured to have the same resistance value. More specifically, the drain of the transistor 161 is connected to a first terminal of the resistor 162, and the second terminal of the resistor 162 and the first terminal of the resistor 163 are connected to a node 171. The second terminal of the resistor 163 is connected to the drain of the transistor 164. The source of the transistor 164 is connected to the ground wiring W GND The wiring to which the gate of the transistor 164 is connected is particularly referred to as the gate wiring W GL The gate wiring W GL The voltage at the gate voltage V GL It is called.

[0060] The operational amplifier 165 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal of the operational amplifier 165 is connected to a node 171. The inverting input terminal of the operational amplifier 165 is supplied with an intermediate voltage (VCC / 2) generated by an intermediate voltage generating circuit 170. The intermediate voltage generating circuit 170 is connected to a power supply wiring W VCC and ground wiring W GND , and generates an intermediate voltage (VCC / 2) based on the power supply voltage VCC and the ground voltage.VCC and ground wiring W GND The output terminal of the operational amplifier 165 is connected to the gate wiring W. GL is connected to.

[0061] The transistors 167 and 168 form a current mirror circuit CM0, which supplies a reference current I REF Current I proportional to BP1 flows as a drain current of the transistor 168. The transmitter circuit 11 is also provided with a current mirror circuit CM1. The current mirror circuit CM1 is configured to include transistors 169 and 161, and depending on the state of the selector SEL_H, one or more high-side transistors MH may also be included as components of the current mirror circuit CM1. At least the transistors 169 and 161 cause the current I BP1 Current I proportional to BP2 flows as the drain current of transistor 161. Current I BP2 flows between the drain and source of the transistor 164 through resistors 162 and 163. The transmitter circuit 11 is also provided with a current mirror circuit CM2. However, depending on the state of the selector SEL_L, the current mirror circuit CM2 is not formed. The current mirror circuit CM2 is configured to include the transistor 164, and depending on the state of the selector SEL_L, one or more low-side transistors ML may also be included as components of the current mirror circuit CM2.

[0062] The total number of unit circuits 111 provided in the high-side output circuit 110 is represented by n. n represents any integer equal to or greater than 2. The total number of unit circuits 121 in the low-side output circuit 120 is also n. When it is necessary to distinguish the n unit circuits 111 provided in the high-side output circuit 110 from one another, the n unit circuits 111 are referred to as unit circuits 111[1] to 111[n]. Similarly, when it is necessary to distinguish the n unit circuits 121 provided in the low-side output circuit 120 from one another, the n unit circuits 121 are referred to as unit circuits 121[1] to 121[n]. Furthermore, any one of the unit circuits 111[1] to 111[n] is referred to as unit circuit 111[i], and any one of the unit circuits 121[1] to 121[n] is referred to as unit circuit 121[i]. i represents any integer.

[0063] 8 shows the configuration and connection relationship of the unit circuits 111[1] to 111[n]. The high-side transistor MH and the selector SEL_H in the unit circuit 111[i] are specifically referred to by the symbols "MH[i]" and "SEL_H[i]", respectively. The sources of the high-side transistors MH[1] to MH[n] are connected to the power supply wiring W VCC , and the drains of the high-side transistors MH[1] to MH[n] are commonly connected to a node 113. That is, unlike the transmitter circuit 11ref (FIG. 6) according to the reference example, in the transmitter circuit 11, the sources of the high-side transistors MH[1] to MH[n] are connected to the power supply wiring W without passing through other transistors (corresponding to the current limiting transistor 914 in FIG. 6). VCC , and the drains of the high-side transistors MH[1] to MH[n] are directly connected to node 113 (connected in common at node 113) without going through a resistive element (corresponding to resistor 913 in FIG. 6). Therefore, the high-side output circuit 110 has a parallel circuit (first parallel circuit) of the high-side transistors MH[1] to MH[n]. In any unit circuit 111[i], the selector SEL_H[i], under the control of the control circuit 150, selects the connection destination of the gate of the high-side transistor MH[i] to the gate wiring W GH Or power wiring W VCC Switch to.

[0064] 9, in the unit circuit 111[i], the gate of the high-side transistor MH[i] is connected to the gate wiring W GH is called the ON control state, and the gate of the high-side transistor MH[i] is connected to the power supply wiring W VCC The state in which the gate wiring W is connected to the GH Gate voltage V GH functions as a voltage for turning on each high-side transistor MH. That is, when the unit circuit 111[i] is in the on-control state, the gate voltage V GH When the power supply voltage VCC and gate voltage V are supplied, the high-side transistor MH[i] is turned on. GH The absolute value of the difference voltage between and is greater than the absolute value of the gate threshold voltage of each high-side transistor MH. When the unit circuit 111[i] is in the off control state, the power supply voltage VCC is supplied to the gate of the high-side transistor MH[i], turning the high-side transistor MH[i] into the off state.

[0065] The control circuit 150 controls the state of the corresponding selector SEL_H[i] for each high-side transistor MH, and selects the connection destination of the gate of the high-side transistor MH[i] from the gate wiring W GH By setting VCC In each unit circuit 111, the selector SEL_H is connected to the gate wiring W GH and the gate of the high-side transistor MH, and a first switch inserted between the power supply wiring W VCCand a second switch inserted between the gate of the high-side transistor MH. Each switch is formed by a semiconductor switching element. In the unit circuit 111[i], the first switch is controlled to be on and the second switch is controlled to be off, so that the unit circuit 111[i] is in an on-control state, and the first switch is controlled to be off and the second switch is controlled to be on, so that the unit circuit 111[i] is in an off-control state.

[0066] The control circuit 150 controls the state of the unit circuits 111[1] to 111[n] individually to an on-control state or an off-control state based on the transmission data signal S_T, thereby individually setting the high-side transistors MH[1] to MH[n] on or off. The control circuit 150 then controls the power supply wiring W through the parallel circuit (first parallel circuit) of the high-side transistors MH[1] to MH[n]. VCC and signal terminal HH (signal current IH; see FIG. 7), a high-side signal SH (first output signal) is generated at signal terminal HH. When only high-side transistor MH[1] of high-side transistors MH[1] to MH[n] is in the on state, the on-resistance value of high-side transistor MH[1] becomes the output resistance value of high-side output circuit 110. When only high-side transistors MH[1] to MH[m] of high-side transistors MH[1] to MH[n] are in the on state, the parallel combined value of the on-resistance values ​​of high-side transistors MH[1] to MH[m] becomes the output resistance value of high-side output circuit 110 (where m is an integer greater than or equal to 2 and less than or equal to n).

[0067] The high-side transistor MH[i] in the on state is a component of the current mirror circuit CM1. When the high-side transistor MH[i] is in the on state, if the voltage at the signal terminal HH is sufficiently low (for example, if it is equal to or close to the intermediate voltage (VCC / 2)), the current I BP1 and I BP2 A current proportional to (for example, current I BP2A current several tens to several hundreds times the drain current of the high-side transistor MH[i] is generated as the drain current of the high-side transistor MH[i]. The high-side transistor MH[i] in the off state is not a component of the current mirror circuit CM1.

[0068] 10 shows the configuration and connection relationship of the unit circuits 121[1] to 121[n]. The low-side transistor ML and the selector SEL_L in the unit circuit 121[i] are specifically referred to by the symbols "ML[i]" and "SEL_L[i]", respectively. The sources of the low-side transistors ML[1] to ML[n] are connected to the ground wiring W GND , and the drains of the low-side transistors ML[1] to ML[n] are commonly connected to a node 123. That is, unlike the transmitter circuit 11ref (FIG. 6) according to the reference example, in the transmitter circuit 11, the sources of the low-side transistors ML[1] to ML[n] are commonly connected to the ground wiring W without passing through other transistors (corresponding to the current limiting transistor 924 in FIG. 6). GND , and the drains of the low-side transistors ML[1] to ML[n] are directly connected to the node 123 (connected in common at the node 123) without going through a resistive element (corresponding to resistor 923 in FIG. 6). Therefore, the low-side output circuit 120 has a parallel circuit (second parallel circuit) of the low-side transistors ML[1] to ML[n]. In any unit circuit 121[i], the selector SEL_L[i], under the control of the control circuit 150, selects the connection destination of the gate of the low-side transistor ML[i] to the gate wiring W GL Or ground wiring W GND Switch to.

[0069] 11, in the unit circuit 121[i], the gate of the low-side transistor ML[i] is connected to the gate wiring W GL is called the on-control state, and the gate of the low-side transistor ML[i] is connected to the ground wiring W GND The state in which the gate wiring W is connected to the GL Gate voltage V GLfunctions as a voltage for turning on each low-side transistor ML. That is, when the unit circuit 121[i] is in the on-control state, the gate voltage V GL When the gate voltage V is supplied, the low-side transistor ML[i] is turned on. GL is greater than the gate threshold voltage of each low-side transistor ML. When the unit circuit 121[i] is in the off-control state, the ground voltage is supplied to the gate of the low-side transistor ML[i], turning the low-side transistor ML[i] into the off-state.

[0070] The control circuit 150 controls the state of the corresponding selector SEL_L[i] for each low-side transistor ML, and selects the connection destination of the gate of the low-side transistor ML[i] as the gate wiring W GL By setting GND In each unit circuit 121, the selector SEL_L is connected to the gate wiring W GL and the gate of the low-side transistor ML, and a third switch inserted between the ground wiring W GND and the gate of the low-side transistor ML. Each switch is formed by a semiconductor switching element. In the unit circuit 121[i], the third switch is controlled to be on and the fourth switch is controlled to be off, so that the unit circuit 121[i] is in an on-control state, and the third switch is controlled to be off and the fourth switch is controlled to be on, so that the unit circuit 121[i] is in an off-control state.

[0071] The control circuit 150 controls the state of the unit circuits 121[1] to 121[n] individually to an on-control state or an off-control state based on the transmission data signal S_T, thereby individually setting the low-side transistors ML[1] to ML[n] on or off. The control circuit 150 then controls the ground wiring W through the parallel circuit (second parallel circuit) of the low-side transistors ML[1] to ML[n]. GND and a signal terminal LL (signal current IL; see FIG. 7), a low-side signal SL (second output signal) is generated at the signal terminal LL. When only the low-side transistor ML[1] among the low-side transistors ML[1] to ML[n] is in the on state, the on-resistance value of the low-side transistor ML[1] becomes the output resistance value of the low-side output circuit 120. When only the low-side transistors ML[1] to ML[m] among the low-side transistors ML[1] to ML[n] are in the on state, the parallel combined value of the on-resistance values ​​of the low-side transistors ML[1] to ML[m] becomes the output resistance value of the low-side output circuit 120 (where m is an integer greater than or equal to 2 and less than or equal to n).

[0072] The low-side transistor ML[i] in the on state is a component of the current mirror circuit CM2. When the low-side transistor ML[i] is in the on state, if the voltage at the signal terminal LL is sufficiently high (for example, if it is equal to or close to the intermediate voltage (VCC / 2)), the current I BP1 and I BP2 A current proportional to (for example, current I BP2 A current several tens to several hundreds times the drain current of the low-side transistor ML[i] is generated as the drain current of the low-side transistor ML[i]. The low-side transistor ML[i] in the off state is not a component of the current mirror circuit CM2.

[0073] Fig. 12 shows the operation flowchart of the transmission circuit 11. When the power supply voltage VCC starts to be supplied to the transceiver 10, the transceiver 10 is activated. When the transceiver 10 is activated, first, it reaches step S10, and in step S10, the transmission circuit 11 is in an initial state. Assume that the transmission data signal S_T is at a low level in the initial state. In the initial state, the control circuit 150 sets all the unit circuits 111 and 121 to an off control state. Also in step S10, the variable i managed by the control circuit 150 is assigned the value 1. After step S10, it proceeds to step S11.

[0074] In step S11, the control circuit 150 monitors the level of the transmission data signal S_T, and in response to the level of the transmission data signal S_T switching from a low level to a high level, it causes a transition from step S11 to step S12. In step S12, the control circuit 150 simultaneously switches the unit circuits 111[i] and 121[i] from an off control state to an on control state. In the subsequent step S13, the control circuit 150 waits using a timer for a predetermined unit time ΔT to elapse, and when the unit time ΔT elapses, it causes a transition to step S14. In step S14, the control circuit 150 checks the validity of "i = n", and if "i = n" holds, it causes a transition to step S16. If "i = n" does not hold in step S14 (therefore, when "i < n"), in step S15, 1 is added to the variable i, and then it returns to step S12.

[0075] In response to the transmission data signal S_T switching from a low level to a high level, after the unit circuits 111[1] and 121[1] are set to the on-control state, every time a unit time ΔT elapses, one of the unit circuits 111 among the unit circuits 111[2] to 111[n] is sequentially switched from the off-control state to the on-control state, and one of the unit circuits 121 among the unit circuits 121[2] to 121[n] is sequentially switched from the off-control state to the on-control state. The timing of the transition from step S11 to step S12 corresponds to time t1, and the timing of the transition from step S14 to step S16 corresponds to time t2 (see FIG. 4). In step S16, the control circuit 150 substitutes 1 for the variable i and causes a transition to step S21.

[0076] In step S21, the control circuit 150 monitors the level of the transmission data signal S_T and causes a transition from step S21 to step S22 in response to the level of the transmission data signal S_T switching from a high level to a low level. In step S22, the control circuit 150 simultaneously switches the unit circuits 111[i] and 121[i] from the on-control state to the off-control state. In the subsequent step S23, the control circuit 150 waits using a timer for a predetermined unit time ΔT to elapse, and when the unit time ΔT elapses, causes a transition to step S24. In step S24, the control circuit 150 checks the validity of "i = n", and if "i = n" holds, causes a transition to step S26. If "i = n" does not hold in step S24 (therefore, if "i < n"), in step S25, 1 is added to the variable i and then the process returns to step S22.

[0077] As a result, after the unit circuits 111[1] and 121[1] are set to the OFF control state in response to the transmission data signal S_T switching from high level to low level, one unit circuit 111 among the unit circuits 111[2] to 111[n] is sequentially switched from the ON control state to the OFF control state, and one unit circuit 121 among the unit circuits 121[2] to 121[n] is sequentially switched from the ON control state to the OFF control state, every time a unit time ΔT elapses. The timing when the process moves from step S21 to step S22 corresponds to time t3, and the timing when the process moves from step S24 to step S26 corresponds to time t4 (see FIG. 4). In step S26, the control circuit 150 assigns 1 to the variable i, causing a transition to step S11. Thereafter, the same operation starting from step S11 is repeated.

[0078] The state in which the transistors MH[1] to MH[n] and ML[1] to ML[n] are all set to off is referred to as the all-off state, and the state in which the transistors MH[1] to MH[n] and ML[1] to ML[n] are all set to on is referred to as the all-on state. Furthermore, the switching of the level of the transmission data signal S_T from low to high is referred to as the rising edge of the transmission data signal S_T, and the switching of the level of the transmission data signal S_T from high to low is referred to as the falling edge of the transmission data signal S_T.

[0079] Then, it can be said that the control circuit 150 performs the following operations. That is (see FIG. 4), when a rising edge of the transmission data signal S_T occurs, starting from the all-off state, the control circuit 150 sequentially increases the number of high-side transistors MH to be turned on and the number of low-side transistors ML to be turned on, so as to gradually increase the level of the high-side signal SH from the level of the voltage VM1 (the first level) toward the level of the voltage VH (the second level), and at the same time gradually decrease the level of the low-side signal SL from the level of the voltage VM2 (the third level) toward the level of the voltage VL (the fourth level). Further, when a falling edge of the transmission data signal S_T occurs, starting from the all-on state, the control circuit 150 sequentially increases the number of high-side transistors MH to be turned off and the number of low-side transistors ML to be turned off, so as to gradually decrease the level of the high-side signal SH from the level of the voltage VH (the second level) toward the level of the voltage VM1 (the first level), and at the same time gradually increase the level of the low-side signal SL from the level of the voltage VL (the fourth level) toward the level of the voltage VM2 (the third level). Here, “0 < VL < VM2” and “VM1 < VH < VCC”. Further, basically “VM1 = VM2” holds, but due to the influence of leakage current or the like, the voltage VM1 may be slightly larger than the voltage VM2.

[0080] In the present embodiment, except for the explanatory matters related to the reference example, the operations of the transceiver 10 described so far (particularly the operations of the transmission circuit 11) are the operations of the transceiver 10 in the normal state. As a state different from the normal state, there is a short-circuit state. A state in which a short-circuit abnormality has occurred is the short-circuit state. In the normal state, no short-circuit abnormality has occurred, and as described above, the high-side signal SH varies between the voltages VM1 and VH and the low-side signal SL varies between the voltages VM2 and VL in response to the transmission data signal S_T. As the short-circuit state, there are a first short-circuit state and a second short-circuit state.

[0081] The first short-circuit state is a state in which a first short-circuit abnormality has occurred. The first short-circuit abnormality refers to an abnormality in which the signal terminal HH is short-circuited to a first specific conductive portion having a voltage below the ground voltage. Typically, the first specified conductive part is ground, and in this case, the first short-circuit abnormality is generally referred to as a ground fault of the signal terminal HH. In the first short-circuit state, the voltage of the signal terminal HH is pulled down to the voltage of the first specified conductive part regardless of the state of the high-side output circuit 110. The second short-circuit state is a state in which a second short-circuit abnormality occurs. The second short-circuit abnormality refers to an abnormality in which the signal terminal LL is shorted to a second specified conductive part having a voltage equal to or higher than the power supply voltage VCC. Typically, the second specified conductive part is a wiring or terminal to which the power supply voltage VCC is applied, and in this case, the second short-circuit abnormality is generally referred to as a short to power of the signal terminal LL. In the second short-circuit state, the voltage of the signal terminal LL is pulled up to the voltage of the second specified conductive part regardless of the state of the low-side output circuit 120. In the normal state, the signal terminal HH is not connected to the first specified conductive part (e.g., ground), and the signal terminal LL is not connected to the second specified conductive part (a wiring or terminal to which the power supply voltage VCC is applied).

[0082] In the first short-circuit state, excessive current should be prevented from flowing through the high-side transistor MH. Similarly, in the second short-circuit state, excessive current should be prevented from flowing through the low-side transistor ML. In the transmitter circuit 11ref according to the reference example shown in FIG. 6, the current limiting transistors 914 and 924 function as current sources to prevent the occurrence of excessive current. On the other hand, in the transmitter circuit 11ref according to the reference example shown in FIG. 6, resistors (913, 923) are connected in series with the high-side transistor 912 and the low-side transistor 922, thereby achieving waveform control of the output signal.

[0083] In contrast, in the transmission circuit 11 of FIG. 7 , the high-side transistor MH is provided with the waveform control function and current limiting function of the output signal (SH), and the low-side transistor ML is provided with the waveform control function and current limiting function of the output signal (SL) by the following device. That is, in a normal state, the high-side output circuit 110 operates one or more high-side transistors MH that are set to on in a linear region, and the low-side output circuit 120 operates one or more low-side transistors ML that are set to on in a linear region. A high-side transistor MH that is set to on specifically refers to a high-side transistor MH that is set to on by the control circuit 150, and therefore is a high-side transistor MH that is in an on state. Similarly, a low-side transistor ML that is set to on specifically refers to a low-side transistor ML that is set to on by the control circuit 150, and therefore is a low-side transistor ML that is in an on state. In the normal state, for any integer i that satisfies "1≦i≦n," when unit circuit 111[i] is in the ON state, high-side transistor MH[i] operates in the linear region, and when unit circuit 121[i] is in the ON state, low-side transistor ML[i] operates in the linear region. Because the transistors (MH[i], ML[i]) in the linear region function as resistive elements, waveform control equivalent to that achieved when resistors (913, 923) are provided as in the reference example (waveform control that gradually changes signals SH and SL to suppress high-frequency components of signals SH and SL) is possible.

[0084] The gate voltage adjustment circuit 160 adjusts the gate voltage V for operating each high-side transistor MH that is set to ON in the linear region. GH and a gate voltage V for operating each low-side transistor ML that is set to ON in the linear region. GL In other words, under normal conditions, the gate voltage V GH is supplied, the gate voltage V is adjusted by the gate voltage adjustment circuit 160 so that the high-side transistor MH[i] operates in the linear region. GHSimilarly, in the normal state, the gate voltage V GL The gate voltage V is supplied to the low-side transistor ML[i] by the gate voltage adjustment circuit 160 so that the low-side transistor ML[i] operates in the linear region. GL is generated and controlled.

[0085] 13 shows the characteristics of the high-side transistor MH. In the graph 610, the drain-source voltage of the high-side transistor MH is V DS The absolute value of the drain current of the high-side transistor MH corresponds to |I D The gate of the high-side transistor MH related to the graph 610 is supplied with a gate voltage V GH is applied, and therefore the gate-source voltage V of the high-side transistor MH related to the graph 610 GS (gate potential as seen from source potential) is "V GH -VCC”. The gate-source voltage V GS When the drain potential decreases from the gate potential, the drain-source voltage V DS As the absolute value of increases, the region moves from the linear region to the saturation region.

[0086] 13 shows the characteristics of the low-side transistor ML. In the graph 620, the drain-source voltage of the low-side transistor ML is V DS The drain current of the low-side transistor ML corresponds to I D The gate of the low-side transistor ML related to the graph 620 is supplied with a gate voltage V GL is applied, and therefore the gate-source voltage V of the low-side transistor ML related to the graph 620 GS (gate potential as seen from source potential) is "V GL ". In the low-side transistor ML, the gate-source voltage V GS Under a constant drain-source voltage V DSAs increases, the linear region moves towards the saturation region.

[0087] In the first short-circuit state, the magnitude of the drain-source voltage of the high-side transistor MH that is set to ON is larger than in the normal state, and as a result, the high-side transistor MH that is set to ON operates in the saturation region. When a certain high-side transistor MH operates in the saturation region, the high-side transistor MH generates a substantially constant drain current regardless of fluctuations in the drain-source voltage, i.e., outputs a substantially constant current. Therefore, in the first short-circuit state, when one or more high-side transistors MH are set to ON, the high-side output circuit 110 operates the one or more high-side transistors MH in the saturation region, thereby suppressing (limiting) an increase in the signal current IH that accompanies a voltage drop at the signal terminal HH (this suppression is more pronounced than when the high-side transistor MH that is set to ON operates in the linear region). Suppressing an increase in the signal current IH that accompanies a voltage drop at the signal terminal HH means, in other words, suppressing an increase in the signal current IH (the increase in the signal current IH compared to the normal state) that occurs when the signal terminal HH is short-circuited to the first specific conductive part. Therefore, the current limiting transistor 914 (see FIG. 6) required in the reference example is not required, and the current limiting function is realized by the high-side transistor MH.

[0088] Similarly, in the second short-circuit state, the magnitude of the drain-source voltage of the low-side transistor ML that is set to on is larger than in the normal state, and as a result, the low-side transistor ML that is set to on operates in the saturation region. When a low-side transistor ML operates in the saturation region, the low-side transistor ML generates a substantially constant drain current regardless of fluctuations in the drain-source voltage, i.e., outputs a substantially constant current. Therefore, in the second short-circuit state, when one or more low-side transistors ML are set to on, the low-side output circuit 120 operates the one or more low-side transistors ML in the saturation region to suppress (limit) the increase in the signal current IL that accompanies the voltage increase at the signal terminal LL (this suppression is achieved more than when the low-side transistor ML that is set to on operates in the linear region). Suppressing the increase in the signal current IL that accompanies the voltage increase at the signal terminal LL means, in other words, suppressing the increase in the signal current IL (the increase in the signal current IL compared to the normal state) that occurs when the signal terminal LL is short-circuited to the second specific conductive part. Therefore, the current limiting transistor 924 (see FIG. 6) that was necessary in the reference example is not required, and the current limiting function is realized by the low-side transistor ML.

[0089] Transistors 161 and 169 and each high-side transistor MH have a common structure, which allows them to have common electrical characteristics. However, compared to the size of each of transistors 161 and 169, the size of each high-side transistor MH is much larger, and the current capability of each high-side transistor MH is much larger than the current capability of transistors 161 and 169. Transistor 164 and each low-side transistor ML have a common structure, which allows them to have common electrical characteristics. However, compared to the size of transistor 164, the size of each low-side transistor ML is much larger, and the current capability of each low-side transistor ML is much larger than the current capability of transistor 164.

[0090] The transmitting circuit 11 is configured (the structure of each transistor of the transmitting circuit 11 and each circuit constant are determined) so that the transistors 161 and 169 and the transistor 164 operate in the linear region regardless of whether the state of the transmitting circuit 11 is the normal state or the short-circuit state, so that each high-side transistor MH that is set on and each low-side transistor ML that is set on operate in the linear region in the normal state, so that each high-side transistor MH that is set on operates in the saturation region in the first short-circuit state, and so that each low-side transistor ML that is set on operates in the saturation region in the second short-circuit state.

[0091] Therefore, each high-side transistor MH that is set to on and each low-side transistor ML that is set to on operate in the linear region in the normal state, and each high-side transistor MH that is set to on operates in the saturation region in the first short-circuit state, and each low-side transistor ML that is set to on operates in the saturation region in the second short-circuit state.

[0092] In practice, the high-side output circuit 110 connects each high-side transistor MH that is set to ON to the power supply wiring W. VCC Depending on the voltage difference between the power supply wiring W and the signal terminal HH (and therefore depending on the magnitude of the drain-source voltage of each high-side transistor MH), the transistor operates in the linear region or the saturation region. VCC Since the voltage difference between the power supply wiring W and the signal terminal HH (and therefore the magnitude of the drain-source voltage of each high-side transistor MH) is relatively small, each high-side transistor MH that is set to ON operates in the linear region. VCC and the signal terminal HH (hence the magnitude of the drain-source voltage of each high-side transistor MH) becomes larger than in the normal state, and as a result, each high-side transistor MH that is set to ON operates in the saturation region. Similarly, the low-side output circuit 120 connects each low-side transistor ML that is set to ON to the ground wiring W GNDDepending on the voltage difference between the signal terminal LL and the ground wiring W (and therefore depending on the magnitude of the drain-source voltage of each low-side transistor ML), the transistor operates in the linear region or the saturation region. GND Since the voltage difference between the signal terminal LL and the ground wiring W (and therefore the magnitude of the drain-source voltage of each low-side transistor ML) is relatively small, each low-side transistor ML that is set to ON operates in the linear region. GND and the signal terminal LL (hence the magnitude of the drain-source voltage of each low-side transistor ML) becomes larger than in the normal state, and as a result, each low-side transistor ML that is set to on operates in the saturation region.

[0093] The transmitter circuit 11 of FIG. 7 can reduce the number of vertically stacked components compared to the reference example (FIG. 6), thereby reducing the number of components. In the reference example, as described above, the output resistance value of each output circuit (910, 920) is determined by the resistors (913, 923). Therefore, the on-resistance of the high-side transistors and low-side transistors (912, 922) must be sufficiently low compared to the resistors (913, 923). A reduction in on-resistance leads to an increase in transistor size. In contrast, the transmitter circuit 11 of FIG. 7 actively uses the high-side transistors and low-side transistors (MH, ML) as resistors, allowing the high-side transistors and low-side transistors to be smaller in size compared to the reference example. As a result, the circuit area and cost can be reduced compared to the reference example. Furthermore, because the size of each transistor (MH, ML) can be reduced, switching noise associated with the switching of each transistor can also be reduced.

[0094] Although the operation in the normal state and the short-circuit state has been described, the following description will be of the transmission circuit 11 in the normal state, and no description of the normal state or the short-circuit state will be provided (this also applies to other embodiments described later).

[0095] The symmetry between the signals SH and SL is ideal when the output resistance of the high-side output circuit 110 and the output resistance of the low-side output circuit 120 are equal. A transistor operating in the linear region functions as a resistor, but it is often not easy to set the resistance as desired and accurately. Therefore, in the transmission circuit 11 of FIG. 7, the gate voltage V is adjusted by the gate voltage adjustment circuit 160 so that the output resistance of the high-side output circuit 110 and the output resistance of the low-side output circuit 120 are equal. GL Dynamically control (adjust)

[0096] In the gate voltage adjustment circuit 160, the transistor 161 functions as a first replica transistor simulating the high-side transistor MH in an ON state, and the transistor 164 functions as a second replica transistor simulating the low-side transistor ML in an ON state. The resistors 162 and 163 function as first and second series resistors. The gate voltage adjustment circuit 160 has a series circuit of a first replica transistor, a first series resistor, a second series resistor, and a second replica transistor. As described above, the resistors 162 and 163 are configured to have the same resistance value. The operational amplifier 165 adjusts the gate voltage V GL (specific gate voltage).

[0097] The series circuit of resistors 162 and 163 simulates the load resistor RL, and the connection node 171 between resistors 162 and 163 simulates the midpoint of the load resistor RL. When the output resistance of the high-side output circuit 110 and the output resistance of the low-side output circuit 120 are equal, the voltage at the midpoint of the load resistor RL matches the intermediate voltage (VCC / 2). Therefore, by controlling the voltage at the connection node 171, which simulates the midpoint of the load resistor RL, to match the intermediate voltage (VCC / 2), the output resistance of the high-side output circuit 110 and the output resistance of the low-side output circuit 120 become equal. Therefore, the transmission circuit 11 of FIG. 7 can achieve good symmetry between the signals SH and SL. Good symmetry between the signals SH and SL suppresses common-mode noise, improving the noise characteristics of the entire system.

[0098] <<Second Example>> A second embodiment will be described. As shown in FIG. 7, an operational amplifier 165 is used to generate a gate voltage V GL By dynamically controlling the symmetry between the signals SH and SL, it is possible to make the symmetry between the signals SH and SL closer to ideal, despite various factors of variation.

[0099] However, if the error from the ideal symmetry between the signals SH and SL can be suppressed within an allowable range, it is also possible to omit the gate voltage adjustment circuit 160 from the transmission circuit 11 of Fig. 7. When the gate voltage adjustment circuit 160 is omitted, a bias circuit (not shown) is provided in the transmission circuit 11, and the bias circuit adjusts an appropriate first bias voltage to the gate voltage V GH As the gate wiring W GH and apply another appropriate second bias voltage to the gate voltage V GL As the gate wiring W GL The first and second bias voltages have predetermined positive DC voltage values, the first bias voltage being lower than the power supply voltage VCC and higher than the second bias voltage.

[0100] <<Third Example>> A third embodiment will now be described. As described above, the high-side protection circuit 130 can protect the high-side transistor MH from a first abnormal voltage that may be applied to the signal terminal HH, and the low-side protection circuit 140 can protect the low-side transistor ML from a second abnormal voltage that may be applied to the signal terminal LL. However, in cases where it is assumed that the first abnormal voltage will not occur, the high-side protection circuit 130 can be omitted from the transmitter circuit 11 of FIG. 7, and in this case, node 113 is directly connected to the signal terminal HH. Similarly, in cases where it is assumed that the second abnormal voltage will not occur, the low-side protection circuit 140 can be omitted from the transmitter circuit 11 of FIG. 7, and in this case, node 123 is directly connected to the signal terminal LL.

[0101] In the transmission circuit 11 of FIG. 7, any one of the protection transistor 131 and the backflow prevention diode 132 may be omitted from the high-side protection circuit 130, and similarly, any one of the protection transistor 141 and the backflow prevention diode 142 may be omitted from the low-side protection circuit 140.

[0102] 7, if the withstand voltage between the drain and source of the high-side transistor MH is sufficiently high, the protective transistor 131 can be omitted, and in this case, the cathode of the blocking diode 132 is directly connected to the signal terminal HH. Similarly, if the withstand voltage between the drain and source of the low-side transistor ML is sufficiently high, the protective transistor 141 can be omitted, and in this case, the cathode of the blocking diode 142 is directly connected to the drain of each low-side transistor ML.

[0103] Alternatively, for example, in the transmission circuit 11 of FIG. 7, if a separate circuit for suppressing the above-mentioned backflow current is provided or if backflow current cannot occur, the backflow prevention diodes 132 and 142 can be omitted, and in this case, the source of the protection transistor 131 is directly connected to the drain of each high-side transistor MH, and the drain of the protection transistor 141 is directly connected to the signal terminal LL.

[0104] <<Fourth Example>> A fourth embodiment will now be described.

[0105] Although the various configurations and operations have been described assuming that the transceiver 10 is applied to a CAN, the network or communication protocol to which the transceiver 10 is applied is not limited to CAN and may be, for example, a Local Interconnect Network (LIN) or a Clock Extension Peripheral Interface (CXPI). Furthermore, the transceiver 10 can be used for serial communication for any purpose, not just for in-vehicle applications.

[0106] A composite electronic component may be configured that incorporates the transceiver 10 and another functional circuit. For example, the other functional circuit may be the MPU 20, in which case an integrated composite electronic component is configured that incorporates the transceiver 10 and the MPU 20. The other functional circuit may also be a circuit that performs various functions, such as a power supply control function, a motor control function, or a light-emitting element control function.

[0107] The transceiver 10 includes a signal output circuit according to the present disclosure. The transmitter circuit 11 is an example of a signal output circuit according to the present disclosure.

[0108] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0109] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0110] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0111] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0112] <<Addendum 1>> The present disclosure, the specific configuration examples of which are shown in the above-described embodiments, will be described in Supplementary Note 1.

[0113] A signal output circuit (11) according to one aspect of the present disclosure includes a first DC wiring (W) configured to apply a predetermined first DC voltage (VCC). VCC), a first signal terminal (HH), a high-side output circuit (110) having a first parallel circuit of a plurality of high-side transistors (MH) provided between the first DC wiring and the first signal terminal, and a second DC wiring (W) configured to apply a second DC voltage (0 V) lower than the first DC voltage. GND a low-side output circuit (120) having a second parallel circuit of a plurality of low-side transistors (ML) provided between the second DC wiring and the second signal terminal; and a control circuit (150) configured to individually set the plurality of high-side transistors on or off and control the current between the first DC wiring and the first signal terminal through the first parallel circuit to generate a first output signal (SH) at the first signal terminal, and to individually set the plurality of low-side transistors on or off and control the current between the second DC wiring and the second signal terminal through the second parallel circuit to generate a second output signal (SL) at the second signal terminal, wherein a first signal current (IH) flows between the first DC wiring and the first signal terminal through the one or more high-side transistors when one or more high-side transistors are set on. In this state, the high-side output circuit operates the one or more high-side transistors in a linear region or a saturation region in accordance with a voltage difference between the first DC wiring and the first signal terminal, and suppresses an increase in the first signal current associated with a voltage drop at the first signal terminal by operating the one or more high-side transistors in the saturation region; and in a state in which the one or more low-side transistors are set on so that a second signal current (IL) flows between the second DC wiring and the second signal terminal through the one or more low-side transistors, the low-side output circuit operates the one or more low-side transistors in a linear region or a saturation region in accordance with a voltage difference between the second DC wiring and the second signal terminal, and suppresses an increase in the second signal current associated with a voltage rise at the second signal terminal by operating the one or more low-side transistors in the saturation region (hereinafter referred to as a configuration α1).

[0114] By operating the high-side transistor in the linear region, the high-side transistor can function as a resistive element. Therefore, the resistor (913) connected in series to the high-side transistor, which was necessary in the reference example of FIG. 6, is unnecessary in the configuration α1 (hence, the number of components can be reduced). The same is true for the low-side transistor. Because the high-side transistor actively functions as a resistive element, the high-side transistor can be small in size. The same is true for the low-side transistor. Reducing the transistor size reduces switching noise associated with switching. Furthermore, in the configuration α1, the one or more high-side transistors are operated in the linear region or saturation region depending on the voltage difference between the first DC wiring and the first signal terminal. Operating the one or more high-side transistors in the saturation region suppresses an increase in the first signal current associated with a voltage drop at the first signal terminal. Therefore, the current limiting transistor (914) for the high-side transistor, which was necessary in the reference example of FIG. 6, is unnecessary in the configuration α1 (hence, the number of components can be reduced). The same is true for the low-side transistor.

[0115] In the signal output circuit according to the above-described configuration α1, when the one or more high-side transistors are set to on in a first short-circuit state (e.g., a ground fault state) in which the first signal terminal is short-circuited to a first specific conductive part having a voltage equal to or lower than the second DC voltage, the high-side output circuit operates the one or more high-side transistors in a saturation region to suppress an increase in the first signal current due to the short-circuiting of the first signal terminal, and when the one or more low-side transistors are set to on in a second short-circuit state (e.g., a power fault state) in which the second signal terminal is short-circuited to a second specific conductive part having a voltage equal to or higher than the first DC voltage, the low-side output circuit may be configured to operate the one or more low-side transistors in a saturation region to suppress an increase in the second signal current due to the short-circuiting of the second signal terminal (hereinafter referred to as configuration α2).

[0116] This prevents an excessive current from flowing through the high-side or low-side transistor in the first or second short-circuit state.

[0117] In the signal output circuit according to the above-described configuration α2, in a normal state in which the first signal terminal is disconnected from the first specified conductive portion and the second signal terminal is disconnected from the second specified conductive portion, the high-side output circuit and the low-side output circuit operate the one or more high-side transistors that are set to on and the one or more low-side transistors that are set to on in a linear region, and in the normal state, the control circuit sequentially increases the number of high-side transistors that are turned on and the number of low-side transistors that are turned on from an all-off state in which all high-side transistors and all low-side transistors are set to off, thereby Alternatively, the level of the output signal may be gradually increased from a first level (VM1) to a second level (VH), the level of the second output signal may be gradually decreased from a third level (VM2) to a fourth level (VL), and the number of high-side transistors that are turned off and the number of low-side transistors that are turned off may be sequentially increased from an all-on state in which all high-side transistors and all low-side transistors are set to on, thereby gradually decreasing the level of the first output signal from the second level to the first level and gradually increasing the level of the second output signal from the fourth level to the third level (hereinafter referred to as configuration α3).

[0118] The signal output circuit according to any one of the above configurations α1 to α3 may further include a first protection circuit (130) inserted between the high-side output circuit and the first signal terminal, and a second protection circuit (140) inserted between the low-side output circuit and the second signal terminal, wherein the first protection circuit protects each high-side transistor from a first abnormal voltage that deviates from a predetermined first allowable voltage range when the first abnormal voltage is applied to the first signal terminal, and the second protection circuit protects each low-side transistor from a second abnormal voltage that deviates from a predetermined second allowable voltage range when the second signal terminal is applied. (Hereinafter, this configuration will be referred to as α4.)

[0119] In the signal output circuit according to the above-described configuration α4, each high-side transistor may be configured by a P-channel MOSFET having a source connected to the first DC wiring, each low-side transistor may be configured by an N-channel MOSFET having a source connected to the second DC wiring, the first protection circuit may be inserted between the drain of each high-side transistor and the first signal terminal, and the second protection circuit may be inserted between the drain of each low-side transistor and the second signal terminal (hereinafter referred to as configuration α5).

[0120] In the signal output circuit according to any one of the above configurations α1 to α5, the first signal terminal is connected to an output resistor (R TM , RL) (hereinafter referred to as configuration α6).

[0121] The signal output circuit according to any one of the above configurations α1 to α5 may be configured to further include a gate voltage adjusting circuit (160) configured to adjust a specific gate voltage for setting each low-side transistor to ON based on an intermediate voltage between the first DC voltage and the second DC voltage (hereinafter referred to as configuration α7).

[0122] This makes it possible to achieve good symmetry between the first output signal and the second output signal.

[0123] The signal output circuit according to any one of the above configurations α1 to α4 further comprises a gate voltage adjustment circuit (160) configured to adjust a specific gate voltage for setting each low-side transistor on based on an intermediate voltage between the first DC voltage and the second DC voltage, wherein each high-side transistor is configured by a P-channel MOSFET having a source connected to the first DC wiring, each low-side transistor is configured by an N-channel MOSFET having a source connected to the second DC wiring, and the gate voltage adjustment circuit adjusts a specific gate voltage for setting each low-side transistor on based on an intermediate voltage between the first DC voltage and the second DC wiring, wherein each high-side transistor is configured by a P-channel MOSFET having a source connected to the second DC wiring, and a first series resistor (162), a second series resistor (163) configured to have the same resistance as the first series resistor, and a second replica transistor (164) configured by an N-channel MOSFET having a source connected to the second DC wiring, wherein a drain of the first replica transistor is connected to a first end of the first series resistor, and a second end of the first series resistor is connected to a drain of the second replica transistor via the second series resistor, and the control circuit applies a gate voltage (V GH ) is supplied to the gate of one or more low-side transistors that are set to ON among the plurality of low-side transistors, and the gate voltage (V GL ), and the gate voltage adjustment circuit may be configured to adjust the gate voltage of the second replica transistor, which is the specific gate voltage, so as to reduce the difference between the voltage at the connection node between the first series resistor and the second series resistor and the intermediate voltage (hereinafter referred to as configuration α8).

[0124] This makes it possible to achieve good symmetry between the first output signal and the second output signal.

[0125] In the signal output circuit according to the above-mentioned configuration α8, the gate of the first replica transistor is connected to the first gate wiring (WGH ), and the high-side output circuit is provided with a high-side selector (SEL_H) for each of the high-side transistors, which switches the connection destination of the gate of the high-side transistor between the first gate wiring and the first DC wiring, and the control circuit, through state control of the corresponding high-side selector for each of the high-side transistors, sets the connection destination of the gate of the high-side transistor to the first gate wiring to turn on the high-side transistor, and sets the connection destination of the gate of the high-side transistor to the first DC wiring to turn off the high-side transistor, and the gate of the second replica transistor is connected to a second gate wiring (W GL ), and the low-side output circuit is provided with a low-side selector (SEL_L) for each of the low-side transistors that switches the connection destination of the gate of the low-side transistor between the second gate wiring and the second DC wiring, and the control circuit may be configured to set the connection destination of the gate of the low-side transistor to the second gate wiring through state control of the corresponding low-side selector for each of the low-side transistors, thereby turning on the low-side transistor, and to set the connection destination of the gate of the low-side transistor to the second DC wiring (hereinafter referred to as configuration α9).

[0126] In the signal output circuit according to any one of the above configurations α7 to α9, the first signal terminal is connected to an output resistor (R TM , RL) (hereinafter referred to as configuration α10).

[0127] A signal output circuit according to another aspect of the present disclosure comprises: a DC wiring configured to apply a predetermined DC voltage (VCC or 0V); a signal terminal (HH or LL); an output circuit (110 or 120) having a parallel circuit of a plurality of output transistors provided between the DC wiring and the signal terminal; and a control circuit (150) configured to individually set the plurality of output transistors on or off and generate an output signal (SH or SL) at the signal terminal by controlling the current between the DC wiring and the signal terminal through the parallel circuit, wherein when one or more output transistors are set on and a signal current (IH or IL) flows between the DC wiring and the signal terminal through the one or more output transistors, the output circuit operates the one or more output transistors in a linear region or a saturation region according to the voltage difference between the DC wiring and the signal terminal, and by operating the one or more output transistors in the saturation region, suppresses an increase in the signal current associated with a voltage drop or voltage rise at the signal terminal (hereinafter referred to as configuration α11).

[0128] By operating the output transistor in the linear region, the output transistor can function as a resistive element. Therefore, the series-connected resistor (913 or 923) to the output transistor, which was necessary in the reference example of FIG. 6, is not necessary in the configuration α11 (thus reducing the number of components). Because the output transistor actively functions as a resistive element, the output transistor can be small in size. Reducing the transistor size reduces switching noise associated with switching. Furthermore, in the configuration α11, the one or more output transistors are operated in the linear region or saturation region depending on the voltage difference between the DC wiring and the signal terminal. Operating the one or more output transistors in the saturation region suppresses the increase in the signal current associated with a voltage drop or voltage rise at the signal terminal. Therefore, the current limiting transistor (914 or 924) for the output transistor, which was necessary in the reference example of FIG. 6, is not necessary in the configuration α11 (thus reducing the number of components).

[0129] In the signal output circuit relating to the above-mentioned configuration α11, when the one or more output transistors are set to on in a short-circuit state (e.g., a ground fault or a power fault state) in which the signal terminal is short-circuited to a specific conductive part having a predetermined voltage different from the DC voltage, the output circuit may be configured to suppress the increase in the signal current due to the short-circuit of the signal terminal by operating the one or more output transistors in a saturation region (hereinafter referred to as configuration α12).

[0130] This prevents an excessive current from flowing through the output transistor in a short-circuit state.

[0131] In the signal output circuit relating to the above-mentioned configuration α12, in a normal state in which the signal terminal is not connected to the specific conductive part, the output circuit operates the one or more output transistors set to on in a linear region, and in the normal state, the control circuit gradually changes the level of the output signal from a first level (VM1 or VM2) to a second level (VH or VL) by sequentially increasing the number of output transistors that are turned on from an all-off state in which all output transistors are set to off, and gradually changes the level of the output signal from the second level to the first level by sequentially increasing the number of output transistors that are turned off from an all-on state in which all output transistors are set to on (hereinafter referred to as configuration α13).

[0132] The signal output circuit according to any one of the above configurations α11 to α13 may further include a protection circuit (130 or 140) inserted between the output circuit and the signal terminal, and the protection circuit may be configured (hereinafter referred to as configuration α14) to protect each output transistor from an abnormal voltage that deviates from a predetermined allowable voltage range when the abnormal voltage is applied to the signal terminal.

[0133] In the signal output circuit according to the above-mentioned configuration α14, each output transistor may be configured by a P-channel or N-channel MOSFET having a source connected to the DC wiring, and the protection circuit may be inserted between the drain of each output transistor and the signal terminal (hereinafter referred to as configuration α15).

[0134] <<Second Note>> A second appendix is ​​provided for the present disclosure, the specific configuration examples of which are shown in the above-described embodiments.

[0135] A signal output circuit (11) according to one aspect of the present disclosure includes a first DC wiring (W) configured to apply a predetermined first DC voltage (VCC). VCC ), a first signal terminal (HH), a high-side output circuit (110) having a first parallel circuit of a plurality of high-side transistors (MH) provided between the first DC wiring and the first signal terminal, and a second DC wiring (W) configured to apply a second DC voltage (0 V) lower than the first DC voltage. GND a low-side output circuit (120) having a second parallel circuit of a plurality of low-side transistors (ML) provided between the second DC wiring and the second signal terminal; a control circuit (150) configured to individually set the plurality of high-side transistors on or off and control the current between the first DC wiring and the first signal terminal through the first parallel circuit to generate a first output signal (SH) at the first signal terminal, and to individually set the plurality of low-side transistors on or off and control the current between the second DC wiring and the second signal terminal through the second parallel circuit to generate a second output signal (SL) at the second signal terminal; and a gate voltage adjustment circuit (160) configured to adjust a specific gate voltage for setting each low-side transistor on based on an intermediate voltage between the first DC voltage and the second DC voltage (hereinafter referred to as configuration β1).

[0136] This makes it possible to achieve good symmetry between the first output signal and the second output signal.

[0137] In the signal output circuit according to the above-described configuration β1, each high-side transistor is configured by a P-channel MOSFET having a source connected to the first DC wiring, and each low-side transistor is configured by an N-channel MOSFET having a source connected to the second DC wiring; the gate voltage adjustment circuit includes a first replica transistor (161) configured by a P-channel MOSFET having a source connected to the first DC wiring, a first series resistor (162), a second series resistor (163) configured to have the same resistance value as the first series resistor, and a second replica transistor (164) configured by an N-channel MOSFET having a source connected to the second DC wiring, the drain of the first replica transistor is connected to a first end of the first series resistor, and the second end of the first series resistor is connected to the drain of the second replica transistor via the second series resistor; and the control circuit adjusts the gate voltage (V GH ) is supplied to the gate of one or more low-side transistors that are set to ON among the plurality of low-side transistors, and the gate voltage (V GL ), and the gate voltage adjustment circuit may be configured to adjust the gate voltage of the second replica transistor, which is the specific gate voltage, so as to reduce the difference between the voltage at the connection node between the first series resistor and the second series resistor and the intermediate voltage (hereinafter referred to as configuration β2).

[0138] This makes it possible to achieve good symmetry between the first output signal and the second output signal.

[0139] In the signal output circuit according to the above-mentioned configuration β2, the gate of the first replica transistor is connected to the first gate wiring (W GH), and the high-side output circuit is provided with a high-side selector (SEL_H) for each of the high-side transistors, which switches the connection destination of the gate of the high-side transistor between the first gate wiring and the first DC wiring, and the control circuit, through state control of the corresponding high-side selector for each of the high-side transistors, sets the connection destination of the gate of the high-side transistor to the first gate wiring to turn on the high-side transistor, and sets the connection destination of the gate of the high-side transistor to the first DC wiring to turn off the high-side transistor, and the gate of the second replica transistor is connected to a second gate wiring (W GL ), and the low-side output circuit is provided with a low-side selector (SEL_L) for each of the low-side transistors that switches the connection destination of the gate of the low-side transistor between the second gate wiring and the second DC wiring, and the control circuit may be configured to set the connection destination of the gate of the low-side transistor to the second gate wiring through state control of the corresponding low-side selector for each of the low-side transistors, thereby turning on the low-side transistor, and to set the connection destination of the gate of the low-side transistor to the second DC wiring (hereinafter referred to as a configuration β3).

[0140] In the signal output circuit according to any one of the above configurations β1 to β3, the control circuit may be configured to: gradually increase the number of high-side transistors that are turned on and the number of low-side transistors that are turned on from an all-off state in which all high-side transistors and all low-side transistors are set to off, thereby gradually increasing the level of the first output signal from a first level (VM1) to a second level (VH) and gradually decreasing the level of the second output signal from a third level (VM2) to a fourth level (VL); and gradually increase the number of high-side transistors that are turned off and the number of low-side transistors that are turned off from an all-on state in which all high-side transistors and all low-side transistors are set to on, thereby gradually decreasing the level of the first output signal from the second level to the first level and gradually increasing the level of the second output signal from the fourth level to the third level (hereinafter referred to as configuration β4).

[0141] The signal output circuit according to the above-described configuration β1 may further include a first protection circuit (130) inserted between the high-side output circuit and the first signal terminal, and a second protection circuit (140) inserted between the low-side output circuit and the second signal terminal, wherein the first protection circuit protects each high-side transistor from a first abnormal voltage that deviates from a predetermined first allowable voltage range when the first abnormal voltage is applied to the first signal terminal, and the second protection circuit protects each low-side transistor from a second abnormal voltage that deviates from a predetermined second allowable voltage range when the second signal terminal is applied to the second signal terminal (hereinafter referred to as configuration β5).

[0142] In the signal output circuit according to the above-described configuration β5, each high-side transistor may be configured by a P-channel MOSFET having a source connected to the first DC wiring, each low-side transistor may be configured by an N-channel MOSFET having a source connected to the second DC wiring, the first protection circuit may be inserted between the drain of each high-side transistor and the first signal terminal, and the second protection circuit may be inserted between the drain of each low-side transistor and the second signal terminal (hereinafter referred to as configuration β6).

[0143] In the signal output circuit according to any one of the above configurations β1 to β6, the first signal terminal is connected to an output resistor (R TM , RL) (hereinafter referred to as configuration β7). [Explanation of symbols]

[0144] 1 ECU 2~5 cables 10 Transceiver 11 Transmitting circuit 12 Receiver circuit 20 MPU 30 Regulator 41 Reverse current prevention diode 42, 43 Capacitor TP, TN, TH, TL terminals IN power supply terminal GND Ground terminal HH, LL output terminals RXD Received data output pin TXD Transmit data input pin R TM Termination resistor VPW Input voltage VCC power supply voltage S_T Transmit data signal S_R Received data signal S_DIF Differential signal SH High side signal SL Low side signal 11ref Transmitter circuit 910 High-side output circuit 911 Unit Circuit 912 High-side transistor 913 Resistance 914 Current limiting transistor 915 Pull-up resistor 920 Low-side output circuit 921 Unit Circuit 922 Low-side transistor 923 Resistance 924 Current limiting transistor 925 pull-down resistor 930 High-side protection circuit 931 Protection Transistor 932 Reverse current prevention diode 940 Low-side protection circuit 941 Protection Transistor 942 Reverse current prevention diode 110 High-side output circuit 111 Unit Circuit 112 pull-up resistor MH high-side transistor SEL_H Selector 120 Low-side output circuit 121 Unit Circuit 122 pull-down resistor ML low-side transistor SEL_L Selector 130 High-side protection circuit 131 Protection transistor 132 Reverse current prevention diode 140 Low-side protection circuit 141 Protection transistor 142 Reverse current prevention diode 150 control circuit 160 Gate voltage adjustment circuit 161, 164, 167-169 Transistors 162, 163 Resistor 165 operational amplifiers 166 Current source 170 Intermediate voltage generation circuit CM0~CM2 current mirror circuit W VCC power wiring W GND Ground wiring W GH , W GL Gate wiring V GH , V GL Gate voltage IH, IL signal current I REF Reference current I BP1 , I BP2 Reference current

Claims

1. a first DC wiring configured to apply a predetermined first DC voltage; a first signal terminal; a high-side output circuit including a first parallel circuit of a plurality of high-side transistors provided between the first DC wiring and the first signal terminal; a second DC wiring configured to apply a second DC voltage lower than the first DC voltage; a second signal terminal; a low-side output circuit having a second parallel circuit of a plurality of low-side transistors provided between the second DC wiring and the second signal terminal; a control circuit configured to individually set the plurality of high-side transistors on or off and control a current between the first DC wiring and the first signal terminal through the first parallel circuit to generate a first output signal at the first signal terminal, and to individually set the plurality of low-side transistors on or off and control a current between the second DC wiring and the second signal terminal through the second parallel circuit to generate a second output signal at the second signal terminal; a gate voltage adjusting circuit configured to adjust a specific gate voltage for turning on each low-side transistor based on an intermediate voltage between the first DC voltage and the second DC voltage. , signal output circuit.

2. each high-side transistor is configured by a P-channel MOSFET having a source connected to the first DC wiring, and each low-side transistor is configured by an N-channel MOSFET having a source connected to the second DC wiring; the gate voltage adjustment circuit includes a first replica transistor configured by a P-channel MOSFET having a source connected to the first DC wiring, a first series resistor, a second series resistor configured to have the same resistance value as the first series resistor, and a second replica transistor configured by an N-channel MOSFET having a source connected to the second DC wiring; a drain of the first replica transistor is connected to a first end of the first series resistor, a second end of the first series resistor is connected to a drain of the second replica transistor via the second series resistor; the control circuit supplies a gate voltage of the first replica transistor to a gate of one or more high-side transistors that are set to on among the plurality of high-side transistors, and supplies a gate voltage of the second replica transistor to a gate of one or more low-side transistors that are set to on among the plurality of low-side transistors; The gate voltage adjusting circuit adjusts the gate voltage of the second replica transistor, which is the specific gate voltage, so as to reduce the difference between the voltage at the connection node between the first series resistor and the second series resistor and the intermediate voltage.

2. The signal output circuit according to claim 1.

3. the gate of the first replica transistor is connected to a first gate wiring; In the high-side output circuit, a high-side selector is provided for each of the high-side transistors, which switches a connection destination of the gate of the high-side transistor between the first gate wiring and the first DC wiring; the control circuit sets the connection destination of the gate of the high-side transistor to the first gate wiring through state control of the corresponding high-side selector for each of the high-side transistors, thereby turning on the high-side transistor, and sets the connection destination of the gate of the high-side transistor to the first DC wiring, thereby turning off the high-side transistor; the gate of the second replica transistor is connected to a second gate wiring; In the low-side output circuit, a low-side selector is provided for each low-side transistor, which switches a connection destination of the gate of the low-side transistor between the second gate wiring and the second DC wiring; The control circuit sets the connection destination of the gate of each of the low-side transistors to the second gate wiring through state control of a corresponding low-side selector, thereby turning on the low-side transistor, and sets the connection destination of the gate of each of the low-side transistors to the second DC wiring, thereby turning off the low-side transistor.

3. The signal output circuit according to claim 2.

4. The control circuit gradually increases the number of high-side transistors that are turned on and the number of low-side transistors that are turned on from an all-off state in which all high-side transistors and all low-side transistors are set to off, thereby gradually increasing the level of the first output signal from the first level to the second level and gradually decreasing the level of the second output signal from the third level to the fourth level, and gradually increasing the number of high-side transistors that are turned off and the number of low-side transistors that are turned off from an all-on state in which all high-side transistors and all low-side transistors are set to on, thereby gradually decreasing the level of the first output signal from the second level to the first level and gradually increasing the level of the second output signal from the fourth level to the third level.

2. The signal output circuit according to claim 1.

5. a first protection circuit inserted between the high-side output circuit and the first signal terminal, and a second protection circuit inserted between the low-side output circuit and the second signal terminal; The first protection circuit protects each high-side transistor from a first abnormal voltage when a first abnormal voltage that deviates from a predetermined first allowable voltage range is applied to the first signal terminal, and the second protection circuit protects each low-side transistor from a second abnormal voltage when a second abnormal voltage that deviates from a predetermined second allowable voltage range is applied to the second signal terminal.

2. The signal output circuit according to claim 1.

6. each high-side transistor is configured by a P-channel MOSFET having a source connected to the first DC wiring, and each low-side transistor is configured by an N-channel MOSFET having a source connected to the second DC wiring; The first protection circuit is inserted between the drain of each high-side transistor and the first signal terminal, and the second protection circuit is inserted between the drain of each low-side transistor and the second signal terminal.

6. The signal output circuit according to claim 5.

7. The first signal terminal is connected to the second signal terminal via an output resistor.

7. A signal output circuit according to claim 1.

Images