Logic integrated circuit, look-up table, reconfiguration circuit, and integrated circuit

Abstract

To reduce a leakage current while suppressing an increase in the number of connection wirings and an increase in the area accompanying the increase in the number of connection wirings.SOLUTION: Control transistors 171a to c are connected to a signal line RH1, are configured to switch an electrical connection between a power supply line PS[0] and the signal line RH1, and their gates are connected to a write control line GSH. Control transistors 172a to c are connected to a signal line RH2, are configured to switch the electrical connection between the power supply line PS[0] and the signal line RH2, and their gates are connected to a write control line GSH in common with the control transistors 171a to c arranged in a lateral direction. Control transistors 181a and b are connected to a write control line SV, and switch the electrical connection between a power supply line PS[1] and the write control line SV. Control transistors 182a and b are connected to a signal line RV, and switch the electrical connection between a power supply line PS[2] and the signal line RV.SELECTED DRAWING: Figure 10A

Description

[Technical Field]

[0001] The present invention relates to a logic integrated circuit having a reconfigurable logic circuit, a lookup table, a reconfigurable circuit, and an integrated circuit, and more particularly to a technology for reducing power consumption and increasing integration of logic integrated circuits. [Background technology]

[0002] A programmable logic integrated circuit (PLC) whose logic circuit can be reconfigured is also called a reconfigurable circuit, and various logic circuits can be reconfigured by rewriting the internal setting information. FIG. 1 is a circuit diagram of a typical reconfigurable circuit. The reconfigurable circuit in FIG. 1 includes a plurality of logic blocks (LBs) 1001 and a plurality of routing blocks (RBs) 1002. The LBs include lookup tables (LUTs) and flip-flops (FFs) such as D-type flip-flops (DFFs). The RBs switch input / output signals to the LBs and switch signal paths between the LBs.

[0003] The number of configurable logic elements (the circuit scale of the reconfigurable circuit) can be adjusted by designing configurable logic blocks (CLBs) with a certain size of LBs and RBs. By adjusting the number of CLBs arranged to be interconnected, semiconductor chips containing reconfigurable circuits of different circuit scales can be manufactured to meet customer needs. Reconfigurable circuits are currently widely used in fields such as prototyping, image processing, and communications.

[0004] The signal switching section, RB, is implemented using an SRAM switch consisting of an SRAM (Static Random Access Memory) and a pass transistor. Recently, as shown in Patent Documents 1 and 2, a technology has been proposed that can reduce chip area and power consumption by replacing the RB with a resistance change element. As shown in Figure 2(a), the above-mentioned resistance change element has a structure in which a resistance change element (RE) made of a solid electrolyte material (IC) containing metal ions is placed between a first wiring layer (T1) and a second wiring layer (T2) formed on top of it. Figure 2(b) shows a symbolic representation of the resistance change element (RE) in Figure 2(a). The resistance value of the resistance change element (RE) in Figures 2(a) and 2(b) can be changed from a high resistance state to a low resistance state or from a low resistance state to a high resistance state as shown in Figure 2(c) by applying a forward bias or reverse bias voltage to both ends (T1, T2) of the resistance change element. The ratio of the low resistance state (ON state) to the high resistance state (OFF state) of the resistance change element (RE) is 10 5 Or even more.

[0005] When using resistance change elements as switches in a reconfigurable circuit, a voltage is constantly applied to all switches in the circuit. Therefore, higher reliability is required compared to memory switches, in which current and voltage are applied only during data read operations. Therefore, instead of a 1T1R structure switch cell consisting of one resistance change element and one transistor, a complementary (1T2R) structure using one transistor and two paired resistance change elements, as shown in Figure 3, has been proposed (Patent Documents 3 and 4).

[0006] Figure 3A is a schematic diagram of a switch cell consisting of two variable resistance elements and a transistor. Figure 3B is a circuit diagram of a switch cell arranged as a cross-point cell for signal switching. Figures 3C and 3D are perspective and plan views, respectively, showing the wiring layout of a switch cell containing variable resistance elements. The switch cell in Figure 3A consists of two variable resistance elements (RE[1], RE[2]) and one transistor (Tr.). One side of the electrodes of the two variable resistance elements (RE[1], RE[2]) are connected to each other, and one of the diffusion layers (source or drain) of the select transistor (Tr.) is connected to this common node. The variable resistance element (RE) utilizes the movement and electrochemical reaction of metal ions in a solid (ionic conductor) where ions can move freely when an electric field is applied. It has a large resistance change and is used as a switch element that can distinguish whether a signal passes or does not pass between electrodes. As shown in Figure 2(a), the resistance change element (RE) is composed of an ion conduction layer (IC) and electrodes (T1) and (T2) that are placed on the opposing surfaces of the ion conduction layer (IC). Metal ions are supplied from electrode (T1) to the ion conduction layer, but not from electrode (T2). Changing the polarity of the applied voltage changes the resistance of the ion conductor, controlling the conduction state between the two electrodes.

[0007] In a crossbar switch, switch cells are located near each crosspoint of vertical wiring (RV[j]) and horizontal wiring (RH[k]). To prevent erroneous writing (disturbance) to a variable resistance element near a different crosspoint when turning on / off the variable resistance element near that crosspoint, the switch cells are also connected to two wirings (SV[j], GH[k]) that control select transistors (Tr.). As shown in Figure 3B, a crossbar switch has at least four types of wiring (RV, RH, SV, GH) running vertically or horizontally. Figures 3A and 3B can be configured in the switch cell region using metal layers A, B, and vias (see Figure 3C). The transistors (Tr.) in the switch cells are formed on a silicon substrate, and the variable resistance elements (RE[1], RE[2]) are formed in the wiring layer.

[0008] The switch cells using the above-mentioned resistance change elements constitute a crossbar switch and are used as signal inputs to routing blocks (RBs) and as changeover switches (multiplexers) for signal switching. A switch cell array using such resistance change elements is proposed in Patent Document 5. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Patent No. 4356542 [Patent Document 2] International Publication No. 2012 / 043502 [Patent Document 3] International Publication No. 2013 / 190742 [Patent Document 4] International Publication No. 2014 / 030393 [Patent Document 5] International Publication No. 2016 / 042750 [Non-patent literature]

[0010] [Non-Patent Document 1] "Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics", Xu Bai,et.al., Proceedings of the 2015 ACM / SIGDA International Symposium on Field-Programmable Gate Arrays, pp.269,(2015). Summary of the Invention [Problem to be solved by the invention]

[0011] When configuring a programmable logic integrated circuit with switch cells using resistance change elements, it is desirable to be able to reduce leakage current while suppressing an increase in the number of connection wires and the resulting increase in area.

[0012] An object of the present invention is to provide a logic integrated circuit that can reduce leakage current while suppressing an increase in the number of connection wires and the resulting increase in area. [Means for solving the problem]

[0013] In order to achieve the above object, a logic integrated circuit according to the present invention is a logic operation circuit having a plurality of first switch cells including a resistance change element and a plurality of second switch cells including a resistance change element, the logic operation circuit including a first output port and a second output port, a plurality of first wirings arranged along a first direction and connected to the first output port, a plurality of second wirings arranged along the first direction and connected to the second output port, a plurality of first write control lines arranged along the first wirings and the second wirings, a plurality of second write control lines arranged along the first wirings and the second wirings, a plurality of third wirings arranged along the second direction, a plurality of third write control lines arranged along the third wirings, the plurality of first switch cells arranged at locations where the first wirings and the third wirings intersect, one control terminal connected to the first write control line and the other control terminal connected to the third write control line, and switching an electrical connection between the first wirings and the third wiring, and the plurality of second switch cells are arranged at locations where the second wiring and the third wiring intersect, and one control terminal is connected to the first write control line and the other control terminal is connected to the third write control line, and switch an electrical connection between the second wiring and the third wiring; a first control transistor is connected to the first wiring and configured to switch an electrical connection between the first wiring and a first power supply line that supplies power to the first wiring, and has a gate connected to the second write control line; a second control transistor is connected to the second wiring and configured to switch an electrical connection between the second wiring and the first power supply line that supplies power to the second wiring, and has a gate connected to the second write control line; a third control transistor is connected to the third write control line and switches an electrical connection between the third write control line and a second power supply line that supplies power to the third write control line; and a fourth control transistor is connected to the third wiring and switches an electrical connection between the third power supply line that supplies power to the third wiring and the third wiring. The first control transistor and the second control transistor arranged in the first direction are connected to the same second write control line via their gates. [Effects of the Invention]

[0014] According to the present invention, it is possible to provide a programmable logic integrated circuit that can reduce leakage current while suppressing an increase in the number of connection wires and the resulting increase in area. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 2 is a block diagram illustrating a reconfigurable circuit including a plurality of logic blocks and a plurality of routing blocks. [Figure 2] (a) is a diagram of the resistance change element, (b) is a symbolic representation of the resistance change element, and (c) is a state table that explains the applied voltage to change the resistance of the resistance change element and the operation method of the state change of the resistance value. [Figure 3A] is a diagram showing the configuration of a switch cell consisting of two variable resistance elements and a transistor. [Figure 3B] 1 is a circuit diagram of a switch cell arranged as a cross-point cell for signal switching. [Figure 3C] FIG. 10 is a perspective view showing a wiring layout of a switch cell including a resistance change element. [Figure 3D] FIG. 10 is a plan view showing a wiring layout of a switch cell including a resistance change element. [Figure 4] 1 is a block diagram showing an example of the configuration of a switch cell array using switch cells and a crossbar switch circuit including a control circuit for switching on / off the switch cells. [Figure 5] FIG. 5 is a conceptual diagram for explaining an interface of the crossbar switch circuit of FIG. 4. [Figure 6] FIG. 10 is a conceptual diagram illustrating an interface of a crossbar switch circuit used as a memory for a lookup table. [Figure 7] 7 is a conceptual diagram showing an example of the configuration of an LUT (LUT architecture A) using the crossbar switch circuit of FIG. 6. FIG. [Figure 8]FIG. 10 is a conceptual diagram illustrating an interface of a crossbar switch circuit used as a memory for a lookup table. [Figure 9] 9 is a conceptual diagram showing an example of a configuration (LUT architecture B) in which an LUT is configured by applying the crossbar switch circuit of FIG. 8. FIG. [Figure 10A] FIG. 10 is a block diagram illustrating a crossbar switch circuit used as a memory for a lookup table according to an embodiment. [Figure 10B] FIG. 10B is a conceptual diagram for explaining an interface of the crossbar switch circuit of FIG. 10A. [Figure 11] (a) is a block diagram of a lookup table (LUT) including a crossbar memory and a multiplexer (MUX), (b) is a block diagram of a reconfigurable circuit including a crossbar switch circuit, and (c) is a block diagram of an integrated circuit including a reconfigurable circuit of an embodiment and an arithmetic circuit, etc. [Figure 12] FIG. 10C is a block diagram showing an example of an LUT using the crossbar switch circuit of FIG. 10B. [Figure 13] 10 is a table showing a comparison of the number of wirings and leakage currents between an LUT using the crossbar switch circuit of the embodiment, an LUT architecture A, and an LUT architecture B. [Figure 14] FIG. 10 is a block diagram illustrating another example of a multiplexer that configures the LUT of the embodiment. [Figure 15] FIG. 1 is a block diagram illustrating an example of implementing M LUTs. [Figure 16] FIG. 10 is a block diagram illustrating an example of an implementation of a memory for saving setting data, which is realized by connecting an output port of the crossbar switch circuit of the embodiment that is not used as the LUT memory side to an output port of a separately prepared crossbar switch circuit. [Figure 17] FIG. 10 is a block diagram illustrating a large scale logic integrated circuit in which CLBs including LBs and RBs are arranged on tiles, and write control lines within each crossbar are shared to eliminate redundant wiring. [Figure 18] FIG. 10 is a circuit diagram showing a configuration of a comparative example. [Figure 19] FIG. 10 is a schematic diagram illustrating a problem in the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0016] Before describing specific embodiments, the problems to be solved by the present invention and comparative examples will be described.

[0017] The crossbar switch circuit 10 in Fig. 4 is a reconfigurable circuit that is the prototype of the logic integrated circuit and reconfigurable circuit according to the embodiment of the present invention. The crossbar switch circuit 10 in Fig. 4 is a crossbar switch circuit for switching signals with J inputs and K outputs (J and K: natural numbers). A crossbar switch circuit with J inputs and K outputs may be expressed as a J x K crossbar in the drawings. Fig. 4 also illustrates control transistors and control wiring for controlling the supply voltage and current source from a power source (PS) for writing when rewriting (or writing) a resistance change element.

[0018] 4 includes a switch cell array 11, a vertical control circuit 12, and a horizontal control circuit 13. The vertical control circuit 12 includes first control transistors 12a to 12c. The horizontal control circuit 13 includes second control transistors 131a to 131c and third control transistors 132a to 132c.

[0019] The switch cell array 11 includes a plurality of switch cells (switches [n, k]). In Fig. 4, as an example of the plurality of switch cells (switches [n, k]), switch cells 11a to 11i are shown arranged in a 3 x 3 array. Each of the switch cells 11a to 11i includes a switch element.

[0020] The switch cells 11a to 11c share a write control line GH[k-1] and a signal line RH[k-1], which are wirings extending in the x-direction (first direction). The write control line GH[k-1] and the signal line RH[k-1] are wirings independent of each other. The signal line RH[k-1] is connected to one diffusion layer of the first control transistor 12a connected to the switch cells 11a to 11c. The power supply line PS[0] is connected to the other diffusion layer of the first control transistor 12a. The write control line GSH[k-1] is connected to the gate electrode of the first control transistor 12a. The write control line GSH[k-1] is a wiring used to change the resistance of the switch element included in the switch cells 11a to 11c.

[0021] Similarly, the switch cells 11d to 11f share the write control line GH[k] and the signal line RH[k], which are wirings in the x direction. The write control line GH[k] and the signal line RH[k] are wirings independent of each other. The signal line RH[k] is connected to one diffusion layer of the first control transistor 12b connected to the switch cells 11d to 11f. The power supply line PS[0] is connected to the other diffusion layer of the first control transistor 12b. The write control line GSH[k] is connected to the gate electrode of the first control transistor 12b. The write control line GSH[k] is a wiring used to change the resistance of the switch element included in the switch cells 11d to 11f.

[0022] Similarly, the switch cells 11g to 11i share the write control line GH[k+1] and the signal line RH[k+1], which are wirings in the x direction. The write control line GH[k+1] and the signal line RH[k+1] are wirings independent of each other. The signal line RH[k+1] is connected to one diffusion layer of the first control transistor 12c connected to the switch cells 11g to 11i. The power supply line PS[0] is connected to the other diffusion layer of the first control transistor 12c. The write control line GSH[k+1] is connected to the gate electrode of the first control transistor 12c. The write control line GSH[k+1] is a wiring used to change the resistance of the switch element included in the switch cells 11g to 11i.

[0023] The switch cells 11a, 11d, and 11g share a write control line SV[j-1] and a signal line RV[j-1], which are wirings extending in the y direction (second direction). The write control line SV[j-1] and the signal line RV[j-1] are wirings independent of each other. The write control line SV[j-1] is connected to one diffusion layer of a second control transistor 131a connected to the switch cells 11a, 11d, and 11g. A power supply line PS[1] is connected to the other diffusion layer of the second control transistor 131a. A driver control line PGV[j-1] is connected to the gate electrode of the second control transistor 131a. Furthermore, the signal line RV[j-1] is connected to one diffusion layer of a third control transistor 132a connected to the switch cells 11a, 11d, and 11g. A power supply line PS[2] is connected to the other diffusion layer of the third control transistor 132a. The driver control line PGV[j-1] is connected to the gate electrode of the third control transistor 132a.

[0024] The switch cells 11b, 11e, and 11h share the write control line SV[j] and signal line RV[j], which are wirings in the y direction. The write control line SV[j] and signal line RV[j] are independent wirings. The write control line SV[j] is connected to one diffusion layer of the second control transistor 131b connected to the switch cells 11b, 11e, and 11h. The power supply line PS[1] is connected to the other diffusion layer of the second control transistor 131b. The driver control line PGV[j] is connected to the gate electrode of the second control transistor 131b. Furthermore, the signal line RV[j] is connected to one diffusion layer of the third control transistor 132b connected to the switch cells 11b, 11e, and 11h. The power supply line PS[2] is connected to the other diffusion layer of the third control transistor 132b. The driver control line PGV[j] is connected to the gate electrode of the third control transistor 132b.

[0025] The switch cells 11c, 11f, and 11i share a write control line SV[j+1] and a signal line RV[j+1], which are wirings in the y direction. The write control line SV[j+1] and the signal line RV[j+1] are independent wirings. The write control line SV[j+1] is connected to one diffusion layer of the second control transistor 131c, which is connected to the switch cells 11c, 11f, and 11i. The power supply line PS[1] is connected to the other diffusion layer of the second control transistor 131c. The driver control line PGV[j+1] is connected to the gate electrode of the second control transistor 131c. Furthermore, the signal line RV[j+1] is connected to one diffusion layer of the third control transistor 132c, which is connected to the switch cells 11c, 11f, and 11i. The power supply line PS[2] is connected to the other diffusion layer of the third control transistor 132c. The gate electrode of the third control transistor 132c is connected to the driver control line PGV[j+1].

[0026] 5 is a conceptual diagram showing an input / output interface, with a J-input / K-output crossbar switch circuit 10 (J×K crossbar) as one block. As shown in FIG. 5, the signal line RV and the driver control line PGV are arranged on one side corresponding to the y direction. Furthermore, the write control line GH, the write control line GSH, and the power supply line PS are arranged on one side corresponding to the x direction, and the signal line RH is arranged on the other side.

[0027] FIG. 6 is a conceptual diagram showing an input / output interface, with a 2-input, K-output crossbar switch circuit 10a (2×K crossbar) as one block. FIG. 6 is an illustration of a crossbar memory used in a look-up table (LUT). As shown in FIG. 6, a signal line RV, to which a power supply level (Vdd) or a ground level (GND) is input, and a driver control line PGV are arranged on one side corresponding to the y direction. Furthermore, a write control line GH, a write control line GSH, and a power supply line PS are arranged on one side corresponding to the x direction, and a signal line RH is arranged on the other side.

[0028] The crossbar switch circuit 10a can function as a memory by inputting a power supply level (Vdd) and a ground level (GND) to two RV ports of the crossbar switch configuration, respectively. By turning on the switch cells of Vdd or GND, the output level of the output node of the crossbar switch circuit 10a can be controlled to Vdd or GND.

[0029] FIG. 7 is a conceptual diagram showing an example of the configuration of an LUT 20 of a comparative example. The example configuration shown in FIG. 7 is hereinafter referred to as LUT architecture A. The LUT 20 of FIG. 7 is implemented by connecting the output from the 2-input, K-output crossbar switch circuit 10a (2×K crossbar) shown in FIG. 6 to the input port of the multiplexer 15. In the example of FIG. 7, the output node (K=2 N ) is the 2nd input of the N-input multiplexer 15. N The LUT 20 is connected to input nodes N and K (where N and K are natural numbers) and functions as one LUT 20.

[0030] The multiplexer 15 in Fig. 7 has a configuration in which multiple complementary elements are combined. Fig. 7 shows an example in which a pair of PMOS (P-channel type Metal Oxide Semiconductor) and NMOS (N-channel type Metal Oxide Semiconductor) CMOS (Metal Oxide Semiconductor) switches 15a are combined in parallel. Note that Fig. 7 shows an example configuration for a two-input LUT in which six switches are combined, but the number of CMOS switches 15a and inputs is set according to the scale of the logic circuit to be configured. Note that in Fig. 7 and subsequent figures, gate lines connected to the gate electrodes of MOS switches such as the CMOS switches that make up the multiplexer are omitted.

[0031] The memory for the look-up table (LUT) in the LB can also be implemented in the same process without using any other memory by using the resistance change type switch cell (crossbar switch) used as the switch for the RB shown in Figures 6 and 7.

[0032] We will now examine in detail the 2-input, K-output crossbar switch circuit 10a (2×K crossbar) in Fig. 6, the number of wires constituting the LUT 20 in Fig. 7 that uses this circuit, and the leakage current. In the crossbar switch configuration shown in Fig. 6, the power supply level (Vdd) and ground level (GND) are input to the two RV ports, respectively, and the outputs are connected to the memory input ports in the LUT 20 as shown in Fig. 7. In this implementation method (LUT architecture A), the wiring resources connecting the LUT crossbar memory and the multiplexer are kept to the minimum required 2 N =K units. On the other hand, 2 N On each of the K lines, the potential difference between GND and Vdd is applied to the switch cell in the off state. If the off resistance per switch cell is 100MΩ, then Vdd = 1V = 10nA × 2 N This leakage occurs with just one N-input LUT.

[0033] On the other hand, other implementation methods are also possible. FIG. 9 is a conceptual diagram showing another example of the configuration of an LUT of a comparative example. The example configuration shown in FIG. 9 is hereinafter referred to as LUT architecture B. FIG. 8 is a conceptual diagram showing an input / output interface of a crossbar switch circuit 10b used in the LUT 21 shown in FIG. 9, in which a 1-input, K-output crossbar switch circuit (1×K crossbar) is treated as one block. As shown in FIG. 8, a signal line RV*, to which a power supply level (Vdd) or a ground level (GND) is input, and a driver control line PGV are arranged on one side corresponding to the y direction. Furthermore, a write control line GH, a write control line GSH, and a power supply line PS are arranged on one side corresponding to the x direction, and a signal line RH* is arranged on the other side. The signal line RV* or a high-impedance state (Hi-Z) is applied to the signal line RH*.

[0034] A crossbar switch circuit 10b1 that inputs a power supply level (Vdd) as a signal line RV* of the 1-input, K-output crossbar switch circuit 10b (1×K crossbar) shown in Fig. 8 and a crossbar switch circuit 10b2 that inputs a ground level (GND) as the signal line RV* are provided. The output of the crossbar switch circuit 10b1 that inputs a power supply level (Vdd) as the signal line RV* is connected to a memory input port of a multiplexer 16 configured with a PMOS 16a shown in Fig. 9. The output of the crossbar switch circuit 10b2 that inputs a ground level (GND) as the signal line RV* is connected to a memory input port of the multiplexer 16 configured with an NMOS 16b shown in Fig. 9. Then, as shown in Fig. 9, the nodes that become the final output stages of the multiplexers 16 configured with both PMOS and NMOS are connected to each other and operated complementarily as an LUT 21.

[0035] This implementation method (LUT architecture B) is configured so that the operating voltage (Vdd = 1V) is applied only to one of the switch cells in the off state. If the off resistance per switch cell is 100MΩ, the leakage current per LUT is 10nA, and in LUT architecture B, the leakage current generated by the resistance change element in the off state is halved compared to LUT architecture A. N It can be made into.

[0036] On the other hand, in LUT architecture B, the wiring resources connecting the LUT crossbar memory and the multiplexer are doubled compared to the case in Figure 6, at 2 × 2 N = 2 × K lines are required. Wiring for writing to the switch cells, such as the write control line GH and the write control line GSH, is also required twice as much, and wiring space for 2 × 3K lines must be secured in the horizontal direction. While the memory size is limited by the wiring space required for writing and reading rather than the size of the resistance change element itself, an increase in the number of wires leads to an increase in the LUT size, which is a problem. More specific embodiments of the present invention will be described below with reference to the drawings.

[0037] [First embodiment] Next, a logic integrated circuit and a reconfigurable circuit according to the first embodiment will be described with reference to Fig. 10A. Fig. 10A is a block diagram for explaining a crossbar switch circuit used as a memory for a lookup table (LUT) as an example of the logic integrated circuit and the reconfigurable circuit of this embodiment. Fig. 10B is a conceptual diagram for explaining an interface of the crossbar switch circuit of Fig. 10A.

[0038] The crossbar switch circuit 30 in FIG. 10A includes switch cells 11a, 11d, and 11g as an example of a plurality of first switch cells including resistance change elements, and switch cells 11b, 11e, and 11h as an example of a plurality of second switch cells including resistance change elements.

[0039] 10A includes control transistors 171a, 171b, and 171c as an example of first control transistors, and control transistors 172a, 172b, and 172c as an example of second control transistors. Furthermore, the crossbar switch circuit 30 of FIG. 10A includes control transistors 181a and 181b as an example of third control transistors, and control transistors 182a and 182b as an example of fourth control transistors. Note that the circuit configuration shown in FIG. 10A conceptually illustrates a portion of the configuration of the crossbar switch circuit 30, and does not represent the entire configuration. Furthermore, the crossbar switch circuit 30 for realizing a reconfigurable circuit is not limited to the number of elements and signal lines shown in FIG. 10A.

[0040] The switch cells 11a and 11b share a write control line GH[k-1] (also referred to as a first write control line), which is a wiring in the x-direction (also referred to as a first direction). The signal line RH1[k-1] is connected to one diffusion layer of the control transistor 171a connected to the switch cell 11a. The signal line RH2[k-1] is connected to one diffusion layer of the control transistor 172a connected to the switch cell 11b. The other diffusion layers of the control transistors 171a and 172a are connected to a power supply line PS[0] (also referred to as a first power supply line). The gate electrodes of the control transistors 171a and 172a are commonly connected to a write control line GSH[k-1] (also referred to as a second write control line).

[0041] The switch cells 11d and 11e share a write control line GH[k], which is an x-direction wiring. The signal line RH1[k] is connected to one diffusion layer of the control transistor 171b connected to the switch cell 11d. The signal line RH2[k] is connected to one diffusion layer of the control transistor 172b connected to the switch cell 11e. The power supply line PS[0] is connected to the other diffusion layers of the control transistors 171b and 172b. The write control line GSH[k] is commonly connected to the gate electrodes of the control transistors 171b and 172b.

[0042] The switch cells 11g and 11h share a write control line GH[k+1], which is an x-direction wiring. The signal line RH1[k+1] is connected to one diffusion layer of the control transistor 171c connected to the switch cell 11g. The signal line RH2[k+1] is connected to one diffusion layer of the control transistor 172c connected to the switch cell 11h. The power supply line PS[0] is connected to the other diffusion layers of the control transistors 171c and 172c. The write control line GSH[k+1] is commonly connected to the gate electrodes of the control transistors 171c and 172c.

[0043] The switch cells 11a, 11d, and 11g share a write control line SV[1] (also referred to as a third write control line) and a signal line RV[1], which are wirings in the y direction (also referred to as a second direction). The write control line SV[1] is connected to one diffusion layer of a control transistor 181a connected to the switch cells 11a, 11d, and 11g. A power supply line PS[1] (also referred to as a second power supply line) is connected to the other diffusion layer of the control transistor 181a. The signal line RV[1] is connected to one diffusion layer of a control transistor 182a connected to the switch cells 11a, 11d, and 11g. A power supply line PS[2] (also referred to as a third power supply line) is connected to the other diffusion layer of the control transistor 182a.

[0044] The switch cells 11b, 11e, and 11h share a write control line SV[2] and a signal line RV[2], which are wirings in the y direction. The write control line SV[2] is connected to one diffusion layer of the control transistor 181b connected to the switch cells 11b, 11e, and 11h. The other diffusion layer of the control transistor 181b is connected to a power supply line PS[1] (also referred to as a second power supply line). The signal line RV[2] is connected to one diffusion layer of the control transistor 182b connected to the switch cells 11b, 11e, and 11h. The other diffusion layer of the control transistor 182b is connected to a power supply line PS[2] (also referred to as a third power supply line).

[0045] FIG. 10B is a conceptual diagram showing an input / output interface, with a 1-input, 2K-output crossbar switch circuit 30 (1×2K crossbar) as one block. FIG. 10B illustrates a crossbar memory used for a lookup table. As shown in FIG. 10B, a signal line RV, to which a power supply level (Vdd) or a ground level (GND) is input, and a driver control line PGV are arranged on one side corresponding to the y direction. Furthermore, a signal line RH1, a write control line GH, a write control line GSH, and a power supply line PS are arranged on one side corresponding to the x direction, and a signal line RH2 is arranged on the other side. Note that the conceptual diagram of the crossbar switch circuit 10 shown in FIG. 10B is merely an example and is not limited to this.

[0046] 10A and 10B, output ports of the crossbar switch, which are examples of the first output port and the second output port, are provided at the left and right boundaries of the crossbar switch. For example, the signal lines RH1[k-1], RH1[k], and RH1[k+1] are connected to the first output port, and the signal lines RH2[k-1], RH2[k], and RH2[k+1] are connected to the second output port.

[0047] The write power supply line PS[0] running vertically in FIG. 10A serves as a power supply source shared by the switch cells 11a, 11d, and 11g provided on the left side thereof and the switch cells 11b, 11e, and 11h provided on the right side thereof.

[0048] In FIG. 10A, control transistors 171a-171c and control transistors 172a-172c are arranged symmetrically across a vertically extending power line PS[0]. Each of the control transistors 171a-c and 172a-c has one diffusion layer connected to the power line PS[0]. The horizontally aligned control transistors 171a and 172a are connected to the same write control line GSH[k-1], the horizontally aligned control transistors 171b and 172b are connected to the same write control line GSH[k], and the horizontally aligned control transistors 171c and 172c are connected to the same write control line GSH[k+1]. The gate line of the control transistor 181a, which controls the write power line from the power line PS[1], and the gate line of the control transistor 182a, which controls the write power line from the power line PS[2], are also connected to the same write control line PSV[1]. The gate line of the control transistor 181b that controls the write power supply line from the power supply line PS[1] and the gate line of the control transistor 182b that controls the write power supply line from the power supply line PS[2] are also connected to the same write control line PSV[2]. Sharing the gate lines of the control transistors is desirable in terms of reducing the number of wirings, but this embodiment is not necessarily limited to this.

[0049] 10A and 10B, either the power supply level (Vdd) or the ground level (GND) is input to the crossbar switch. When the input is the power supply level (Vdd), the output from the crossbar switch circuit 30 is controlled to be either Vdd or a high resistance state (high impedance state: Hi-Z). When the input is the ground level (GND), the output is controlled to be either GND or a high resistance state (high impedance state: Hi-Z).

[0050] As shown in Fig. 11(a), the lookup table 32 may include, for example, a crossbar switch circuit 30 and a multiplexer 31b as shown in Fig. 10A, and as shown in Fig. 11(b), the reconfigurable circuit may include the crossbar switch circuit 30 as shown in Fig. 10A. Also, as shown in Fig. 11(c), an integrated circuit 70 may include a reconfigurable circuit 71 configured according to the above-described embodiment and an arithmetic circuit 72 that is not reconfigurable but is capable of signal processing functions, and the reconfigurable circuit 71 and the arithmetic circuit 72 may transmit and receive signals to and from each other via a signal switching unit 73.

[0051] The lookup table 32 (LUT32) of FIG. 12 includes a crossbar switch circuit 30a which is one form of the crossbar switch circuit 30 of FIG. 10B, a multiplexer 31a which is composed of a plurality of PMOS switches 311a, a multiplexer 31b which is composed of a plurality of NMOS switches 311b, and a crossbar switch circuit 30b which is one form of the crossbar switch circuit 30 of FIG. 10B.

[0052] The multiplexer 31a is configured with a plurality of PMOS switches 311a, and in FIG. 12, six PMOS switches 311a are included. N The data is selected and output according to the input signal to the LUT32.

[0053] The multiplexer 31b is configured with a plurality of NMOS switches 311b, and in FIG. 12, six NMOS switches 311b are included. N The LUT 32 selects and outputs one of these pieces of data according to the input signal to the LUT 32. In Fig. 12, the PMOS switch 311a at the output stage of the multiplexer 31a and the NMOS switch 311b at the output stage of the multiplexer 31b are connected to form the output node OUT.

[0054] As shown in Figure 12, the lookup table 32 (LUT32) has input ports arranged separately on the left and right for PMOS and NMOS, respectively. The input of the multiplexer 31a in Figure 12 is connected to the output port of the crossbar switch circuit 30a arranged on the left side. The input of the multiplexer 31b in Figure 12 is connected to the output port of the crossbar switch circuit 30b arranged on the right side. The input signal to the gate of the PMOS switch 311a of the multiplexer 31a of the LUT32 and the input signal to the gate of the NMOS switch 311b of the multiplexer 31b are related to each other, and one conduction path is selected from the left and right for each set of gate input signals to the LUT32.

[0055] When the switch cell connected to the source of the PMOS side in two crossbars connected to both ends of one conduction path is turned on to output Vdd, the switch cell in the crossbar connected to the drain of the opposite NMOS side is turned off to output a high resistance state (high impedance state: Hi-Z).

[0056] As a result, the Vdd level can be output at the output node OUT where the source and drain of the PMOS switch 311a at the final stage of the multiplexer 31a in the LUT 32 and the NMOS switch 311b at the final stage of the multiplexer 31b are connected to each other.

[0057] Conversely, when the switch cell in the crossbar switch connected to the source of the PMOS switch 311a is turned off to output a high impedance state (Hi-Z), the switch cell in the crossbar switch connected to the drain of the opposite NMOS switch 311b is turned on to output GND, which allows the GND level to be output at the output node OUT where the sources and drains of the NMOS switch 311b and PMOS switch 311a in the LUT 32 are connected to each other.

[0058] In this way, by rewriting the switch cells on the path selected for each set of gate input signals to the LUT 32 while paying attention to the complementarity described above, the LUT 32 can execute a desired logical operation.

[0059] 13 is a table showing a comparison of the number of wirings and leakage currents of an LUT using a crossbar switch circuit according to the architecture of this embodiment, the aforementioned LUT architecture A, and the aforementioned LUT architecture B. In particular, the table shows a comparison of the number of wirings required vertically and horizontally, including the signal lines and write lines of M N-input LUTs in a CLB, and the leakage current caused by the resistance change elements in the OFF state. In the case of this embodiment, since the operating voltage is applied to only one switch cell in the OFF state, the leakage current is reduced to half that of LUT architecture A. N Furthermore, the number of Vdd and GND wirings can be reduced, and the output nodes from each crossbar switch for the LUT memory can be input to adjacent LUTs, so signal lines do not run in parallel unnecessarily. This reduces the wiring space required to alleviate wiring congestion, and also reduces the circuit area.

[0060] Second Embodiment Next, a logic integrated circuit and a reconfigurable circuit according to a second embodiment will be described with reference to FIG. 14. In the first embodiment, a crossbar switch circuit used as a memory for a look-up table (LUT) was described as an example of a logic integrated circuit and a reconfigurable circuit. However, the present invention is not limited to the logic integrated circuit and the reconfigurable circuit of the first embodiment having the above-described configuration. For example, the multiplexers 31a and 31b constituting the LUT 32 of the embodiment shown in FIG. 12 are not limited to this.

[0061] 14 is a block diagram showing another example of a multiplexer constituting the LUT 32 of the embodiment. In FIG. 12, the source and drain of the PMOS switch 311a and the NMOS switch 311b are connected to an output node OUT. A PMOS switch 321a and an NMOS switch 321b are interposed between the output node OUT and the PMOS switch 311a or the NMOS switch 311b. As shown in FIG. 14, a multiplexer 31c includes multiple PMOS switches 311a, and one PMOS switch 321a is connected between the PMOS switch 311a and the output node OUT. A multiplexer 31d includes multiple NMOS switches 311b, and one PMOS switch 321b is connected between the NMOS switch 311b and the output node OUT.

[0062] 14, by controlling the two gate voltages of the PMOS switch 321a and NMOS 321b when writing to the switch cell, it is possible to prevent the write voltage or write current from flowing between different crossbar switch circuits via the signal transmission path of the lookup table. In other words, it is possible to suppress current and voltage interference between crossbars when writing to the switch cell in the crossbar switch.

[0063] Third Embodiment Next, a logic integrated circuit and a reconfigurable circuit according to a third embodiment will be described with reference to FIG. 15. In the first embodiment, a crossbar switch circuit used as a memory for a look-up table (LUT) was described as an example of a logic integrated circuit and a reconfigurable circuit. This embodiment is an application example using the crossbar switch circuit of the first embodiment. FIG. 15 is a block diagram for explaining an example of implementing M LUTs. It is also possible to arrange multiple LUTs of the first embodiment adjacent to each other. FIG. 15 shows an example of a logic integrated circuit and a reconfigurable circuit in which M LUTs (LUT[0], LUT[1], ...) are cascade-connected.

[0064] The logic integrated circuit and reconfigurable circuit of Fig. 15 include crossbar switch circuits 40a, 40b, and 40c, which are one form of the 1-input, 2K-output crossbar switch circuit 30 (1 x 2K crossbar) of the first embodiment described above, and multiplexers 41a and 41b (MUX41a, 41b) arranged between the crossbar switch circuits. In the crossbar switch circuits 40a and 40c, Vdd is applied to the signal line RV. In the crossbar switch circuit 40b, GND is applied to the signal line RV.

[0065] The multiplexer 41a selects and outputs the output from the second output port of the crossbar switch circuit 40a. The multiplexer 41b selects and outputs the output from the second output port of the crossbar switch circuit 40b. The crossbar switch circuit 40a and the multiplexer 41a form an LUT[0], and the crossbar switch circuit 40a and the multiplexer 41a form an LUT[1].

[0066] [Fourth embodiment] Next, a logic integrated circuit and a reconfigurable circuit according to a fourth embodiment will be described with reference to Fig. 16. In the first embodiment, a crossbar switch circuit used as a memory for a look-up table (LUT) was described as an example of a logic integrated circuit and a reconfigurable circuit. This embodiment is an application example using the crossbar switch circuit of the first embodiment. Fig. 16 shows an example in which an output port on the side not used as the LUT memory side of the crossbar switch circuit of the embodiment is connected to an output port of a separately prepared crossbar switch circuit.

[0067] The logic integrated circuit and reconfigurable circuit of FIG. 16 include a crossbar switch circuit 50a, which is one form of the 1-input, 2K-output crossbar switch circuit 30 (1×2K crossbar) of the first embodiment described above, and a multiplexer 51a configured with a plurality of PMOS switches 511a. The logic integrated circuit and reconfigurable circuit of FIG. 16 further include a CMOS switch 52 and a 1-input, 1K-output crossbar switch circuit 50b (1×1K crossbar). The crossbar switch circuit 50a outputs K data lines from a second output port, and the multiplexer 51a selects and outputs these to form a lookup table (LUT). In the crossbar switch circuit 50a, Vdd is applied to the signal line RV. In the crossbar switch circuit 50b, GND is applied to the signal line RV.

[0068] In this embodiment, a first output port that is not used as a crossbar memory for the LUT, separate from the second output port that constitutes part of the LUT of the crossbar switch circuit 50a, is utilized. In this way, a memory circuit for setting parameters can be configured by interconnecting the output port of a separately prepared crossbar switch circuit 50b and the first output port of the crossbar switch circuit 50a via a CMOS switch 52. With this configuration, it is possible to effectively utilize the unused output port (first output port) of the crossbar switch circuit 40a located at the end, as shown in FIG. 15.

[0069] Fifth Embodiment Next, an integrated circuit including a logic integrated circuit and a reconfigurable circuit according to the fifth embodiment will be described with reference to Fig. 17. Fig. 17 is a block diagram for explaining a large scale logic integrated circuit in which reconfigurable circuits including LB and RB are arranged on tiles, and the write control lines in each crossbar are shared to eliminate redundant wiring.

[0070] 17, a larger-scale integrated circuit 60 can be configured by arranging and interconnecting multiple reconfigurable circuits 61 (CLBs: Configurable Logic Blocks). Each reconfigurable circuit 61 includes a routing block 61a (RB61a) and a logic block 61b (LB61b) having an LUT and memory. Such reconfigurable circuits 61 are arranged on tiles, and the write control lines within each crossbar are shared.

[0071] [Comparative example and its operation] 18 and 19, a logic integrated circuit and a reconfigurable circuit will be described as a comparative example (Japanese Patent No. 6908120) of the first embodiment. The logic integrated circuit of this comparative example has different configurations of first control transistors 171a-171c and second control transistors 172a-172c. Specifically, the first control transistors 171a-171c aligned in the y direction are connected to the same write control line PGV[1], and the second control transistors 172a-172c aligned in the y direction are connected to the same write control line PGV[2].

[0072] In the logic integrated circuit and reconfigurable circuit of this comparative example, the number of wires can be reduced compared to LUT architecture A and LUT architecture B. However, as will be explained in FIG. 19, there is a problem that writing cannot be performed correctly because so-called sneak paths occur.

[0073] Specifically, consider the case where, for example, when resistive change elements RE[1], RE[2], and RE[3] are ON and a write operation is performed on RE[4], a write voltage VSET, a ground voltage GND, and a high impedance HZ are applied to power supply lines PS[0], PS[1], and PS[2], respectively. A low voltage ("0") is applied to write control line GH[k+1], a high voltage ("1") is applied to write control line GH[k], and a high voltage ("1") is applied to write control line PGV[1]. At this time, a sneak path is created in which current flows from control transistor 171c to resistive change elements RE[2], RE[1], and RE[3] in this order. As a result, both ends of resistive change element RE[4] reach the same potential VSET, preventing write operation. This occurs because control transistors 171a to 171c, which are aligned in the y direction, are simultaneously in a conductive state. In the first embodiment, the control transistors 171a to 171c and 172a to 172c are connected to the write control line GSH extending in the x-direction, so that such sneak paths can be avoided and the number of connection wires can be reduced.

[0074] Other Embodiments Although the preferred embodiments have been described above, the present invention is not limited to these embodiments.

[0075] Furthermore, if necessary, a synchronous circuit such as a DFF may be included in the logic block (LB) of the reconfigurable circuit, and the setting memory described in the fourth embodiment above may be used as an input signal to the selector to select synchronous or asynchronous signals.

[0076] Input / output signals between each LB may be connected via a routing block (RB) implemented by a crossbar, as shown in Figure 17. The crossbar circuit shown in Figure 4 is preferably implemented using the same resistance change elements for the RB. By constructing the desired signal paths, a reconfigurable circuit capable of performing larger-scale logical operations may be constructed. Note that multiple crossbars can use common write control lines to improve the efficiency of control signal lines.

[0077] As shown in Figure 1, input / output signals between each LB are connected via a routing block (RB). By constructing the desired signal path, it is possible to build a reconfigurable circuit that can perform larger-scale logical operations. The RBs are implemented as crossbar circuits using the same resistive change elements. As shown in Figure 17, when CLBs consisting of some LBs and RBs are arranged in a repeated fashion, each CLB contains a crossbar circuit, but the control signal lines for writing to the switch cells in these crossbar circuits are shared between the CLBs.

[0078] The resistance change element used in the switch cell may be a resistance change element whose resistance state changes and is maintained when a voltage above a certain level is applied for a predetermined period of time, such as ReRAM (Resistance Random Access Memory) using transition metal oxides or NanoBridge (a registered trademark of NEC Corporation) using ion conductors. Furthermore, from the viewpoint of high resistance to disturbance when signals are continuously passed through the element, the resistance change element is a bipolar type resistance change element whose polarity is in the direction of the voltage applied to change the resistance. A more desirable configuration is one in which two bipolar type resistance change elements are connected in series facing each other, with a switch (transistor) located at the junction of the two switches.

[0079] The present invention has been described above using the above-described embodiments as exemplary examples. However, the present invention is not limited to the above-described embodiments. In other words, the present invention can be applied in various aspects that can be understood by a person skilled in the art within the scope of the present invention. [Explanation of symbols]

[0080] 11a, 11b, 11d, 11e, 11g, 11h...Switch cells 171a to 171c, 172a to 172c, 181a, 181b, 182a, 182b...control transistors 30, 40a, 40b, 40c, 50a, 50b...Crossbar switch circuit 31, 31a, 31b, 31c, 31d, 41a, 41b, 51a...Multiplexer 32...Lookup table 52...CMOS switch 60, 70... Integrated circuits 61, 71... Reconfiguration circuit 61a...Routing block 61b...Logical block 72...Arithmetic circuit 73...Signal switching section

Claims

1. A logic operation circuit having a plurality of first switch cells including a resistance change element and a plurality of second switch cells including a resistance change element, a first output port and a second output port; a plurality of first wirings (RH1) arranged along a first direction and connected to the first output port; a plurality of second wirings (RH2) arranged along the first direction and connected to the second output port; a plurality of first write control lines (GH) arranged along the first wiring and the second wiring; a plurality of second write control lines (GSH) arranged along the first wiring and the second wiring; a plurality of third wirings (RVs) arranged along the second direction; a plurality of third write control lines (SV) arranged along the third wiring; the plurality of first switch cells, which are arranged at intersections of the first wiring and the third wiring, have one control terminal connected to the first write control line (GH) and the other control terminal connected to the third write control line (SV), and switch electrical connections between the first wiring and the third wiring; the plurality of second switch cells, which are arranged at intersections of the second wiring and the third wiring, have one control terminal connected to the first write control line (GH) and the other control terminal connected to the third write control line (SV), and switch electrical connections between the second wiring and the third wiring; a first control transistor (171a-c) connected to the first wiring (RH1) and configured to switch an electrical connection between the first wiring and a first power supply line (PS[0]) that supplies power to the first wiring (RH1), and the first wiring, the gate of which is connected to the second write control line; a second control transistor (172a-c) connected to the second wiring (RH2) and configured to switch an electrical connection between the first power supply line (PS[0]) that supplies power to the second wiring (RH2) and the second wiring, the gate of which is connected to the second write control line; a third control transistor (181 a, b) connected to the third write control line (SV) and switching an electrical connection between the third write control line and a second power supply line (PS[1]) that supplies power to the third write control line; a fourth control transistor (182a, b) connected to the third wiring (RV) and switching an electrical connection between the third wiring and a third power supply line (PS[2]) that supplies power to the third wiring (RV); Including, a logic operation circuit, wherein the first control transistor and the second control transistor arranged in the first direction are connected to the same second write control line via gates;

2. 10. A lookup table comprising: a crossbar memory including the logical operation circuit according to claim 1; and a multiplexer that selects and outputs an output from the first output port or the second output port of the crossbar memory.

3. 3. The lookup table according to claim 2, comprising a plurality of logic operation circuits according to claim 1, a lookup table including: a plurality of switches for selecting an output from the first output port of one of the logic operation circuits, the plurality of switches being transistors of a first conductivity type; a plurality of switches for selecting an output from the second output port of another of the logic operation circuits, the plurality of switches being transistors of a second conductivity type; and an output node derived from a switch in an output stage of the plurality of switches of transistors of the first conductivity type and a switch in an output stage of the plurality of switches of transistors of the second conductivity type.

4. 4. The lookup table of claim 3, a first conductivity type transistor switch inserted between a switch of an output stage of the plurality of switches of the first conductivity type transistors and the output node, and a second conductivity type transistor switch inserted between a switch of an output stage of the plurality of switches of the second conductivity type transistors and the output node.

5. 3. The lookup table of claim 2, The first output port or the second output port that is not selected by the multiplexer that selects the output from the first output port or the second output port is a lookup table that outputs data for parameter setting.

6. A reconfiguration circuit comprising: a first crossbar memory including the logic operation circuit of claim 1; a second crossbar memory including the logic operation circuit of claim 1; and a multiplexer that selects an output from a first output port of the first crossbar memory and outputs the selected output to a second output port of the second crossbar memory.

7. 10. An integrated circuit comprising a plurality of the logic operation circuits according to claim 1, the lookup tables according to claim 2, or the reconfigurable circuits according to claim 6, which are interconnected.

8. a logic operation circuit according to claim 1, a lookup table according to claim 2, or a reconfiguration circuit according to claim 6; and an arithmetic circuit that is not reconfigurable but is capable of signal processing functions; An integrated circuit in which the logic operation circuit, the look-up table, or the reconfiguration circuit and the operation circuit capable of signal processing function transmit and receive signals to and from each other via a signal switching unit.

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