Semiconductor memory device
The semiconductor memory device with vertical channel transistors and a layered structure enhances integration density and electrical performance, overcoming the limitations of two-dimensional devices by optimizing layer configurations.
Patent Information
- Application Number
- JP2024207883
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-03-07
- Filing Date
- 2024-11-29
- Publication Date
- 2025-09-19
AI Technical Summary
The integration density of two-dimensional semiconductor memory devices is limited by the area occupied by unit memory cells and requires expensive fine patterning technology, hindering cost-effective high-density semiconductor memory development.
The semiconductor memory device incorporates vertical channel transistors with a specific layer structure comprising bit lines, etch stop layers, mold insulating structures, metal oxide patterns, and word lines, which include multiple insulating layers with opposing surfaces to enhance integration density and electrical characteristics.
The proposed structure increases integration density and improves electrical performance, addressing the limitations of traditional two-dimensional devices while reducing manufacturing costs.
Smart Images
Figure 2025137378000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to semiconductor memory devices, and more particularly to semiconductor memory devices including vertical channel transistors (VCTs). [Background technology]
[0002] In order to achieve both the superior performance and low price desired by consumers, it is necessary to increase the integration density of semiconductor memory devices. Since integration density is an important factor in determining the price of semiconductor memory devices, a particularly high integration density is required.
[0003] In two-dimensional (2D) or planar semiconductor memory devices, the integration density is primarily determined by the area occupied by a unit memory cell and is greatly affected by the level of fine patterning technology. However, because pattern miniaturization requires extremely expensive equipment, the integration density of two-dimensional semiconductor memory devices is still limited, even though it has increased. Therefore, semiconductor memory devices including vertical channel transistors, in which the channel extends vertically, have been proposed. Summary of the Invention [Problem to be solved by the invention]
[0004] SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having improved integration density and electrical characteristics.
[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned here will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]
[0006] In one aspect of the present invention, a semiconductor memory device includes, on a substrate, bit lines extending in a first direction; an etch stop layer disposed on the bit lines; a mold insulating structure layer disposed on the etch stop layer and including a channel trench extending in a second direction; a metal oxide pattern disposed on the bit lines and extending along sidewalls of the channel trench; word lines disposed on the metal oxide pattern and extending in the second direction; and an information storage pattern disposed on the metal oxide pattern and connected to the metal oxide pattern, wherein the mold insulating structure layer includes a first mold insulating layer on the etch stop layer and a second mold insulating layer on the first mold insulating layer, the second mold insulating layer having top and bottom surfaces opposite each other in a third direction, the bottom surface of the second mold insulating layer facing the bit lines, and a height from a top surface of the bit lines to a top of the metal oxide pattern is greater than a height from a top surface of the bit lines to a top surface of the second mold insulating layer.
[0007] Another aspect of the semiconductor memory device of the present invention for solving the above problems includes, on a substrate, bit lines extending in a first direction; an etch stop layer disposed on the bit lines; a mold insulating structure layer disposed on the etch stop layer and including a channel trench extending in a second direction; a metal oxide pattern disposed on the bit lines and extending along sidewalls of the channel trench; word lines disposed on the metal oxide pattern and extending in the second direction; and an information storage pattern disposed on the metal oxide pattern and connected to the metal oxide pattern, wherein the mold insulating structure layer includes a first mold insulating layer, a second mold insulating layer, and a third mold insulating layer sequentially disposed on the etch stop layer, the second mold insulating layer being disposed between the first mold insulating layer and the third mold insulating layer, the second mold insulating layer having top and bottom surfaces opposite in a third direction, the bottom surface of the second mold insulating layer facing the bit lines, and a height from a top surface of the bit lines to a top of the metal oxide pattern being greater than a height from a top surface of the bit lines to a bottom surface of the second mold insulating layer.
[0008] Another aspect of the semiconductor memory device of the present invention for solving the above problem includes, on a substrate, bit lines extending in a first direction, first and second metal oxide patterns disposed on the bit lines and spaced apart in the first direction, a mold insulating structure film disposed on the bit lines and between the first and second metal oxide patterns, first word lines disposed on the first metal oxide patterns and extending in a second direction, a second word line disposed on the second metal oxide patterns and extending in the second direction, and a metal oxide layer disposed on the first and second metal oxide patterns and spaced apart in the first direction. and an information storage pattern connected to the second metal oxide pattern, the mold insulating structure film including a first mold insulating film, a second mold insulating film, and a third mold insulating film sequentially arranged on the bit line, the second mold insulating film being arranged between the first mold insulating film and the third mold insulating film, the second mold insulating film and the third mold insulating film having top and bottom surfaces opposite to each other in a third direction, the top surface of the second mold insulating film facing the bottom surface of the third mold insulating film, and a width of the top surface of the second mold insulating film in the first direction greater than a width of the bottom surface of the third mold insulating film in the first direction.
[0009] Other specific features of the present invention are included in the detailed description and drawings. [Brief explanation of the drawings]
[0010] [Figure 1] 1 is a layout diagram illustrating a semiconductor memory device according to some embodiments. [Figure 2] FIG. 2 is a cross-sectional view taken along the lines AA and BB in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along lines CC and DD in FIG. [Figure 4] FIG. 3 is an enlarged view of part P in FIG. 2. [Figure 5] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 6]1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 7] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 8] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 9] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 10] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 11] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 12] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 13] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 14] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 15] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 16] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 17] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 18] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 19] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 20] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 21] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 22] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 23] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 24] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 25] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 26] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 27] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 28] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 29] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 30] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 31] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 32] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 33] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 34] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 35] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 36] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. [Figure 37] 1A to 1C are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION
[0011] In this specification, terms such as "first" and "second" are used to describe various elements or components, but these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, a first element or component referred to below may of course be a second element or component within the technical concept of the present invention.
[0012] Figure 1 is a layout diagram illustrating a semiconductor memory device according to some embodiments. Figure 2 is a cross-sectional view taken along lines AA and BB in Figure 1. Figure 3 is a cross-sectional view taken along lines CC and DD in Figure 1. Figure 4 is an enlarged view of part P in Figure 2.
[0013] A semiconductor memory device according to an embodiment of the present invention may include a memory cell including a vertical channel transistor (VCT).
[0014] 1 to 4, a semiconductor memory device according to some embodiments may include a substrate 100, a peripheral gate structure PG, a bit line BL, a word line WL, an oxide pattern structure AP, a mold insulating structure film 120, and an information storage pattern DSP.
[0015] The substrate 100 may be a silicon substrate 100 or may include other materials such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.
[0016] The peripheral gate structure PG is disposed on a substrate 100. The substrate 100 may include a cell array region and a peripheral circuit region. The peripheral gate structure PG is disposed across the cell array region and the peripheral circuit region. In other words, a portion of the peripheral gate structure PG is disposed in the cell array region of the substrate 100, and the remainder of the peripheral gate structure PG is disposed in the peripheral circuit region of the substrate 100.
[0017] The peripheral gate structure PG may include a sensing transistor, a transfer transistor, a driving transistor, etc. It goes without saying that the types of transistors arranged in the cell array region and the peripheral circuit region vary depending on the design layout of the semiconductor memory device.
[0018] The peripheral gate structure PG may include a peripheral gate insulating film 215, a peripheral lower conductive pattern 223, and a peripheral upper conductive pattern 225. The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high-k insulating film having a higher dielectric constant than a silicon oxide film, or a combination thereof. The high-k insulating film may include, but is not limited to, at least one of a metal oxide, a metal oxynitride, a metal silicon oxide, and a metal silicon oxynitride.
[0019] The peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may each include a conductive material. For example, the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may each include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, a metal, and a metal alloy. The peripheral gate structure PG is illustrated as including a plurality of conductive patterns, but is not limited thereto.
[0020] In some embodiments of the semiconductor memory device, the two-dimensional material may be a metal material and / or a semiconductor material. The two-dimensional material may include a two-dimensional allotrope or a two-dimensional compound, such as, but not limited to, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). In other words, the above-mentioned two-dimensional materials are merely listed as examples, and the two-dimensional materials that may be included in the semiconductor memory device of the present invention are not limited to the above-mentioned materials.
[0021] The first peripheral lower insulating film 227 and the second peripheral lower insulating film 228 are disposed on the substrate 100. The first peripheral lower insulating film 227 and the second peripheral lower insulating film 228 are each made of an insulating material. The first peripheral wiring line 241a and the peripheral contact plug 241b are disposed in the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228. Although the first peripheral wiring line 241a and the peripheral contact plug 241b are illustrated as being different films, they are not limited to this. The boundary between the first peripheral wiring line 241a and the peripheral contact plug 241b does not have to be distinct. The first peripheral wiring line 241a and the peripheral contact plug 241b each include a conductive material.
[0022] The first peripheral upper insulating film 261 and the second peripheral upper insulating film 262 are disposed on the first peripheral wiring line 241a and the peripheral contact plug 241b, respectively. The first peripheral upper insulating film 261 and the second peripheral upper insulating film 262 are made of an insulating material.
[0023] The second peripheral wiring line 243 and the peripheral via plug 242 are disposed on the first peripheral wiring line 241a. The peripheral via plug 242 is disposed in the first peripheral upper insulating film 261. The second peripheral wiring line 243 is disposed in the second peripheral upper insulating film 262.
[0024] The second peripheral wiring line 243 and the peripheral via plug 242 may be connected to the first peripheral wiring line 241a. The peripheral via plug 242 may connect the first peripheral wiring line 241a and the second peripheral wiring line 243. The second peripheral wiring line 243 and the peripheral via plug 242 each include a conductive material. Although the second peripheral wiring line 243 and the peripheral via plug 242 are shown to be made of different layers, this is not limiting. The boundary between the second peripheral wiring line 243 and the peripheral via plug 242 does not need to be distinct.
[0025] The third peripheral upper insulating film 263, the fourth peripheral upper insulating film 264, and the fifth peripheral upper insulating film 265 are sequentially disposed on the second peripheral wiring line 243. The third peripheral upper insulating film 263, the fourth peripheral upper insulating film 264, and the fifth peripheral upper insulating film 265 are each made of an insulating material.
[0026] The fourth peripheral upper insulating film 264 is made of a different insulating material from the third peripheral upper insulating film 263 and the fifth peripheral upper insulating film 265. For example, the fourth peripheral upper insulating film 264 is made of an oxide-based insulating material, and the third peripheral upper insulating film 263 and the fifth peripheral upper insulating film 265 are made of a nitride-based insulating material, but the materials are not limited thereto.
[0027] The cell connecting plug 244 is disposed in the third peripheral upper insulating film 263, the fourth peripheral upper insulating film 264, and the fifth peripheral upper insulating film 265. The cell connecting plug 244 may be connected to the second peripheral wiring line 243. The cell connecting plug 244 includes a conductive material. Unlike the illustration, the cell connecting plug 244 may be disposed in the peripheral upper insulating films 261, 262, 263, 264, and 265, each of which is a single layer.
[0028] The bit lines BL are disposed on the peripheral gate structures PG. More specifically, the bit lines BL are disposed on the fifth peripheral upper insulating film 265. For example, the bit lines BL may be in contact with the fifth peripheral upper insulating film 265.
[0029] The bit lines BL may extend longitudinally in the second direction D2. Adjacent bit lines BL may be spaced apart in the first direction D1. The bit lines BL include long sidewalls extending in the second direction D2 and short sidewalls extending in the first direction D1.
[0030] Although not shown in the drawing, each bit line BL may extend from the cell array region to the peripheral circuit region, and an end of each bit line BL may be disposed on the peripheral circuit region of the substrate 100.
[0031] Each bit line BL is disposed on the cell connecting plug 244. Each bit line BL may be connected to the cell connecting plug 244. Each bit line BL may include, for example, at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal, and a metal alloy. Each bit line BL is illustrated as being a single layer, but is not limited thereto.
[0032] The cell lower insulating layer 131 is disposed on the fifth peripheral upper insulating layer 265. The cell lower insulating layer 131 is disposed between the bit lines BL spaced apart in the first direction D1. The cell lower insulating layer 131 is made of an insulating material.
[0033] The mold insulating structure layer 120 is disposed on the bit lines BL and the cell lower insulating layer 131. The etching stop layer 130 is disposed between the mold insulating structure layer 120 and the cell lower insulating layer 131.
[0034] The mold insulating structure film 120 may include a first mold insulating film 121, a second mold insulating film 122, and a third mold insulating film 123.
[0035] The first mold insulating film 121, the second mold insulating film 122, and the third mold insulating film 123 are sequentially arranged on the bit line BL. The first mold insulating film 121, the second mold insulating film 122, and the third mold insulating film 123 may extend in the first direction D1.
[0036] The second mold insulating film 122 is disposed between the first mold insulating film 121 and the third mold insulating film 123. The second mold insulating film 122 may include a top surface 122US and a bottom surface 122BS of the second mold insulating film that are opposite to each other in the third direction D3. The bottom surface 122BS of the second mold insulating film faces the bit line BL.
[0037] The second mold insulating film 122 is disposed on the first mold insulating film 121. The third mold insulating film 123 is disposed on the second mold insulating film 122. The top surface of the first mold insulating film 121 may contact the bottom surface 122BS of the second mold insulating film. The top surface 122US of the second mold insulating film may contact the bottom surface 123BS of the third mold insulating film. For example, the height H5 from the top surface BL_US of the bit line to the bottom surface 122BS of the second mold insulating film may be smaller than the height from the top surface BL_US of the bit line to the bottom surface 123BS of the third mold insulating film.
[0038] The first mold insulating film 121 is disposed on the etching stop layer 130. For example, the etching stop layer 130 is disposed between the first mold insulating film 121 and the bit line BL and the cell lower insulating film 131.
[0039] 4, the width 122US_W1 of the top surface 122US of the second mold insulating film in the second direction D2 may be larger than the width 123BS_W1 of the bottom surface 123BS of the third mold insulating film in the second direction D2. In other words, between oxide pattern structures AP adjacent in the second direction D2, the width 122US_W1 of the top surface 122US of the second mold insulating film in the first direction D1 may be larger than the width 123BS_W1 of the bottom surface 123BS of the third mold insulating film in the first direction D1. The second mold insulating film 122 and the third mold insulating film 123 may have a "T" shape rotated 180 degrees.
[0040] The mold insulating structure film 120 and the etch stop film 130 are each made of an insulating material. The first mold insulating film 121 and the second mold insulating film 122 may each contain different materials. The first mold insulating film 121 may contain a silicon oxide-based insulating material, for example, silicon oxide. The second mold insulating film 122 may contain a silicon nitride-based insulating material, for example, silicon nitride. The third mold insulating film 123 may contain the same material as the first mold insulating film 121.
[0041] The etch stop layer 130 may include a material having an etching selectivity with respect to the mold insulating structure layer 120. For example, the etch stop layer 130 may include an insulating material having an etching selectivity with respect to the first mold insulating layer 121.
[0042] The mold insulating film 120 may include a plurality of channel trenches CH_T. Each channel trench CH_T may extend longitudinally in a first direction D1. Adjacent channel trenches CH_T may be spaced apart in a second direction D2. Each channel trench CH_T intersects with a bit line BL. One channel trench CH_T may expose a plurality of bit lines BL adjacent to each other in the first direction D1.
[0043] The bottom surface of each channel trench CH_T may be defined by the bit line BL and the cell lower insulating film 131. The sidewalls of each channel trench CH_T may be defined by the mold insulating structure film 120 and the etch stop film 130. The sidewalls of the channel trench CH_T may be the sidewalls of the mold insulating structure film 120 and the sidewalls of the etch stop film 130. For example, the sidewalls of the channel trench CH_T may be the sidewalls of the etch stop film 130, the sidewalls of the first mold insulating film 121, and the sidewalls of the second mold insulating film 122.
[0044] An oxide pattern structure AP is disposed on each bit line BL. Multiple oxide pattern structures AP may be connected to one bit line BL. Multiple oxide pattern structures AP disposed on one bit line BL may be spaced apart in the second direction D2.
[0045] The oxide pattern structure AP is disposed in a channel trench CH_T extending in a first direction D1. A plurality of oxide pattern structures AP are disposed in one channel trench CH_T. The plurality of oxide pattern structures AP disposed in the channel trench CH_T may be spaced apart in the first direction D1.
[0046] For example, the oxide pattern structure AP may be arranged two-dimensionally along a first direction D1 and a second direction D2 that intersect with each other.
[0047] The oxide pattern structure AP may include a first metal oxide pattern AP1, a second metal oxide pattern AP2, and a third metal oxide pattern AP3. The third metal oxide pattern AP3 may connect the first metal oxide pattern AP1 and the second metal oxide pattern AP2. The first metal oxide pattern AP1 and the second metal oxide pattern AP2 may be spaced apart in a second direction D2.
[0048] The first metal oxide pattern AP1, the second metal oxide pattern AP2, and the third metal oxide pattern AP3 are disposed on the bit line BL. The first metal oxide pattern AP1, the second metal oxide pattern AP2, and the third metal oxide pattern AP3 may be connected to the bit line BL. The first metal oxide pattern AP1, the second metal oxide pattern AP2, and the third metal oxide pattern AP3 may contact the top surface BL_US of the bit line BL.
[0049] The oxide pattern structure AP may extend along the sidewalls and bottom surface of the channel trench CH_T. In cross-sectional views such as those in Figures 2 and 4, the oxide pattern structure AP may have a "U" shape. For example, the third metal oxide pattern AP3 may extend along the bottom surface of the channel trench CH_T, and the first metal oxide pattern AP1 and the second metal oxide pattern AP2 may extend along a portion of the bottom surface of the channel trench CH_T and the sidewalls of the channel trench CH_T.
[0050] The oxide pattern structure AP may include a first oxide pattern structure AP and a second oxide pattern structure AP adjacent in the second direction D2, and the mold insulating structure film 120 is disposed between the first oxide pattern structure AP and the second oxide pattern structure AP adjacent in the second direction D2.
[0051] For example, the mold insulating structure film 120 is disposed between the first metal oxide pattern AP1 of the first oxide pattern structure AP and the second metal oxide pattern AP2 of the second oxide pattern structure AP. For example, the first metal oxide pattern AP1 and the second metal oxide pattern AP2 may be in contact with the mold insulating structure film 120. Specifically, parts of the oxide pattern structure AP may be in contact with the etch stop film 130, the first mold insulating film 121, and the second mold insulating film 122.
[0052] 4, the topmost portion AP_UUS of the oxide pattern structure may be the topmost portion of the first metal oxide pattern AP1. The topmost portion AP_UUS of the oxide pattern structure may be the topmost portion of the second metal oxide pattern AP2. A height H1 from the top surface BL_US of the bit line to the topmost portion AP_UUS of the oxide pattern structure may be greater than a height H5 from the top surface BL_US of the bit line to the bottom surface 122BS of the second mold insulating film. A height H1 from the top surface BL_US of the bit line to the topmost portion AP_UUS of the oxide pattern structure may be greater than a height H2 from the top surface BL_US of the bit line to the top surface 122US of the second mold insulating film. For example, a portion of the oxide pattern structure AP protruding in the third direction D3 from the top surface 122US of the second mold insulating film may not contact the third mold insulating film 123.
[0053] In some embodiments of the semiconductor memory device, the oxide pattern structure AP may include an oxide semiconductor material. The oxide pattern structure AP may include, for example, one of indium gallium zinc oxide (IGZO), impurity-doped indium zinc oxide (IZO), indium oxide (InO), zinc oxide (ZnO), gallium oxide (GaO), tin oxide (SnO), aluminum zinc oxide (AZO), and indium tin oxide (ITO). In the impurity-doped indium zinc oxide (IZO), the doped impurity may include at least one of magnesium (Mg), strontium (Sr), barium (Ba), scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), tin (Sn), and tantalum (Ta).
[0054] The IGZO (indium gallium zinc oxide) included in the oxide pattern structure AP may be Ga-rich IGZO, In-rich IGZO, or IGZO (In:Ga:Zn=1:1:1). Ga-rich IGZO has a higher gallium ratio than IGZO (In:Ga:Zn=1:1:1) and a lower indium ratio than IGZO (In:Ga:Zn=1:1:1). In-rich IGZO has a higher indium ratio than IGZO (In:Ga:Zn=1:1:1) and a lower gallium ratio than IGZO (In:Ga:Zn=1:1:1). However, the material included in the oxide pattern structure AP is not limited thereto.
[0055] The word lines WL are disposed on the oxide pattern structures AP. The word lines WL are disposed in the channel trenches CH_T.
[0056] The word lines WL may include a first word line WL1 and a second word line WL2. For example, the first word line WL1 and the second word line WL2 are disposed on the oxide pattern structure AP. Also, the first word line WL1 and the second word line WL2 are disposed in the channel trench CH_T.
[0057] Each of the first word lines WL1 and the second word lines WL2 may extend in a first direction D1. The first word lines WL1 and the second word lines WL2 may be alternately arranged in a second direction D2. The first word lines WL1 and the second word lines WL2 may be spaced apart in the second direction D2.
[0058] The first word line WL1 and the second word line WL2 may be spaced apart from the bit line BL in the third direction D3. The first word line WL1 and the second word line WL2 may intersect with the bit line BL.
[0059] The first word line WL1 and the second word line WL2 are disposed on the first metal oxide pattern AP1 and the second metal oxide pattern AP2, respectively. The first word line WL1 may include an inner wall facing the mold insulating structure film 120 and an outer wall opposite the inner wall in the second direction D2. The boundary between the first metal oxide pattern AP1 and the third metal oxide pattern AP3 may be an extension of the outer wall of the first word line WL1 in the third direction D3.
[0060] The second word line WL2 may include an inner wall facing the mold insulating structure film 120 and an outer wall opposite the inner wall in the second direction D2. The boundary between the second metal oxide pattern AP2 and the third metal oxide pattern AP3 may be an extension of the outer wall of the second word line WL2 in the third direction D3.
[0061] The first word line WL1 and the second word line WL2 are disposed between the first metal oxide pattern AP1 and the second metal oxide pattern AP2. The first word line WL1 may be closer to the first metal oxide pattern AP1 than the second metal oxide pattern AP2. The second word line WL2 may be closer to the second metal oxide pattern AP2 than the first metal oxide pattern AP1.
[0062] Each of the first word lines WL1 and second word lines WL2 may have a width in the second direction D2. The width of the first word line WL1 in the second direction D2 at a portion overlapping with the oxide pattern structure AP in the first direction D1 is different from the width of the first word line WL1 in the second direction D2 at a portion not overlapping with the oxide pattern structure AP in the first direction D1. The width of the second word line WL2 in the second direction D2 at a portion overlapping with the oxide pattern structure AP in the first direction D1 is different from the width of the second word line WL2 in the second direction D2 at a portion not overlapping with the oxide pattern structure AP in the first direction D1.
[0063] For example, each of the first word line WL1 and the second word line WL2 may include a first word line portion WLa and a second word line portion WLb, and the width of the first word line portion WLa in the second direction D2 may be smaller than the width of the second word line portion WLb in the second direction D2.
[0064] The first portion WLa of the word line is disposed on the oxide pattern structure AP. Specifically, the first word line WL1 disposed on the first metal oxide pattern AP1 can be the first portion WLa of the word line. The second word line WL2 disposed on the second metal oxide pattern AP2 can be the first portion WLa of the word line.
[0065] Each of the first and second word lines WL1 and WL2 may include first and second word line portions WLa and WLb alternately arranged along the first direction D1. Each oxide pattern structure AP is arranged between the second word line portions WLb adjacent to each other in the first direction D1. In the first word line WL1, each first metal oxide pattern AP1 is arranged between the second word line portions WLb adjacent to each other in the first direction D1. In the second word line WL2, each second metal oxide pattern AP2 is arranged between the second word line portions WLb adjacent to each other in the second direction D2.
[0066] The second portion WLb of the word line is not disposed on the oxide pattern structure AP. The height of the first portion WLa of the word line in the third direction D3 may be smaller than the height of the second portion WLb of the word line in the third direction D3.
[0067] The first word line WL1 and the second word line WL2 may include a conductive material, such as at least one of doped polysilicon, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal, and a metal alloy.
[0068] 4, the top of the word line WL_UUS may be the top of the first word line WL1. The top of the word line WL_UUS may be the top of the second word line WL2. A height H4 from the top surface BL_US of the bit line to the top of the word line WL_UUS may be greater than a height H1 from the top surface BL_US of the bit line to the top of the oxide pattern structure AP_UUS. The height H4 from the top surface BL_US of the bit line to the top of the word line WL_UUS may be the same as the height H1 from the top surface BL_US of the bit line to the top of the oxide pattern structure AP_UUS.
[0069] The gate insulating film GOX is disposed between the first word line WL1 and the oxide pattern structure AP and the second word line WL2 and the oxide pattern structure AP. The gate insulating film GOX is disposed between the first word line WL1 and the first metal oxide pattern AP1 and the second word line WL2 and the second metal oxide pattern AP2. The gate insulating film GOX may extend in the first direction D1 alongside the first word line WL1 and the second word line WL2.
[0070] The gate insulating film GOX may extend in the third direction D3 between the first word line WL1 and the first metal oxide pattern AP1, and may extend in the third direction D3 between the second word line WL2 and the second metal oxide pattern AP2.
[0071] The gate insulating film GOX may extend in the second direction D2 between the first word line WL1 and the first metal oxide pattern AP1. The gate insulating film GOX may extend in the second direction D2 between the second word line WL2 and the second metal oxide pattern AP2. In some embodiments, the gate insulating film GOX may not be disposed on the third metal oxide pattern AP3. In cross-sectional views such as those shown in FIGS. 2 and 4, the gate insulating film GOX between the first word line WL1 and the first metal oxide pattern AP1 may be separated from the gate insulating film GOX between the second word line WL2 and the second metal oxide pattern AP2.
[0072] The gate insulating film GOX may include a silicon oxide film, a silicon oxynitride film, a high-dielectric-constant insulating film having a higher dielectric constant than a silicon oxide film, or a combination thereof.
[0073] A portion of the gate insulating film GOX protrudes in the third direction D3 from the topmost portion AP_UUS of the oxide pattern structure A portion of the gate insulating film GOX protrudes in the third direction D3 from the topmost portion WL_UUS of the word line WL_UUS.
[0074] 4, a height H9 from the top surface BL_US of the bit line to the top GOX_UUS of the gate insulating film may be greater than a height H1 from the top surface BL_US of the bit line to the top AP_UUS of the oxide pattern structure. The height H9 from the top surface BL_US of the bit line to the top GOX_UUS of the gate insulating film may be greater than a height H4 from the top surface BL_US of the bit line to the top WL_UUS of the word line.
[0075] The gate isolation pattern GSS is disposed on the bit line BL and the cell lower insulating film 131. The gate isolation pattern GSS is disposed in the channel trench CH_T. The gate isolation pattern GSS is disposed on the oxide pattern structure AP and the word line WL.
[0076] The gate isolation pattern GSS may be in contact with the oxide pattern structure AP. The gate isolation pattern GSS may be disposed on the third metal oxide pattern AP3. The gate isolation pattern GSS may be spaced apart from the bit line BL in the third direction D3.
[0077] The gate isolation pattern GSS may be disposed between the first word line WL1 and the second word line WL2 adjacent to each other in the second direction D2. The gate isolation pattern GSS may contact the first word line WL1 and the second word line WL2. The first word line WL1 and the second word line WL2 may be separated by the gate isolation pattern GSS. The gate isolation pattern GSS may extend in the first direction D1 between the first word line WL1 and the second word line WL2.
[0078] The first word line WL1 is disposed between the gate isolation pattern GSS and the oxide pattern structure AP. The second word line WL2 is disposed between the gate isolation pattern GSS and the oxide pattern structure AP. The first word line WL1 is disposed between the gate isolation pattern GSS and the first metal oxide pattern AP1. The second word line WL2 is disposed between the gate isolation pattern GSS and the second metal oxide pattern AP2.
[0079] The gate isolation pattern GSS may include a horizontal portion and a protruding portion. The protruding portion of the gate isolation pattern GSS protrudes in a third direction D3 from the horizontal portion of the gate isolation pattern GSS toward the bit line BL. The protruding portion of the gate isolation pattern GSS may be closer to the bit line BL than the horizontal portion of the gate isolation pattern GSS. The protruding portion of the gate isolation pattern GSS may extend in the third direction between the first word line WL1 and the second word line WL2. The protruding portion of the gate isolation pattern GSS may contact the top surface of the third metal oxide pattern AP3. The horizontal portion of the gate isolation pattern GSS is disposed on the top surfaces of the first word line WL1 and the second word line WL2. When cut in a cross section intersecting with the first direction D1, the gate isolation pattern GSS may have a "T" shape in the cross section.
[0080] The gate isolation pattern GSS may include a gate isolation liner 151 and a gate isolation filling film 153. The gate isolation liner 151 may extend along upper surfaces of the first word line WL1 and the second word line WL2 and along outer walls of the first word line WL1 and the second word line WL2. The gate isolation liner 151 may extend along the third metal oxide pattern AP3. The gate isolation liner 151 may be in contact with the third metal oxide pattern AP3. The gate isolation liner 151 may extend along the gate insulating film GOX that protrudes above the upper surfaces of the first word line WL1 and the second word line WL2. The height from the upper surface BL_US of the bit line to the top of the gate isolation liner 151 may be the same as, but is not limited to, the height H9 from the upper surface BL_US of the bit line to the top of the gate insulating film GOX_UUS.
[0081] The gate isolation filling layer 153 is disposed on the gate isolation liner 151. The gate isolation filling layer 153 may be in contact with the gate isolation liner 151. When cut along a cross section intersecting with the first direction D1, the gate isolation filling layer 153 may have a "T" shape in the cross section. The height from the upper surface BL_US of the bit line to the top of the gate isolation filling layer 153 may be the same as the height from the upper surface BL_US of the bit line to the top of the gate isolation liner 151, but is not limited thereto.
[0082] The gate isolation liner 151 and the gate isolation filling layer 153 are each made of an insulating material. Unlike the illustration, the gate isolation pattern GSS may be a single layer.
[0083] With respect to the upper surface of the bit line BL_US as a reference, the upper surface of the gate isolation pattern GSS may be located at the same height as the upper surface of the mold insulating structure film 120, but is not limited thereto.
[0084] A height H8 from the top surface BL_US of the bit line to the top GSS_UUS of the gate isolation pattern may be greater than a height H1 from the top surface BL_US of the bit line to the top AP_UUS of the oxide pattern structure. A height H8 from the top surface BL_US of the bit line to the top GSS_UUS of the gate isolation pattern may be greater than a height H4 from the top surface BL_US of the bit line to the top WL_UUS of the word line.
[0085] The landing pad LP is disposed on the oxide pattern structure AP, the mold insulating structure film 120, the gate isolation pattern GSS, and the gate insulating film GOX. The landing pad LP is disposed on the first metal oxide pattern AP1, the second mold insulating film 122, the gate isolation pattern GSS, and the gate insulating film GOX. The landing pad LP is disposed on the second metal oxide pattern AP2, the second mold insulating film 122, the gate isolation pattern GSS, and the gate insulating film GOX.
[0086] The landing pad LP may contact the first metal oxide pattern AP1 and the second metal oxide pattern AP2, and may be connected to the first metal oxide pattern AP1 and the second metal oxide pattern AP2.
[0087] The landing pad LP may be in contact with the second mold insulating film 122. For example, the landing pad LP may be in contact with the upper surface 122US of the second mold insulating film. The landing pad LP may be in contact with the third mold insulating film 123. For example, the landing pad LP may be in contact with the sidewall 123SW of the third mold insulating film.
[0088] The landing pad LP may include a horizontal portion and a protruding portion. The horizontal portion of the landing pad LP is disposed on the upper surface 123US of the third mold insulating film and the uppermost portion GSS_UUS of the gate isolation pattern. The protruding portion of the landing pad LP protrudes from the horizontal portion of the landing pad LP in the third direction D3 toward the bit line BL. The protruding portion of the landing pad LP is disposed between the third mold insulating film 123 and the gate isolation pattern GSS. The protruding portion of the landing pad LP may contact the upper surface 122US of the second mold insulating film and the uppermost portion AP_UUS of the oxide pattern structure. The protruding portion of the landing pad LP may contact the sidewall 123SW of the third mold insulating film, the sidewall of the gate insulating film GOX, and the sidewall of the oxide pattern structure AP.
[0089] The bottom LP_UBS of the landing pad may contact the upper surface 122US of the second mold insulating film. For example, the height H3 from the upper surface BL_US of the bit line to the bottom LP_UBS of the landing pad may be the same as the height H2 from the upper surface BL_US of the bit line to the upper surface 122US of the second mold insulating film. For example, the height H3 from the upper surface BL_US of the bit line to the bottom LP_UBS of the landing pad may be smaller than the height H1 from the upper surface BL_US of the bit line to the top AP_UUS of the oxide pattern structure.
[0090] The landing pad LP may include a conductive material, such as at least one of doped polysilicon, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal, and a metal alloy.
[0091] The pad isolation insulating pattern 235 is disposed between the landing pads LP. The pad isolation insulating pattern 235 is disposed on the gate isolation pattern GSS and the mold insulating structure film 120. The pad isolation insulating pattern 235 is disposed on the gate isolation filling film 153 and the third mold insulating film 123. The pad isolation insulating pattern 235 may contact an upper surface of the gate isolation filling film 153 and an upper surface 123US of the third mold insulating film. When viewed from a plane intersecting the third direction D3, the landing pads LP may be arranged in a matrix along the second direction D2 and the first direction D1. The upper surfaces of the landing pads LP may be flush with the upper surfaces of the pad isolation insulating patterns 235, but are not limited thereto.
[0092] The information storage patterns DSP are disposed on the landing pads LP, respectively. The information storage patterns DSP may contact the entire or part of the upper surface of the landing pads LP. The information storage patterns DSP may be connected to the landing pads LP. The information storage patterns DSP may be connected to the first metal oxide pattern AP1 and the second metal oxide pattern AP2, respectively.
[0093] The information storage patterns DSP may be arranged in a matrix along the second direction D2 and the first direction D1 as shown in Figure 1. The information storage patterns DSP may completely or partially overlap the landing pads LP in the third direction D3.
[0094] For example, the data storage pattern DSP may be a capacitor, and the first metal oxide pattern AP1 and the second metal oxide pattern AP2 may be connected to the capacitor, respectively.
[0095] The information storage pattern DSP may include a capacitor dielectric layer 253 interposed between the storage electrode 251 and the plate electrode 255. In this case, the storage electrode 251 may be in contact with the landing pad LP. In a plan view, the storage electrode 251 may have various shapes, such as a circle, an oval, a rectangle, a square, a diamond, or a hexagon. The storage electrode 251 may completely or partially overlap the landing pad LP. The storage electrode 251 may be in contact with the entire or a portion of the upper surface of the landing pad LP. The storage electrode 251 may penetrate the upper cell etch stop layer 247. The upper cell etch stop layer 247 is made of an insulating material.
[0096] Alternatively, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electrical pulse applied to the memory element. For example, the data storage pattern DSP may include a phase-change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material, whose crystalline state changes depending on the amount of current.
[0097] 5 to 7 are diagrams illustrating semiconductor memory devices according to some embodiments. For convenience of explanation, differences from the description using FIGS. 1 to 4 will be mainly described. For reference, FIGS. 6 and 7 are enlarged views of a portion P in FIG. 5.
[0098] 5 to 7, in semiconductor memory devices according to some embodiments, a height H1 from an upper surface BL_US of a bit line to a top AP_UUS of an oxide pattern structure may be the same as a height H3 from an upper surface BL_US of a bit line to a bottom LP_UBS of a landing pad, and the bottom LP_UBS of the landing pad may contact the top AP_UUS of the oxide pattern structure.
[0099] In FIG. 6, the height H1 from the upper surface BL_US of the bit line to the top AP_UUS of the oxide pattern structure may be smaller than the height H2 from the upper surface BL_US of the bit line to the upper surface 122US of the second mold insulating film.
[0100] The protruding portions of the landing pads LP may contact the uppermost portion AP_UUS of the oxide pattern structure and the upper surface 122US of the second mold insulating film, the sidewalls of the gate insulating film GOX, the sidewalls of the second mold insulating film 122, and the sidewalls 123SW of the third mold insulating film.
[0101] In FIG. 7, the height H1 from the upper surface BL_US of the bit line to the top AP_UUS of the oxide pattern structure may be the same as the height H2 from the upper surface BL_US of the bit line to the upper surface 122US of the second mold insulating film.
[0102] The bottom portion LP_UBS of the landing pad LP may contact the top portion AP_UUS of the oxide pattern structure and the upper surface 122US of the second mold insulating film. The protruding portion of the landing pad LP may contact the top portion AP_UUS of the oxide pattern structure and the upper surface 122US of the second mold insulating film. The protruding portion of the landing pad LP may contact the sidewall of the gate insulating film GOX and the sidewall 123SW of the third mold insulating film.
[0103] 8 to 12 are diagrams illustrating semiconductor memory devices according to some embodiments. For convenience of explanation, the following description will focus on differences from the description using FIGS. 1 to 4. For reference, FIGS. 10 to 12 are enlarged views of a portion P in FIG. 8.
[0104] 8 to 12, a semiconductor memory device according to some embodiments may further include a residue insulating pattern RP on an upper surface of the mold insulating structure layer 120.
[0105] The residual insulating pattern RP is disposed on the upper surface 123US of the third mold insulating film and may be in contact with the upper surface 123US of the third mold insulating film.
[0106] The residual insulating pattern RP may include a first residual insulating pattern RP1 and a second residual insulating pattern RP2. The first residual insulating pattern RP1 is disposed on the second residual insulating pattern RP2. The second residual insulating pattern RP2 is disposed on the upper surface 123US of the third mold insulating film. The bottom surface of the first residual insulating pattern RP1 may contact the uppermost portion RP2_UUS of the second residual insulating pattern. The bottom surface of the second residual insulating pattern RP2 may contact the upper surface 123US of the third mold insulating film.
[0107] The width of the first residual insulating pattern RP1 in the second direction D2 and the width of the second residual insulating pattern RP2 in the second direction D2 may be the same as the width of the third mold insulating film 123 in the second direction D2, but is not limited to this.
[0108] The height H6 from the top surface BL_US of the bit line to the top RP1_UUS of the first residual insulating pattern may be the same as the height H8 from the top surface BL_US of the bit line to the top GSS_UUS of the gate isolation pattern, but this is merely an example and is not limited thereto.
[0109] The height H7 from the top surface BL_US of the bit line to the top RP2_UUS of the second residual insulating pattern may be the same as the height H9 from the top surface BL_US of the bit line to the top GOX_UUS of the gate insulating film, but this is merely an example and is not limited thereto.
[0110] The first residual insulating pattern RP1 and the gate isolation liner 151 may include the same material. The second residual insulating pattern RP2 and the gate insulating film GOX may include the same material. For example, the second residual insulating pattern RP2 may include a silicon oxide film, a silicon oxynitride film, a high-k insulating film having a higher dielectric constant than a silicon oxide film, or a combination thereof.
[0111] In other words, the first residual insulating pattern RP1 may be directly connected to the gate isolation liner 151 to form a first insulating liner. The portion of the first insulating liner disposed on the upper surface 123US of the third mold insulating layer may be the first residual insulating pattern RP1. The second residual insulating pattern RP2 may be directly connected to the gate insulating layer GOX to form a second insulating liner. The portion of the second insulating liner disposed on the upper surface 123US of the third mold insulating layer may be the second residual insulating pattern RP2.
[0112] The horizontal portions of the gate isolation pattern GSS are disposed on the upper surfaces of the first word lines WL1 and WL2 and on the top surface GOX_UUS of the gate insulating film. The gate isolation liner 151 is disposed on the top surface GOX_UUS of the gate insulating film. The height from the top surface BL_US of the bit lines to the top of the gate isolation liner 151 may be greater than the height H9 from the top surface BL_US of the bit lines to the top surface GOX_UUS of the gate insulating film.
[0113] The pad isolation insulating pattern 235 is disposed on the residual insulating pattern RP. The pad isolation insulating pattern 235 may contact the first residual insulating pattern RP1.
[0114] The horizontal portion of the landing pad LP may contact the gate isolation liner 151 and the top surface of the first residual insulating pattern RP1, but not the top surface GOX_UUS of the gate insulating film. The protruding portion of the landing pad LP may contact the sidewall of the first residual insulating pattern RP1 and the sidewall of the second residual insulating pattern RP2.
[0115] In FIG. 10, the height H1 from the upper surface BL_US of the bit line to the top AP_UUS of the oxide pattern structure may be greater than the height H2 from the upper surface BL_US of the bit line to the upper surface 122US of the second mold insulating film.
[0116] In FIG. 11, the height H1 from the upper surface BL_US of the bit line to the top AP_UUS of the oxide pattern structure may be smaller than the height H2 from the upper surface BL_US of the bit line to the upper surface 122US of the second mold insulating film.
[0117] In FIG. 12, the height H1 from the upper surface BL_US of the bit line to the top AP_UUS of the oxide pattern structure may be the same as the height H2 from the upper surface BL_US of the bit line to the upper surface 122US of the second mold insulating film.
[0118] 13 to 17 are diagrams illustrating semiconductor memory devices according to some embodiments. For convenience of explanation, the following description will focus on differences from the description using FIGS. 1 to 4. For reference, FIGS. 15 to 17 are enlarged views of part P in FIG. 13.
[0119] 13 to 17, in semiconductor memory devices according to some embodiments, a second residual insulating pattern RP2 may be disposed on the mold insulating structure layer 120. The second residual insulating pattern RP2 may be disposed on an upper surface 123US of the third mold insulating layer. A bottom surface of the second residual insulating pattern RP2 may contact the upper surface 123US of the third mold insulating layer.
[0120] The width of the second residual insulating pattern RP2 in the second direction D2 may be the same as the width of the third mold insulating layer 123 in the second direction D2, but is not limited thereto.
[0121] The height H7 from the top surface BL_US of the bit line to the top RP2_UUS of the second residual insulating pattern may be the same as the height H9 from the top surface BL_US of the bit line to the top GOX_UUS of the gate insulating film, but this is merely an example and is not limited thereto.
[0122] The height H7 from the top surface BL_US of the bit line to the top RP2_UUS of the second residual insulating pattern may be the same as the height H8 from the top surface BL_US of the bit line to the top GSS_UUS of the gate isolation pattern, but this is merely an example and is not limited thereto.
[0123] The second residual insulating pattern RP2 and the gate insulating film GOX may include the same material. For example, the second residual insulating pattern RP2 may include a silicon oxide film, a silicon oxynitride film, a high-k insulating film having a higher dielectric constant than a silicon oxide film, or a combination thereof.
[0124] In other words, the second residual insulating pattern RP2 may be directly connected to the gate insulating film GOX to form a second insulating liner, and the portion of the second insulating liner disposed on the upper surface 123US of the third mold insulating film may be the second residual insulating pattern RP2.
[0125] The pad isolation insulating pattern 235 is disposed on the second residual insulating pattern RP2 and may be in contact with the second residual insulating pattern RP2.
[0126] The horizontal portion of the landing pad LP may contact the top surface of the second residual insulating pattern RP2, and the protruding portion of the landing pad LP may contact the sidewall of the second residual insulating pattern RP2.
[0127] In FIG. 15, the height H1 from the upper surface BL_US of the bit line to the uppermost portion AP_UUS of the oxide pattern structure may be greater than the height H2 from the upper surface BL_US of the bit line to the upper surface 122US of the second mold insulating film.
[0128] 16, a height H1 from the upper surface BL_US of the bit line to the uppermost portion AP_UUS of the oxide pattern structure may be smaller than a height H2 from the upper surface BL_US of the bit line to the upper surface 122US of the second mold insulating film. In this case, a second residual insulating pattern RP2 may be disposed on the mold insulating structure film 120.
[0129] 17, a height H1 from the upper surface BL_US of the bit line to the top AP_UUS of the oxide pattern structure may be the same as a height H2 from the upper surface BL_US of the bit line to the upper surface 122US of the second mold insulating film. In this case, a second residual insulating pattern RP2 may be disposed on the mold insulating structure film 120.
[0130] 18 and 19 are diagrams illustrating semiconductor memory devices according to some embodiments. For convenience of explanation, differences from the contents described using FIGS. 1 to 4 will be mainly described. For reference, FIG. 19 is an enlarged view of part P in FIG. 18.
[0131] 18 and 19, in a semiconductor memory device according to some embodiments, the first metal oxide pattern AP1 and the second metal oxide pattern AP2 spaced apart in the second direction D2 are not connected in the channel trench CH_T.
[0132] The gate isolation pattern GSS may contact the bit line BL. The gate isolation liner 151 may contact the top surface of the bit line BL_US. The first metal oxide pattern AP1 and the second metal oxide pattern AP2 may be spatially separated by the gate isolation pattern GSS.
[0133] 20-29 are views illustrating intermediate stages in a method for manufacturing a semiconductor memory device according to some embodiments.
[0134] 20 and 21, a peripheral gate structure PG may be formed on the substrate 100. As shown in FIG.
[0135] A first peripheral wiring line 241 a and a peripheral contact plug 241 b may be formed on the substrate 100 .
[0136] Peripheral upper insulating films 261, 262, 263, 264, and 265 may be sequentially formed on the first peripheral wiring line 241a and the peripheral contact plug 241b. The second peripheral wiring line 243, the peripheral via plug 242, and the cell connecting plug 244 may be formed in the peripheral upper insulating films 261, 262, 263, 264, and 265.
[0137] Next, the bit line BL is formed on the fifth peripheral upper insulating film 265. The bit line BL may extend longitudinally in the second direction D2 on the substrate 100. The cell lower insulating film 131 may be formed on the fifth peripheral upper insulating film 265. The cell lower insulating film 131 exposes an upper surface BL_US of the bit line.
[0138] 22 and 23, the mold insulating structure film 120 may be formed on the substrate 100. Specifically, a first mold insulating film 121, a second mold insulating film 122, and a third mold insulating film 123 may be formed on the bit line BL and the cell lower insulating film 131 in this order.
[0139] The etching stop layer 130 is formed between the mold insulating structure layer 120 and the bit line BL and cell lower insulating layer 131, but is not limited thereto.
[0140] The first mold insulating layer 121 may be formed on the etch stop layer 130 using a silicon oxide-based insulating material. For example, the first mold insulating layer 121 may be formed on silicon oxide. The second mold insulating layer 122 may be formed on the first mold insulating layer 121 using a silicon nitride-based insulating material. For example, the second mold insulating layer 122 may be formed on silicon nitride. The third mold insulating layer 123 may be formed on the second mold insulating layer 122 using a silicon oxide-based insulating material. For example, the third mold insulating layer 123 may be formed on the second mold insulating layer 122 using silicon oxide.
[0141] The mold insulating structure film 120 may include a plurality of channel trenches CH_T extending in the first direction D1. The channel trenches CH_T may intersect with the bit lines BL. The channel trenches CH_T expose the bit lines BL.
[0142] 24 and 25, an oxide pattern structure AP may be formed in the channel trench CH_T. Next, a gate insulating film GOX is formed on the oxide pattern structure AP. The gate insulating film GOX may be formed along the oxide pattern structure AP and the upper surface of the mold insulating structure film 120. In the portion where the oxide pattern structure AP is not formed, the gate insulating film GOX may be formed along the sidewall and upper surface of the mold insulating structure film 120. The gate insulating film GOX may be formed using at least one of, but not limited to, physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) techniques.
[0143] Next, the first word line WL1 and the second word line WL2 are formed on the gate insulating film GOX. The first word line WL1 and the second word line WL2 may be formed along the sidewall of the channel trench CH_T.
[0144] Forming the first word line WL1 and the second word line WL2 may include depositing a gate conductive layer on the gate insulating layer GOX and then performing an anisotropic etching process on the gate conductive layer.
[0145] During the anisotropic etching process for the gate conductive layer, a portion of the gate insulating film GOX may be etched. As a result, the gate insulating film GOX between the first word line WL1 and the oxide pattern structure AP may be separated from the gate insulating film GOX between the second word line WL2 and the oxide pattern structure AP. Unlike the illustration, during the anisotropic etching process for the gate conductive layer, the gate insulating film GOX may be used as an etch stop layer.
[0146] The gate isolation pattern GSS is formed on the first word line WL1 and the second word line WL2. The gate isolation pattern GSS may fill the channel trench CH_T. More specifically, the gate isolation liner 151 may be formed along the profile of the first word line WL1 and the profile of the second word line WL2. The gate isolation liner 151 may also be formed on the upper surface of the gate insulating film GOX.
[0147] 26 and 27, the gate isolation liner 151, the gate insulating film GOX and the gate isolation filling film 153 are removed by an etching process.
[0148] Specifically, the oxide pattern structure AP and the gate isolation liner 151 formed on the upper surface of the mold insulating structure film 120, the gate insulating film GOX, and the gate isolation filling film 153 located at the same level therewith may be removed.
[0149] Referring to FIG. 28, the oxide pattern structure AP is removed by an etching process.
[0150] In this case, the etching process of the oxide pattern structure AP can be omitted depending on the selectivity of the constituent materials of the oxide pattern structure AP and the third mold insulating film 123 of the mold insulating structure film 120, but is not limited thereto.
[0151] Referring to FIG. 29, the third mold insulating film 123 is removed by an etching process.
[0152] A portion of the top surface of the second mold insulating film 122 is exposed in the third direction. A portion of the sidewall of the oxide pattern structure AP is exposed in the second direction.
[0153] Next, referring to FIGS. 2 and 3, a pre-landing pad layer may be formed on the mold insulating structure layer 120, the gate isolation pattern GSS, and the oxide pattern structure AP.
[0154] The pre-landing pad film may be patterned to form landing pads LP on the oxide pattern structures AP.
[0155] Next, a data storage pattern DSP is formed on the landing pad LP. The data storage pattern DSP is connected to the oxide pattern structure AP and may be formed on the gate isolation pattern GSS.
[0156] 30 to 32 are views illustrating intermediate stages of a method for fabricating a semiconductor memory device according to some embodiments. For convenience of explanation, the following description will focus on differences from the method described with reference to FIGS. 20 to 29.
[0157] For reference, the manufacturing method described with reference to FIG. 30 may be the manufacturing process performed from FIG.
[0158] Referring to FIG. 30, an etching process removes a portion of the gate isolation liner 151 and the gate insulating film GOX.
[0159] Specifically, the gate isolation liner 151 and the gate insulating film GOX formed on the upper surfaces of the oxide pattern structure AP and the mold insulating structure film 120 may be removed, so that the remaining insulating pattern RP is not connected to the gate isolation liner 151 and the gate insulating film GOX in the cross-sectional view taken along AA.
[0160] Referring to FIG. 31, the oxide pattern structure AP is removed by an etching process.
[0161] In this case, the etching process of the oxide pattern structure AP can be omitted depending on the selectivity of the constituent materials of the oxide pattern structure AP and the third mold insulating film 123 of the mold insulating structure film 120, but is not limited thereto.
[0162] Referring to FIG. 32, the third mold insulating film 123 is removed by an etching process.
[0163] A portion of the top surface of the second mold insulating film 122 is exposed in the third direction. A portion of the sidewall of the oxide pattern structure AP is exposed in the second direction.
[0164] Next, referring to FIGS. 8 and 9, a pre-landing pad film is formed on the mold insulating structure film 120, the gate isolation pattern GSS and the oxide pattern structure AP.
[0165] The pre-landing pad film may be patterned to form landing pads LP on the oxide pattern structures AP.
[0166] Next, a data storage pattern DSP is formed on the landing pad LP. The data storage pattern DSP is connected to the oxide pattern structure AP and may be formed on the gate isolation pattern GSS.
[0167] 33 to 37 are views illustrating intermediate steps for explaining a method for manufacturing a semiconductor memory device according to some embodiments. For convenience of explanation, the following description will focus on differences from the method described with reference to FIGS. 20 to 29.
[0168] For reference, the manufacturing method described with reference to FIG. 33 may be the manufacturing process performed from FIG. 24 onwards.
[0169] 33 and 34, an etching process removes a portion of the gate isolation liner 151 and the gate isolation filling film 153.
[0170] Specifically, the gate isolation liner 151 formed on the gate insulating film GOX and the gate isolation filling film 153 located at the same level as the gate isolation liner 151 may be removed.
[0171] Referring to FIG. 35, a part of the gate insulating film GOX is removed by an etching process.
[0172] Specifically, the oxide pattern structure AP and the gate insulating film GOX formed on the upper surface of the mold insulating structure film 120 may be removed, so that the second residual insulating pattern RP2 is not connected to the gate insulating film GOX in the cross-sectional view taken along AA.
[0173] Referring to FIG. 36, the oxide pattern structure AP is removed by an etching process.
[0174] In this case, the etching process of the oxide pattern structure AP can be omitted depending on the selectivity of the constituent materials of the oxide pattern structure AP and the third mold insulating film 123 of the mold insulating structure film 120, but is not limited thereto.
[0175] Referring to FIG. 37, the third mold insulating film 123 is removed by an etching process.
[0176] A portion of the top surface of the second mold insulating film 122 is exposed in the third direction. A portion of the sidewall of the oxide pattern structure AP is exposed in the second direction.
[0177] Next, referring to FIGS. 13 and 14, a pre-landing pad layer may be formed on the mold insulating structure layer 120, the gate isolation pattern GSS, and the oxide pattern structure AP.
[0178] The pre-landing pad film may be patterned to form landing pads LP on the oxide pattern structures AP.
[0179] Next, a data storage pattern DSP is formed on the landing pad LP. The data storage pattern DSP is connected to the oxide pattern structure AP and may be formed on the gate isolation pattern GSS.
[0180] Although the present invention has been described above with reference to the accompanying drawings, it should be understood that the present invention is not limited to the above-described embodiments and can be manufactured in various different forms, and that those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. [Explanation of symbols]
[0181] 100 boards BL bit line PG peripheral gate structure 130 Etching stop film 120 Molded insulating structural film 121 First mold insulating film 122 Second mold insulating film 123 Third mold insulating film AP oxide pattern structure AP1 First metal oxide pattern AP2 Second metal oxide pattern WL Word Line WL1 First word line WL2 Second word line GOX gate insulating film GSS gate isolation pattern DSP Information Storage Pattern
Claims
1. a bit line extending in a first direction on the substrate; an etch stop layer disposed on the bit line; a mold insulating structure film disposed on the etch stop film and including a channel trench extending in a second direction; a metal oxide pattern disposed on the bit line and extending along a sidewall of the channel trench; a word line disposed on the metal oxide pattern and extending in the second direction; and an information storage pattern disposed on and connected to the metal oxide pattern; the mold insulating structure layer includes a first mold insulating layer on the etching stop layer and a second mold insulating layer on the first mold insulating layer; the second mold insulating film includes a top surface and a bottom surface that are opposite to each other in a third direction; a bottom surface of the second mold insulating film facing the bit line; a height from an upper surface of the bit line to a top of the metal oxide pattern is greater than a height from an upper surface of the bit line to an upper surface of the second mold insulating film.
2. 2. The semiconductor memory device of claim 1, wherein the first mold insulating layer comprises a different material than the second mold insulating layer.
3. the first mold insulating film includes silicon oxide; 3. The semiconductor memory device of claim 2, wherein the second mold insulating layer comprises silicon nitride.
4. 3. The semiconductor memory device of claim 2, wherein the mold insulating structure layer further comprises a third mold insulating layer on the second mold insulating layer.
5. The semiconductor memory device of claim 4 , wherein the third mold insulating layer includes the same material as the first mold insulating layer.
6. a landing pad disposed between the metal oxide pattern and the information storage pattern; 2. The semiconductor memory device of claim 1, wherein the landing pad contacts the second mold insulating film.
7. 7. The semiconductor memory device of claim 6, wherein a height from an upper surface of the bit line to a bottom of the landing pad is the same as a height from an upper surface of the bit line to an upper surface of the second mold insulating film.
8. 7. The semiconductor memory device of claim 6, wherein a height from an upper surface of the bit line to a top of the metal oxide pattern is greater than a height from an upper surface of the bit line to a bottom of the landing pad.
9. a bit line extending in a first direction on the substrate; an etch stop layer disposed on the bit line; a mold insulating structure film disposed on the etch stop film and including a channel trench extending in a second direction; a metal oxide pattern disposed on the bit line and extending along a sidewall of the channel trench; a word line disposed on the metal oxide pattern and extending in the second direction; and an information storage pattern disposed on and connected to the metal oxide pattern; the mold insulating structure layer includes a first mold insulating layer, a second mold insulating layer, and a third mold insulating layer sequentially disposed on the etching stop layer; the second mold insulating film is disposed between the first mold insulating film and the third mold insulating film; the second mold insulating film includes a top surface and a bottom surface that are opposite to each other in a third direction; a bottom surface of the second mold insulating film facing the bit line; a height from an upper surface of the bit line to a top of the metal oxide pattern is greater than a height from an upper surface of the bit line to a bottom surface of the second mold insulating film.
10. a bit line extending in a first direction on the substrate; a first metal oxide pattern and a second metal oxide pattern disposed on the bit line and spaced apart in the first direction; a mold insulating structure film disposed on the bit line and between the first metal oxide pattern and the second metal oxide pattern; a first word line disposed on the first metal oxide pattern and extending in a second direction; a second word line disposed on the second metal oxide pattern and extending in the second direction; and an information storage pattern disposed on the first metal oxide pattern and the second metal oxide pattern and connected to the first metal oxide pattern and the second metal oxide pattern; the mold insulating structure film includes a first mold insulating film, a second mold insulating film, and a third mold insulating film sequentially disposed on the bit line; the second mold insulating film is disposed between the first mold insulating film and the third mold insulating film; the second mold insulating film and the third mold insulating film each include a top surface and a bottom surface that are opposite to each other in a third direction; an upper surface of the second mold insulating film facing a bottom surface of the third mold insulating film; a width of an upper surface of the second mold insulating film in the first direction is greater than a width of a bottom surface of the third mold insulating film in the first direction.