Active matrix substrate, display device, and manufacturing method for active matrix substrate

Abstract

To improve the opening ratio of a display device and an active matrix substrate including an oxide semiconductor TFT with a top gate structure.SOLUTION: A pixel TFT is an oxide semiconductor TFT with a top gate structure. An active matrix substrate includes a first interlayer insulating layer covering a gate electrode and an oxide semiconductor layer, and a second interlayer insulating layer provided thereon. A source electrode is provided on the second interlayer insulating layer. The first interlayer insulating layer includes a first source opening part. The second interlayer insulating layer includes a second source opening part existing inside the first source opening part. The source electrode is connected to a source contact region of the oxide semiconductor layer in the second source opening part.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an active matrix substrate and a display device, and also to a method for manufacturing the active matrix substrate. [Background technology]

[0002] Currently, display devices that include an active matrix substrate in which a switching element is provided for each pixel are widely used. An active matrix substrate that includes thin film transistors (hereinafter referred to as "TFTs") as switching elements is called a TFT substrate. In this specification, the regions of the TFT substrate that correspond to the pixels of the display device are called pixel regions. Furthermore, the TFTs provided as switching elements in each pixel region of the active matrix substrate are sometimes called "pixel TFTs."

[0003] In recent years, it has been proposed to use oxide semiconductors as the material for the active layer of TFTs, instead of amorphous silicon or polycrystalline silicon. A TFT having an oxide semiconductor film as its active layer is called an "oxide semiconductor TFT." Patent Document 1 discloses an active matrix substrate that uses an In-Ga-Zn-O based semiconductor film as the active layer of the TFT.

[0004] Oxide semiconductors have higher mobility than amorphous silicon. Therefore, oxide semiconductor TFTs can operate at higher speeds than amorphous silicon TFTs. Furthermore, oxide semiconductor films can be formed using a simpler process than polycrystalline silicon films, making them suitable for use in devices requiring large areas.

[0005] TFT structures are broadly divided into bottom-gate and top-gate structures. Currently, the bottom-gate structure is often adopted for oxide semiconductor TFTs, but the use of a top-gate structure has also been proposed (e.g., Patent Document 2). With the top-gate structure, the gate insulating layer can be made thin, resulting in high current supply performance. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-134475 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-204077 Summary of the Invention [Problem to be solved by the invention]

[0007] In recent years, display devices have become increasingly high-definition. For such high-definition display devices, it is necessary to reduce the pixel size while maintaining a sufficiently high aperture ratio. Therefore, there is a demand for pixel structures that can improve the aperture ratio by reducing the pixel TFT size and miniaturizing the wiring.

[0008] The present invention has been made in view of the above problems, and an object of the present invention is to improve the aperture ratio of an active matrix substrate and a display device that include an oxide semiconductor TFT with a top-gate structure. [Means for solving the problem]

[0009] According to embodiments of the present invention, there are provided an active matrix substrate, a display device, and a method for manufacturing an active matrix substrate, as described in the following items.

[0010] [Item 1] a display area including a plurality of pixel areas and a peripheral area located around the display area; A substrate; pixel TFTs supported by the substrate and provided corresponding to each of the plurality of pixel regions; a pixel electrode disposed in each of the plurality of pixel regions and electrically connected to the pixel TFT; Equipped with The pixel TFT is an oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on both sides of the channel region; a gate insulating layer provided on the channel region of the oxide semiconductor layer; a gate electrode provided on the gate insulating layer and facing the channel region with the gate insulating layer interposed therebetween; a source electrode electrically connected to the source contact region of the oxide semiconductor layer; An active matrix substrate having: a first interlayer insulating layer covering the gate electrode and the oxide semiconductor layer; a second interlayer insulating layer provided on the first interlayer insulating layer; Furthermore, the source electrode is provided on the second interlayer insulating layer, the first interlayer insulating layer has a first source opening formed to expose at least a portion of the source contact region; the second interlayer insulating layer has a second source opening that is smaller than the first source opening in plan view and is positioned inside the first source opening; the source electrode is connected to the source contact region at the second source opening.

[0011] [Item 2] the pixel TFT has a drain electrode electrically connected to the drain contact region of the oxide semiconductor layer; the drain electrode is provided on the second interlayer insulating layer, the first interlayer insulating layer has a first drain opening formed to expose at least a portion of the drain contact region; the second interlayer insulating layer has a second drain opening that is smaller than the first drain opening in a plan view and is positioned inside the first drain opening; Item 2. The active matrix substrate according to item 1, wherein the drain electrode is connected to the drain contact region at the second drain opening.

[0012] [Item 3] the peripheral region has a first connection portion that electrically connects a first wiring formed from the same conductive film as the gate electrode and a second wiring formed from the same conductive film as the source electrode, the first interlayer insulating layer has a first gate opening formed to expose at least a portion of the first wiring; the second interlayer insulating layer has a second gate opening that is smaller than the first gate opening in plan view and is located inside the first gate opening; 3. The active matrix substrate according to item 1 or 2, wherein the second wiring is connected to the first wiring at the second gate opening.

[0013] [Item 4] a conductive light-shielding layer provided on the substrate; a lower insulating layer covering the light-shielding layer; Furthermore, the oxide semiconductor layer is provided on the lower insulating layer, the peripheral region has a second connection portion that electrically connects a third wiring formed from the same conductive film as the light-shielding layer and a fourth wiring formed from the same conductive film as the source electrode, the first interlayer insulating layer has a first bottom opening formed to expose at least a portion of the third wiring; the lower insulating layer has a second bottom opening that is smaller than the first bottom opening in plan view and is positioned inside the first bottom opening; the second interlayer insulating layer has a third bottom opening that is smaller than the first bottom opening in a plan view, is formed so as to be located inside the first bottom opening, and is continuous with the second bottom opening; 4. The active matrix substrate according to any one of items 1 to 3, wherein the fourth wiring is connected to the third wiring in the second bottom opening and the third bottom opening.

[0014] [Item 5] a display area including a plurality of pixel areas and a peripheral area located around the display area; A substrate; pixel TFTs supported by the substrate and provided corresponding to each of the plurality of pixel regions; a pixel electrode disposed in each of the plurality of pixel regions and electrically connected to the pixel TFT; Equipped with The pixel TFT is an oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on both sides of the channel region; a gate insulating layer provided on the channel region of the oxide semiconductor layer; a gate electrode provided on the gate insulating layer and facing the channel region with the gate insulating layer interposed therebetween; a drain electrode electrically connected to the drain contact region of the oxide semiconductor layer; An active matrix substrate having: a first interlayer insulating layer covering the gate electrode and the oxide semiconductor layer; a second interlayer insulating layer provided on the first interlayer insulating layer; Furthermore, the drain electrode is provided on the second interlayer insulating layer, the first interlayer insulating layer has a first drain opening formed to expose at least a portion of the drain contact region; the second interlayer insulating layer has a second drain opening that is smaller than the first drain opening in a plan view and is positioned inside the first drain opening; the drain electrode is connected to the drain contact region at the second drain opening.

[0015] [Item 6] the peripheral region has a first connection portion that electrically connects a first wiring formed from the same conductive film as the gate electrode and a second wiring formed from the same conductive film as the drain electrode, the first interlayer insulating layer has a first gate opening formed to expose at least a portion of the first wiring; the second interlayer insulating layer has a second gate opening that is smaller than the first gate opening in plan view and is located inside the first gate opening; Item 6. The active matrix substrate according to item 5, wherein the second wiring is connected to the first wiring at the second gate opening.

[0016] [Item 7] a conductive light-shielding layer provided on the substrate; a lower insulating layer covering the light-shielding layer; Furthermore, the oxide semiconductor layer is provided on the lower insulating layer, the peripheral region has a second connection portion that electrically connects a third wiring formed from the same conductive film as the light-shielding layer and a fourth wiring formed from the same conductive film as the drain electrode, the first interlayer insulating layer has a first bottom opening formed to expose at least a portion of the third wiring; the lower insulating layer has a second bottom opening that is smaller than the first bottom opening in plan view and is positioned inside the first bottom opening; the second interlayer insulating layer has a third bottom opening that is smaller than the first bottom opening in a plan view, is formed so as to be located inside the first bottom opening, and is continuous with the second bottom opening; Item 7. The active matrix substrate according to item 5 or 6, wherein the fourth wiring is connected to the third wiring in the second bottom opening and the third bottom opening.

[0017] [Item 8] 8. The active matrix substrate according to any one of items 1 to 7, wherein the thickness of the second interlayer insulating layer is smaller than the thickness of the first interlayer insulating layer.

[0018] [Item 9] 9. The active matrix substrate according to any one of items 1 to 8, wherein the second interlayer insulating layer has a thickness of 200 nm or less.

[0019] [Item 10] 10. The active matrix substrate according to any one of items 1 to 9, wherein the second interlayer insulating layer is a silicon nitride layer or has a laminated structure including a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer.

[0020] [Item 11] 11. The active matrix substrate according to any one of items 1 to 10, wherein the oxide semiconductor layer includes an In—Ga—Zn—O-based semiconductor.

[0021] [Item 12] Item 12. The active matrix substrate according to item 11, wherein the In-Ga-Zn-O based semiconductor includes a crystalline portion.

[0022] [Item 13] 13. A display device comprising the active matrix substrate according to any one of items 1 to 12.

[0023] [Item 14] an opposing substrate disposed opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; Item 14. The display device according to item 13, which is a liquid crystal display device comprising:

[0024] [Item 15] A method for manufacturing the active matrix substrate according to item 1, (A) forming the oxide semiconductor layer, the gate insulating layer, and the gate electrode; (B) forming the first interlayer insulating layer so as to cover the gate electrode and the oxide semiconductor layer; (C) forming the first source opening in the first interlayer insulating layer by a photolithography process and etching; (D) forming the second interlayer insulating layer on the first interlayer insulating layer and in the first source opening; (E) forming the second source opening in the second interlayer insulating layer by a photolithography process and etching; (F) forming the source electrode on the second interlayer insulating layer and in the second source opening; The manufacturing method includes the steps of:

[0025] [Item 16] Item 5. A method for manufacturing an active matrix substrate according to item 5, (A) forming the oxide semiconductor layer, the gate insulating layer, and the gate electrode; (B) forming the first interlayer insulating layer so as to cover the gate electrode and the oxide semiconductor layer; (C) forming the first drain opening in the first interlayer insulating layer by a photolithography process and etching; (D) forming the second interlayer insulating layer on the first interlayer insulating layer and in the first drain opening; (E) forming the second drain opening in the second interlayer insulating layer by a photolithography process and etching; (F) forming the drain electrode on the second interlayer insulating layer and in the second drain opening; The manufacturing method includes the steps of: [Effects of the Invention]

[0026] According to the embodiments of the present invention, it is possible to improve the aperture ratio of an active matrix substrate and a display device that include an oxide semiconductor TFT with a top gate structure. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a schematic diagram showing an example of a planar structure of an active matrix substrate 100 according to an embodiment of the present invention. [Figure 2] FIG. 1 is a plan view schematically showing an active matrix substrate 100. [Figure 3] 3A is a cross-sectional view schematically showing the active matrix substrate 100, taken along line 3A-3A' in FIG. [Figure 4A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 4B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 4C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 5A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 5B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 5C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 6A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 6B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 6C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 7A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 7B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 8A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 8B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 9] FIG. 1 is a cross-sectional view schematically showing an active matrix substrate 900 of a comparative example. [Figure 10] FIG. 10 is a cross-sectional view schematically showing another active matrix substrate 200 according to an embodiment of the present invention. [Figure 11] FIG. 10 is a cross-sectional view schematically showing still another active matrix substrate 300 according to an embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view that schematically shows a liquid crystal display device 1000 that includes an active matrix substrate 100 (200, 300) according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following, an active matrix substrate for a liquid crystal display device that performs display in FFS (Fringe Field Switching) mode, which is a type of lateral electric field mode, will be exemplified as an embodiment of the present invention, but the present invention is not limited to the following embodiment.

[0029] [Embodiment 1] An active matrix substrate 100 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing an example of the planar structure of the active matrix substrate 100.

[0030] As shown in FIG. 1, the active matrix substrate 100 has a display region DR and a peripheral region (also called a "frame region" or "non-display region") FR. The display region DR includes a plurality of pixel regions P. The pixel regions P are arranged in a matrix having a plurality of rows and a plurality of columns. The pixel regions P correspond to the pixels of a liquid crystal display device, and may also be simply called "pixels." The peripheral region FR is located around the display region DR and does not contribute to display.

[0031] In the display region DR, a plurality of gate lines GL extending in the row direction and a plurality of source lines SL extending in the column direction are formed. Each pixel region P is, for example, a region surrounded by a pair of adjacent gate lines GL and a pair of adjacent source lines SL.

[0032] Peripheral circuits are arranged in the non-display region FR. Here, a gate driver GD that drives the gate lines GL is integrally (monolithically) formed in the non-display region FR, and a source driver SD that drives the source lines SL is also implemented. Note that a source shared driving (SSD) circuit that drives the source bus lines SL in a time-division manner may also be arranged in the non-display region FR, or the SSD circuit may be integrally formed like the gate driver GD.

[0033] In each pixel region P of the display region DR, a thin film transistor (TFT) 10 and a pixel electrode PE electrically connected to the TFT 10 are arranged. The TFT 10 arranged in each pixel region P is sometimes called a "pixel TFT." The pixel TFT 10 is supplied with a gate signal (scanning signal) from the corresponding gate line GL and with a source signal (display signal) from the corresponding source line SL.

[0034] Next, a more specific configuration of the active matrix substrate 100 will be described with reference to Figures 2 and 3. Figure 2 is a plan view schematically showing the active matrix substrate 100. Figure 3 is a cross-sectional view schematically showing the active matrix substrate 100, showing a cross section taken along line 3A-3A' in Figure 2.

[0035] The active matrix substrate 100 includes a substrate 1, pixel TFTs 10 supported by the substrate 1 and provided corresponding to each pixel region P, and pixel electrodes PE disposed in each pixel region P and electrically connected to the pixel TFTs 10. As already explained, the active matrix substrate 100 is for use in an FFS mode liquid crystal display device, and therefore further includes a common electrode CE.

[0036] The substrate 1 is transparent and insulating. In the example shown, a conductive light-shielding layer 2 is provided on the substrate 1, and a lower insulating layer 3 is provided to cover the light-shielding layer 2. The pixel TFT 10 is provided on the lower insulating layer 3.

[0037] The pixel TFT 10 has an oxide semiconductor layer 4, a gate insulating layer 5, a gate electrode 6, a source electrode 7, and a drain electrode 8. The pixel TFT 10 has a top gate structure.

[0038] The oxide semiconductor layer 4 is provided on the lower insulating layer 3. The oxide semiconductor layer 4 includes a channel region 4a, a source contact region 4b, and a drain contact region 4c. The channel region 4a overlaps the light-shielding layer 2 when viewed from the normal direction of the substrate 1 (i.e., in a plan view). The source contact region 4b and the drain contact region 4c are located on both sides of the channel region 4.

[0039] The gate insulating layer 5 is provided on the channel region 4a of the oxide semiconductor layer 4. The gate electrode 6 is provided on the gate insulating layer 5. The gate electrode 6 faces the channel region 4a via the gate insulating layer 5. The gate electrode 6 is electrically connected to the corresponding gate bus line GL. In the example shown, the gate electrode 6 is formed integrally with the gate bus line GL. More specifically, the portion of the gate bus line GL that overlaps with the oxide semiconductor layer 4 in a plan view functions as the gate electrode 6.

[0040] A first interlayer insulating layer 11 is provided so as to cover the gate electrode 6 and the oxide semiconductor layer 4. In addition, a second interlayer insulating layer 12 is provided on the first interlayer insulating layer 11.

[0041] The first interlayer insulating layer 11 has a first source opening 11a and a first drain opening 11b. The first source opening 11a is formed so as to expose at least a portion of the source contact region 4b. The first drain opening 11b is formed so as to expose at least a portion of the drain contact region 4c. The shapes of the first source opening 11a and the first drain opening 11b in plan view are generally circular in the illustrated example, but are not limited thereto and may be various shapes such as generally elliptical, generally rectangular, or generally regular polygonal.

[0042] The second interlayer insulating layer 12 has a second source opening 12a and a second drain opening 12b. The second source opening 12a is smaller than the first source opening 11a in a plan view and is formed so as to be located inside the first source opening 11a. The second drain opening 12b is smaller than the first drain opening 12a in a plan view and is formed so as to be located inside the first drain opening 12a. Note that the shapes of the second source opening 12a and the second drain opening 12b in a plan view are substantially circular in the illustrated example, but are not limited to this and may be various shapes such as substantially elliptical, substantially rectangular, or substantially regular polygonal.

[0043] The source electrode 7 and the drain electrode 8 are provided on the second interlayer insulating layer 12. The source electrode 7 is electrically connected to the corresponding source bus line SL. In the example shown in the figure, the source electrode 7 is formed integrally with the source bus line SL. More specifically, the portion of the source bus line SL that overlaps with the oxide semiconductor layer 4 in a plan view functions as the source electrode 7. The source electrode 7 is also electrically connected to the source contact region 4b of the oxide semiconductor layer 4. As shown in FIG. 3, the source electrode 7 is connected to the source contact region 4b at the second source opening 12a. That is, the second source opening 12a functions as a source contact hole.

[0044] The drain electrode 8 is electrically connected to the pixel electrode PE. The drain electrode 8 is also electrically connected to the drain contact region 4c of the oxide semiconductor layer 4. As shown in Fig. 3, the drain electrode 8 is connected to the drain contact region 4c at the second drain opening 12b. That is, the second drain opening 12b functions as a drain contact hole.

[0045] A third interlayer insulating layer 13 is formed to cover the pixel TFT 10. The third interlayer insulating layer 13 may be, for example, an organic insulating layer made of an organic insulating material. The third interlayer insulating layer 13 may have a layered structure including an inorganic insulating layer made of an inorganic insulating material and an organic insulating layer provided on the inorganic insulating layer.

[0046] The common electrode CE is provided on the third interlayer insulating layer 13. A dielectric layer 14 is provided so as to cover the common electrode CE.

[0047] The pixel electrode PE is provided on the dielectric layer 14. The pixel electrode PE is connected to the dielectric layer 14 through a pixel contact hole CH formed in the third interlayer insulating layer 13. P , it is connected to the drain electrode 8 of the pixel TFT 10. Although not shown here, the pixel electrode PE has at least one slit (opening).

[0048] The active matrix substrate 100 is used in an FFS mode liquid crystal display device. The FFS mode is a horizontal electric field display mode in which a pair of electrodes is provided on one of the substrates and an electric field is applied to the liquid crystal molecules in a direction parallel to the substrate surface (horizontal direction). In this example, an electric field represented by electric field lines is generated that extends from the pixel electrode PE, passes through the liquid crystal layer (not shown), and then passes through slit-shaped openings in the pixel electrode PE to the common electrode CE. This electric field has a component horizontal to the liquid crystal layer. The horizontal electric field mode has the advantage of achieving a wider viewing angle than the vertical electric field mode, because the liquid crystal molecules do not rise from the substrate.

[0049] An electrode structure in which a pixel electrode PE is disposed on a common electrode CE via a dielectric layer 14 is disclosed, for example, in International Publication No. 2012 / 086513. Note that the common electrode CE may also be disposed on the pixel electrode PE via a dielectric layer 14. Such an electrode structure is described, for example, in Japanese Patent Application Laid-Open Nos. 2008-032899 and 2010-008758. For reference, the disclosures of International Publication Nos. 2012 / 086513, 2008-032899, and 2010-008758 are incorporated herein by reference in their entirety.

[0050] 4A to 8B, a method for manufacturing the active matrix substrate 100 according to this embodiment will be described. 4A to 8B are cross-sectional views illustrating the steps in the method for manufacturing the active matrix substrate 100.

[0051] 4A, a light-shielding layer 2 is formed on a substrate 1. Specifically, a conductive film for the light-shielding layer (thickness: for example, 50 nm or more and 500 nm or less) is formed on an insulating substrate 1 by a sputtering method or the like, and then the conductive film is patterned to form the light-shielding layer 2.

[0052] The substrate 1 may be, for example, a glass substrate or a heat-resistant plastic substrate (resin substrate).

[0053] The conductive film for the light-shielding layer can be, for example, a metal film containing an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy film containing these elements. A laminated film containing multiple films of these elements can also be used. For example, a laminated film having a three-layer structure of titanium film-aluminum film-titanium film or a three-layer structure of molybdenum film-aluminum film-molybdenum film can be used. The conductive film for the light-shielding layer is not limited to a three-layer structure, but can also have a single-layer structure, a two-layer structure, or a laminated structure of four or more layers. Here, a laminated film with a Ti film (thickness: 15 nm to 70 nm) as the lower layer and a Cu film (thickness: 200 nm to 400 nm) as the upper layer is used as the conductive film for the light-shielding layer.

[0054] Next, as shown in FIG. 4B, a lower insulating layer 3 (thickness: for example, 200 nm or more and 500 nm or less) is formed so as to cover the light-shielding layer 2.

[0055] The lower insulating layer 3 may be a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy;x>y) layer, a silicon nitride oxide (SiNxOy;x>y) layer, an aluminum oxide layer, or a tantalum oxide layer, as appropriate. The lower insulating layer 3 may have a laminated structure. Here, for example, a CVD method is used to form the lower insulating layer 3 having a laminated film structure with a silicon nitride layer (thickness: 100 nm to 500 nm) as a lower layer and a silicon oxide layer (thickness: 20 nm to 300 nm) as an upper layer.

[0056] 4C, an oxide semiconductor layer 4 is formed on the lower insulating layer 3. The oxide semiconductor layer 4 is obtained, for example, by forming an oxide semiconductor film (thickness: for example, 15 nm to 200 nm) by a sputtering method and then patterning the oxide semiconductor film by a photolithography process. The oxide semiconductor film is not particularly limited, but may be, for example, an In-Ga-Zn-O based semiconductor film.

[0057] Then, as shown in FIG. 5A, a gate insulating layer 5 and a gate electrode 6 are formed on the oxide semiconductor layer 4. Specifically, first, an insulating film (thickness: e.g., 80 nm to 250 nm) and a gate conductive film (thickness: e.g., 50 nm to 500 nm) are formed in this order to cover the oxide semiconductor layer 4. The insulating film can be formed, for example, by a CVD method, and the gate conductive film can be formed, for example, by a sputtering method. The insulating film can be an insulating film similar to the lower insulating layer 3 (the insulating film exemplified as the lower insulating layer 3). The gate conductive film can be a conductive film similar to the light-shielding layer conductive film. Here, for example, a silicon oxide film is used as the insulating film, and the gate conductive film is a stacked film having a Ti film (thickness: 15 nm to 70 nm) as a lower layer and a Cu film (thickness: 200 nm to 400 nm) as an upper layer. Next, the gate conductive film is patterned to form a gate electrode 6, and the insulating film is patterned to form a gate insulating layer 5. The gate conductive film can be patterned by, for example, wet etching or dry etching, and the insulating film can be patterned by, for example, dry etching.

[0058] Thereafter, the oxide semiconductor layer 4 is subjected to a resistance reduction treatment using the gate electrode 6 as a mask. The resistance reduction treatment is, for example, a plasma treatment. As a result, the regions of the oxide semiconductor layer 4 that do not overlap with the gate electrode 6 and the gate insulating layer 5 become low-resistance regions (source contact region 4b and drain contact region 4c) that have a lower resistivity than the regions that overlap with the gate electrode 6 and the gate insulating layer 5 (channel region 4a).

[0059] Next, as shown in FIG. 5B, a first interlayer insulating layer 11 is formed to cover the gate electrode 6 and the oxide semiconductor layer 4. The first interlayer insulating layer 11 can be formed by, for example, a CVD method. The thickness of the first interlayer insulating layer 11 is, for example, 300 nm or more and 800 nm or less. The first interlayer insulating layer 11 can be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer.

[0060] 5C, a first source opening 11a and a first drain opening 11b are formed in the first interlayer insulating layer 11 so as to expose at least a portion of the source contact region 4b and at least a portion of the drain contact region 4c of the oxide semiconductor layer 4. Specifically, the first source opening 11a and the first drain opening 11b can be formed by a photolithography process and etching. The etching can be, for example, dry etching. The photoresist layer formed by the photolithography process is stripped after etching.

[0061] Next, as shown in FIG. 6A, a second interlayer insulating layer 12 is formed on the first interlayer insulating layer 11 and in the first source opening 11a and the first drain opening 11b. The second interlayer insulating layer 12 can be formed, for example, by a CVD method. The thickness of the second interlayer insulating layer 11 is, for example, 50 nm or more and 200 nm or less. The second interlayer insulating layer 12 can be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. The second interlayer insulating layer 12 may have a stacked structure.

[0062] Next, as shown in FIG. 6B, second source openings 12a and second drain openings 12b are formed in the second interlayer insulating layer 12. The second source openings 12a are formed to be smaller than the first source openings 11a in a plan view and to be located inside the first source openings 11a. The second drain openings 12b are formed to be smaller than the first drain openings 12a in a plan view and to be located inside the first drain openings 12a. Specifically, the formation of the second source openings 12a and the second drain openings 12b can be performed by a photolithography process and etching. The etching can be, for example, dry etching. The photoresist layer formed by the photolithography process is peeled off after etching.

[0063] Next, as shown in FIG. 6C , a source electrode 7 is formed on the second interlayer insulating layer 12 and in the second source opening 12a, and a drain electrode 8 is formed on the second interlayer insulating layer 12 and in the second drain opening 12b. Specifically, a source conductive film (thickness: e.g., 50 nm to 500 nm) is formed on the second interlayer insulating layer 12 and in the second source opening 12a and the second drain opening 12b, and then the source conductive film is patterned to form the source electrode 7 and the drain electrode 8. The source conductive film can be patterned by, for example, dry etching or wet etching. The source conductive film may be made of an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy containing any of these elements. For example, the source conductive film may have a three-layer structure of titanium film-aluminum film-titanium film, or a three-layer structure of molybdenum film-aluminum film-molybdenum film. The source conductive film is not limited to a three-layer structure, but may have a single layer, a two-layer structure, or a laminated structure of four or more layers. Here, a laminated film is used, with a Ti film (thickness: 15 nm to 70 nm) as the lower layer and a Cu film (thickness: 200 nm to 400 nm) as the upper layer.

[0064] 7A, a third interlayer insulating layer 13 is formed to cover the pixel TFT 10. Here, an organic insulating layer (thickness: for example, 1 μm to 3 μm, preferably 2 μm to 3 μm) is formed using a photosensitive resin material as the third interlayer insulating layer 13. An opening 13a overlapping at least a portion of the drain electrode 8 is formed in the third interlayer insulating layer 13.

[0065] Next, as shown in FIG. 7B, a common electrode CE is formed on the third interlayer insulating layer 13. Specifically, after a transparent conductive film (thickness: for example, 20 nm or more and 300 nm or less) is formed on the third interlayer insulating layer 13, the transparent conductive film is patterned to form the common electrode CE. Here, for example, an indium-zinc oxide film is formed as the transparent conductive film by sputtering, and then patterned by wet etching. Metal oxides such as indium-tin oxide (ITO), indium-zinc oxide, and ZnO can be used as materials for the transparent electrode film.

[0066] 8A, a dielectric layer 14 (thickness: for example, 50 nm to 500 nm) is formed on the third interlayer insulating layer 13 and the common electrode CE. The material of the dielectric layer 14 may be the same as the material exemplified for the first interlayer insulating layer 11. Here, a silicon nitride film is formed as the dielectric layer 14 by, for example, a CVD method.

[0067] 8B, an opening 14a that overlaps at least a portion of the drain electrode 8 is formed in the dielectric layer 14. The opening 14a can be formed by, for example, dry etching. As a result, a pixel contact hole CHp that exposes at least a portion of the drain electrode 8 is obtained.

[0068] Thereafter, the pixel electrode PE (thickness: for example, 20 nm to 300 nm) is formed on the dielectric layer 14, thereby obtaining the active matrix substrate 100 shown in FIG. 3 and the like. Specifically, the pixel electrode PE can be formed by forming a transparent conductive film on the dielectric layer 14 and then patterning the transparent conductive film. The material of the transparent conductive film for the pixel electrode PE may be the same as the material exemplified for the transparent conductive film for the common electrode CE. Here, an indium-zinc oxide film is formed as the transparent conductive film by sputtering, and then patterned by wet etching.

[0069] Here, advantages of the active matrix substrate 100 of this embodiment will be explained in comparison with an active matrix substrate 900 of a comparative example shown in FIG.

[0070] The active-matrix substrate 900 of the comparative example differs from the active-matrix substrate 100 of the present embodiment in that it does not include a second interlayer insulating layer 12. In the active-matrix substrate 900 of the comparative example, the source electrode 7 and the drain electrode 8 are connected to the source contact region 4b and the drain contact region 4c of the oxide semiconductor layer 4 through first source openings 11a and first drain openings 11b formed in the first interlayer insulating layer 11. In other words, the first source openings 11a and first drain openings 11b of the first interlayer insulating layer 11 function as source contact holes and drain contact holes.

[0071] Generally, the thicker the insulating layer in which the contact holes are formed, the larger the hole diameter. Therefore, in the active matrix substrate 900 of the comparative example, if the thickness of the first interlayer insulating layer 11 is made sufficiently large to ensure sufficient insulation between the gate metal layer (a collective term for electrodes and wiring formed from a gate conductive film) and the source metal layer (a collective term for electrodes and wiring formed from a source conductive film), the hole diameters of the source contact hole (first source opening 11a) and the drain contact hole (first drain opening 11b) will become large.

[0072] In contrast, in the active matrix substrate 100 of this embodiment, a first interlayer insulating layer 11 and a second interlayer insulating layer 12 are provided between the gate metal layer and the source metal layer, and the second interlayer insulating layer 12 is formed with a second source opening 12a that is smaller than the first source opening 11a of the first interlayer insulating layer 11 and positioned inside the first source opening 11a, and a second drain opening 12b that is smaller than the first drain opening 12a of the first interlayer insulating layer 11 and positioned inside the first drain opening 12a. The second source opening 12a and the second drain opening 12b of the second interlayer insulating layer 12 function as a source contact hole and a drain contact hole, respectively. Therefore, even if the total thickness of first interlayer insulating layer 11 and second interlayer insulating layer 12 is sufficiently large to ensure sufficient insulation between the gate metal layer and the source metal layer, the thickness of second interlayer insulating layer 12 itself, in which second source opening 12a and second drain opening 12b, which function as contact holes, are formed, can be made relatively small, thereby reducing the diameters of the source contact hole (second source opening 12a) and the drain contact hole (second drain opening 12b). Furthermore, because second source opening 12a is located within first source opening 11a, the thickness of the photoresist layer formed on second interlayer insulating layer 12 in the photolithography process for forming second source opening 12a is thicker near the sidewall of first source opening 11a. Therefore, the shift amount during dry etching is smaller near the sidewall of first source opening 11a, which also reduces the diameter of the source contact hole. Similarly, because the second drain opening 12b is located within the first drain opening 11b, the thickness of the photoresist layer is thicker near the sidewall of the first drain opening 11b. Therefore, the shift amount during dry etching is smaller near the sidewall of the first drain opening 11b, which also makes it possible to reduce the diameter of the drain contact hole. Furthermore, because the diameter of the source contact hole can be reduced, the width of the source bus line SL can also be reduced.As described above, in the active matrix substrate 100 of this embodiment, the size of the pixel TFTs 10 can be reduced and the wiring can be made finer, thereby improving the aperture ratio. Therefore, even if the pixel size is reduced to increase the resolution of the display device, the aperture ratio can be improved or maintained.

[0073] The thinner the second interlayer insulating layer 12, the smaller the shift amount (lateral spread) during dry etching when forming the second source opening 12a and the second drain opening 12b, allowing for further miniaturization of the source contact holes and the drain contact holes. Furthermore, the thinner the second interlayer insulating layer 12, the thinner the photoresist layer formed on the second interlayer insulating layer 12 in the photolithography process, allowing for higher resolution during exposure, thereby allowing for further miniaturization of the source contact holes and the drain contact holes. Therefore, from the perspective of further miniaturizing the source contact holes and the drain contact holes, the thickness t2 of the second interlayer insulating layer 12 is preferably smaller than the thickness t1 of the first interlayer insulating layer 11. Specifically, the thickness t2 of the second interlayer insulating layer 12 is preferably 200 nm or less, and more preferably 150 nm or less.

[0074] The size ratio between first source opening 11a and second source opening 12a in a plan view is not particularly limited, but the circle-equivalent diameter of second source opening 12a is, for example, 25% or less of the circle-equivalent diameter of first source opening 11a. Similarly, the size ratio between first drain opening 11b and second drain opening 12b in a plan view is not particularly limited, but the circle-equivalent diameter of second drain opening 12b is, for example, 25% or less of the circle-equivalent diameter of first drain opening 11b.

[0075] Furthermore, if the second interlayer insulating layer 12 is a silicon nitride layer or has a stacked structure including a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer, it becomes easier to form tapered shapes on the sidewalls of the second source opening 12 a and the second drain opening 12 b.

[0076] [Embodiment 2] An active matrix substrate 200 according to this embodiment will be described with reference to Fig. 10. Fig. 10 is a cross-sectional view schematically showing the active matrix substrate 200. The following description will focus on differences between the active matrix substrate 200 and the active matrix substrate 100 according to the first embodiment.

[0077] The structure of the display region DR (pixel region P) is shown on the right side of Fig. 10, and the structure of the peripheral region FR is shown on the left side of Fig. 10. The structure of the display region DR of the active matrix substrate 200 is substantially the same as the structure of the display region DR of the active matrix substrate 100 of embodiment 1, and therefore a description thereof will be omitted.

[0078] As shown in FIG. 10, the peripheral region FR of the active matrix substrate 200 has a first connection portion CP1 and a second connection portion CP2.

[0079] The first connection portion CP1 electrically connects a first wiring 15 formed from the same conductive film (i.e., a gate conductive film) as the gate electrode 6, and a second wiring 16 formed from the same conductive film (i.e., a source conductive film) as the source electrode 7 and the drain electrode 8.

[0080] In the peripheral region FR, the first interlayer insulating layer 11 has a first gate opening 11c formed to expose at least a portion of the first wiring 15. The second interlayer insulating layer 12 has a second gate opening 12c formed to be smaller than the first gate opening 11c in a plan view and positioned inside the first gate opening 11c. The second wiring 16 is connected to the first wiring 15 at the second gate opening 12c.

[0081] The second connection portion CP2 electrically connects the third wiring 17 formed from the same conductive film as the light-shielding layer 2 (i.e., the conductive film for the light-shielding layer) to the fourth wiring 18 formed from the same conductive film as the source electrode 7 and the drain electrode 8 (i.e., the conductive film for the source).

[0082] In the peripheral region FR, the first interlayer insulating layer 11 has a first bottom opening 11d formed to expose at least a portion of the third wiring 17. The lower insulating layer 3 has a second bottom opening 3d formed to be smaller than the first bottom opening 11d and positioned inside the first bottom opening 11d in a plan view. The second interlayer insulating layer 12 has a third bottom opening 12d formed to be smaller than the first bottom opening 11d and positioned inside the first bottom opening 11d in a plan view. The third bottom opening 12d is continuous with the second bottom opening 3d. The fourth wiring 18 is connected to the third wiring 17 through the second bottom opening 3d and the third bottom opening 12d.

[0083] In the active matrix substrate 200 of this embodiment, in the first connection portion CP1 in the peripheral region FR, the second gate opening 12c of the second interlayer insulating layer 12 functions as a contact hole as described above, and therefore, for the same reasons as the source contact holes and drain contact holes in the pixel region P, the contact holes can be made smaller.

[0084] Furthermore, in the second connection portion CP2 in the peripheral region FR, as described above, the second bottom opening 3d in the lower insulating layer 3 and the third bottom opening 12d in the second interlayer insulating layer 12 function as contact holes, thereby enabling the contact holes to be miniaturized in the second connection portion CP2 as well. When electrically connecting the lower metal layer (a collective term for electrodes and wiring formed from a conductive film for a light-shielding layer) and the source metal layer, the etching depth is greater by the amount of the lower insulating layer 3 than when electrically connecting the gate metal layer and the source metal layer, and therefore the diameter of the contact hole is likely to be larger. Furthermore, it is necessary to form the opening in the lower insulating layer 3 while maintaining a selectivity so as not to over-etch the oxide semiconductor layer 4.

[0085] In this embodiment, the second bottom opening 3d and the third bottom opening 12d are formed smaller than the first bottom opening 11d of the first interlayer insulating layer 11 so as to be positioned inside the first bottom opening 11d, and are made to function as contact holes, thereby making it possible to suitably miniaturize the contact holes also in the second connection portion CP2.

[0086] [Other configuration examples] In the first and second embodiments, the second source opening 12a located inside the first source opening 11a is used as the source contact hole, and the second drain opening 12b located inside the first drain opening 11b is used as the drain contact hole, thereby enabling miniaturization of both the source contact hole and the drain contact hole. However, the embodiments of the present invention are not limited to such configurations. The embodiments of the present invention may also be configured such that a structure in which an opening in the second interlayer insulating layer 12 is formed so as to be located inside the opening in the first interlayer insulating layer 11 is applied to only one of the source contact hole and the drain contact hole, thereby enabling miniaturization of only one of the source contact hole and the drain contact hole. An example of such a configuration is shown in FIG. 11.

[0087] In the active matrix substrates 100 and 200 of Embodiments 1 and 2, the source bus lines SL and the source electrodes 7 are provided on the second interlayer insulating layer 12. In contrast, in the active matrix substrate 300 shown in FIG. 11 , the source bus lines SL and the source electrodes 7 are provided below the lower insulating layer 3. That is, the source bus lines SL and the source electrodes 7 are covered by the lower insulating layer 3. The source bus lines SL and the source electrodes 7 may be formed from the same conductive film (conductive film for light-shielding layer) as the light-shielding layer 2. The source contact region 4b of the oxide semiconductor layer 4 and the source electrode 7 are connected through an opening 3e formed in the lower insulating layer 3. That is, the opening 3e in the lower insulating layer 3 functions as a source contact hole.

[0088] 11, the second drain opening 12b of the second interlayer insulating layer 12 also functions as a drain contact hole, so that the drain contact hole can be made smaller. Although not shown here, it goes without saying that a configuration can be adopted in which only the source contact hole is made smaller.

[0089] [About oxide semiconductors] The oxide semiconductor contained in the oxide semiconductor layer 4 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of crystalline oxide semiconductors include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors whose c-axes are oriented approximately perpendicular to the layer surface.

[0090] The oxide semiconductor layer 4 may have a stacked structure of two or more layers. The oxide semiconductor layer 4 having a stacked structure may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer, or may include multiple crystalline oxide semiconductor layers with different crystal structures. The oxide semiconductor layer 4 having a stacked structure may also include multiple amorphous oxide semiconductor layers. When the oxide semiconductor layer 4 has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor in the lower layer is preferably larger than that of the oxide semiconductor in the upper layer. However, when the difference in energy gap between these layers is relatively small, the energy gap of the oxide semiconductor in the upper layer may be larger than that of the oxide semiconductor in the lower layer.

[0091] The materials, structures, film formation methods, and configurations of oxide semiconductor layers having a stacked structure of the amorphous oxide semiconductor and the above-mentioned crystalline oxide semiconductors are described, for example, in JP 2014-007399 A. The entire disclosure of JP 2014-007399 A is incorporated herein by reference.

[0092] The oxide semiconductor layer 4 may contain at least one metal element selected from the group consisting of In, Ga, and Zn. In an embodiment of the present invention, the oxide semiconductor layer 4 contains, for example, an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer 11 can be formed from an oxide semiconductor film containing an In-Ga-Zn-O-based semiconductor.

[0093] The In-Ga-Zn-O based semiconductor may be amorphous or crystalline, and a crystalline In-Ga-Zn-O based semiconductor with its c-axis oriented generally perpendicular to the layer plane is preferred as the crystalline In-Ga-Zn-O based semiconductor.

[0094] The crystal structure of crystalline In-Ga-Zn-O-based semiconductors is disclosed, for example, in the aforementioned Japanese Patent Application Laid-Open Nos. 2014-007399, 2012-134475, and 2014-209727. The disclosures of Japanese Patent Application Laid-Open Nos. 2012-134475 and 2014-209727 are incorporated herein by reference in their entirety. TFTs having an In-Ga-Zn-O-based semiconductor layer have high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one-hundredth that of an a-Si TFT). Therefore, they are suitable for use as driver TFTs (e.g., TFTs included in a driver circuit provided on the same substrate as a display area, around a display area including multiple pixels) and pixel TFTs (TFTs provided in pixels).

[0095] The oxide semiconductor layer 4 may contain other oxide semiconductors instead of the In-Ga-Zn-O-based semiconductor. For example, it may contain an In-Sn-Zn-O-based semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer 4 may include an In-Al-Zn-O based semiconductor, an In-Al-Sn-Zn-O based semiconductor, a Zn-O based semiconductor, an In-Zn-O based semiconductor, a Zn-Ti-O based semiconductor, a Cd-Ge-O based semiconductor, a Cd-Pb-O based semiconductor, CdO (cadmium oxide), an Mg-Zn-O based semiconductor, an In-Ga-Sn-O based semiconductor, an In-Ga-O based semiconductor, a Zr-In-Zn-O based semiconductor, an Hf-In-Zn-O based semiconductor, an Al-Ga-Zn-O based semiconductor, a Ga-Zn-O based semiconductor, an In-Ga-Zn-Sn-O based semiconductor, or the like.

[0096] [Liquid crystal display device] The active matrix substrates 100, 200 and 300 according to the embodiments of the present invention can be suitably used in a liquid crystal display device. An example of a liquid crystal display device is shown in FIG.

[0097] The liquid crystal display device 1000 shown in Figure 12 includes an active matrix substrate 100 (or active matrix substrates 200, 300), a counter substrate 600 arranged opposite to the active matrix substrate 100, and a liquid crystal layer 30 arranged between the active matrix substrate 100 and the counter substrate 600.

[0098] The active matrix substrate 100 includes a TFT 10 (not shown) disposed in each pixel region P, a pixel electrode PE electrically connected to the TFT 10, a dielectric layer 14 provided to cover the pixel electrode PE, and a common electrode CE provided on the dielectric layer 14 and facing the pixel electrode PE. At least one slit s is formed in the common electrode CE for each pixel region P.

[0099] Alignment films 31 and 32 are provided on the outermost surfaces of the active matrix substrate 100 and the counter substrate 600 facing the liquid crystal layer 30. The counter substrate 600 typically has a color filter layer and a black matrix (neither of which are shown).

[0100] The thickness (cell gap) of the liquid crystal layer 30 can be determined by columnar spacers (not shown here) provided on the liquid crystal layer 30 side of the counter substrate 600.

[0101] Although the liquid crystal display device 1000 shown here is an FFS mode liquid crystal display device, which is a type of lateral electric field mode, the active matrix substrate according to the embodiment of the present invention may be used in liquid crystal display devices of other display modes. In a liquid crystal display device of a vertical electric field mode, such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, the common electrode is provided on the opposing substrate side.

[0102] Furthermore, the display device according to the embodiment of the present invention is not limited to a liquid crystal display device, but may be another display device, such as an organic EL display device, which includes an organic EL layer provided on pixel electrodes. [Industrial Applicability]

[0103] According to the embodiment of the present invention, it is possible to improve the aperture ratio of an active matrix substrate and a display device including an oxide semiconductor TFT with a top-gate structure. The active matrix substrate according to the embodiment of the present invention is suitable for use in various display devices such as liquid crystal display devices and organic EL display devices. [Explanation of symbols]

[0104] 1 board 2 Light blocking layer 3 Lower insulating layer 3d Second bottom opening 4. Oxide semiconductor layer 4c Channel region 4b Source contact region 4c Drain contact area 5 Gate insulating layer 6 gate electrode 7. Source electrode 8 Drain electrode 10 pixel TFT 11 First interlayer insulating layer 11a First source opening 11b First drain opening 11c First Gate Opening 11d First bottom opening 12 Second interlayer insulating layer 12a Second source opening 12b Second drain opening 12c Second Gate Opening 12d Third bottom opening 13 Third interlayer insulating layer 14 Dielectric layer 30 Liquid crystal layer 31, 32 Alignment film 100, 200, 300 Active matrix substrate 600 Opposing substrate 1000 lcd display device DR display area FR hidden area P pixel area PE pixel electrode CE common electrode GL gate wiring SL Source wiring GD Gate driver SD Source Driver CH P Pixel Contact Hole CP1 First connection part CP2 Second connection part

Claims

1. a display area including a plurality of pixel areas and a peripheral area located around the display area; A substrate; pixel TFTs supported by the substrate and provided corresponding to each of the plurality of pixel regions; a pixel electrode disposed in each of the plurality of pixel regions and electrically connected to the pixel TFT; Equipped with The pixel TFT is an oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on both sides of the channel region; a gate insulating layer provided on the channel region of the oxide semiconductor layer; a gate electrode provided on the gate insulating layer and facing the channel region with the gate insulating layer interposed therebetween; a source electrode electrically connected to the source contact region of the oxide semiconductor layer; An active matrix substrate having: a first interlayer insulating layer covering the gate electrode and the oxide semiconductor layer; a second interlayer insulating layer provided on the first interlayer insulating layer; Furthermore, the source electrode is provided on the second interlayer insulating layer, the first interlayer insulating layer has a first source opening formed to expose at least a portion of the source contact region; the second interlayer insulating layer has a second source opening that is smaller than the first source opening in plan view and is formed so as to be located inside the first source opening; the source electrode is connected to the source contact region at the second source opening.

2. the pixel TFT has a drain electrode electrically connected to the drain contact region of the oxide semiconductor layer; the drain electrode is provided on the second interlayer insulating layer, the first interlayer insulating layer has a first drain opening formed to expose at least a portion of the drain contact region; the second interlayer insulating layer has a second drain opening that is smaller than the first drain opening in a plan view and is formed so as to be located inside the first drain opening; The active matrix substrate according to claim 1 , wherein the drain electrode is connected to the drain contact region at the second drain opening.

3. the peripheral region has a first connection portion that electrically connects a first wiring formed from the same conductive film as the gate electrode and a second wiring formed from the same conductive film as the source electrode, the first interlayer insulating layer has a first gate opening formed to expose at least a portion of the first wiring; the second interlayer insulating layer has a second gate opening that is smaller than the first gate opening in plan view and is positioned inside the first gate opening; 3. The active matrix substrate according to claim 1, wherein the second wiring is connected to the first wiring at the second gate opening.

4. a conductive light-shielding layer provided on the substrate; a lower insulating layer covering the light-shielding layer; Furthermore, the oxide semiconductor layer is provided on the lower insulating layer, the peripheral region has a second connection portion that electrically connects a third wiring formed from the same conductive film as the light-shielding layer and a fourth wiring formed from the same conductive film as the source electrode, the first interlayer insulating layer has a first bottom opening formed to expose at least a portion of the third wiring; the lower insulating layer has a second bottom opening that is smaller than the first bottom opening in plan view and is positioned inside the first bottom opening; the second interlayer insulating layer has a third bottom opening that is smaller than the first bottom opening in a plan view, is formed so as to be located inside the first bottom opening, and is continuous with the second bottom opening; 3. The active matrix substrate according to claim 1, wherein the fourth wiring is connected to the third wiring in the second bottom opening and the third bottom opening.

5. a display area including a plurality of pixel areas and a peripheral area located around the display area; A substrate; pixel TFTs supported by the substrate and provided corresponding to each of the plurality of pixel regions; a pixel electrode disposed in each of the plurality of pixel regions and electrically connected to the pixel TFT; Equipped with The pixel TFT is an oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on both sides of the channel region; a gate insulating layer provided on the channel region of the oxide semiconductor layer; a gate electrode provided on the gate insulating layer and facing the channel region with the gate insulating layer interposed therebetween; a drain electrode electrically connected to the drain contact region of the oxide semiconductor layer; An active matrix substrate having: a first interlayer insulating layer covering the gate electrode and the oxide semiconductor layer; a second interlayer insulating layer provided on the first interlayer insulating layer; Furthermore, the drain electrode is provided on the second interlayer insulating layer, the first interlayer insulating layer has a first drain opening formed to expose at least a portion of the drain contact region; the second interlayer insulating layer has a second drain opening that is smaller than the first drain opening in a plan view and is formed so as to be located inside the first drain opening; the drain electrode is connected to the drain contact region at the second drain opening.

6. the peripheral region has a first connection portion that electrically connects a first wiring formed from the same conductive film as the gate electrode and a second wiring formed from the same conductive film as the drain electrode, the first interlayer insulating layer has a first gate opening formed to expose at least a portion of the first wiring; the second interlayer insulating layer has a second gate opening that is smaller than the first gate opening in plan view and is positioned inside the first gate opening; The active matrix substrate according to claim 5 , wherein the second wiring is connected to the first wiring at the second gate opening.

7. a conductive light-shielding layer provided on the substrate; a lower insulating layer covering the light-shielding layer; Furthermore, the oxide semiconductor layer is provided on the lower insulating layer, the peripheral region has a second connection portion that electrically connects a third wiring formed from the same conductive film as the light-shielding layer and a fourth wiring formed from the same conductive film as the drain electrode, the first interlayer insulating layer has a first bottom opening formed to expose at least a portion of the third wiring; the lower insulating layer has a second bottom opening that is smaller than the first bottom opening in plan view and is positioned inside the first bottom opening; the second interlayer insulating layer has a third bottom opening that is smaller than the first bottom opening in a plan view, is formed so as to be located inside the first bottom opening, and is continuous with the second bottom opening; 7. The active matrix substrate according to claim 5, wherein the fourth wiring is connected to the third wiring in the second bottom opening and the third bottom opening.

8. 6. The active matrix substrate according to claim 1, wherein the second interlayer insulating layer has a thickness smaller than that of the first interlayer insulating layer.

9. 6. The active matrix substrate according to claim 1, wherein the second interlayer insulating layer has a thickness of 200 nm or less.

10. 6. The active matrix substrate according to claim 1, wherein the second interlayer insulating layer is a silicon nitride layer or has a laminated structure including a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer.

11. 6. The active matrix substrate according to claim 1, wherein the oxide semiconductor layer includes an In--Ga--Zn--O based semiconductor.

12. 12. The active matrix substrate according to claim 11, wherein the In--Ga--Zn--O based semiconductor includes a crystalline portion.

13. A display device comprising the active matrix substrate according to claim 1 or 5.

14. an opposing substrate disposed opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; The display device according to claim 13, which is a liquid crystal display device comprising:

15. A method for manufacturing an active matrix substrate according to claim 1, comprising the steps of: (A) forming the oxide semiconductor layer, the gate insulating layer, and the gate electrode; (B) forming the first interlayer insulating layer so as to cover the gate electrode and the oxide semiconductor layer; (C) forming the first source opening in the first interlayer insulating layer by a photolithography process and etching; (D) forming the second interlayer insulating layer on the first interlayer insulating layer and in the first source opening; (E) forming the second source opening in the second interlayer insulating layer by a photolithography process and etching; (F) forming the source electrode on the second interlayer insulating layer and in the second source opening; The manufacturing method includes the steps of:

16. 6. A method for manufacturing an active matrix substrate according to claim 5, comprising the steps of: (A) forming the oxide semiconductor layer, the gate insulating layer, and the gate electrode; (B) forming the first interlayer insulating layer so as to cover the gate electrode and the oxide semiconductor layer; (C) forming the first drain opening in the first interlayer insulating layer by a photolithography process and etching; (D) forming the second interlayer insulating layer on the first interlayer insulating layer and in the first drain opening; (E) forming the second drain opening in the second interlayer insulating layer by a photolithography process and etching; (F) forming the drain electrode on the second interlayer insulating layer and in the second drain opening; The manufacturing method includes the steps of:

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