Semiconductor device

Abstract

To provide a semiconductor device including a transistor with low on resistance and high withstanding voltage.SOLUTION: A semiconductor device according to this embodiment includes a first semiconductor layer, a first transistor, and a second transistor. The first semiconductor layer includes a first surface and a second surface on the opposite side of the first surface, and includes a concave region depressed from the first surface toward the second surface, and a convex region of the first semiconductor layer that projects with respect to the concave region. The first transistor includes a first gate insulating film provided in the convex region of the first semiconductor layer, a side part gate insulating film provided at a side wall of the convex region, a first gate electrode provided on the first gate insulating film, and a side part gate electrode provided on the side part gate insulating film and connected to the first gate electrode. The second transistor includes a second gate insulating film that is provided on the convex region and is thinner than the first gate insulating film, and a second gate electrode provided on the second gate insulating film.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices are known in which a plurality of transistors are formed on a semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-143850 [Patent Document 2] Patent Publication No. 2021-150508 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device is provided that includes a transistor having a low on-resistance and a high withstand voltage. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes a first semiconductor layer, a first transistor, and a second transistor. The first semiconductor layer includes a first surface and a second surface opposite the first surface, a concave region recessed from the first surface toward the second surface, and a convex region of the first semiconductor layer protruding from the concave region. The first transistor includes a first gate insulating film provided in the convex region of the first semiconductor layer, a side gate insulating film provided on a sidewall of the convex region, a first gate electrode provided on the first gate insulating film, and a side gate electrode provided on the side gate insulating film and connected to the first gate electrode. The second transistor includes a second gate insulating film provided on the convex region and thinner than the first gate insulating film, and a second gate electrode provided on the second gate insulating film. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a first embodiment. [Figure 3] FIG. [Figure 4] FIG. 1 is a cross-sectional view illustrating a memory cell having a three-dimensional structure. [Figure 5] FIG. 1 is a cross-sectional view illustrating a memory cell having a three-dimensional structure. [Figure 6] FIG. 2 is a plan view showing an example of the configuration of transistors that form the logic circuit of the CMOS chip according to the first embodiment. [Figure 7] 2 is a cross-sectional view showing an example of the configuration of a transistor that constitutes a logic circuit of the CMOS chip according to the first embodiment. FIG. [Figure 8] FIG. 2 is a plan view showing an example of the configuration of a transistor that constitutes a word line switch of the CMOS chip according to the first embodiment. [Figure 9] 3 is a cross-sectional view showing an example of the configuration of a transistor that constitutes a word line switch of the CMOS chip according to the first embodiment. [Figure 10] 3A to 3C are cross-sectional views showing an example of a method for manufacturing the transistor according to the first embodiment. [Figure 11] 11A to 11C are cross-sectional views showing an example of a method for manufacturing a transistor, following FIG. 10. [Figure 12] 12A to 12C are cross-sectional views showing an example of a method for manufacturing a transistor, following FIG. 11. [Figure 13] 13A to 13C are cross-sectional views showing an example of a method for manufacturing a transistor, following FIG. 12. [Figure 14] 14 is a cross-sectional view showing an example of a method for manufacturing a transistor, following FIG. 13. [Figure 15] 15A to 15C are cross-sectional views showing an example of a method for manufacturing a transistor, following FIG. 14. [Figure 16] FIG. 10 is a cross-sectional view showing an example of the configuration of a transistor that configures a word line switch according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual. In the specification and drawings, the same elements are designated by the same reference numerals.

[0008] (First embodiment) 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to a first embodiment. The semiconductor memory device is, for example, a semiconductor memory such as a NAND flash memory. The semiconductor memory device includes a memory cell array MA and a peripheral circuit PC as a control circuit for controlling the memory cell array MA.

[0009] The memory cell array MA includes a plurality of memory blocks MB. Each of the memory blocks MB includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of the memory strings MS is connected to the peripheral circuit PC via a common source layer SL.

[0010] The memory string MS includes a drain-side select transistor STD connected in series between a bit line BL and a source layer SL, a plurality of memory cells MC, and a source-side select transistor STS. Hereinafter, the drain-side select transistor STD and the source-side select transistor STS may be simply referred to as select transistors STD, STS, etc.

[0011] A memory cell MC is a FET (Field Effect Transistor) that includes a semiconductor layer that functions as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of the memory cell MC changes depending on the amount of charge in the charge storage film. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. These word lines WL are connected in common to all memory strings MS in one memory block MB.

[0012] The memory cells MC are provided at the intersections of the word lines WL and the bit lines BL, and data can be written or read via the bit lines BL by applying a write voltage or a read voltage between the word lines WL and the bit lines BL. Data can also be erased from the memory cells MC by applying an erase voltage between the word lines WL and the bit lines BL.

[0013] The select transistors STD and STS are FETs that include a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. The gate electrodes of the select transistors STD and STS are connected to select gate lines SGD and SGS, respectively. The drain-side select gate line SGD is provided corresponding to the string unit SU and is commonly connected to all memory strings MS in one string unit SU. The source-side select gate line SGS is commonly connected to all memory strings MS in multiple string units SU in one memory block MB. A structure in which the source-side select transistor STS, memory cells MC, and drain-side select transistor STD are connected in series is called a "memory string" or "string unit."

[0014] The peripheral circuit PC includes an operating voltage generation circuit 121 that generates an operating voltage, an address decoder 122 that decodes address data, a block selection circuit 123 and a voltage selection circuit 124 that transfer the operating voltage to the memory cell array MA in accordance with the output signal of the address decoder 122, a sense amplifier module 125 connected to the bit line BL, and a sequencer 126 that controls these.

[0015] The operating voltage generation circuit 121 has a plurality of operating voltage output terminals 131. The operating voltage generation circuit 121 includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit. In accordance with control signals from the sequencer 126, the operating voltage generation circuit 121 sequentially generates a plurality of operating voltages to be applied to the bit lines BL, source layers SL, word lines WL, and select gate lines SGD and SGS during read, write, and erase operations on the memory cell array MA, and outputs the operating voltages to the plurality of operating voltage output terminals 131. The operating voltages output from the operating voltage output terminals 131 are adjusted as appropriate in accordance with the control signals from the sequencer 126.

[0016] The address decoder 122 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 133. The address decoder 122 sequentially references address data in the address register in accordance with, for example, a control signal from the sequencer 126, decodes the address data, and turns on the block drive transistors 135 and voltage selection transistors 137 corresponding to the address data, while turning off the other block drive transistors 135 and voltage selection transistors 137. For example, if the block drive transistors 135 and voltage selection transistors 137 are N-channel transistors, the voltages of the block selection line BLKSEL and voltage selection line 133 corresponding to the address data are set to the "H" state, and the other voltages are set to the "L" state. Note that if the block drive transistors 135 and voltage selection transistors 137 are P-channel transistors, reverse voltages may be applied to the block selection line BLKSEL and voltage selection line 133.

[0017] In the illustrated example, the address decoder 122 is provided with one block select line BLKSEL for each memory block MB. However, this configuration can be modified as appropriate. For example, the address decoder 122 may be provided with one block select line BLKSEL for each of two or more memory blocks MB.

[0018] The block selection circuit 123 includes a plurality of block selection units 134 corresponding to the memory blocks MB. Each of the plurality of block selection units 134 includes a plurality of block drive transistors 135 corresponding to the word lines WL and the select gate lines SGD, SGS. The block drive transistors 135 are, for example, high voltage (HV (High Voltage)) transistors. The drain electrodes (or source electrodes) of the block drive transistors 135 are electrically connected to the corresponding word lines WL or select gate lines SGD, SGS, respectively. The source electrodes (or drain electrodes) are electrically connected to the operating voltage output terminal 131 via the wiring CG and the voltage selection circuit 124, respectively. The gate electrodes are commonly connected to the corresponding block select lines BLKSEL.

[0019] The block selection circuit 123 further includes a plurality of transistors (not shown). These transistors are high-voltage (HV) transistors connected between the select gate lines SGD and SGS and a ground voltage supply terminal. These transistors electrically connect the select gate lines SGD and SGS included in the unselected memory blocks MB to the ground voltage supply terminal. The word lines WL included in the unselected memory blocks MB are in a floating state.

[0020] The voltage selection circuit 124 includes a plurality of voltage selection units 136 corresponding to the word lines WL and the select gate lines SGD, SGS. Each of the plurality of voltage selection units 136 includes a plurality of voltage selection transistors 137. The voltage selection transistors 137 are, for example, high-voltage (HV) transistors. The drain terminals (or source terminals) of the voltage selection transistors 137 are electrically connected to the corresponding word lines WL or select gate lines SGD, SGS via the wiring CG and the block selection circuit 123. The source terminals (or drain terminals) are electrically connected to the corresponding operating voltage output terminals 131. The gate electrodes are connected to the corresponding voltage selection lines 133.

[0021] The sense amplifier module 125 is connected to a plurality of bit lines BL. The sense amplifier module 125 includes, for example, a plurality of sense amplifier units corresponding to the bit lines BL. Each sense amplifier unit includes a clamp transistor that charges the bit line BL based on the voltage generated by the operating voltage generation circuit 121, a sense transistor that senses the voltage or current of the bit line BL, and a plurality of latch circuits that hold the output signal of the sense transistor, write data, etc.

[0022] The sequencer 126 outputs control signals to the operating voltage generation circuit 121, the address decoder 122, and the sense amplifier module 125 in accordance with the input command and the state of the semiconductor device. For example, the sequencer 126 sequentially references the command data in the command register in accordance with the clock signal, decodes this command data, and outputs it to the operating voltage generation circuit 121, the address decoder 122, and the sense amplifier module 125.

[0023] 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the first embodiment. Hereinafter, the stacking direction of the stacked body 20 is referred to as the Z direction. A direction that intersects with the Z direction, for example, a direction perpendicular to it, is referred to as the Y direction. A direction that intersects with both the Z direction and the Y direction, for example, a direction perpendicular to it, is referred to as the X direction.

[0024] The semiconductor memory device 1 includes an array chip 2 having a memory cell array MA, and a CMOS chip 3 having peripheral circuits PC such as a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded together at a bonding surface B1, and are electrically connected to each other via wiring joined at the bonding surfaces. Figure 2 shows the array chip 2 provided on the CMOS chip 3.

[0025] The CMOS chip 3 includes a substrate 30, transistors 31, 135, and 137, a via 32, wirings 33 and 34, and an interlayer insulating film 35.

[0026] The substrate 30 is a semiconductor substrate such as a silicon substrate. The transistors 31, 135, and 137 are NMOS or PMOS transistors provided on the substrate 30. The transistor 31 is a low-voltage (LV (Low Voltage), VLV (Very Low Voltage)) transistor and constitutes, for example, a CMOS circuit that controls the memory cell array MA of the array chip 2. The transistor 31 constitutes logic circuits such as a sense amplifier, a row decoder, and a column decoder. Therefore, the transistor 31 is required to operate at high speed. On the other hand, the transistors 135 and 137 are used as word line switches (drivers) for applying voltages to the word lines WL. Therefore, the transistor 135 is a high-voltage (HV) transistor with a higher withstand voltage than the transistor 31 and functions as a block driver transistor of the block selection circuit 123 in FIG. 1. The transistor 137 is also a high-voltage transistor with a higher withstand voltage than the transistor 31 and functions as a voltage selection transistor of the voltage selection circuit 124 in FIG. 1. The transistors 135 and 137 are required to operate at high speed, but preferably have high breakdown voltage, low threshold voltage, and low on-resistance. Note that semiconductor elements such as resistors and capacitors other than the transistors 31, 135, and 137 may also be formed on the substrate 30.

[0027] The via 32 electrically connects the transistors 31, 135, and 137 to the wiring 33, or between the wiring 33 and the wiring 34. The wiring 33 and 34 form a multilayer wiring structure within the interlayer insulating film 35. The wiring 34 is buried in the interlayer insulating film 35 and is exposed almost flush with the surface of the interlayer insulating film 35. The wiring 33 and 34 are electrically connected to the transistor 31 and the like. The via 32 and the wiring 33 and 34 are made of a metal such as copper or tungsten. The interlayer insulating film 35 covers and protects the transistors 31, 135, and 137, the via 32, and the wiring 33 and 34. The interlayer insulating film 35 is made of an insulating film such as a silicon oxide film.

[0028] The array chip 2 includes a stacked body 20, columns CL, slits ST (LI), source layers SL, a metal layer 40, contact plugs CCw, contact plugs 29, bonding pads 50, and an interlayer insulating film 25.

[0029] The stacked body 20 is provided above the transistors 31, 135, and 137, and is positioned in the Z direction with respect to the substrate 30. The stacked body 20 is configured by alternately stacking a plurality of electrode films 21 and a plurality of insulating films 22 along the Z direction. The stacked body 20 configures a memory cell array MA. The electrode films 21 are made of a conductive metal such as tungsten. The insulating films 22 are made of an insulating film such as a silicon oxide film. The insulating films 22 insulate the electrode films 21 from one another. That is, the plurality of electrode films 21 are stacked in an insulated state from one another. The number of stacked electrode films 21 and insulating films 22 is arbitrary. The insulating films 22 may be, for example, a porous insulating film or an air gap.

[0030] One or more electrode films 21 at the top and bottom ends of the stack 20 in the Z direction function as a source-side select gate SGS and a drain-side select gate SGD, respectively. The electrode film 21 between the source-side select gate SGS and the drain-side select gate SGD functions as a word line WL. The word line WL is the gate electrode of the memory cell MC. The source-side select gate SGS is the gate electrode of the source-side select transistor. The drain-side select gate SGD is the gate electrode of the drain-side select transistor. The source-side select gate SGS is provided in an upper region of the stack 20. The drain-side select gate SGD is provided in a lower region of the stack 20. The upper region refers to the region of the stack 20 farther from the CMOS chip 3 (the side closer to the metal layer 40), and the lower region refers to the region of the stack 20 closer to the CMOS chip 3.

[0031] The semiconductor memory device 1 has a plurality of memory cells MC connected in series between a source-side select transistor STS controlled by a source-side select gate SGS and a drain-side select transistor STD controlled by a drain-side select gate SGD, forming a memory string. The memory string is connected to a bit line BL, for example, through a via 28. The bit line BL is a wiring 23 provided below the stacked body 20 and extending in the X direction (the direction of the paper in FIG. 2). Therefore, hereinafter, the bit line BL will also be referred to as the bit line 23.

[0032] A plurality of pillars CL are provided in the stacked body 20. The pillars CL extend in the stacking direction (Z direction) of the stacked body 20 so as to penetrate the stacked body 20, and are provided from a via 28 connected to the bit line 23 to the source layer SL. The internal structure of the pillars CL will be described later. In this embodiment, the pillars CL are formed in two stages in the Z direction. However, there is no problem if the pillars CL are formed in one stage. Alternatively, the pillars CL may be formed in three or more stages.

[0033] Although not shown in FIG. 2, a plurality of slits ST (see FIG. 3) are provided in the stacked body 20. The slits ST extend in the Y direction and penetrate the stacked body 20 in the stacking direction (Z direction) of the stacked body 20. An insulating film such as a silicon oxide film is filled in the slits ST, and the insulating film is configured in a plate shape. The slits ST electrically separate the electrode films 21 of the stacked body 20. Alternatively, the inner walls of the slits ST may be covered with an insulating film such as a silicon oxide film, and a conductive material may be further embedded inside the insulating film. In this case, the conductive material can also function as a source wiring that reaches the source layer SL.

[0034] A source layer SL is provided on the stacked body 20. The source layer SL is an example of a first semiconductor layer. The source layer SL is provided corresponding to the stacked body 20. The source layer SL has a face F1 and a face F2 opposite to the face F1. The stacked body 20 (memory cell array MA) is provided on the face F1 side of the source layer SL, and a metal layer 40 is provided on the face F2 side. The metal layer 40 includes a source line 41 and a power supply line 42. The source layer SL is commonly connected to one end of each of the pillars CL and applies a common source potential to the pillars CL in the same memory cell array MA. That is, the source layer SL functions as a common source electrode of the memory cell array MA. The source layer SL is made of a conductive material such as doped polysilicon. The metal layer 40 is made of a metal material with lower resistance than the source layer SL, such as copper, aluminum, or tungsten. Note that 2s denotes a step portion of the electrode film 21 provided to connect the contact plug CCw to each electrode film 21. The staircase portion 2s will be described later with reference to FIG.

[0035] On the other hand, a bonding pad 50 is provided above the stacked body 20 in an area where the source layer SL is not provided. The bonding pad 50 is connected to a metal wire or the like (not shown) and receives a power supply or a signal from outside the semiconductor memory device 1. The bonding pad 50 is provided so as to be connected to one end of the contact plug 29 in the Z direction. The bonding pad 50 is connected to the transistors 31, 135, and 137 of the CMOS chip 3 via the contact plug 29, the wiring 24, and the wiring 34. Therefore, the external power supply supplied from the bonding pad 50 is supplied to the transistors 31, 135, and 137. Alternatively, a signal or power is supplied to the transistors 31, 135, and 137 or the memory cell array MA via the bonding pad 50.

[0036] The contact plugs CCw are provided on the periphery of the stacked body 20 and extend in the Z direction within the interlayer insulating film 25. The contact plugs CCw are electrically connected between the electrode films 21 (word lines WL) and the wiring 24. The contact plugs CCw are provided in staircase portions 2s formed in a staircase shape at the end of the stacked body 20 and are electrically connected to the electrode films 21. The contact plugs CCw are provided to transmit the word line voltage from the CMOS chip 3 to the electrode films 21. The contact plugs CCw are made of a metal such as copper or tungsten.

[0037] The contact plugs 29 are provided in the peripheral portion of the stacked body 20 and extend in the Z direction through the interlayer insulating film 25. The contact plugs 29 are contact plugs provided from the wiring 24 to the bonding pads 50. The contact plugs 29 are formed simultaneously in the same process as the contact plugs CCw connected to the word lines WL.

[0038] The contact plug 29 is electrically connected between the bonding pad 50 and the wiring 24. The contact plug 29 is used to supply a power supply voltage or a signal from the bonding pad 50 to the array chip 2 or the CMOS chip 3. The contact plug 29 is made of a metal such as copper or tungsten. The power supply voltage is, for example, a power supply voltage VDD or a reference voltage (for example, a ground voltage) VSS that is lower than the power supply voltage VDD. The signal may be an external control signal, or may be write data or read data.

[0039] In this embodiment, the array chip 2 and the CMOS chip 3 are formed separately and are bonded together at the bonding surface B1. Therefore, the array chip 2 does not include transistors 31, 135, and 137. The CMOS chip 3 does not include a stacked body 20 (memory cell array MA). The transistors 31, 135, and 137 and the stacked body 20 are all located on the surface F1 side of the source layer SL. The metal layer 40 is located on the surface F2 side of the source layer SL.

[0040] A via 28, a wiring 23, and a wiring 24 are provided in the −Z direction of the stacked body 20. The wirings 23 and 24 are buried in an interlayer insulating film 25. The wiring 24 is exposed to be substantially flush with the surface of the interlayer insulating film 25. The wirings 23 and 24 are electrically connected to the semiconductor body 210 of the columnar body CL (see FIG. 4 ). The via 28, the wiring 23, and the wiring 24 are made of a metal such as copper or tungsten. The interlayer insulating film 25 covers and protects the stacked body 20, the via 28, the wiring 23, and the wiring 24. The interlayer insulating film 25 is made of an insulating film such as a silicon oxide film.

[0041] The interlayer insulating film 25 and the interlayer insulating film 35 are bonded to each other at the bonding surface B1, and as a result, the wiring 24 and the wiring 34 are bonded to each other in a substantially flush manner at the bonding surface B1. As a result, the array chip 2 and the CMOS chip 3 are electrically connected to each other via the wiring 24 and the wiring 34.

[0042] FIG. 3 is a schematic plan view showing the stack 20. The stack 20 includes a staircase portion 2s and a memory cell array MA. The staircase portion 2s is provided, for example, at an end of the stack 20. The memory cell array MA is sandwiched or surrounded by the staircase portion 2s. The slit ST(LI) is provided from the staircase portion 2s at one end of the stack 20, through the memory cell array MA, to the staircase portion 2s at the other end of the stack 20. The slit SHE is provided at least in the memory cell array MA. The slit SHE is shallower in the Z direction than the slit ST(LI) and extends approximately parallel to the slit ST(LI). The slit SHE electrically separates the electrode film 21 for each drain-side select gate SGD. The slit ST may be a source wiring LI that is electrically isolated from the electrode film 21 of the stack 20 and electrically connected to the source layer SL. That is, the slit ST may be a source wiring LI that is electrically isolated from the electrode film 21 of the stack 20 that constitutes the memory cell array MA and is electrically connected to the source layer SL.

[0043] The portion of the stack 20 sandwiched between the two slits ST shown in FIG. 3 is a memory block MB. The memory block MB constitutes, for example, the smallest unit for erasing data. The slit SHE is provided within the memory block MB. The stack 20 between the slit ST and the slit SHE is called a finger. The drain-side select gate SGD is separated into each finger. Therefore, when writing or reading data, one finger in the memory block MB can be selected by the drain-side select gate SGD.

[0044] 4 and 5 are cross-sectional views illustrating a memory cell having a three-dimensional structure. Each of the multiple pillars CL is provided in a memory hole MH provided in the stacked body 20. Each pillar CL extends from one end of the stacked body 20 through the stacked body 20 along the Z direction, extending into the stacked body 20 and the source layer SL. Each of the multiple pillars CL includes a semiconductor body 210, a memory film 220, and a core layer 230. Each pillar CL includes a core layer 230 provided in its center, a semiconductor body (semiconductor member) 210 provided around the core layer 230, and a memory film 220 provided around the semiconductor body 210. The semiconductor body 210 extends in the stacking direction (Z direction) within the stacked body 20. The semiconductor body 210 is electrically connected to the source layer SL. The memory film 220 is provided between the semiconductor body 210 and the electrode film 21 and has a charge trapping portion. A plurality of pillars CL, one selected from each finger, are commonly connected to one bit line 23 through vias 28 shown in Fig. 2. Each of the pillars CL is provided, for example, in the region of the memory cell array MA.

[0045] As shown in FIG. 5, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. A block insulating film 221a constituting part of the memory film 220 may be provided between the electrode film 21 and the insulating film 22. The block insulating film 221a is, for example, silicon oxide or metal oxide. One example of a metal oxide is aluminum oxide. A barrier film 21b may be provided between the electrode film 21 and the insulating film 22 and between the electrode film 21 and the memory film 220. When the electrode film 21 is made of tungsten, for example, the barrier film 21b is, for example, a stacked film of titanium nitride and titanium. The block insulating film 221a suppresses back tunneling of charges from the electrode film 21 to the memory film 220. The barrier film 21b improves adhesion between the electrode film 21 and the block insulating film 221a.

[0046] The semiconductor body 210 has, for example, a cylindrical shape with a bottom. The semiconductor body 210 is made of, for example, polysilicon. The semiconductor body 210 is made of, for example, undoped silicon. The semiconductor body 210 may also be p-type silicon. The semiconductor body 210 serves as the channels of the drain-side select transistor, the memory cell MC, and the source-side select transistor. That is, the multiple memory cells MC have storage areas between the semiconductor body 210 and the electrode film 21 that serves as the word line WL, and are stacked in the Z direction. One end of the multiple semiconductor bodies 210 in the same memory cell array MA is electrically connected in common to the source layer SL.

[0047] The memory film 220 includes, for example, a cover insulating film 221, a charge trapping film 222, a tunnel insulating film 223, and a block insulating film 221a. Portions of the memory film 220 other than the block insulating film 221a are provided between the inner wall of the memory hole MH and the semiconductor body 210. The memory film 220 has, for example, a cylindrical shape. The charge trapping film 222 and the tunnel insulating film 223 each extend in the Z direction.

[0048] The cover insulating film 221 is provided between the insulating film 22 and the charge trapping film 222, and between the block insulating film 221a and the charge trapping film 222. The cover insulating film 221 contains, for example, silicon oxide. The cover insulating film 221 protects the charge trapping film 222 from being etched when a sacrificial film (not shown) is replaced with the electrode film 21 (replacement step). Note that if the replacement step is not used to form the electrode film 21, the cover insulating film 221 may be omitted.

[0049] The charge trapping film 222 is provided between the cover insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 contains, for example, silicon nitride, and has trap sites that trap charges within the film. The portion of the charge trapping film 222 sandwiched between the electrode film 21, which becomes the word line WL, and the semiconductor body 210 constitutes the storage region of the memory cell MC as a charge trap portion. The threshold voltage of the memory cell MC changes depending on the presence or absence of charge in the charge trap portion or the amount of charge trapped in the charge trap portion. This allows the memory cell MC to retain information.

[0050] The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 includes, for example, silicon oxide or a combination of silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 into the charge trapping film 222 (write operation), and when holes are injected from the semiconductor body 210 into the charge trapping film 222 (erase operation), the electrons and holes each pass through (tunnel) the potential barrier of the tunnel insulating film 223.

[0051] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The core layer 230 has, for example, a columnar shape. The core layer 230 includes, for example, silicon oxide and is insulating.

[0052] Fig. 6 is a plan view showing an example of the configuration of a transistor 31 that constitutes the logic circuit of the CMOS chip 3 according to the first embodiment. Fig. 7 is a cross-sectional view showing an example of the configuration of a transistor 31 that constitutes the logic circuit of the CMOS chip 3 according to the first embodiment. Fig. 7 shows a cross section taken along line 7-7 in Fig. 6. Figs. 6 and 7 show the configuration of one transistor 31.

[0053] 6, a convex region Raa is surrounded by a concave region Rsti. The convex region Raa is, for example, an element formation region (active area). The concave region Rsti is, for example, a formation region for an element isolation part STI (Shallow Trench Isolation). The concave region Rsti is filled with an insulating material such as a silicon oxide film around the convex region Raa where the transistor 31 is formed.

[0054] The transistor 31 has a drain D31 provided in the convex region Raa on one side of the gate electrode G31, and a source S31 provided in the convex region Raa on the other side of the gate electrode G31.

[0055] The contacts CT are electrically connected to the wirings 33 and 34 through vias 32 and the like.

[0056] The substrate 30 in FIG. 7 may be a semiconductor substrate such as a silicon substrate. The substrate 30 is an example of a semiconductor layer. The substrate 30 includes a first surface F11 on which a control circuit including transistors 31, 135, 137, etc. is provided, and a second surface F12 on the opposite side of the first surface F11. The substrate 30 has a recessed region Rsti on the first surface F1 side that is recessed from the first surface F11 toward the second surface F12. The recessed region Rsti is filled with an insulating film such as a silicon oxide film, and forms an element isolation portion STI31. The element isolation portion STI31 electrically isolates adjacent transistors 31. The substrate 30 also has a protruding region Raa that protrudes from the recessed region Rsti. The protruding region Raa is surrounded by the recessed region Rsti and is defined by the recessed region Rsti.

[0057] The transistor 31 is provided on the first face F11 of the convex region Raa. The transistor 31 includes a gate insulating film IN31 and a gate electrode G31.

[0058] The gate insulating film IN31 is provided on the first surface F11 of the convex region Raa. The film thickness of the gate insulating film IN31 is thinner than that of the gate insulating film IN135 of the transistor 135 shown in FIG. The gate insulating film IN31 is made of, for example, an insulating film such as a silicon oxide film. The gate electrode G31 is provided on the gate insulating film IN31.

[0059] The gate electrode G31 is formed of a laminated film including, for example, a first gate electrode portion G31p1, a second gate electrode portion G31p2, and a third gate electrode portion G31m. The first and second gate electrode portions G31p1 and G31p2 are made of a conductive material such as doped polysilicon containing boron as an impurity. The third gate electrode portion G31m is made of a conductive metal material such as tungsten or copper.

[0060] FIG. 8 is a plan view showing an example of the configuration of a transistor 135 that constitutes a word line switch of the CMOS chip 3 according to the first embodiment. FIG. 9 is a cross-sectional view showing an example of the configuration of a transistor 135 that constitutes a word line switch of the CMOS chip 3 according to the first embodiment. FIG. 9 shows a cross section taken along line 9-9 in FIG. 8. FIGS. 8 and 9 show the configuration of four transistors 135. The configuration of transistor 137 may be the same as that of transistor 135. Therefore, a description of the configuration of transistor 137 will be omitted here.

[0061] 8, the convex region Raa is surrounded by the concave region Rsti. The transistor 135 has a drain D135 provided in the convex region Raa on one side of the gate electrode G135, and a source S135 provided in the convex region Raa on the other side of the gate electrode G135. In FIG. 8, multiple transistors 135 share the source S135.

[0062] The reference voltage source 150 is formed in the recessed region Rsti and is made of the same material as the gate electrode G135. The reference voltage source 150 is electrically connected to the substrate 30, maintained at a predetermined reference voltage (for example, ground voltage), and electrically isolates the transistors from each other.

[0063] The substrate 30 in Fig. 9 is the same substrate as the substrate 30 in Fig. 7. Therefore, the transistors 135, 137, and 139 are provided on the same substrate 30.

[0064] The transistor 135 is provided on the first face F11 of the convex region Raa. The transistor 135 includes a gate insulating film IN135, a side gate insulating film IN135s, a gate electrode G135, and a side gate electrode G135s.

[0065] The gate insulating film IN135 is provided on the first face F11 of the convex region Raa. The film thickness of the gate insulating film IN135 is thicker than that of the gate insulating film IN31 of the transistor 31. The film thickness of the gate insulating film IN31 is, for example, 10 nm or less, and the film thickness of the gate insulating film IN135 is, for example, 30 nm or more. The gate insulating film IN135 is, for example, an insulating film such as a silicon oxide film.

[0066] The side gate insulating film IN135s is provided on the side surface F11s of the convex region Raa. That is, the side gate insulating film IN135s is provided in the recess of the recessed region Rsti and is provided on the element isolation part STI135. The thickness of the side gate insulating film IN135s is thicker than that of the gate insulating film IN135. This makes it possible to increase the gate width of the transistor 135 while maintaining a high breakdown voltage. Like the gate insulating film IN135, the side gate insulating film IN135s is made of an insulating film such as a silicon oxide film.

[0067] The gate electrode G135 is provided on the gate insulating film IN135. The gate electrode G135 is composed of, for example, a stacked film including a first gate electrode portion G135p1, a second gate electrode portion G135p2, and a third gate electrode portion G135m. The first and second gate electrode portions G135p1 and G135p2 are in the same layer as the first and second gate electrode portions G31p1 and G31p2, respectively, and contain, for example, boron as an impurity. The third gate electrode portion G135m is in the same layer as the third gate electrode portion G31m and is made of, for example, a conductive metal material such as tungsten or copper. Note that the third gate electrode portion G135m does not have to be made of a metal material, as long as it has a lower resistance than the first and second gate electrode portions G31p1 and G31p2.

[0068] In this embodiment, the gate electrodes G31 and G135 have a three-layer laminated structure, but may be a single conductive layer, or may have a two-layer or four or more layer laminated structure.

[0069] The side gate electrode G135s is provided on the side gate insulating film IN135s and is connected to the gate electrode G135 on the first face F11. The side gate electrode G135s is configured in the same layer as the first gate electrode portion G135p1.

[0070] The side gate electrode G135s is provided in the recess of the recessed region Rsti, and is embedded between the side gate insulating films IN135s on the element isolation part STI135.

[0071] In this embodiment, the side gate electrode G135s is composed of the second gate electrode portion G135p2 of the stacked structure of the gate electrodes G31 and G135. However, the side gate electrode G135s may be composed of the third gate electrode portion G135m. Furthermore, the side gate electrode G135s may have a stacked structure of two or more layers.

[0072] The contacts CT are electrically connected to the wirings 33 and 34 through vias 32 etc. The contacts CT on the source side or drain side are electrically connected to the word lines WL through contact plugs CCw of the array chip 2.

[0073] In the region where the transistor 135 is formed, only the bottom of the recessed region Rsti is filled with an insulating film such as a silicon oxide film to form the STI 135. The STI 135 electrically isolates adjacent transistors 135. The transistors 31, 135, and 137 in FIGS. 7 to 9 may be provided on the same substrate 30 and the same raised region Raa.

[0074] According to this embodiment, the transistor 31 constituting the logic circuit of the peripheral circuit PC of the CMOS chip 3 is a low-voltage (LV, VLV) transistor that has a channel region on the first surface F11 of the active area Raa and does not have a channel region on the side surface of the active area Raa, as shown in Fig. 7. This enables the logic circuit of the peripheral circuit PC to consume less power, operate at high speed, and be easily miniaturized.

[0075] On the other hand, as shown in FIG. 9, the block driver transistor 135 of the block selection circuit 123 and the voltage selection transistor 137 of the voltage selection circuit 124 are high-voltage (HV) transistors, each having a channel region on both the first face F11 and the side face F11s of the active area Raa and a gate insulating film IN135 thicker than that of the transistor 31. Therefore, the channel width (gate width) of the transistors 135 and 137 functioning as word line switches (drivers) in the peripheral circuit PC is increased, reducing the on-resistance and improving the current drive capability to the word line WL. Furthermore, since the side face F11s of the active area Raa is used as the channel region, the planar size (size in the gate width direction) of the transistors 135 and 137 can be suppressed from increasing. Furthermore, while maintaining a constant current drive capability, the planar size (size in the gate width direction) of the transistors 135 and 137 can be reduced. When a plurality of transistors 135, 137 are connected in parallel as a word line switch, the distance (pitch) between the transistors 135 or the distance (pitch) between the transistors 137 can be reduced while maintaining the current driving capabilities of the transistors 135, 137.

[0076] Furthermore, the thickness of the side gate insulating film IN135s of the transistors 135 and 137 is thicker than that of the gate insulating film IN135. This allows the breakdown voltage of the transistors 135 and 137 to be maintained at a level equivalent to that of a high-breakdown-voltage transistor that does not have a channel region on the side surface F11s. As a result, the transistors 135 and 137 according to this embodiment can achieve both low on-resistance and high breakdown voltage while maintaining the threshold voltage.

[0077] (Method of manufacturing transistors 31, 135, and 137) Next, a method for manufacturing the transistors 31, 135, and 137 will be described.

[0078] 10 to 15 are cross-sectional views showing an example of a method for manufacturing the transistors 31, 135, and 137 according to the first embodiment. The transistors 31, 135, and 137 are formed on the same substrate 30. Note that FIGS. 10 to 15 show the transistors 31 and 135 side by side, and do not show the transistor 137. The transistor 137 can be formed in the same manner as the transistor 135.

[0079] Gate insulating films IN31 and IN135 are formed on the first surface F11 of the substrate 30. The gate insulating film IN135 is formed to be thicker than the gate insulating film IN31. For example, after forming an insulating film such as a silicon oxide film over the entire first surface F11, lithography and etching techniques are used to selectively remove the insulating film in the region where the gate insulating film IN31 is to be formed, and then an insulating film such as a silicon oxide film is formed again over the entire first surface F11. In this way, a relatively thick insulating film may be formed in the region where the gate insulating film IN135 is to be formed, and a relatively thin insulating film may be formed in the region where the gate insulating film IN31 is to be formed.

[0080] Next, the material of the first gate electrode portions G31p1 and G135p1 (for example, doped polysilicon) is formed on the gate insulating films IN31 and IN135, and the material of the hard mask HM1 (for example, a silicon nitride film) is formed on the material of the first gate electrode portions G31p1 and G135p1.

[0081] Next, the material of the hard mask HM1 in the recessed region Rsti is selectively etched using lithography and etching techniques. Furthermore, the hard mask HM1 is used as a mask to process the material of the first gate electrode portions G31p1 and G135p1, the gate insulating films IN31 and IN135, and the substrate 30. As a result, trenches are formed in the recessed region Rsti.

[0082] Next, a material (e.g., a silicon oxide film) of the element isolation portions STI31 and STI135 is formed in the trenches of the recessed regions Rsti. The material of the element isolation portions STI31 and STI135 is planarized using a CMP (Chemical Mechanical Polishing) method or the like. As a result, the structure shown in FIG. 10 is obtained.

[0083] Next, the material of the element isolation portion STI135 is selectively etched using lithography and etching techniques. As shown in FIG. 11 , in the formation region of the transistor 135, an upper portion of the material of the element isolation portion STI135 in the recessed region Rsti is removed, leaving the element isolation portion STI135 at the bottom of the recessed region Rsti. As a result, in the formation region of the transistor 135, the side surface F11s of the active area Raa (part of the sidewall of the recessed region Rsti) is exposed. The element isolation portion STI135 in the formation region of the transistor 135 functions as an isolation region for the transistor 135. On the other hand, as shown in FIG. 11 , in the formation region of the transistor 31, the recessed region Rsti remains filled with the material of the element isolation portion STI31. The element isolation portion STI31 in the formation region of the transistor 31 functions as an isolation region for the transistor 31.

[0084] Next, a material for the side gate insulating film IN135s (e.g., a silicon oxide film) is formed on the side surface F11s of the active area Raa and the hard mask HM1. Next, the material for the side gate insulating film IN135s is etched back. As a result, as shown in FIG. 12, the side gate insulating film IN135s remains on the side surface F11s of the active area Raa in the formation region of the transistor 135. The structure of the formation region of the transistor 31 in FIG. 12 is the same as that in FIG. 11.

[0085] Next, as shown in FIG. 13, the hard mask HM1 is removed using a hot phosphoric acid solution or the like.

[0086] 14, a material (e.g., doped polysilicon) of the gate electrode portions G31p2 and G135p2 is deposited on the element isolation portions STI31 and STI135, the side gate insulating film IN135s, and the gate electrode portions G31p1 and G135p1. As a result, in the formation region of the transistor 135, the gate electrode portion G135p2 is embedded inside the recessed region Rsti. The gate electrode portion G135p2 faces the side surface F11s of the active area Raa via the side gate insulating film IN135s, and contributes to increasing the channel width (gate width) of the transistor 135.

[0087] Next, the upper portions of the material of the gate electrode portions G31p2 and G135p2 are etched back. Next, as shown in FIG. 15, the material of the third gate electrode portions G31m and G135m (e.g., tungsten) is deposited on the gate electrode portions G31p2 and G135p2. This forms the gate electrodes G31 and G135.

[0088] Next, although not shown, an interlayer insulating film, via contacts, a wiring structure, etc. are formed on the gate electrodes G31 and G135, and the CMOS chip 3 is completed.

[0089] Thereafter, the CMOS chip 3 and the array chip 2 formed separately from the CMOS chip 3 are bonded together to complete the semiconductor memory device 1 shown in FIG.

[0090] Thus, according to this embodiment, the transistors 135 and 137 can be formed simultaneously in a common semiconductor manufacturing process on the same substrate as the transistor 31. This reduces the number of additional manufacturing processes, and suppresses increases in manufacturing costs.

[0091] (Second embodiment) 16 is a cross-sectional view showing an example of the configuration of a transistor 135 that constitutes a word line switch according to the second embodiment. The configuration of the transistor 137 may be the same as the configuration of the transistor 135. Therefore, a description of the configuration of the transistor 137 will be omitted here.

[0092] In the second embodiment, in the recessed region Rsti of the transistor 135, the material of the side gate electrode G135s (for example, doped polysilicon) covers the side gate insulating film IN135s but does not fill the recessed region Rsti.

[0093] On the other hand, the material (e.g., tungsten) of the third gate electrode portion G135m covers the side gate electrode G135s in the recessed region Rsti. The material of the third gate electrode portion G135m may be embedded in the recessed region Rsti. Even with this configuration, the transistor 135 has the same function as the transistor 135 according to the first embodiment.

[0094] Other configurations of the second embodiment may be similar to those of the first embodiment, and therefore the second embodiment can achieve the same effects as the first embodiment.

[0095] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0096] 1. Semiconductor memory device 2. Array chip 3 CMOS chips MA Memory Cell Array MC memory cell PC peripheral circuits BL bit line WL Word Line 30 boards 31,135,137 transistors Raa convex area Rsti concave region G31, G135 gate electrodes D31, D135 Drain S31,S135 sauce IN31, IN135 gate insulating film G31p1, G135p1 First gate electrode part G31p2, G135p2 Second gate electrode part G31m, G135m Third gate electrode part IN135s side gate insulating film G135s side gate electrode

Claims

1. a first semiconductor layer including a first surface and a second surface opposite to the first surface, the first semiconductor layer including a recessed region recessed from the first surface toward the second surface, and a protruding region protruding from the recessed region; a first transistor including a first gate insulating film provided in the convex region of the first semiconductor layer, a side gate insulating film provided on a side wall of the convex region, a first gate electrode provided on the first gate insulating film, and a side gate electrode provided on the side gate insulating film and connected to the first gate electrode; a second transistor including a second gate insulating film provided on the convex region and thinner than the first gate insulating film, and a second gate electrode provided on the second gate insulating film.

2. The semiconductor device according to claim 1 , wherein said side gate insulating film is thicker than said first gate insulating film.

3. the first and second gate electrodes are each formed of a laminated film of a first conductive layer and a second conductive layer provided on the first surface of the convex region, 2. The semiconductor device according to claim 1, wherein said side gate electrode is formed of said second conductive layer provided on said side gate insulating film.

4. The semiconductor device according to claim 1 , wherein the first and second transistors are provided in the same convex region.

5. a memory cell array including a plurality of memory cells provided corresponding to intersections of the first wiring and the second wiring, and capable of writing or reading data via the second wiring by applying a voltage to the first wiring; The semiconductor device according to claim 1 , wherein a source or a drain of the first transistor is electrically connected to the first wiring.

6. 6. The semiconductor device according to claim 5, wherein a first chip including said first transistor, said second transistor, and said first semiconductor layer is bonded to a second chip including said memory cell array.

7. 2. The semiconductor device according to claim 1, wherein an insulating material is buried in said recessed region in addition to said side gate insulating film and said side gate electrode.

8. a first semiconductor layer including a first surface and a second surface opposite to the first surface, the first semiconductor layer including a recessed region recessed from the first surface toward the second surface, and a protruding region protruding from the recessed region; a first transistor including a first gate insulating film provided in the convex region of the first semiconductor layer, a side gate insulating film provided on a side wall of the convex region and thicker than the first gate insulating film, a first gate electrode provided on the first gate insulating film, and a side gate electrode provided on the side gate insulating film and connected to the first gate electrode.

9. a memory cell array including a plurality of memory cells provided at intersections of first wirings and second wirings, in which data can be written or read via the second wirings by applying a voltage to the first wirings; a first semiconductor layer including a first surface and a second surface opposite to the first surface, the first semiconductor layer including a recessed region recessed from the first surface toward the second surface, and a protruding region protruding from the recessed region; a first transistor including a first gate insulating film provided in a convex region of the first semiconductor layer, a side gate insulating film provided on a side wall of the convex region, a first gate electrode provided on the first gate insulating film, and a side gate electrode provided on the side gate insulating film and connected to the first gate electrode; The semiconductor device, wherein the source or drain of the first transistor is electrically connected to the first wiring.

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