Semiconductor device

Abstract

To provide a semiconductor device 11 that can achieve higher performance at the same time regarding an IGBT region 17 and a diode region 19.SOLUTION: A semiconductor device 11 includes an IGBT region 17 and a diode region 19 formed in a drift layer 101 of a first conductivity type. The diode region 19 has a structure in which a cathode electrode 21b, a cathode layer 116, a buffer layer 113, a drift layer 101, an anode layer 117, an insulating layer 111, and an anode electrode 23b are stacked from a back side to a front side. In the anode electrode 23b, a third penetration contact part 33 with a columnar shape is formed with the depth reaching the anode layer 117 while penetrating the insulating layer 111. In the third penetration contact part 33, a second high-concentration contact layer 37 of a second conductivity type is formed. The third penetration contact part 33 and the second high-concentration contact layer 37 are provided selectively along a depth direction so as to be in contact with a front side surface of a concave part 117a of the anode layer 117.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] The applicant of the present application has disclosed an invention of a semiconductor device relating to a reverse conducting IGBT (Insulated Gate Bipolar Transistor) (hereinafter referred to as "RC-IGBT") in which an IGBT and a diode are built in the same chip (see, for example, Patent Document 1).

[0003] The semiconductor device (RC-IGBT) disclosed in Patent Document 1 (see Abstract and Figure 1) includes two body layers, a first trench therebetween, a first gate electrode formed on a sidewall on the first body layer side via a gate insulating film, and a second gate electrode formed on a sidewall on the second body layer side via a gate insulating film, with the first gate electrode and the second gate electrode being separated by the first insulating film. The diode includes two body layers and a trench therebetween. The diode trench includes a first electrode formed on a sidewall on the third body layer side via an insulating film, and a second electrode formed on a sidewall on the third body layer side via an insulating film, with the two electrodes being separated by the second insulating film.

[0004] According to the semiconductor device disclosed in Patent Document 1, the recovery characteristics of the diode section can be improved by reducing the area of ​​the p-body layer in the diode section of the RC-IGBT to suppress hole injection. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2023-147422 Summary of the Invention [Problem to be solved by the invention]

[0006] For example, in a semiconductor device (RC-IGBT) such as that shown in Patent Document 1, various approaches have been attempted to simultaneously achieve high performance in the IGBT region and the diode region.

[0007] An object of the present invention is to provide a semiconductor device that can simultaneously achieve high performance in both the IGBT region and the diode region by using a new approach that differs from existing technology. [Means for solving the problem]

[0008] In order to solve the above problems, the semiconductor device according to the present invention comprises: A semiconductor device (11) configured by forming an IGBT region (17) and a diode region (19) in a drift layer (101) of a first conductivity type, the diode region (19) has a structure in which a cathode electrode (21b), a cathode layer (116), a buffer layer (113), the drift layer (101), an anode layer (117), an insulating layer (111), and an anode electrode (23b) are stacked from the back side to the front side, a third through contact portion (33) having a columnar shape and a predetermined depth that penetrates the insulating layer (111) and reaches the anode layer (117) is formed in the anode electrode (23b) belonging to the diode region (19); the third through contact portion (33) is provided so as to fit into a recess (117a) formed in the anode layer (117); a second high-concentration contact layer (37) of a second conductivity type is formed between a back surface of the third through contact portion (33) and a front surface of the recess (117a) of the anode layer (117); The third through contact portion (33) and the second high-concentration contact layer (37) are selectively provided along the depth direction so as to contact the front side surface of the recess (117a) of the anode layer (117). This is its most important feature.

[0009] According to the present invention, high performance can be achieved simultaneously in the IGBT region and the diode region. Problems, configurations, and effects other than those described above will be described in detail in the following embodiments. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a perspective view schematically illustrating a schematic configuration of a semiconductor device according to a comparative example. [Figure 2] 1 is a perspective view schematically illustrating a schematic configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 3A] FIG. 10 is a perspective view schematically illustrating the general configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 3B] FIG. 10 is a cross-sectional view schematically illustrating the general configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 4A] 4A is a cross-sectional view taken along line 4A-4A shown in FIG. 3B. [Figure 4B] 4B is a cross-sectional view taken along line 4B-4B in FIG. 3B. [Figure 4C] 4C is a cross-sectional view taken along line 4C-4C shown in FIG. 3B. [Figure 5] FIG. 10 is a plan view schematically illustrating a general configuration of a semiconductor device according to a modified example of the present invention. [Figure 6] 1 is a circuit diagram of a power conversion device to which a semiconductor device according to the present invention is applied as a switching element. DETAILED DESCRIPTION OF THE INVENTION

[0011] Semiconductor devices according to embodiments of the present invention will be described in detail with reference to the appropriate drawings. In the description of the semiconductor device according to the embodiment of the present invention, components having common functions are denoted by common reference numerals, and duplicated descriptions thereof will be omitted as a general rule.

[0012] In this specification, n + , n, n - , and p + , p, p- Each notation indicates the relative level of impurity concentration for each conductivity type. + has a relatively high n-type impurity concentration compared to n, - indicates that the n-type impurity concentration is relatively low compared to n. + has a relatively high p-type impurity concentration compared to p, - indicates that the p-type impurity concentration is relatively low compared to p. + type, n - The type is simply n-type and p + type, p - The type is sometimes abbreviated as simply p-type.

[0013] In this specification, for the convenience of expressing the positional relationship between a plurality of members, the following terms are defined. That is, the side facing the collector electrode / cathode electrode 21 (see FIG. 1, for example) is called the "back" side, and the side facing the emitter electrode / anode electrode 23 is called the "front" side. The relative direction between the collector electrode / cathode electrode 21 and the emitter electrode / anode electrode 23 is called the "depth direction." "Deep" means a state toward the back side in the depth direction, and "depth" means the degree to which it is toward the back side in the depth direction. The direction in which the IGBT region 17 and the diode region 19 are arranged is called the "width direction." The direction in which the IGBT region 17 and the diode region 19 are connected from one end to the other end is called the "depth direction."

[0014] Below, the semiconductor device 10 according to the comparative example of the present invention, the semiconductor device 11A according to the first embodiment, the semiconductor device 11B according to the second embodiment, and the semiconductor device 11 according to the modified example will be described by taking as examples an embodiment in which the first conductivity type is n-type and the second conductivity type is p-type.

[0015] [Semiconductor device 10 according to comparative example] First, a semiconductor device 10 according to a comparative example will be described with reference to FIG. 1. FIG. 1 is a perspective view that schematically illustrates the general configuration of the semiconductor device 10 according to the comparative example. Note that FIG. 1 shows selective cross sections cut out to show the internal configuration of the semiconductor device 10 according to the comparative example in detail. The semiconductor device 10 according to the comparative example actually has a cubic appearance. This is also true for FIGS. 2 and 3A.

[0016] As shown in FIG. 1, a semiconductor device (RC-IGBT) 10 according to the comparative example includes an IGBT region 17 and a diode region 19 within the same chip. The IGBT region 17 and the diode region 19 each extend in the width direction with a boundary portion 18 sandwiched therebetween.

[0017] The RC-IGBT 10 according to the comparative example has a structure in which the collector electrode / cathode electrode 21, collector layer 115 / cathode layer 116, buffer layer 113, drift layer 101, channel layer 103 / anode layer 117, insulating layer 111, and emitter electrode / anode electrode 23 are stacked from the back side to the front side.

[0018] The collector electrode and cathode electrode 21 each have a common thickness in the depth direction and are electrodes that extend integrally across the width direction across the boundary portion 18. Of the collector electrode and cathode electrode 21, the portion that belongs to the IGBT region 17 is called the collector electrode 21a, while the portion that belongs to the diode region 19 is called the cathode electrode 21b.

[0019] The collector layer 115 and the cathode layer 116 have the same thickness in the depth direction, and are provided so as to be in close contact with the front and side surfaces of the collector electrode and cathode electrode 21 .

[0020] The collector layer 115 is provided so as to be in close contact with the front side surface of the collector electrode 21a. The collector layer 115 is of the second conductivity type (p-type), and its impurity concentration is set to [p].

[0021] The cathode layer 116 is provided so as to be in close contact with the front surface of the cathode electrode 21b. The cathode layer 116 is of the first conductivity type (n-type), and its impurity concentration is [n + ] is set.

[0022] The buffer layer 113 has a common thickness in the depth direction and is provided so as to be in close contact with the front and side surfaces of the collector layer 115 and the cathode layer 116. The buffer layer 113 is of the first conductivity type (n-type), and its impurity concentration is set to [n].

[0023] The drift layer 101 has a common thickness in the depth direction and is provided so as to be in close contact with the front and side surfaces of the buffer layer 113. The drift layer 101 is of the first conductivity type (n type) and has an impurity concentration of [n - ] is set.

[0024] The channel layer 103 and the anode layer 117 each have a specific thickness in the depth direction, and are provided so as to be in close contact with the front and side surfaces of the drift layer 101.

[0025] The channel layer 103 has a substantially rectangular shape when viewed from the front in the depth direction, and is formed in a substantially rod-like shape with a length equal to the depth dimension of the RC-IGBT 10. The channel layer 103 is in close contact with the front surface of the drift layer 101 that belongs to the IGBT region 17, and a plurality of channel layers 103 are provided so that the individual channel layers 103 are spaced apart from each other in the width direction. A substantially trough-shaped recess 103a extending along the depth direction is provided in the center of the front side of the channel layer 103 in the width direction. The channel layer 103 is of the second conductivity type (p-type), and its impurity concentration is set to [p].

[0026] The anode layer 117 has a substantially rectangular shape when viewed from the front in the depth direction, and is formed in a substantially rod-like shape with a length equal to the depth dimension of the RC-IGBT 10. The anode layer 117 is in close contact with the front side surface of the portion of the drift layer 101 that belongs to the diode region 19, and a plurality of anode layers 117 are provided such that the individual anode layers 117 are spaced apart from each other in the width direction. A substantially trough-shaped recess 117a extending along the depth direction is provided in the center of the front side of the anode layer 117 in the width direction. The anode layer 117 is of the second conductivity type (p-type), and its impurity concentration is set to [p].

[0027] The insulating layer 111 is provided so as to surround each of the channel layer 103, the source layer 105, the gate electrode 25, the anode layer 117, and the buried emitter electrode 119. A portion of the insulating layer 111 is provided so as to be in close contact with the front and side surfaces of the drift layer 101. The insulating layer 111 (including the gate oxide film 107) serves to provide electrical insulation between the drift layer 101 and the emitter electrode / anode electrode 23, between the drift layer 101 and the gate electrode 25, between the drift layer 101 and the field plate electrode 109, and between the drift layer 101 and the buried emitter electrode 119.

[0028] The emitter electrode and anode electrode 23 each have a common thickness in the depth direction and are electrodes that extend integrally across the width direction across the boundary 18. Of the emitter electrode and anode electrode 23, the portion that belongs to the IGBT region 17 is called the emitter electrode 23a, while the portion that belongs to the diode region 19 is called the anode electrode 23b.

[0029] The emitter electrode 23a belonging to the IGBT region 17 has a columnar, convex first through contact portion 31 formed therein, which penetrates the insulating layer 111 and the source layer 105 and has a predetermined depth reaching the channel layer 103.

[0030] The source layer 105 is selectively provided along the depth direction so as to be in close contact with the front side surface of the channel layer 103 except for the recess 103a (see FIG. 4B). The source layer 105 is of the first conductivity type (n-type), and its impurity concentration is [n + ] is set.

[0031] The first through contact portion 31 is provided to fit into the recess 103a relating to the channel layer 103. The backside surface of the first through contact portion 31 is disposed to face the frontside surface (bottom surface) of the recess 103a relating to the channel layer 103. A first high-concentration contact layer 35 is formed continuously along the depth direction between the backside surface of the first through contact portion 31 and the frontside surface (bottom surface) of the recess 103a relating to the channel layer 103 (see FIG. 4A). The first high-concentration contact layer 35 is of the second conductivity type (p-type), and its impurity concentration is [p + ] is set.

[0032] A gate electrode 25 is provided on the channel layer 103 so as to sandwich the channel layer 103 in the width direction. A source layer 105 and an insulating layer 111 are selectively interposed between the gate electrode 25 and the emitter electrode 23a (including the first through-contact portion 31). In addition, an insulating layer 111 is interposed between the drift layer 101 and the gate electrode 25, and between the channel layer 103 and the gate electrode 25.

[0033] Here, since the first through-contact portion 31 penetrates the source layer 105, the first high-concentration contact layer 35 is located deeper (closer to the drift layer 101) than the source layer 105. This provides the effect of suppressing latch-up in the IGBT region 17.

[0034] More specifically, when the IGBT region 17 of the RC-IGBT 10 according to the comparative example is turned off, the holes accumulated in the drift layer 101 are discharged to the emitter electrode 23a via the channel layer 103 and the first high-concentration contact layer 35. At this time, since the first high-concentration contact layer 35 is located deeper than the source layer 105, the holes accumulated in the drift layer 101 are easily guided to the first high-concentration contact layer 35, and are discharged to the channel layer [p] 103 and the source layer [n + ] 105 is less likely to turn on, and as a result, latch-up in the IGBT region can be suppressed.

[0035] On the other hand, a third through contact portion 33 having a columnar and convex shape is formed in the anode electrode 23b belonging to the diode region 19, penetrating the insulating layer 111 and having a predetermined depth reaching the anode layer 117.

[0036] The third through contact portion 33 is provided so as to fit into the recess 117a of the anode layer 117. The back side of the third through contact portion 33 is disposed so as to face the front side (bottom) of the recess 117a of the anode layer 117. A second high-concentration contact layer 37 is formed between the back side of the third through contact portion 33 and the front side (bottom) of the recess 117a of the anode layer 117. The third through contact portion 33 and the second high-concentration contact layer 37 are provided continuously along the depth direction so as to be in close contact with the front side (bottom) of the recess 117a of the anode layer 117. The second high-concentration contact layer 37 is of the second conductivity type (p-type), and its impurity concentration is [p + ] is set.

[0037] A buried emitter electrode 119 is provided on the anode layer 117 so as to sandwich the anode layer 117 in the width direction. An insulating layer 111 is provided between the anode layer 117 and the buried emitter electrode 119 so as to be interposed therebetween.

[0038] A field plate electrode 109 is formed near a boundary 18 between the IGBT region 17 and the diode region 19 to separate the gate electrode 25 and the buried emitter electrode 119. The field plate electrode 109 contributes to improving the breakdown voltage of the RC-IGBT 10 by alleviating electric field concentration at a predetermined location. A columnar, convex second through contact 32 is formed near the boundary 18, penetrating the insulating layer 111 to a predetermined depth that reaches the field plate electrode 109. A gate oxide film 107 (insulating layer 111) is provided between the field plate electrode 109 and the drift layer 101.

[0039] In each of the IGBT region 17 and the diode region 19, a plurality of trenches 106 are formed at appropriate intervals in the width direction, penetrating the channel layer 103, the source layer 105, and the anode layer 117 and reaching the drift layer 101. The trenches 106, for example in the IGBT region 17, extend the layout of the current channel in the channel layer 103 facing the gate electrode 25 in the depth direction, thereby contributing to reducing the on-resistance of the RC-IGBT 10.

[0040] In the semiconductor device (RC-IGBT) 10 according to the comparative example, the first through contact portion 31 and the first high-concentration contact layer 35 belonging to the IGBT region 17, and the third through contact portion 33 and the second high-concentration contact layer 37 belonging to the diode region 19 are simultaneously formed in the same process. This has the advantage of reducing manufacturing costs due to the simplification of the manufacturing process. Note that the pair of the first high-concentration contact layer 35 and the second high-concentration contact layer 37 is simultaneously formed by introducing impurities using the insulating layer 111 as a mask after the pair of the first through contact portion 31 and the third through contact portion 33 are simultaneously formed.

[0041] However, in the semiconductor device (RC-IGBT) 10 according to the comparative example, the third through contact portion 33 and the second high-concentration contact layer 37 belonging to the diode region 19 are formed continuously along the depth direction. In this case, since the area of ​​the second high-concentration contact layer 37 is relatively large, there is a problem that the amount of holes injected when the diode region 19 is conductive becomes excessive, resulting in a large recovery loss.

[0042] [Semiconductor device 11A according to the first embodiment] Next, the semiconductor device (RC-IGBT) 11A according to the first embodiment will be described with reference to Fig. 2. Fig. 2 is a perspective view that schematically shows the general configuration of the semiconductor device 11A according to the first embodiment.

[0043] As shown in FIG. 2, the semiconductor device (RC-IGBT) 11A according to the first embodiment includes an IGBT region 17 and a diode region 19A in the same chip, similar to the semiconductor device 10 according to the comparative example.

[0044] The semiconductor device 10 according to the comparative example and the semiconductor device 11A according to the first embodiment share the same configuration related to the IGBT region 17, but differ in part in the configuration related to the diode region 19A. Therefore, the following description will focus on these different parts and serve as a substitute for the description of the semiconductor device 11A according to the first embodiment.

[0045] In the semiconductor device 10 according to the comparative example, as shown in FIG. 1, the third through contact portion 33 and the second high-concentration contact layer 37 belonging to the diode region 19 are formed continuously along the depth direction. In contrast, in the semiconductor device 11A according to the first embodiment, as shown in FIG. 2, the third through contact portion 33 and the second high-concentration contact layer 37 belonging to the diode region 19A are selectively formed along the depth direction.

[0046] Here, "the third through contact portion 33 and the second high-concentration contact layer 37 are selectively formed along the depth direction" means that a first region 41 in which a pair of the third through contact portion 33 and the second high-concentration contact layer 37 does not exist and a second region 43 in which a pair of the third through contact portion 33 and the second high-concentration contact layer 37 exists are alternately provided along the depth direction with respect to the insulating layer 111 and the anode layer 117.

[0047] In the first region 41, there is no pair of the third through contact portion 33 and the second high-concentration contact layer 37, and an insulating layer 111 and an anode electrode 23b are sequentially stacked on the front side of the anode layer 117 toward the front side.

[0048] In contrast, in the second region 43, a set of a third through contact portion 33 and a second high-concentration contact layer 37 exists, and on the front side (bottom surface) of the recess 117a relating to the anode layer 117, the second high-concentration contact layer 37, the third through contact portion 33, and the anode electrode 23b are each stacked in sequence toward the front side.

[0049] It should be noted here that in the semiconductor device 11A according to the first embodiment, the recesses 117a of the anode layer 117 are provided in the anode layer 117 in the form of rectangular columnar holes dug at predetermined intervals along the depth direction, as shown in Fig. 2. Incidentally, in the semiconductor device 10 according to the comparative example, the recesses 117a of the anode layer 117 are provided in the anode layer 117 in the form of trough-shaped holes dug continuously along the depth direction, as shown in Fig. 1. The width direction dimension W1 of the recess 117a in the anode layer 117 is set to a value smaller than the width direction dimension W2 of the anode layer 117. However, for ease of comparison, the width direction dimension W1 of the recess 117a in the anode layer 117 is assumed to be common to both the semiconductor device 11A according to the first embodiment and the semiconductor device 10 according to the comparative example.

[0050] It can be seen that the first total area S1 obtained by integrating the individual areas of the second high-concentration contact layer 37 in the semiconductor device 11A according to the first embodiment is narrower than the third total area S3 obtained by integrating the individual areas of the second high-concentration contact layer 37 in the semiconductor device 10 according to the comparative example by the amount that the locations of the recesses 117a in the anode layer 117 are appropriately thinned out along the depth direction. Here, the total area S obtained by integrating the individual areas of the second high-concentration contact layer 37 has a positive correlation with the amount of holes injected when the diode region 19 is conductive. Therefore, according to the semiconductor device 11A of the first embodiment, the amount of holes injected when the diode region 19 is conductive can be suppressed compared to the semiconductor device 10 of the comparative example, thereby reducing recovery loss.

[0051] In the semiconductor device 11A according to the first embodiment, similarly to the semiconductor device 10 according to the comparative example, the first heavily doped contact layer 35 is located deeper than the source layer 105. Therefore, holes accumulated in the drift layer 101 are easily guided to the first heavily doped contact layer 35, and the holes accumulated in the channel layer [p] 103 and the source layer [n + ] 105 is less likely to turn on, and as a result, the effect of suppressing latch-up in the IGBT region 17 can be expected. Furthermore, in the semiconductor device 11A according to the first embodiment, as in the semiconductor device 10 according to the comparative example, the first through contact portion 31 and the first high-concentration contact layer 35 belonging to the IGBT region 17, and the third through contact portion 33 and the second high-concentration contact layer 37 belonging to the diode region 19 are formed simultaneously in the same process, and therefore, the effect of reducing manufacturing costs can be expected due to the simplification of the manufacturing process.

[0052] 2, when the third through contact portion 33 is seen through from the front side, the third through contact portion 33 has a rectangular shape that extends to the bottom surface of a rectangular columnar hole provided in the anode layer 117. Therefore, the third through contact portion 33 has apexes 33a at its four corners where three sides of the third through contact portion 33 meet in the anode layer 117.

[0053] When the diode region 19A performs a recovery operation, the holes accumulated in the drift layer 101 are discharged to the anode electrode 23b via the anode layer 117 and the second high-concentration contact layer 37. At this time, since the third through-contact portion 33 has apexes 33a at the four corners of the anode layer 117, the hole current generated by the movement of holes tends to concentrate at the apexes 33a. As a result, the semiconductor device 11A according to the first embodiment has room for improvement in that the breakdown resistance decreases when the diode region 19A performs a recovery operation.

[0054] [Semiconductor device 11B according to the second embodiment] Next, a semiconductor device (RC-IGBT) 11B according to a second embodiment will be described with reference to FIGS. 3A, 3B, and 4A to 4C as appropriate. FIG. 3A is a perspective view schematically illustrating the general configuration of the semiconductor device 11B according to the second embodiment. FIG. 3B is a cross-sectional view schematically illustrating the general configuration of the semiconductor device 11B according to the second embodiment. FIG. 4A is a cross-sectional view taken along line 4A-4A in FIG. 3B. FIG. 4B is a cross-sectional view taken along line 4B-4B in FIG. 3B. FIG. 4C is a cross-sectional view taken along line 4C-4C in FIG. 3B.

[0055] In this specification, when there is no need to distinguish between the semiconductor device 11A according to the first embodiment and the semiconductor device 11B according to the second embodiment, they will be collectively referred to as "semiconductor device 11." Furthermore, when there is no need to distinguish between the diode region 19A belonging to the semiconductor device 11A of the first embodiment and the diode region 19B belonging to the semiconductor device 11B of the second embodiment, they will be collectively referred to as the "diode region 19."

[0056] As shown in Figures 3A and 3B, the semiconductor device (RC-IGBT) 11B of the second embodiment has an IGBT region 17 and a diode region 19B within the same chip, similar to the semiconductor device 10 of the comparative example and the semiconductor device 11A of the first embodiment.

[0057] The semiconductor device 11A according to the first embodiment and the semiconductor device 11B according to the second embodiment share the same configuration related to the IGBT region 17, but differ in part in the configuration related to the diode region 19B. Therefore, the following description will focus on these different parts and replace the description of the semiconductor device 11B according to the second embodiment.

[0058] In the semiconductor device 11A according to the first embodiment, as shown in FIG. 2, the third through contact portion 33 and the second high-concentration contact layer 37 belonging to the diode region 19A are selectively formed along the depth direction, and the width dimension W1 of the recess 117a relating to the anode layer 117 is set to a smaller value than the width dimension W2 of the anode layer 117. In contrast, in the semiconductor device 11B of the second embodiment, as shown in Figures 3A and 3B, the third penetrating contact portion 33 and the second high-concentration contact layer 37 belonging to the diode region 19B are the same as those of the semiconductor device 11A of the first embodiment in that they are selectively formed along the depth direction, but differ from the semiconductor device 11A of the first embodiment in that the width dimension W1 of the recess 117a of the anode layer 117 is set to be equal to the width dimension W2 of the anode layer 117.

[0059] What is noteworthy here is that, as shown in Figures 3A and 4C, when anode layer 117 is viewed from the side along the width direction, recesses 117a related to anode layer 117 are provided so as to penetrate both side walls of anode layer 117 along the width direction. However, for ease of comparison, the width dimension W2 of the anode layer 117 is assumed to be common to the semiconductor device 11B according to the second embodiment, the semiconductor device 11A according to the first embodiment, and the semiconductor device 10 according to the comparative example. Furthermore, for ease of comparison, the spacing at which the second high-concentration contact layer 37 is selectively provided along the depth direction and the depth dimension T1 of the second high-concentration contact layer 37 are assumed to be common to both the semiconductor device 11B according to the second embodiment and the semiconductor device 11A according to the first embodiment.

[0060] The second total area S2 obtained by integrating the individual areas of the second high-concentration contact layer 37 in the semiconductor device 11B according to the second embodiment is narrower than the third total area S3 obtained by integrating the individual areas of the second high-concentration contact layer 37 in the semiconductor device 10 according to the comparative example, when taking into consideration the fact that the width dimension W1 of the recess 117a in the anode layer 117 is wider and that the locations of the recess 117a in the anode layer 117 are appropriately thinned out along the depth direction. Here, the total area S obtained by integrating the individual areas of the second high-concentration contact layer 37 has a positive correlation with the amount of holes injected when the diode region 19 is conductive. Therefore, according to the semiconductor device 11B of the second embodiment, the amount of holes injected when the diode region 19B is conductive can be suppressed compared to the semiconductor device 10 of the comparative example, thereby reducing recovery loss.

[0061] Furthermore, in the semiconductor device 11A according to the first embodiment, the third through contact portion 33 has an apex 33a at each of its four corners where three sides meet in the anode layer 117, whereas in the semiconductor device 11B according to the second embodiment, the third through contact portion 33 does not have an apex 33a where three sides meet in the anode layer 117. Here, as described above, when the diode region 19 performs recovery operation, if the third through-contact portion 33 has peaks 33a at the four corners of the anode layer 117, as in the semiconductor device 11A according to the first embodiment, the hole current generated by the movement of holes tends to concentrate at the peaks 33a, which raises the concern that the breakdown resistance of the diode region 19 may be reduced when the diode region 19 performs recovery operation. Therefore, compared to the semiconductor device 11A according to the first embodiment, the semiconductor device 11B according to the second embodiment can avoid local concentration of hole current when the diode region 19B performs recovery operation, and as a result, it is expected to have the effect of increasing the breakdown resistance.

[0062] In the semiconductor device 11B according to the second embodiment, the first high-concentration contact layer 35 is located deeper than the source layer 105, as in the semiconductor device 11A according to the first embodiment. Therefore, holes accumulated in the drift layer 101 are easily guided to the first high-concentration contact layer 35, and the holes accumulated in the channel layer [p] 103 and the source layer [n + ] 105 is less likely to turn on, and as a result, the effect of suppressing latch-up in the IGBT region 17 can be expected. Furthermore, in the semiconductor device 11B of the second embodiment, as in the semiconductor device 11A of the first embodiment, the first through contact portion 31 and the first high-concentration contact layer 35 belonging to the IGBT region 17, and the third through contact portion 33 and the second high-concentration contact layer 37 belonging to the diode region 19B are formed simultaneously in the same process, and therefore, it is possible to expect the effect of reducing manufacturing costs due to the simplification of the manufacturing process.

[0063] [Semiconductor device 11 according to a modified example] Next, a semiconductor device 11 according to a modification will be described with reference to FIG. 5. FIG. 5 is a plan view of the semiconductor device 11 according to the modification, viewed from the front in the depth direction. The semiconductor device 11 according to the modification includes a plurality of IGBT regions 17 and diode regions 19. The semiconductor device 11 according to the modification also includes a peripheral region 43 provided to ensure a breakdown voltage. The semiconductor device 11 according to the modification has a configuration in which the respective components of the semiconductor device 11A according to the first embodiment and the semiconductor device 11B according to the second embodiment are mounted on a single semiconductor chip.

[0064] That is, in the semiconductor device 11 relating to the modified example, the diode region 19 is provided with a plurality of sets each including the anode layer 117, the recess 117a relating to the anode layer 117, the third through contact portion 33, and the second high-concentration contact layer 37, and in a first set 41 of the plurality of sets, a first setting mode is adopted in which the width dimension W1 of the recess 117a relating to the anode layer 117 belonging to the first set 41 is set to a value smaller than the width dimension W2 of the anode layer 117, and in a second set 42 of the plurality of sets, a second setting mode is adopted in which the width dimension W1 of the recess 117a relating to the anode layer 117 belonging to the second set 42 is set to be equal to the width dimension W2 of the anode layer 117.

[0065] As a premise, when diode region 19 of semiconductor device (RC-IGBT) 11 according to the present invention is in a conductive state, holes are injected from anode layer 117 into drift layer 101, and holes are accumulated in drift layer 101 near diode region 19. Furthermore, near boundary 18 between IGBT region 17 and diode region 19, holes are also injected from channel layer 103 of IGBT region 17 into drift layer 101 and accumulated therein. When the diode region 19 performs a recovery operation, the holes accumulated in the drift layer 101 are discharged to the anode electrode 23b via the anode layer 117 and the second high-concentration contact layer 37. Here, in the vicinity of the boundary portion 18, it is necessary to discharge not only the holes injected and accumulated from the anode layer 117 but also the holes injected and accumulated from the channel layer 103. That is, in this region, the number of holes to be discharged is large, and from the viewpoint of quickly discharging the holes to the anode electrode 23b, it is preferable that the total area S of the second high-concentration contact layer 37 is large.

[0066] Therefore, in the semiconductor device 11 according to the modified example, the width dimension W1 of the recess 117a of the anode layer 117 may be set in accordance with the widthwise separation distance by which the anode layer 117 is separated in the width direction from the boundary 18 between the IGBT region 17 and the diode region 19, so that the smaller the widthwise separation distance, the larger the widthwise dimension W1 of the recess 117a of the anode layer 117. Here, the width direction dimension W1 of the recess 117a of the anode layer 117 is synonymous with the total area S obtained by integrating the individual areas of the second high-concentration contact layer 37. With this configuration, the widthwise dimension W1 of the recess 117a of the anode layer 117 is set to be larger in areas where the number of holes is relatively large (closer to the boundary 18), thereby improving the efficiency of hole discharge to the anode electrode 23b and contributing to improved switching characteristics.

[0067] Furthermore, in the semiconductor device 11 according to the modified example, when the widthwise separation distance of the anode layer 117 from the boundary portion 18 is within a predetermined threshold, the second setting mode for the second group is adopted, and when the widthwise separation distance exceeds a predetermined threshold, the first setting mode for the first group may be adopted. With this configuration, in a region where the number of holes is relatively large (the widthwise separation distance of the anode layer 117 from the boundary portion 18 is within a predetermined threshold), the second setting mode is adopted, in which the widthwise dimension W1 of the recessed portion 117a of the anode layer 117 is set to be equal to the widthwise dimension W2 of the anode layer 117, while in a region where the number of holes is relatively small (the widthwise separation distance of the anode layer 117 from the boundary portion 18 exceeds a predetermined threshold), the first setting mode is adopted, in which the widthwise dimension W1 of the recessed portion 117a of the anode layer 117 is set to a value smaller than the widthwise dimension W2 of the anode layer 117, making it possible to adjust the amount of holes discharged to each anode electrode 23b depending on the number of holes that appear. This can contribute to further improvement of the switching characteristics.

[0068] The semiconductor device 11 according to the present invention has the following configuration. That is, the semiconductor device 11 according to the present invention is a drift layer (101) of a first conductivity type; a plurality of IGBT regions (17) formed in the drift layer (101); a plurality of diode regions (19) formed in the drift layer (101); a plurality of second conductivity type channel layers (103) formed in the drift layer (101) associated with the IGBT region (17); a plurality of first conductivity type source layers (105) formed in the channel layer (103); a plurality of second conductivity type anode layers (117) formed in the drift layer (101) associated with the diode region (19); a plurality of trenches (106) that penetrate the channel layer (103), the source layer (105), and the anode layer (117) and reach the drift layer (101); a gate oxide film (107) formed in the trench groove (106); a plurality of gate electrodes (25) selectively formed in the gate oxide film (107) so as to face the drift layer (101), the channel layer (103), and the source layer (105); a plurality of buried emitter electrodes (119) selectively formed in the gate oxide film (107) so as to face the drift layer (101) and the anode layer (117); a plurality of field plate electrodes (109) formed in the gate oxide film (107) so as to face the drift layer (101) and be spaced apart from the gate electrode (25) and the buried emitter electrode (119); an insulating layer (111) covering the source layer (105), the anode layer (117), the gate electrode (25), the buried emitter electrode (119), and the field plate electrode (109); a plurality of first through contact portions (31) that penetrate the insulating layer (111) and the source layer (105) and reach the channel layer (103); a plurality of second through contact portions (32) that penetrate the insulating layer (111) and reach the field plate electrode (109); a plurality of third through contact portions (33) that penetrate the insulating layer (111) and reach the anode layer (117); a plurality of first high-concentration contact layers (35) of a second conductivity type selectively formed in a region of the channel layer (103) that contacts the first through-contact portion (31); a plurality of second high-concentration contact layers (37) of a second conductivity type selectively formed in a region of the anode layer (117) that contacts the third through contact portion (33); an emitter electrode (23a) covering the insulating layer (111) and burying the first through contact portion (31), the second through contact portion (32), and the third through contact portion (33); a buffer layer (113) of a first conductivity type formed on the drift layer (101); a collector layer (115) of a second conductivity type formed on the buffer layer (113) in the IGBT region (17); a cathode layer (116) of a first conductivity type formed on the buffer layer (113) in the diode region (19); A semiconductor device (11) comprising the collector layer (115) and a collector electrode (21a) formed on the cathode layer (116), the first through contact portion (31) is formed continuously along the direction in which the trench groove (106) extends, and is selectively formed with respect to the channel layer (103) in a direction perpendicular to the direction in which the trench groove (106) extends; The third through contact portion (33) is formed intermittently along the direction in which the trench groove (106) extends, and is formed with a width that spans the entire anode layer (117) in a direction perpendicular to the direction in which the trench groove (106) extends. However, the gate oxide film (107) is included in the concept of the insulating layer (111). According to the semiconductor device 11 of the present invention, it is possible to provide a semiconductor device 11 that can simultaneously achieve high performance in the IGBT region 17 and the diode region 19 by using a new approach that differs from existing technology.

[0069] [Power conversion device 500] Next, a power conversion device 500 in which the semiconductor device 11 according to the present invention is applied as switching elements 501 to 506 will be described with reference to FIG. FIG. 6 is a circuit diagram of a power conversion device 500 in which the semiconductor device 11 according to the present invention is applied as a switching element, and shows an example of the circuit configuration of the power conversion device 500 and the connection relationship between a DC power supply and a three-phase AC motor (AC load).

[0070] As shown in FIG. 6, the power conversion device 500 includes a pair of DC terminals, namely, P terminal 531 and N terminal 532, and AC terminals, namely, U terminal 533, V terminal 534, and W terminal 535, the number of which is the same as the number of phases of the AC output.

[0071] Power conversion device 500 includes a switching leg consisting of a pair of power switching elements 501 and 502 connected in series, with U-terminal 533 connected to their series connection point as its output. It also includes a switching leg consisting of power switching elements 503 and 504 connected in series with the same configuration, with V-terminal 534 connected to their series connection point as its output. It also includes a switching leg consisting of power switching elements 505 and 506 connected in series with the same configuration, with W-terminal 535 connected to their series connection point as its output.

[0072] Three-phase switching legs consisting of power switching elements 501 to 506 are connected between DC terminals P terminal 531 and N terminal 532, and DC power is supplied from a DC power supply (not shown). Three-phase AC terminals of power conversion device 500, namely U terminal 533, V terminal 534, and W terminal 535, are connected to a three-phase AC motor (not shown) as a three-phase AC power supply.

[0073] Diodes 521 to 526 are connected in anti-parallel to the power switching elements 501 to 506, respectively. Gate circuits 511 to 516 are connected to the input terminals of the gates of the power switching elements 501 to 506, which are each made of an IGBT, and the power switching elements 501 to 506 are controlled by the gate circuits 511 to 516, respectively. The gate circuits 511 to 516 are controlled in an integrated manner by an integrated control circuit (not shown).

[0074] Gate circuits 511-516 comprehensively and appropriately control power switching elements 501-506, converting DC power from DC power supply Vcc into three-phase AC power, which is output from U terminal 533, V terminal 534, and W terminal 535.

[0075] The power conversion device 500 according to the present invention has AC terminals in the same number as the number of phases of the AC output, switching legs connected between the pair of DC terminals and each having a parallel circuit of a switching element and a reverse-polarity diode connected in series, in the same number as the number of phases of the AC output, and a gate circuit for controlling the switching elements, in which the semiconductor device (RC-IGBT) 11 according to the present invention is used as the switching elements.

[0076] By applying the semiconductor device (RC-IGBT) 11 of the present invention to the power conversion device 500, the power switching elements 501 to 506 and the diodes 521 to 526 can be mounted together on a single semiconductor chip, thereby making it possible to reduce the size of the power conversion device 500 and improve its heat dissipation characteristics. Furthermore, by applying the semiconductor device 11 according to the present invention to the power converter 500, it is possible to provide the power converter 500 in which the recovery characteristics of the diode region 19 are improved.

[0077] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments and modifications have been described to aid in understanding the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0078] In the description of the semiconductor device 11 according to the present invention, an example in which the first conductivity type is n-type and the second conductivity type is p-type has been given, but the present invention is not limited to this example. Semiconductor device 11 in which the first conductivity type is p-type and the second conductivity type is n-type is also included within the technical scope of the present invention.

[0079] Finally, in the embodiments and modifications of the present invention, the control lines and information lines shown are those that are considered necessary for explanation, and do not necessarily show all the control lines and information lines on the product. [Explanation of symbols]

[0080] 11, 11A, 11B Semiconductor device (RC-IGBT) 17 IGBT area 18 Boundary 19, 19A, 19B Diode Area 21a Collector electrode 21b Cathode electrode 23a Emitter electrode 23b Anode electrode 25 gate electrode 31 first through contact portion 33 Third through contact part 33a Top 35 First high concentration contact layer 37 Second high-concentration contact layer 41 First Group 42 Second set 43 Outer area 101 Drift Layer 103 Channel Layer 103a Recessed portion relating to the channel layer 105 Source Layer 106 Trench 107 Gate oxide 111 Insulating layer 113 Buffer Layer 115 Collector layer 116 Cathode layer 117 Anode layer 117a Recessed portion relating to the anode layer 500 Power Converter 501, 502, 503, 504, 505, 506 Power switching elements 521, 522, 523, 524, 525, 526 Diodes 531 P terminal 532 N terminal 533 U terminal 534 V terminal 535 W terminal

Claims

1. A semiconductor device (11) configured by forming an IGBT region (17) and a diode region (19) in a drift layer (101) of a first conductivity type, The diode region (19) has a structure in which a cathode electrode (21b), a cathode layer (116), a buffer layer (113), the drift layer (101), an anode layer (117), an insulating layer (111), and an anode electrode (23b) are stacked from the back side to the front side, A columnar third through contact portion (33) is formed in the anode electrode (23b) belonging to the diode region (19), the third through contact portion (33) having a predetermined depth that penetrates the insulating layer (111) and reaches the anode layer (117); The third through contact portion (33) is provided so as to fit into a recess (117a) formed in the anode layer (117), a second high-concentration contact layer (37) of a second conductivity type is formed between the back side of the third through contact portion (33) and the front side of the recess (117a) of the anode layer (117); The third through contact portion (33) and the second high-concentration contact layer (37) are selectively provided along the depth direction so as to contact the front side surface of the recess (117a) of the anode layer (117). A semiconductor device characterized by:

2. 2. The semiconductor device according to claim 1, The recesses (117a) of the anode layer (117) are provided in the anode layer (117) in the form of rectangular columnar holes dug at predetermined intervals along the depth direction. A semiconductor device characterized by:

3. 3. The semiconductor device according to claim 2, The width dimension (W1) of the recess (117a) of the anode layer (117) is set to a value smaller than the width dimension (W2) of the anode layer (117). A semiconductor device characterized by:

4. 3. The semiconductor device according to claim 2, The width dimension (W1) of the recess (117a) of the anode layer (117) is set to be equal to the width dimension (W2) of the anode layer (117). A semiconductor device characterized by:

5. The semiconductor device according to any one of claims 1 to 4, The IGBT region (17) has a structure in which a collector electrode (21 a), a collector layer (115), a buffer layer (113), the drift layer (101), a channel layer (103), an insulating layer (111), and an emitter electrode (23 a) are stacked from the back side to the front side, The emitter electrode (23a) belonging to the IGBT region (17) is formed with a columnar first through contact portion (31) having a predetermined depth that penetrates the insulating layer (111) and the source layer (105) and reaches the channel layer (103); The first through contact portion (31) is provided so as to fit into a recess (103a) formed in the channel layer (103), a first high-concentration contact layer (35) of a second conductivity type is formed between the backside surface of the first through contact portion (31) and the front side surface of the recess (103a) relating to the channel layer (103); The first through contact portion (31) and the first high-concentration contact layer (35) are provided continuously along the depth direction so as to contact the front side surface of the recess (103a) of the channel layer (103). A semiconductor device characterized by:

6. 6. The semiconductor device according to claim 5, The first high concentration contact layer (35) belonging to the IGBT region (17) is located deeper than the source layer (105). A semiconductor device characterized by:

7. 6. The semiconductor device according to claim 5, The first through contact portion (31) and the first high concentration contact layer (35) belonging to the IGBT region (17), and the third through contact portion (33) and the second high concentration contact layer (37) belonging to the diode region (19) are formed simultaneously in the same process. A semiconductor device characterized by:

8. 3. The semiconductor device according to claim 1, The diode region (19) is provided with a plurality of sets including the anode layer (117), the recess (117a) related to the anode layer (117), the third through-contact portion (33), and the second high-concentration contact layer (37); a first set of the plurality of sets employs a first setting mode in which a width direction dimension (W1) of the recess (117a) associated with the anode layer (117) belonging to the first set is set to a value smaller than a width direction dimension (W2) of the anode layer (117); In a second set of the plurality of sets, a second setting mode is adopted in which the width direction dimension (W1) of the recess (117a) related to the anode layer (117) belonging to the second set is set to be equal to the width direction dimension (W2) of the anode layer (117). A semiconductor device characterized by:

9. 9. The semiconductor device according to claim 8, The widthwise dimension (W1) of the recess (117a) of the anode layer (117) is set in accordance with a widthwise separation distance by which the anode layer (117) is separated in the width direction from a boundary portion (18) between the IGBT region (17) and the diode region (19), such that the smaller the widthwise separation distance, the larger the widthwise dimension (W1) of the recess (117a) of the anode layer (117). A semiconductor device characterized by:

10. 10. The semiconductor device according to claim 9, If the widthwise separation distance of the anode layer (117) relative to the boundary (18) is within a predetermined threshold, a second setting for the second set is adopted, whereas if the widthwise separation distance exceeds a predetermined threshold, a first setting for the first set is adopted. A semiconductor device characterized by:

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