Nitrogen-rich silicon nitride film for thin film transistor

Abstract

To provide nitrogen-rich silicon nitride, a method for depositing nitrogen-rich silicon nitride, and a transistor and a device containing nitrogen-rich silicon nitride.SOLUTION: In a thin film transistor (TFT) 800, a passivation film stack 156 includes a silicon oxide layer 160 disposed on a workpiece, and a nitrogen-rich silicon nitride layer 170 disposed on the silicon oxide layer. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atom% (at%) to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%. In addition, the passivation film stack may include a silicon oxide layer, a nitrogen-rich silicon nitride layer, and a third layer containing any type of silicon nitride such as nitrogen-rich silicon nitride and / or hydrogen-rich silicon nitride.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to deposition processes, and more particularly to vapor deposition processes for depositing silicon nitride and other materials onto workpieces. [Background technology]

[0002] Liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), and microLED panels are often used in flat panel displays. Typically, LCDs generally contain two glass substrates bonded together with a layer of liquid crystal material sandwiched between them. The glass substrates may be semiconductor substrates or transparent substrates such as glass, quartz, sapphire, or clear plastic films. LCDs may also contain light-emitting diodes for backlighting.

[0003] As the resolution requirements for LCDs increase, it becomes desirable to control a large number of individual regions of the liquid crystal cell, called pixels. Modern display panels may have approximately 8 million pixels (4K resolution), approximately 33 million pixels (8K resolution), or even more. At least this many transistors are formed on the glass substrate, allowing each pixel to be switched between an energized and de-energized state relative to the other pixels disposed on the substrate.

[0004] Silicon-containing materials are the building blocks of most TFTs, being used to form channel materials such as polysilicon for low-temperature polysilicon (LTPS) TFTs, and even as components utilized in forming the TFT's gate dielectric layer, interface layer, passivation layer, and / or etch stop layer.

[0005] In metal oxide channel-based TFTs, silicon-containing passivation layers cannot protect the device against humidity and gas diffusion, especially in the case of In-Ga-Zn oxide (IGZO) channel semiconductors. The diffusion of humidity (H2O) and / or gases (e.g., H2, O2, and / or N2) into the IGZO channel semiconductor and other layers can destabilize the entire device. Typically, humidity and gases are generated by various underlying layers and can diffuse through or out of passivation layers containing hydrogen-rich silicon oxide and / or hydrogen-rich silicon nitride.

[0006] Therefore, there is a need for passivation materials to reduce or eliminate the diffusion of moisture and / or gases within TFTs or other types of devices. Summary of the Invention

[0007]

[0003] Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride, methods for depositing nitrogen-rich silicon nitride, and transistors and other devices containing nitrogen-rich silicon nitride. In one or more embodiments, a passivation film stack contains a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percent (at%) to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%. In one or more examples, the passivation film stack contains a silicon oxide layer, a nitrogen-rich silicon nitride layer, and a third layer containing any type of silicon nitride, such as nitrogen-rich silicon nitride and / or hydrogen-rich silicon nitride.

[0008] In another embodiment, the passivation film stack includes a silicon oxide layer disposed on the workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, the nitrogen-rich silicon nitride layer having a water resistivity of about 1×10 -8 g / m 2 / day ~ approx. 1 x 10-4 g / m 2 / day and has a silicon-hydrogen bond concentration of about 0.1% to about 10%, and the nitrogen-rich silicon nitride layer has a nitrogen to silicon ratio of greater than 1.03 to about 2. In some examples, the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration of about 0.5% to about 6% and a total hydrogen bond concentration (including the nitrogen-hydrogen bond concentration) of less than 30%.

[0009] In some embodiments, a method for depositing a silicon nitride material includes heating a workpiece to a temperature of about 200°C to about 250°C, exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition (PE-CVD) process, and depositing a nitrogen-rich silicon nitride layer on the workpiece. The deposition gas contains a silicon precursor, a nitrogen precursor, and a carrier gas, and the molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are about 1: about 4 to about 8: about 20 to about 80, respectively. In some examples, the molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are about 1: about 5 to about 7: about 30 to about 50, respectively. In one or more examples, the silicon precursor is or contains silane, the nitrogen precursor is or contains ammonia, and the carrier gas is or contains nitrogen (N).

[0010] So that the techniques of the above-listed features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above will be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only exemplary embodiments and, therefore, should not be considered as limiting the scope of the invention, as other equally effective embodiments may be recognized. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a schematic diagram of a thin film transistor (TFT) structure containing a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein. [Figure 2] 1 is a schematic diagram of another TFT structure containing a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein. [Figure 3] 1 is a schematic diagram of another TFT structure containing a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein. [Figure 4] 1 is a schematic diagram of another TFT structure containing a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein. [Figure 5] 1 is a schematic diagram of another TFT structure containing a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein. [Figure 6] 1 is a schematic diagram of another TFT structure containing a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein. [Figure 7] 1 is a schematic diagram of a TFT structure containing two nitrogen-rich silicon nitride layers according to one or more embodiments described and discussed herein. [Figure 8] 1 is a schematic diagram of another TFT structure containing two nitrogen-rich silicon nitride layers according to one or more embodiments described and discussed herein. DETAILED DESCRIPTION OF THE INVENTION

[0012] For ease of understanding, the same reference numerals have been used, where possible, to designate like elements that are common to the figures. It is contemplated that elements and features of one or more embodiments may be beneficially incorporated in other embodiments.

[0013]

[0002] Embodiments of the present disclosure generally relate to passivation film stacks containing nitrogen-rich silicon nitride, methods for depositing the passivation film stacks, and transistors and other devices containing the passivation film stacks. In one or more embodiments, the passivation film stack includes a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. In some examples, the passivation film stack is disposed on the workpiece and includes a silicon oxide layer, a nitrogen-rich silicon nitride layer, and a third layer containing any type of silicon nitride, such as nitrogen-rich silicon nitride and / or hydrogen-rich silicon nitride.

[0014] A nitrogen-rich silicon nitride layer contains more nitrogen and / or less hydrogen than conventional silicon nitride. Conventional silicon nitride is typically nitrogen-poor and / or hydrogen-rich silicon nitride. Thus, a hydrogen-rich silicon nitride layer has a higher hydrogen concentration than the nitrogen-rich silicon nitride layer described and discussed herein. Additionally, a nitrogen-rich silicon nitride layer has a higher water resistance than nitrogen-poor and / or hydrogen-rich silicon nitride.

[0015] In one or more embodiments, the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percent (at%), about 22 at%, about 24 at%, about 25 at%, about 26 at%, about 27 at%, about 28 at%, about 29 at%, about 30 at%, or about 31 at% to about 32 at%, about 33 at%, about 34 at%, about 35 at%, about 36 at%, about 37 at%, or about 38 at% or greater. For example, a nitrogen-rich silicon nitride layer may have a silicon concentration of about 20 at % to about 38 at %, about 22 at % to about 38 at %, about 25 at % to about 38 at %, about 27 at % to about 38 at %, about 28 at % to about 38 at %, about 30 at % to about 38 at %, about 31 at % to about 38 at %, about 32 at % to about 38 at %, about 33 at % to about 38 at %, about 35 at % to about 38 at %, about 36 at % to about 38 at %, about 20 at % to about 35 at %, about 22 at % to about 35 at %, about 25 at % to about 35 at %, about 27 at % to about 35 at %, about 28 at % to about 35 at %, about 30 at % to about 35 at %, about 31 at % to about 35 at %. t%, about 32at% to about 35at%, about 33at% to about 35at%, about 20at% to about 34at%, about 22at% to about 34at%, about 25at% to about 3 4at%, approximately 27at% to approximately 34at%, approximately 28at% to approximately 34at%, approximately 30at% to approximately 34at%, approximately 31at% to approximately 34at%, approximately 32at% to approximately 34at%, about 33at% to about 34at%, about 20at% to about 33at%, about 22at% to about 33at%, about 25at% to about 33at%, about 27at% to about 33 at%, about 28 at% to about 33 at%, about 30 at% to about 33 at%, about 31 at% to about 33 at%, or about 32 at% to about 33 at%.

[0016] In some embodiments, the nitrogen-rich silicon nitride layer has a nitrogen concentration of about 40 at%, about 42 at%, about 43 at%, about 44 at%, about 45 at%, about 46 at%, about 48 at%, about 50 at%, or about 52 at% to about 54 at%, about 55 at%, about 58 at%, about 60 at%, about 65 at%, about 70 at%, about 72 at%, or about 75 at% or more. For example, the nitrogen-rich silicon nitride layer has a nitrogen concentration of about 40 at% to about 75 at%, about 42 at% to about 75 at%, about 43 at% to about 75 at%, about 44 at% to about 75 at%, about 45 at% to about 75 at%, about 48 at% to about 75 at%, about 50 at% to about 75 at%, about 55 at% to about 75 at%, about 60 at% to about 75 at%, about 65 at% to about 75 at%, about 70 at% to about 75 at%, about 40 at% to about 65 at%, about 42 at% to about 65 at%, about 43 at% to about 65 at%, about 44 at% to about 65 at%, about 45 at% to about 65 at%, or about 48 at% to about 65 at%. about 50 at% to about 65 at%, about 55 at% to about 65 at%, about 60 at% to about 65 at%, about 62 at% to about 65 at%, about 40 at% to about 58 at%, about 42 at% to about 58 at%, about 43 at% to about 58 at%, about 44 at% to about 58 at%, about 45 at% to 58 at%, about 48 at% to about 58 at%, about 50 at% to about 58 at%, about 55 at% to about 58 at%, about 40 at% to about 55 at%, about 42 at% to about 55 at%, about 43 at% to about 55 at%, about 44 at% to about 55 at%, about 45 at% to about 55 at%, about 48 at% to about 55 at%, about 50 at% to about 55 at%, or about 52 at% to about 55 at%.

[0017] In one or more embodiments, the nitrogen-rich silicon nitride layer has a hydrogen concentration of about 10 at%, about 12 at%, about 15 at%, about 18 at%, or about 20 at% to about 21 at%, about 22 at%, about 23 at%, about 25 at%, about 27 at%, about 30 at%, about 32 at%, or about 35 at% or greater. For example, the nitrogen-rich silicon nitride layer has a hydrogen concentration of about 10 at% to about 35 at%, about 12 at% to about 35 at%, about 15 at% to about 35 at%, about 18 at% to about 35 at%, about 19 at% to about 35 at%, about 20 at% to about 35 at%, about 21 at% to about 35 at%, about 22 at% to about 35 at%, about 23 at% to about 35 at%, about 24 at% to about 35 at%, about 25 at% to about 35 at%, about 28 at% to about 35 at%, about 30 at% to about 35 at%, about 10 at% to about 25 at%, about 12 at% to about 2 5at%, about 15at% to about 25at%, about 18at% to about 25at%, about 19at% to about 25at%, about 20at% to 25at%, about 21at% to 25at%, about 22at% to 25at%, about 23at% to 25at%, about 24at% to 25at%, about 10 at% to about 23 at%, about 12 at% to about 23 at%, about 15 at% to about 23 at%, about 18 at% to about 23 at%, about 19 at% to about 23 at%, about 20 at% to about 23 at%, about 21 at% to about 23 at%, or about 22 at% to about 23 at%.

[0018] In one or more examples, the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at% to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%. In other examples, the nitrogen-rich silicon nitride layer has a silicon concentration of about 27 at% to about 34 at%, a nitrogen concentration of about 42 at% to about 65 at%, and a hydrogen concentration of about 18 at% to about 25 at%. In some examples, the nitrogen-rich silicon nitride layer has a silicon concentration of about 28 at% to about 33 at%, a nitrogen concentration of about 43 at% to about 58 at%, and a hydrogen concentration of about 19 at% to about 23 at%.

[0019] In one or more embodiments, the nitrogen-rich silicon nitride layer has a nitrogen to silicon ratio greater than 1, greater than 1.02, greater than 1.03, or greater than 1.05, such as about 1.06, about 1.08, about 1.10, about 1.12, about 1.15, about 1.18, about 1.20, about 1.22, or about 1.25 to about 1.28, about 1.30, about 1.35, about 1.38, about 1.40, about 1.45, about 1.50, about 1.55, about 1.60, about 1.80, about 1.90, or about 2 or greater. For example, a nitrogen-rich silicon nitride layer may have a nitrogen to silicon ratio of greater than 1.03 to about 2, greater than 1.03 to about 1.9, greater than 1.03 to about 1.8, greater than 1.03 to about 1.7, greater than 1.03 to about 1.6, greater than 1.03 to about 1.5, greater than 1.03 to about 1.45, greater than 1.03 to about 1.4, greater than 1.03 to about 1.39, greater than 1.03 to about 1.38, 1.03 to about 1.36, greater than 1.03 to about 1.35, greater than 1.03 to about 1.3, 1.03 greater than 1.03 to about 1.25, greater than 1.03 to about 1.2, greater than 1.03 to about 1.15, greater than 1.03 to about 1.1, about 1.05 to about 2, about 1.05 to about 1.9, about 1.05 to about 1.8, about 1.05 to about 1.7, about 1.05 to about 1.6, about 1.05 to about 1.5, about 1.05 to about 1.45, about 1.05 to about 1.4, about 1.05 to about 1.39, about 1.05 to about 1.38, about 1.05 to about 1.36, about 1.05 to about 1.35, about 1.05 to about 1.3, about 1.05 to about 1.25, about 1.05 to about 1.2, about 1.05 to about 1.15, about 1.05 to about 1.1, about 1.1 to about 2, about 1.1 to about 1.9, about 1.1 to about 1.8, about 1.1 to about 1.7, about 1.1 to about 1.6, about 1.1 to about 1.5, about 1.1 to about 1.45, about 1.1 to about 1.4, about 1.1 to about 1.39, about 1.1 to about 1.38, about 1.1 to about 1.36, about 1.1 to about 1.35, about 1.1 to about 1. 3, about 1.1 to about 1.25, about 1.1 to about 1.2, about 1.1 to about 1.15, about 1.2 to about 2, about 1.2 to about 1.9, about 1.2 to about 1.8, about 1.2 to about 1.7, about 1.2 to about 1.6, about 1.2 to about 1.5, about 1.2 to about 1.45, about 1.2 to about 1.4, about 1.2 to about 1.39, about 1.2 to about 1.38, about 1.2 to about 1.36, about 1.2 to about 1.35, about 1.2 to about 1.3, or about 1.2 to about 1.25.

[0020] In some embodiments, the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration as determined by Fourier transform infrared (FT-IR) spectroscopy of less than about 0.05%, about 0.1%, about 0.2%, about 0.5%, about 0.8%, about 1%, about 1.2%, about 1.5%, about 1.8%, or about 2% to about 2.2%, about 2.5%, about 2.8%, about 3%, about 3.5%, about 4%, about 5%, about 6%, about 8%, about 10%, about 12%, about 14%, about 15%, about 16%, about 17%, or 18%. For example, the nitrogen-rich silicon nitride layer may have a silicon-hydrogen bond concentration, as determined by FT-IR spectroscopy, of about 0.1% to less than about 18%, about 0.1% to about 17%, about 0.1% to about 15%, about 0.1% to about 12%, about 0.1% to about 10%, about 0.1% to about 8%, about 0.1% to about 6%, about 0.1% to about 5%, about 0.1% to about 4%, about 0.1% to about 3%, about 0.1% to about 2%, about 0.1% to about 1%, about 0.5% to less than 18%, about 0.5% to about 17%, about 0.5% to about 15%, about 0.5% to about 12%, about 0.5% to about 10%, about 0.5% to about 8%, about 0.5% to about 6%, about 0.5% to about 5%, about 0.5% to about 4%, about 0.5% to about 3%, about 0.5% to about 2%, about 0.5% to 1%, about 1% to less than about 18%, about 1% to about 17%, about 1% to about 15%, about 1% to about 12%, about 1% to about 10%, about 1% to about 8%, about 1% to about 6%, about 1% to about 5%, about 1% to about 4%, about 1% to about 3%, about 1% to about 2%, or about 1% to about 1.5%.

[0021] In one or more embodiments, the nitrogen-rich silicon nitride layer has a nitrogen-hydrogen bond concentration as determined by FT-IR spectroscopy of about 1%, about 3%, about 5%, about 6%, about 8%, about 10%, about 12%, about 15%, or about 18% to about 20%, about 22%, about 25%, about 26%, about 27%, about 28%, about 28%, or about 30%. For example, the nitrogen-rich silicon nitride layer may have a nitrogen-hydrogen bond concentration, as determined by FT-IR spectroscopy, of about 1% to about 30%, about 3% to about 30%, about 5% to about 30%, about 8% to about 30%, about 10% to about 30%, about 12% to about 30%, about 15% to about 30%, about 18% to about 30%, about 20% to about 30%, about 25% to about 30%, about 1% to about 25%, or about 3% to about 25%. %, about 5% to about 25%, about 8% to about 25%, about 10% to about 25%, about 12% to about 25%, about 15% to about 25%, about 18% to about 25%, about 20% to about 25%, about 1% to about 22%, about 3% to about 22%, about 5% to about 22%, about 8% to about 22%, about 10% to about 22%, about 12% to about 22%, about 15% to about 22%, about 18% to about 22%, or about 20% to about 22%.

[0022] The total hydrogen bond concentration of the nitrogen-rich silicon nitride layer is the sum of the silicon-hydrogen bond concentration and the nitrogen-hydrogen bond concentration. In one or more embodiments, the nitrogen-rich silicon nitride layer has a total hydrogen bond concentration of less than 30%, as determined by FT-IR spectroscopy, such as about 1%, about 2%, about 3%, about 5%, about 6%, about 8%, about 10%, about 12%, about 15%, about 16%, or about 18% to about 20%, about 22%, about 23%, about 24%, about 25%, about 26%, about 27%, about 28%, about 28%, about 29%, or less than 30%. For example, the nitrogen-rich silicon nitride layer may have a nitrogen-hydrogen bond concentration, as determined by FT-IR spectroscopy, of about 1% to less than 30%, about 3% to less than 30%, about 5% to less than 30%, about 8% to less than 30%, about 10% to less than 30%, about 12% to less than 30%, about 15% to less than 30%, about 18% to less than 30%, about 20% to less than 30%, about 25% to less than 30%, about 1% to about 28%, about 3% to about 28%, about 5% to about 28%, about 8% to about 28%, about 10% to about 28%, about 12% to about 28%, about 15% about 28%, about 18% to about 28%, about 20% to about 28%, about 1% to about 24%, about 3% to about 24%, about 5% to about 24%, about 8% to about 24%, about 10% to about 24%, about 12% to about 24%, about 15% to about 24%, about 18% to about 24%, about 20% to about 24%, about 1% to about 23%, about 3% to about 23%, about 5% to about 23%, about 8% to about 23%, about 10% to about 23%, about 12% to about 23%, about 15% to about 23%, about 16% to about 23%, about 18% to about 23%, or about 20% to about 23%.

[0023] The nitrogen-rich silicon nitride layer has a relatively high water resistance when compared to conventional silicon nitride. In one or more embodiments, the nitrogen-rich silicon nitride layer has a water resistance of about 1×10 according to a standard water vapor transmission rate (WVTR) test conducted at 85% relative humidity and 85° C. -8 g / m 2 / day or more, for example, about 2 × 10 -8 g / m 2 / day, approximately 5 × 10 -8 g / m 2 / day, approximately 1 × 10 -7 g / m 2 / day, approximately 5 × 10 -7 g / m2 / day, approximately 1 × 10 -6 g / m 2 / day, or approximately 5 × 10 -6 g / m 2 / day ~ approx. 1 x 10 -5 g / m 2 / day, approximately 5 × 10 -5 g / m 2 / day, approximately 1 × 10 -4 g / m 2 / day, approximately 5 × 10 -4 g / m 2 / day, or approximately 1 x 10 -3 g / m 2 For example, a nitrogen-rich silicon nitride layer has a water resistance of about 1×10 / day according to the WVTR standard test conducted at 85% relative humidity and 85°C. -8 g / m 2 / day ~ approx. 1 x 10 -4 g / m 2 / day, approximately 1 × 10 -7 g / m 2 / day ~ approx. 5 x 10 -4 g / m 2 / day, or approximately 5 × 10 -6 g / m 2 / day ~ approx. 1 x 10 -5 g / m 2 In one or more examples, a nitrogen-rich silicon nitride layer having a thickness of about 2000 Å has a water resistance of about 2.8×10 per day according to a WVTR standard test conducted at 100% relative humidity and 40° C. -4 g / m 2 / day ~ approx. 4 x 10 -4 g / m 2 / day.

[0024] In one or more embodiments, a method for depositing a nitrogen-rich silicon nitride material or layer includes heating a workpiece to a processing temperature, exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition (PE-CVD) process, and depositing a nitrogen-rich silicon nitride material or layer on the workpiece. In other embodiments, a method for depositing a nitrogen-rich silicon nitride material or layer includes heating a workpiece to a processing temperature, sequentially exposing the workpiece to a silicon precursor and a nitrogen precursor during a thermal atomic layer deposition (ALD) process or a plasma-enhanced ALD (PE-ALD) process, and depositing a nitrogen-rich silicon nitride material or layer on the workpiece. In the embodiments described and discussed herein, the workpiece may be or include a substrate, a thin film transistor (TFT) structure or portion thereof, a gate structure or portion thereof, or any other type of electronic device or portion thereof related to displays, semiconductors, photovoltaics, microelectronics, and / or other fields. In some examples, the workpiece includes one or more layers containing silicon oxide. In one or more examples, the method includes depositing a silicon oxide layer on the workpiece and then depositing a nitrogen-rich silicon nitride layer on the silicon oxide layer.

[0025] During a PE-CVD or other deposition process, the substrate or workpiece can be heated to or maintained at a processing temperature, which can be about 25°C, about 50°C, about 80°C, about 100°C, about 150°C, or about 200°C to about 220°C, about 235°C, about 250°C, about 280°C, about 300°C, about 350°C, or about 400°C or higher. For example, the treatment temperature may be from about 25°C to about 400°C, from about 25°C to about 300°C, from about 25°C to about 280°C, from about 25°C to about 265°C, from about 25°C to about 250°C, from about 25°C to about 235°C, from about 25°C to about 220°C, from about 25°C to about 200°C, from about 25°C to about 180°C, from about 25°C to about 150°C, from about 25°C to about 125°C, from about 25°C to about 100°C, from about 25°C to about 80°C, from about 25°C to about 50°C, from about 100°C to about 400°C, from about 100°C to about 300°C, from about 100°C to about 280°C, from about 100°C to about 265°C, or from about 1 The heating temperature may be about 00°C to about 250°C, about 100°C to about 235°C, about 100°C to about 220°C, about 100°C to about 200°C, about 100°C to about 180°C, about 100°C to about 150°C, about 100°C to about 125°C, about 200°C to about 400°C, about 200°C to about 300°C, about 200°C to about 280°C, about 200°C to about 265°C, about 200°C to about 250°C, about 200°C to about 235°C, about 200°C to about 220°C, about 220°C to about 250°C, about 230°C to about 250°C, or about 235°C to about 250°C. In one or more examples, the processing temperature is less than 350°C, less than 300°C, less than 280°C, less than 265°C, less than 250°C, less than 235°C, or less than 200°C.

[0026] In one or more embodiments, during a PE-CVD or other deposition process, the deposition gas may include one or more silicon precursors, one or more nitrogen precursors, and one or more carrier gases. The silicon precursor may be or include one or more of silane, disilane, trisilane, tetrasilane, silicon tetrafluoride, or any combination thereof. The nitrogen precursor may be or include ammonia, hydrazine, methylamine, dimethylamine, nitrogen (N), one or more plasmas thereof, or any combination thereof. The carrier gas may be or include one or more of nitrogen (N), hydrogen (H), argon, helium, neon, xenon, krypton, or any combination thereof. In one or more examples, the silicon precursor is or includes silane, the nitrogen precursor is or includes ammonia, and the carrier gas is or includes nitrogen.

[0027] The flow rate of the silicon precursor in the deposition gas can be about 100 sccm (standard cubic centimeters per minute), about 150 sccm, about 180 sccm, about 200 sccm, about 220 sccm, or about 250 sccm to about 280 sccm, about 300 sccm, about 320 sccm, about 350 sccm, about 400 sccm, about 450 sccm, about 500 sccm, about 650 sccm, about 800 sccm, or about 1000 sccm. For example, the flow rate of the silicon precursor may be from about 100 sccm to about 1,000 sccm, from about 100 sccm to about 800 sccm, from about 100 sccm to about 500 sccm, from about 100 sccm to about 400 sccm, from about 100 sccm to about 350 sccm, from about 100 sccm to about 300 sccm, from about 100 sccm to about 250 sccm, from about 100 sccm to about 200 sccm, from about 200 sccm to about 1,000 sccm, from about 200 sccm to about 800 sccm, from about 200 sccm to about 500 sccm, from about 200 sccm to about 400 sccm, from about 200 sccm to about 350 sccm, or from about 200 sccm to about 350 sccm. The viscosity may be about 200 sccm to about 300 sccm, about 200 sccm to about 250 sccm, about 200 sccm to about 225 sccm, about 250 sccm to about 1,000 sccm, about 250 sccm to about 800 sccm, about 250 sccm to about 500 sccm, about 250 sccm to about 400 sccm, about 250 sccm to about 350 sccm, about 250 sccm to about 300 sccm, about 250 sccm to about 280 sccm, about 270 sccm to about 300 sccm, about 285 sccm to about 300 sccm, about 270 sccm to about 320 sccm, or about 285 sccm to about 320 sccm.

[0028] The flow rate of the nitrogen precursor in the deposition gas can be about 800 sccm, about 1000 sccm, about 1200 sccm, about 1350 sccm, about 1500 sccm, or about 1600 sccm to about 1650 sccm, about 1700 sccm, about 1800 sccm, about 2000 sccm, about 2200 sccm, about 2500 sccm, about 3000 sccm, about 3500 sccm, about 4000 sccm, or about 5000 sccm. For example, the flow rate of the nitrogen precursor may be about 1000 sccm to about 5000 sccm, about 1000 sccm to about 4000 sccm, about 1000 sccm to about 3000 sccm, about 1000 sccm to about 2500 sccm, about 1000 sccm to about 2000 sccm, about 1000 sccm to about 1800 sccm, about 1000 sccm to about 1500 sccm, about 1500 sccm to about 5000 sccm, or about 1500 sccm to about 4000 sccm. m, about 1500 sccm to about 3000 sccm, about 1500 sccm to about 2500 sccm, about 1500 sccm to about 2000 sccm, about 1500 sccm to about 1800 sccm, about 1800 sccm to about 5000 sccm, about 1800 sccm to about 4000 sccm, about 1800 sccm to about 3000 sccm, about 1800 sccm to about 2500 sccm, or about 1800 sccm to about 2000 sccm.

[0029] The flow rate of the carrier gas in the deposition gas can be about 1 SLM (standard liters per second), about 3 SLM, about 4 SLM, about 5 SLM, about 6 SLM, or about 8 SLM to about 9 SLM, about 10 SLM, about 12 SLM, about 15 SLM, about 18 SLM, about 20 SLM, about 22 SLM, about 25 SLM, or about 30 SLM. For example, the flow rate of the carrier gas can be about 1 SLM to about 30 SLM, about 5 SLM to about 30 SLM, about 8 SLM to about 30 SLM, about 10 SLM to about 30 SLM, about 12 SLM to about 30 SLM, about 15 SLM to about 30 SLM, about 20 SLM to about 30 SLM, about 1 SLM to about 20 SLM, about 5 SLM to about 20 SLM, about 8 SLM to about 20 SLM, about 10 SLM to about 20 SLM, about 12 SLM to about 20 SLM, about 15 SLM to about 20 SLM, about 18 SLM to about 20 SLM, about 1 SLM to about 15 SLM, about 5 SLM to about 15 SLM, about 8 SLM to about 15 SLM, about 10 SLM to about 15 SLM, about 12 SLM to about 15 SLM, or about 13 SLM to about 15 SLM.

[0030] In one or more examples, the deposition gas has a molar ratio of silicon precursor to nitrogen precursor to carrier gas where the silicon precursor is about 1, i.e., the molar ratio of nitrogen precursor to carrier gas is in the range of about 4 to about 8, and the molar ratio of carrier gas is in the range of about 20 to about 80, respectively. In other examples, the deposition gas has a molar ratio of silicon precursor to nitrogen precursor to carrier gas where the silicon precursor is about 1, i.e., the molar ratio of nitrogen precursor to carrier gas is in the range of about 5 to about 7, and the molar ratio of carrier gas is in the range of about 30 to about 50, respectively. In some examples, the deposition gas has a molar ratio of silicon precursor to nitrogen precursor to carrier gas where the silicon precursor is about 1, i.e., the molar ratio of nitrogen precursor to carrier gas is in the range of about 5.5 to about 6.5, and the molar ratio of carrier gas is in the range of about 35 to about 45, respectively.

[0031] The PE-CVD or other deposition process can be carried out in various plasma systems, such as a capacitively coupled plasma (CCP) system, an inductively coupled plasma (ICP) system with high-density plasma (HDP), or a remote plasma system (RPS), or other PE-CVD or PE-ALD process chamber or system. During the PE-CVD or other deposition process, the plasma can have an RF power of less than 2400 watts (W), such as about 800 W, about 1000 W, about 1200 W, about 1500 W, about 1700 W, or about 1800 W to about 1900 W, about 2000 W, about 2100 W, about 2200 W, or about 2300 W. For example, the plasma may be generated by controlling the RF power to between about 800 W and less than 2400 W, between about 800 W and about 2200 W, between about 800 W and about 2000 W, between about 800 W and about 1900 W, between about 800 W and about 1800 W, between about 800 W and about 1600 W, between about 800 W and about 1200 W, between about 1200 W and less than 2400 W, between about 1200 W and about 2200 W, between about 1200 W and about It can be 2000W, about 1200W to about 1900W, about 1200W to about 1800W, about 1200W to about 1600W, about 1200W to about 1500W, about 1500W to less than 2400W, about 1500W to about 2200W, about 1500W to about 2000W, about 1500W to about 1900W, or about 1500W to about 1800W.

[0032] In one or more embodiments, the nitrogen-rich silicon nitride layer is part of a passivation film stack including a silicon oxide layer and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. In some examples, the passivation film stack also includes a third layer containing silicon nitride disposed on the nitrogen-rich silicon nitride layer. The third layer may be or include any type of silicon nitride, such as nitrogen-rich silicon nitride, nitrogen-poor silicon nitride, and / or hydrogen-rich silicon nitride. In other embodiments, the nitrogen-rich silicon nitride layer is part of an oxide buffer film stack including an oxide buffer layer containing nitrogen-rich silicon nitride disposed on an oxide buffer layer containing silicon oxide.

[0033] In some embodiments, a silicon oxide layer and / or a silicon oxide-containing oxide buffer layer can be deposited or otherwise formed during a PE-CVD process. The PE-CVD process includes exposing a workpiece to an oxide deposition gas and depositing a silicon oxide layer and / or a silicon oxide-containing oxide buffer layer on the workpiece. The oxide deposition gas can include one or more silicon precursors, one or more oxidizers, and optionally one or more carrier gases. The silicon precursors can be or include one or more of silane, disilane, trisilane, tetrasilane, silicon tetrafluoride, or any combination thereof. The oxidizers can be or include nitrous oxide, oxygen, ozone, water, one or more peroxides, one or more plasmas thereof, or any combination thereof. The carrier gas, if included, can be or include one or more of nitrogen (N), hydrogen (H), argon, helium, neon, krypton, or any combination thereof. In one or more examples, the silicon precursor is or contains a silane and the oxidizing agent is or contains nitrous oxide.

[0034] The flow rate of the silicon precursor in the oxide deposition gas can be about 20 sccm, about 35 sccm, about 50 sccm, about 60 sccm, about 80 sccm, or about 100 sccm to about 120 sccm, about 135 sccm, about 150 sccm, about 165 sccm, about 180 sccm, about 200 sccm, about 250 sccm, about 280 sccm, about 300 sccm, about 350 sccm, about 400 sccm, or about 500 sccm. For example, the flow rate of the silicon precursor may be from about 20 sccm to about 500 sccm, from about 20 sccm to about 400 sccm, from about 20 sccm to about 350 sccm, from about 20 sccm to about 300 sccm, from about 20 sccm to about 250 sccm, from about 20 sccm to about 220 sccm, from about 20 sccm to about 200 sccm, from about 20 sccm to about 180 sccm, from about 20 sccm to about 165 sccm, Approximately 20sccm to approximately 150sccm, approximately 20sccm to approximately 135sccm, approximately 20sccm to approximately 120sccm, approximately 20sccm to approximately 100sccm, approximately 20sccm to approximately 80sccm, Approximately 20sccm to approximately 50sccm, approximately 100sccm to approximately 500sccm, approximately 100sccm to approximately 400sccm, approximately 100sccm to approximately 350sccm, approximately 100sccm to approximately 300scm cm, about 100sccm~about 250sccm, about 100sccm~about 220sccm, about 100sccm~about 200sccm, about 100sccm~about 180sccm, about 100sccm~ Approx. 165sccm, Approx. 100sccm ~ Approx. 150sccm, Approx. 100sccm ~ Approx. 135sccm, Approx. 100sccm ~ Approx. 120sccm, Approx. 140sccm ~ Approx. 500sccm, Approx. 140 sccm to about 400 sccm, about 140 sccm to about 350 sccm, about 140 sccm to about 300 sccm, about 140 sccm to about 250 sccm, about 140 sccm to about 220 sccm, about 140 sccm to about 200 sccm, about 140 sccm to about 180 sccm, about 140 sccm to about 165 sccm, or about 140 sccm to about 150 sccm.

[0035] The flow rate of the oxidizer in the oxide deposition gas can be about 1 SLM, about 2 SLM, about 3 SLM, about 4 SLM, about 5 SLM, or about 6 SLM to about 7 SLM, about 8 SLM, about 9 SLM, about 10 SLM, about 11 SLM, about 12 SLM, about 14 SLM, about 16 SLM, about 18 SLM, or about 20 SLM. For example, the flow rate of the oxidizer in the oxide deposition gas can be about 1 SLM to about 20 SLM, about 1 SLM to about 18 SLM, about 1 SLM to about 15 SLM, about 1 SLM to about 12 SLM, about 1 SLM to about 10 SLM, about 1 SLM to about 8 SLM, about 1 SLM to about 6 SLM, about 1 SLM to about 5 SLM, about 4 SLM to about 20 SLM, about 4 SLM to about 18 SLM, about 4 SLM to about 15 SLM, about 4 SLM to about 12 SLM, about 4 SLM to about 10 SLM, about 4 SLM to about 8 SLM, about 4 SLM to about 6 SLM, about 8 SLM to about 20 SLM, about 8 SLM to about 18 SLM, about 8 SLM to about 15 SLM, about 8 SLM to about 12 SLM, or about 8 SLM to about 10 SLM.

[0036] In some examples, during the PE-CVD process, the oxide deposition gas is exposed to a plasma having an RF power of about 800 W, about 1000 W, about 1500 W, about 1800 W, or about 2000 W to about 2200 W, about 2500 W, about 2800 W, about 3000 W, about 3500 W, about 4000 W, about 4500 W, or about 5000 W or more. For example, during a PE-CVD process, the oxide deposition gas is exposed to a plasma having an RF power of about 800 W to about 5000 W, about 1000 W to about 4000 W, about 1000 W to about 3500 W, about 1000 W to about 3000 W, about 1000 W to about 2500 W, about 1000 W to about 2000 W, about 2000 W to about 4000 W, about 2000 W to about 3500 W, about 2000 W to about 3000 W, about 2000 W to about 2500 W, about 2000 W to about 2200 W, or about 2800 W to about 3200 W.

[0037] 1 is a schematic diagram of a thin film transistor (TFT) structure 100 containing a passivation film stack 156 including a silicon oxide layer 160 and a nitrogen-rich silicon nitride layer 170 according to one or more embodiments described and discussed herein. The TFT structure 100 contains a buffer layer 110 disposed on a substrate 102 and a first metal layer 120 disposed on the buffer layer 110. The buffer layer 110 is disposed between the substrate 102 and the first metal layer 120.

[0038] The substrate 102 can be a semiconductor substrate, a display substrate, or any other type of substrate. In some examples, the substrate 102 can be transparent. The substrate 102 can be or include glass, quartz, sapphire, plastic or polymer (e.g., a clear plastic film), silicon, silicon oxide, gallium, gallium arsenide, doped variants thereof, or any combination thereof. The buffer layer 110 can be or include silicon oxide, silicon nitride, silicon oxynitride, dopants thereof, or any combination thereof. The buffer layer 110 can include one, two, three, four, or more layers of the same and / or different materials. In some examples, the buffer layer 110 can be or include a silicon oxide stack and a silicon nitride stack. For example, the buffer layer 110 can include a first silicon oxide layer, a first silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the first silicon nitride layer. The buffer layer 110 can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the buffer layer 110 can have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0039] The first metal layer 120 may be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The first metal layer 120 may have a thickness of about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the first metal layer 120 may have a thickness of about 500 Å to about 10000 Å, about 1000 Å to about 10000 Å, or about 1500 Å to about 8000 Å.

[0040] The TFT structure 100 contains a gate insulator layer 130 disposed on and / or over a first metal layer 120 and disposed on a buffer layer 110. A metal oxide layer 140 is disposed on the gate insulator layer 130. A second metal layer, or contact metal layer 150, is disposed on and / or over the metal oxide layer 140 and disposed on the gate insulator layer 130 to form a gate structure.

[0041] The gate insulator layer 130 may be or include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. The gate insulator layer 130 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the gate insulator layer 130 may have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0042] The metal oxide layer 140 may be or include molybdenum oxide, copper oxide, aluminum oxide, titanium oxide, indium oxide, tin oxide, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), alloys thereof, dopants thereof, or any combination thereof. The metal oxide layer 140 may have a thickness of about 50 Å, about 100 Å, about 250 Å, or about 500 Å to about 800 Å, about 1000 Å, about 1200 Å, about 1500 Å, about 1800 Å, or about 2000 Å. For example, the metal oxide layer 140 may have a thickness of about 50 Å to about 2000 Å, about 100 Å to about 2000 Å, or about 500 Å to about 1500 Å.

[0043] The second metal layer or contact metal layer 150 may be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The second metal layer or contact metal layer 150 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the second metal layer or contact metal layer 150 may have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0044] A passivation film stack 156 is disposed on and over the gate structure such that a silicon oxide layer 160 is disposed on at least one or more of the contact metal layer 150, the metal oxide layer 140, the gate insulator layer 130, or any combination thereof. In one or more examples, the silicon oxide layer 160 is disposed on the contact metal layer 150, the metal oxide layer 140, and the gate dielectric layer 130. A nitrogen-rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0045] The silicon oxide layer 160 may be or may contain silicon dioxide or silica. The silicon oxide layer 160 may have a thickness of about 50 nm, about 100 nm, about 200 nm to about 300 nm, about 500 nm, about 800 nm, or about 1,000 nm or more. For example, the silicon oxide layer 160 may have a thickness of about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 200 nm, about 50 nm to about 100 nm, about 100 nm to about 1,000 nm, about 100 nm to about 800 nm, about 100 nm to about 500 nm, about 100 nm to about 300 nm, or about 100 nm to about 200 nm.

[0046] The nitrogen-rich silicon nitride layer 170 contains the compositions described and discussed herein and can have a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, or about 1000 nm or more. For example, the nitrogen-rich silicon nitride layer 170 may have a thickness of about 1 nm to about 1000 nm, about 1 nm to about 800 nm, about 1 nm to about 500 nm, about 1 nm to about 300 nm, about 1 nm to about 250 nm, about 1 nm to about 200 nm, about 1 nm to about 150 nm, about 1 nm to about 100 nm, about 1 nm to about 80 nm, about 1 nm to about 50 nm, about 1 nm to about 25 nm, about 1 nm to about 15 nm, about 1 nm to about 10 nm, about 1 nm to about 5 nm, about 20 nm to about 1000 nm, about 20 nm to about 800 nm, about 20 nm to about 500 nm, about It can be 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about 25 nm, about 50 nm to about 1000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, about 50 nm to about 100 nm, or about 50 nm to about 80 nm.

[0047] In one or more examples, the silicon oxide layer 160 is between about 50 nm and about 500 nm thick, and the nitrogen-rich silicon nitride layer 170 is between about 1 nm and about 200 nm thick.

[0048] FIG. 2 is a schematic diagram of a TFT structure 200 according to one or more embodiments described and discussed herein. The TFT structure 200 contains a passivation film stack 158 including a silicon oxide layer 160, a nitrogen-rich silicon nitride layer 170, and a silicon nitride-containing third layer 180 disposed on the nitrogen-rich silicon nitride layer 170. The third layer 180 may be or include any type of silicon nitride, such as nitrogen-rich silicon nitride, nitrogen-poor silicon nitride, and / or hydrogen-rich silicon nitride. The silicon and nitrogen in the third layer 180 may have a stoichiometric ratio or Si:N ratio of about 1:1, about 1:1.1, about 1:1.2, about 1:1.3, or about 3:4. In some examples, the third layer 180 is or includes a hydrogen-rich silicon nitride layer, which has a higher hydrogen concentration than the nitrogen-rich silicon nitride layer 170. In another example, the third layer 180 is or contains a nitrogen-rich silicon nitride layer that has the same or substantially the same nitrogen concentration as the nitrogen-rich silicon nitride layer 170 .

[0049] The silicon nitride-containing third layer 180 can be deposited by any deposition process, such as one or more thermal vapor deposition processes and / or plasma vapor deposition processes. Exemplary deposition processes may be or include chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), sputtering, or physical vapor deposition (PVD), or any combination thereof. In some examples, the silicon nitride-containing third layer 180 is deposited by a plasma system, such as a capacitively coupled plasma (CCP) system or an inductively coupled plasma (ICP) system using high-density plasma (HDP).

[0050] The silicon nitride-containing third layer 180 contains a composition described and discussed herein. The nitrogen-rich silicon nitride layer 170 can have a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, or about 1,000 nm or more. For example, the third layer 180 containing silicon nitride may have a thickness of about 1 nm to about 1,000 nm, about 5 nm to about 1,000 nm, about 5 nm to about 800 nm, about 5 nm to about 500 nm, about 5 nm to about 300 nm, about 5 nm to about 250 nm, about 5 nm to about 200 nm, about 5 nm to about 150 nm, about 5 nm to about 100 nm, about 5 nm to about 80 nm, about 5 nm to about 50 nm, about 5 nm to about 25 nm, about 5 nm to about 15 nm, about 5 nm to about 10 nm, about 20 nm to about 1,000 nm, about 20 nm to about 800 nm, about 20 nm to about 1000 nm, about 20 nm to about 15 ... It can be about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about 25 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 50 nm to about 100 nm.

[0051] In one or more examples, silicon oxide layer 160 is about 50 nm to about 500 nm thick, nitrogen-rich silicon nitride layer 170 is about 1 nm to about 200 nm thick, and silicon nitride-containing third layer 180 is about 5 nm to about 500 nm thick.

[0052] 3 is a schematic diagram of a TFT structure 300 according to one or more embodiments described and discussed herein. The TFT structure 300 contains a buffer layer 110 disposed on a substrate 102, a first metal layer 120 disposed on the buffer layer 110, and a gate insulator layer 130 disposed on the first metal layer 120 and the buffer layer 110.

[0053] The TFT assembly 300 further includes a metal oxide layer 140 disposed on the gate insulator layer 130, and an etch stop layer (ESL) 320 disposed on and over the metal oxide layer 140 and disposed on the gate insulator layer 130. The TFT assembly 300 also includes a second metal layer, or contact metal layer 150, disposed on the etch stop layer 320 and the metal oxide layer 140. The second metal layer, or contact metal layer 150, extends through or through the etch stop layer 320 and contacts the metal oxide layer 140 by a via or contact passage.

[0054] Etch stop layer 320 may be or include silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. Etch stop layer 320 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, or about 1500 Å to about 2000 Å, about 2500 Å, about 3000 Å, about 3500 Å, about 4000 Å, or about 5000 Å. For example, etch stop layer 320 may have a thickness of about 50 Å to about 5000 Å, about 100 Å to about 5000 Å, or about 1000 Å to about 5000 Å.

[0055] The silicon oxide layer 160 is disposed on and / or over the second or contact metal layer 150, the etch stop layer 320, or both. For example, the silicon oxide layer 160 of the passivation film stack 156 is disposed on and over the second or contact metal layer 150 and over the etch stop layer 320. A nitrogen-rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0056] 4 is a schematic diagram of a TFT structure 400 according to one or more embodiments described and discussed herein. The TFT 400 contains a passivation film stack 158 including a silicon oxide layer 160, a nitrogen-rich silicon nitride layer 170, and a silicon nitride-containing third layer 180 disposed on the nitrogen-rich silicon nitride layer 170.

[0057] 5 is a schematic diagram of a TFT structure 500 according to one or more embodiments described and discussed herein. The TFT 500 system contains a buffer layer 110 disposed on a substrate 102, a metal oxide layer 140 disposed on the buffer layer 110, a gate insulator layer 520 disposed on the metal oxide layer 140, and a first metal layer, or gate metal layer 530, disposed on the gate insulator layer 520. The gate insulator layer 520 is disposed between the metal oxide layer 140 and the first metal layer, or gate metal layer 530.

[0058] The gate insulator layer 520 may be or include silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. The gate insulator layer 520 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, or about 1500 Å to about 2000 Å, about 2500 Å, about 3000 Å, about 3500 Å, about 4000 Å, or about 5000 Å. For example, the gate insulator layer 520 may have a thickness of about 50 Å to about 5000 Å, about 100 Å to about 5000 Å, or about 1000 Å to about 5000 Å.

[0059] The first metal layer, or gate metal layer 530, may be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The first metal layer, or gate metal layer 530, may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the first metal layer, or gate metal layer 530, may have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0060] The TFT 500 also contains an interlayer dielectric (ILD) layer 540 disposed on and / or over at least one of the buffer layer 110, the metal oxide layer 140, the gate insulator layer 520, and / or the gate metal layer 530. In one or more examples, the interlayer dielectric layer 540 disposed on the at least one buffer layer 110 is disposed on and over the metal oxide layer 140, the gate dielectric layer 520, and the gate metal layer 530.

[0061] The interlevel dielectric layer 540 may be or include one or more layers of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. In one or more examples, the interlevel dielectric layer 540 may include a bilayer of silicon nitride disposed on a silicon oxide. In other examples, the interlevel dielectric layer 540 may include a bilayer of silicon oxide disposed on a silicon nitride. The interlevel dielectric layer 540 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the interlevel dielectric layer 540 can have a thickness between about 50 Å and about 10,000 Å, between about 500 Å and about 10,000 Å, or between about 1,000 Å and about 8,000 Å.

[0062] A second metal layer, or contact metal layer 150, is disposed over the ILD layer 540 and the metal oxide layer 140. The second metal layer, or contact metal layer 150, extends through or through the interlevel dielectric layer 540 and contacts the metal oxide layer 140 by a via or contact passage.

[0063] The silicon oxide layer 160 of the passivation film stack 156 is disposed on at least one of the ILD layer 540 and the contact metal layer 150. For example, the silicon oxide layer 160 is disposed on and over the ILD layer 540 and the contact metal layer 150. A nitrogen-rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0064] 6 is a schematic diagram of a TFT structure 600 according to one or more embodiments described and discussed herein. TFT system 600 has all of the layers or components as TFT system 500, but also includes a third metal layer 550 disposed on substrate 102. Buffer layer 110 is disposed on and / or over third metal layer 550 and is disposed on substrate 102.

[0065] The third metal layer 550 may be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The third metal layer 550 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, or about 1500 Å to about 2000 Å, about 2500 Å, about 3000 Å, about 3500 Å, about 4000 Å, or about 5000 Å. For example, the third metal layer 550 may have a thickness of about 50 Å to about 5000 Å, about 100 Å to about 5000 Å, or about 1000 Å to about 5000 Å.

[0066] Figure 7 is a schematic diagram of a TFT 700 according to one or more embodiments described and discussed herein. Figure 8 is a schematic diagram of a TFT 800 according to embodiments described and discussed herein. Each of the TFTs 700, 800 contains at least two nitrogen-rich silicon nitride layers, such as a nitrogen-rich silicon nitride layer 170 and a first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material.

[0067] The TFT 700, 800 includes a buffer layer 710 disposed on the substrate 102, the buffer layer 710 including one or more low-temperature polysilicon (LTPS) materials. The LTPS material may be or include one or more polysilicon materials, amorphous silicon (α-Si) materials, microcrystalline silicon materials, dopants thereof, or any combination thereof. The buffer layer 710 can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, buffer layer 710 can have a thickness of about 50 Å to about 10,000 Å, about 500 Å to about 10,000 Å, or about 1,000 Å to about 8,000 Å.

[0068] The TFT 700, 800 includes a polysilicon layer 720 disposed on a buffer layer 710, a first gate insulator layer 730 disposed on the polysilicon layer 720 and the buffer layer 710, a first metal layer 732 disposed on the first gate insulator layer 730, and a first interlayer dielectric (ILD) layer 740 disposed on at least one of the first metal layer 732 and the first gate insulator layer 730. The polysilicon layer 720 may be or include one or more polysilicon materials, amorphous silicon (α-Si) materials, microcrystalline silicon materials, dopants thereof, or any combination thereof. The polysilicon layer 720 may have a thickness of about 50 Å, about 100 Å, about 250 Å, or between about 500 Å and about 600 Å, about 800 Å, about 1000 Å, about 1500 Å, about 1800 Å, or about 2000 Å. For example, polysilicon layer 720 can have a thickness between about 50 Å and about 2000 Å, between about 100 Å and about 2000 Å, or between about 500 Å and about 1500 Å.

[0069] The first gate insulator layer 730 may be or include silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. The first gate insulator layer 730 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, or about 1500 Å to about 2000 Å, about 2500 Å, about 3000 Å, about 3500 Å, about 4000 Å, or about 5000 Å. For example, the first gate insulator layer 730 may have a thickness of about 50 Å to about 5000 Å, about 100 Å to about 5000 Å, or about 1000 Å to about 5000 Å.

[0070] The first metal layer 732 may be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The first metal layer 732 may have a thickness of about 100 Å, about 150 Å, about 200 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the first metal layer 732 may have a thickness of about 100 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0071] The first ILD layer 740 may be or include one or more layers of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. In one or more examples, the interlayer dielectric 740 may include a bilayer of silicon nitride disposed on a silicon oxide. In other examples, the first ILD layer 740 may include a bilayer of silicon oxide disposed on a silicon nitride. The first ILD layer 740 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the first ILD layer 740 can have a thickness between about 50 Å and about 10,000 Å, between about 500 Å and about 10,000 Å, or between about 1,000 Å and about 8,000 Å.

[0072] In one or more embodiments, the TFT 700, 800 includes an oxide buffer film 756 that contains one or more first oxide buffer layers 760 and one or more second oxide buffer layers 770. The first oxide buffer layer 760 contains a nitrogen-rich silicon nitride material and is disposed on the first ILD layer 740. The second oxide buffer layer 770 contains a silicon oxide material and is disposed on the first oxide buffer layer 760.

[0073] The first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material has a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, or about 1000 nm or more. For example, the first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material may have a thickness of about 1 nm to about 1000 nm, about 5 nm to about 1000 nm, about 5 nm to about 800 nm, about 5 nm to about 500 nm, about 5 nm to about 300 nm, about 5 nm to about 250 nm, about 5 nm to about 200 nm, about 5 nm to about 150 nm, about 5 nm to about 100 nm, about 5 nm to about 80 nm, about 5 nm to about 50 nm, about 5 nm to about 25 nm, about 5 nm to about 15 nm, about 5 nm to about 10 nm, about 20 nm to about 1000 nm, about 20 nm to about 800 nm , about 20 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about 25 nm, about 50 nm to about 1000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 50 nm to about 100 nm.

[0074] The second oxide buffer layer 770 containing a silicon oxide material has a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, or about 1000 nm or more. For example, the second oxide buffer layer 770 containing a silicon oxide material may have a thickness of about 1 nm to about 1000 nm, about 5 nm to about 1000 nm, about 5 nm to about 800 nm, about 5 nm to about 500 nm, about 5 nm to about 300 nm, about 5 nm to about 250 nm, about 5 nm to about 200 nm, about 5 nm to about 150 nm, about 5 nm to about 100 nm, about 5 nm to about 80 nm, about 5 nm to about 50 nm, about 5 nm to about 25 nm, about 5 nm to about 15 nm, about 5 nm to about 10 nm, about 20 nm to about 1000 nm, about 20 nm to about 800 nm, about 20 nm to about 800 nm, about 20 nm to about 10 ... The thickness can be 0 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about 25 nm, about 50 nm to about 1000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 50 nm to about 100 nm.

[0075] In one or more examples, the first oxide buffer layer 760, which contains a nitrogen-rich silicon nitride material, is about 50 nm to about 500 nm thick, and the second oxide buffer layer 770, which contains a silicon oxide material, is about 5 nm to about 500 nm thick.

[0076] The second metal layer 750 is in contact with the first oxide buffer layer 760 and the polysilicon layer 720 in both TFTs 700, 800. In one or more embodiments of TFT 700, the second metal layer 750 is also in contact with the first ILD layer 740, as shown in FIG. 7. For example, the second metal layer 750 is disposed on the first ILD layer 740, and a first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material is disposed on and / or over the second metal layer 750. In one or more embodiments of TFT 800, the second metal layer 750 is also in contact with a second oxide buffer layer 770, as shown in FIG. 8. For example, the second metal layer 750 is disposed on the first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material, and a second oxide buffer layer 770 is disposed on and / or over the second metal layer 750.

[0077] The TFTs 700, 800 also contain a metal oxide layer 140 disposed on the second oxide buffer layer 770, a second gate insulator layer 520 disposed on the metal oxide layer 140, and a third metal gate layer, such as a gate metal layer 530, disposed on the second gate insulator layer 520. The TFTs 700, 800 further contain a second ILD layer, such as an ILD layer 540, disposed on at least one of the second oxide buffer layer 770, the metal oxide layer 140, the second gate insulator layer 520, and the gate metal layer 530.

[0078] 7 and 8, the TFTs 700, 800 contain a fourth contact metal layer, such as a contact metal layer 150, disposed on the second ILD layer 540 and in contact with the metal oxide layer 140 or the second metal layer 750, or both. A silicon oxide layer 160 of a passivation film stack 156 is disposed on at least one second ILD layer 540 and on and / or over the contact metal layer 150. A nitrogen-rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0079] Embodiments of the present disclosure may further relate to any one or more of the following items 1-23.

[0080] 1. A passivation film stack comprising: a silicon oxide layer disposed on a workpiece; and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percentage (at%) to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%.

[0081] 2. A thin film transistor comprising the passivation film stack of paragraph 1, comprising: a buffer layer disposed on a substrate; a first metal layer disposed on the buffer layer; a gate insulator layer disposed on the first metal layer and the buffer layer; a metal oxide layer disposed on the gate insulator layer; and a second metal layer disposed on the metal oxide layer and the gate insulator layer, wherein a silicon oxide layer of the passivation film stack is disposed on at least one of the second metal layer, the metal oxide layer, and the gate insulator layer.

[0082] 3. The thin film transistor of claim 2, wherein the passivation film stack further comprises a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, the hydrogen-rich silicon nitride layer having a higher hydrogen concentration than the nitrogen-rich silicon nitride layer.

[0083] 4. A thin film transistor comprising the passivation film stack of paragraph 1, comprising: a buffer layer disposed on a substrate; a first metal layer disposed on the buffer layer; a gate insulator layer disposed on the first metal layer and the buffer layer; a metal oxide layer disposed on the gate insulator layer; an etch stop layer disposed on the metal oxide layer and the gate insulator layer; and a second metal layer disposed on the etch stop layer and the metal oxide layer, wherein a silicon oxide layer of the passivation film stack is disposed on at least one of the second metal layer and the etch stop layer.

[0084] 5. The thin film transistor of claim 4, wherein the passivation film stack further comprises a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, the hydrogen-rich silicon nitride layer having a higher hydrogen concentration than the nitrogen-rich silicon nitride layer.

[0085] 6. A thin film transistor comprising the passivation film stack of paragraph 1, the thin film transistor including: a buffer layer disposed on a substrate; a metal oxide layer disposed on the buffer layer; a gate insulator layer disposed on the metal oxide layer; a first metal layer disposed on the gate insulator layer; an interlayer dielectric layer disposed on at least one of the buffer layer, the metal oxide layer, the gate insulator layer, and the first metal layer; and a second metal layer disposed on the interlayer dielectric layer and the metal oxide layer, wherein a silicon oxide layer of the passivation film stack is disposed on at least one of the interlayer dielectric layer and the second metal layer.

[0086] 7. The thin film transistor of claim 6, further comprising a third metal layer disposed on the substrate, and a buffer layer disposed over the third metal layer and the substrate.

[0087] 8. A thin film transistor comprising the passivation film stack of claim 1, comprising: a buffer layer comprising low temperature polysilicon disposed on a substrate; a polysilicon layer disposed on the buffer layer; a first gate insulator layer disposed on the polysilicon layer and the buffer layer; a first metal layer disposed on the first gate insulator layer; a first interlayer dielectric layer disposed on at least one of the first metal layer and the first gate insulator layer; a first oxide buffer layer comprising nitrogen-rich silicon nitride disposed on the first interlayer dielectric; a second oxide buffer layer comprising silicon oxide disposed on the first oxide buffer layer; and a second oxide buffer layer comprising the first oxide buffer layer and the polysilicon layer. a second metal layer in contact with the gate insulator layer; a metal oxide layer disposed on the second oxide buffer layer; a second gate insulator layer disposed on the metal oxide layer; a third metal layer disposed on the second gate insulator layer; a second interlayer dielectric layer disposed on at least one of the second oxide buffer layer, the metal oxide layer, the second gate insulator layer, and the third metal layer; and a fourth metal layer disposed on the second interlayer dielectric and in contact with the metal oxide layer or the second metal layer, or both, wherein a silicon oxide layer of a passivation film stack is disposed on at least one of the second interlayer dielectric layer and the fourth metal layer.

[0088] 9. The thin film transistor of paragraph 8, wherein the second metal layer is further in contact with the first interlayer dielectric layer or the second oxide buffer layer.

[0089] 10. A passivation film stack comprising: a silicon oxide layer disposed on a workpiece; and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, wherein the nitrogen-rich silicon nitride layer has a water resistance of about 1×10 -8 g / m 2 / day ~ approx. 1 x 10 -4 g / m 2 / day, a silicon-hydrogen bond concentration of about 0.1% to about 10%, and the nitrogen-rich silicon nitride layer has a nitrogen to silicon ratio of greater than 1.03 to about 2.

[0090] 11. A method for depositing a silicon nitride material, comprising: heating a workpiece to a temperature of about 200°C to about 250°C; exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition process; and depositing a nitrogen-rich silicon nitride layer on the workpiece, wherein the deposition gas comprises a silicon precursor, a nitrogen precursor, and a carrier gas, and the molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are about 1: in the range of about 4 to about 8: in the range of about 20 to about 80, respectively.

[0091] 12. The method according to item 11, wherein the molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are about 1: about 5 to about 7: about 30 to about 50, respectively, the silicon precursor comprises silane, the nitrogen precursor comprises ammonia, and the carrier gas comprises nitrogen (N2).

[0092] 13. The method of claim 11, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at% to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%, and the nitrogen-rich silicon nitride layer has a nitrogen to silicon ratio of greater than 1.03 to about 2.

[0093] 14. The passivation film stack, thin film transistor, and / or method of any one of paragraphs 1 to 13, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 27 at% to about 34 at%.

[0094] 15. The passivation film stack, thin film transistor, and / or method of any one of paragraphs 1 to 14, wherein the nitrogen-rich silicon nitride layer has a nitrogen concentration of about 42 at% to about 65 at%.

[0095] 16. The passivation film stack, thin film transistor, and / or method of any one of paragraphs 1 to 15, wherein the nitrogen-rich silicon nitride layer has a hydrogen concentration of about 18 at% to about 25 at%.

[0096] 17. The passivation film stack, thin film transistor, and / or method of any one of paragraphs 1 to 16, wherein the nitrogen-rich silicon nitride layer has a nitrogen to silicon ratio of greater than 1.03 to about 2.

[0097] 18. The passivation film stack, thin film transistor, and / or method of any one of paragraphs 1 to 17, wherein the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration of about 0.5% to about 6%.

[0098] 19. The passivation film stack, thin film transistor, and / or method of any one of paragraphs 1 to 18, wherein the nitrogen-rich silicon nitride layer has a total hydrogen bond concentration of less than 30%.

[0099] 20. Nitrogen-rich silicon nitride layers have a water resistance of approximately 1 x 10 -8 g / m 2 / day ~ approx. 1 x 10 -4 g / m 2 20. The passivation film stack, thin film transistor, and / or method according to any one of items 1 to 19, wherein the number of times is 1 / day.

[0100] 21. The passivation film stack, thin film transistor, and / or method of any one of paragraphs 1 to 20, wherein the nitrogen-rich silicon nitride layer has a thickness of from about 1 nm to about 500 nm.

[0101] 22. The passivation film stack, thin film transistor, and / or method of any one of paragraphs 1 to 21, wherein the silicon oxide layer has a thickness of from about 50 nm to about 1000 nm.

[0102] 23. The passivation film stack, thin film transistor, and / or method of any one of paragraphs 1 to 22, further comprising a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, the hydrogen-rich silicon nitride layer having a higher hydrogen concentration than the nitrogen-rich silicon nitride layer.

[0103] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments may be devised without departing from the basic scope of the disclosure, the scope of the present invention being determined by the appended claims. All documents set forth herein, including any priority documents and / or testing procedures, are incorporated herein by reference to the extent not inconsistent herewith. While various forms of the present disclosure have been illustrated and described, as is apparent from the foregoing general description and specific embodiments, various changes can be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not limited by the foregoing general description and specific embodiments. Similarly, the term "comprising" is considered synonymous with the term "including" for purposes of U.S. law. Similarly, whenever a composition, element, or group of elements is preceded by the transitional phrase "comprising," it is understood that the same composition or group of elements where the description of the composition, element, or element is preceded by the transitional phrase "consisting essentially of," "consisting of," "selected from the group of consisting of," or "is" is also contemplated, and vice versa.

[0104] Some embodiments and features have been described using a set of upper numerical limits and a set of lower numerical limits. It should be understood that ranges including combinations of any two values, e.g., any lower value with any upper value, any two lower values, and / or any two upper values, are contemplated unless otherwise indicated. Specific lower values, upper values, and ranges appear in one or more of the appended claims.

Claims

1. a silicon oxide layer disposed on the workpiece; a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer; and A passivation film stack comprising: A passivation film stack, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percentage (at %) to about 35 at %, a nitrogen concentration of about 40 at % to about 75 at %, and a hydrogen concentration of about 10 at % to about 35 at %.

2. 10. The passivation film stack of claim 1, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 27 at% to about 34 at%, a nitrogen concentration of about 42 at% to about 65 at%, and a hydrogen concentration of about 18 at% to about 25 at%, and wherein the nitrogen-rich silicon nitride layer has a nitrogen to silicon ratio of greater than 1.03 to about 2.

3. 10. The passivation film stack of claim 1, wherein the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration of about 0.5% to about 6%.

4. 10. The passivation film stack of claim 1, wherein the nitrogen-rich silicon nitride layer has a total hydrogen bond concentration of less than 30%.

5. The nitrogen-rich silicon nitride layer has a water resistance of about 1×10 －８ g / m ２ / day to about 1 x 10 －４ g / m ２ 10. The passivation film stack of claim 1, wherein the passivation film stack has a thermal conductivity of 1000 psig / day.

6. 10. The passivation film stack of claim 1, wherein the nitrogen-rich silicon nitride layer has a thickness of about 1 nm to about 500 nm.

7. 10. The passivation film stack of claim 1, wherein the silicon oxide layer has a thickness of about 50 nm to about 1000 nm.

8. 10. The passivation film stack of claim 1, further comprising a hydrogen-rich silicon nitride layer disposed on said nitrogen-rich silicon nitride layer, said hydrogen-rich silicon nitride layer having a higher hydrogen concentration than said nitrogen-rich silicon nitride layer.

9. 10. A thin film transistor comprising the passivation film stack of claim 1, a buffer layer disposed on the substrate; a first metal layer disposed on the buffer layer; a gate insulator layer disposed over the first metal layer and the buffer layer; a metal oxide layer disposed on the gate insulator layer; a second metal layer disposed over the metal oxide layer and the gate insulator layer; a thin film transistor, wherein the silicon oxide layer of the passivation film stack is disposed over at least one of the second metal layer, the metal oxide layer, and the gate insulator layer;

10. 10. The thin film transistor of claim 9, wherein the passivation film stack further comprises a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, the hydrogen-rich silicon nitride layer having a higher hydrogen concentration than the nitrogen-rich silicon nitride layer.

11. 10. A thin film transistor comprising the passivation film stack of claim 1, a buffer layer disposed on the substrate; a first metal layer disposed on the buffer layer; a gate insulator layer disposed over the first metal layer and the buffer layer; a metal oxide layer disposed on the gate insulator layer; an etch stop layer disposed over the metal oxide layer and the gate insulator layer; a second metal layer disposed on the etch stop layer and the metal oxide layer; a thin film transistor, wherein the silicon oxide layer of the passivation film stack is disposed over at least one of the second metal layer and the etch stop layer;

12. 12. The thin film transistor of claim 11, wherein the passivation film stack further comprises a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, the hydrogen-rich silicon nitride layer having a higher hydrogen concentration than the nitrogen-rich silicon nitride layer.

13. 10. A thin film transistor comprising the passivation film stack of claim 1, a buffer layer disposed on the substrate; a metal oxide layer disposed on the buffer layer; a gate insulator layer disposed on the metal oxide layer; a first metal layer disposed on the gate insulator layer; an interlayer dielectric layer disposed on at least one of the buffer layer, the metal oxide layer, the gate insulator layer, and the first metal layer; a second metal layer disposed over the interlevel dielectric layer and the metal oxide layer; a thin film transistor, wherein the silicon oxide layer of the passivation film stack is disposed over at least one of the interlayer dielectric layer and the second metal layer;

14. 14. The thin film transistor of claim 13, further comprising a third metal layer disposed on the substrate, the buffer layer being disposed over the third metal layer and the substrate.

15. 10. A thin film transistor comprising the passivation film stack of claim 1, a buffer layer comprising low temperature polysilicon disposed on the substrate; a polysilicon layer disposed on the buffer layer; a first gate insulator layer disposed over the polysilicon layer and the buffer layer; a first metal layer disposed on the first gate insulator layer; a first interlayer dielectric layer disposed on at least one of the first metal layer and the first gate insulator layer; a first oxide buffer layer comprising nitrogen-rich silicon nitride disposed on the first interlayer dielectric; a second oxide buffer layer comprising silicon oxide disposed on the first oxide buffer layer; a second metal layer in contact with the first oxide buffer layer and the polysilicon layer; a metal oxide layer disposed on the second oxide buffer layer; a second gate insulator layer disposed on the metal oxide layer; a third metal layer disposed on the second gate insulator layer; a second interlayer dielectric layer disposed on at least one of the second oxide buffer layer, the metal oxide layer, the second gate insulator layer, and the third metal layer; a fourth metal layer disposed on the second interlayer dielectric and in contact with the metal oxide layer, the second metal layer, or both; a silicon oxide layer of the passivation film stack disposed over at least one of the second interlayer dielectric layer and the fourth metal layer;

16. 16. The thin film transistor of claim 15, wherein the second metal layer is further in contact with the first interlayer dielectric layer or the second oxide buffer layer.

17. a silicon oxide layer disposed on the workpiece; a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer; and A passivation film stack comprising: The nitrogen-rich silicon nitride layer has a water resistance of about 1×10 －８ g / m ２ / day to about 1 x 10 －４ g / m ２ / day, and the silicon-hydrogen bond concentration is about 0.1% to about 10%; The nitrogen-rich silicon nitride layer has a nitrogen to silicon ratio of greater than 1.03 to about 2.

18. 1. A method for depositing a silicon nitride material, comprising: heating the workpiece to a temperature of about 200°C to about 250°C; exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition process; and depositing a nitrogen-rich silicon nitride layer on the workpiece; the deposition gas comprises a silicon precursor, a nitrogen precursor, and a carrier gas; The method, wherein the molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are about 1: in the range of about 4 to about 8: in the range of about 20 to about 80, respectively.

19. The molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are about 1: in the range of about 5 to about 7: in the range of about 30 to about 50, respectively, and the silicon precursor comprises silane, the nitrogen precursor comprises ammonia, and the carrier gas is nitrogen (N ２ 20. The method of claim 18, comprising:

20. 20. The method of claim 18, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at% to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%, and the nitrogen-rich silicon nitride layer has a nitrogen to silicon ratio of greater than 1.03 to about 2.

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