Semiconductor storage device and method for manufacturing semiconductor storage device

Abstract

To improve the electrical characteristics of a pillar.SOLUTION: A semiconductor storage device of an embodiment comprises a laminate in which a plurality of conductive layers are stacked spaced apart from each other, and a plate-like part extending in the laminate in a lamination direction of the laminate and a first direction crossing the lamination direction, and penetrating the conductive layers from the uppermost layer to an N-th layer (where N is an integer of 1 or more) among the plurality of conductive layers. The plate-like part includes a wing part protruding toward the N-th conductive layer at a height position of at least the N-th conductive layer among the plurality of conductive layers.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] A semiconductor memory device such as a three-dimensional nonvolatile memory includes, for example, multiple pillars that penetrate a stack of multiple conductive layers. The intersections of the multiple conductive layers and the pillars function as memory cells. To independently control the memory cells belonging to each pillar, one or more conductive layers, including the topmost conductive layer of the stack, are separated by a plate-like portion.

[0003] To achieve high-density arrangement of multiple pillars, the plate-like portion is formed by removing the upper end of the pillar at a position where it overlaps with some of the pillars. However, there is a problem in that the electrical characteristics of the pillars that overlap with the plate-like portion and are partially removed are deteriorated. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-047853 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve the electrical characteristics of pillars. [Means for solving the problem]

[0006] The semiconductor memory device of the embodiment comprises a stack of multiple conductive layers stacked at a distance from each other, and a plate-shaped portion extending through the stack in the stacking direction of the stack and in a first direction intersecting the stacking direction, and penetrating through Nth (N is an integer greater than or equal to 1) conductive layers from the top layer of the multiple conductive layers, and the plate-shaped portion has a wing portion protruding into the Nth conductive layer at least at a height position of the Nth conductive layer of the multiple conductive layers. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor memory device according to an embodiment. [Figure 2] 1 is a cross-sectional view taken along the Y direction showing an example of the configuration of a semiconductor memory device according to an embodiment. [Figure 3] FIG. 2 is a diagram showing an example of a configuration of an isolation layer of the semiconductor memory device according to the embodiment. [Figure 4] 5A to 5C are cross-sectional views taken along the Y direction illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 5] 5A to 5C are cross-sectional views taken along the Y direction illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] 5A to 5C are cross-sectional views taken along the Y direction illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] 5A to 5C are cross-sectional views taken along the Y direction illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 5A to 5C are cross-sectional views taken along the Y direction illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] 5A to 5C are cross-sectional views taken along the Y direction illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10] 5A to 5C are cross-sectional views taken along the Y direction illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] 5A to 5C are cross-sectional views taken along the Y direction illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 12]5A to 5C are cross-sectional views taken along the Y direction illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0009] (Configuration example of semiconductor memory device) 1A and 1B are diagrams illustrating a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, FIG. 1A is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1B is a schematic plan view illustrating the layout of the semiconductor memory device 1.

[0010] However, hatching is omitted in Fig. 1(a) for ease of viewing. Also, Fig. 1(a) shows components that do not necessarily exist on the same cross section, and some upper layer wiring, etc. are omitted.

[0011] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor memory device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0012] As shown in FIG. 1(a), the semiconductor memory device 1 includes, from the bottom of the page, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which a peripheral circuit CBA is provided.

[0013] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical continuity is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals from the outside to the semiconductor memory device 1 are provided in the same layer as the electrode film EL. A select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order on the source line SL to form a stacked body LM.

[0014] 1(a) and 1(b), a memory region MR is arranged in the center of the multiple word lines WL in the X direction, and staircase regions SR are arranged at both ends of the multiple word lines WL in the X direction. Note that in this specification, the direction in which the terrace surfaces of the word lines WL of each step in the staircase region SR face is defined as the upward direction in the semiconductor memory device 1.

[0015] The memory region MR and the staircase region SR are divided into multiple regions by multiple plate-like contacts LI that extend in the X direction, penetrating multiple word lines WL, etc. The region that is arranged between adjacent plate-like contacts LI in the Y direction and includes the memory region MR and the staircase region SR is called a block region BLK. As will be described later, the memory region MR includes multiple memory cells that store data in a non-volatile manner, and the block region BLK is the unit for erasing this data.

[0016] Furthermore, a plurality of isolation layers SHE are arranged between adjacent plate contacts LI in the Y direction, penetrating the select gate lines SGD and extending in the X direction. The isolation layers SHE extend in the X direction throughout the entire memory region MR, and reach parts of the staircase regions SR at both ends in the X direction.

[0017] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL and the select gate lines SGD, SGS in the stacking direction. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0018] In the staircase region SR, the word lines WL and select gate lines SGD, SGS are processed in a staircase shape and terminate in the staircase region SR. As the distance from the memory region MR in the X direction increases, the word lines WL and select gate lines SGD, SGS constituting the terrace portion move from the upper layer to the lower layer, and the height position of the terrace portion decreases toward the source line SL.

[0019] The above-mentioned separation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the separation layer SHE penetrates the portions above the multiple word lines WL, thereby dividing these upper layers into the patterns of multiple select gate lines SGD. The separation layer configured in this manner is an example of a plate-shaped portion.

[0020] Contacts CC connected to the word lines WL and select gate lines SGD, SGS of each layer are arranged in the terrace portion of each stage formed by multiple word lines WL and select gate lines SGD, SGS. One contact CC is connected to each word line WL and select gate line SGS per layer. One contact CC is connected to each select gate line SGD per layer for each section separated by a separation layer SHE.

[0021] Here, in one block region BLK, the multiple contacts CC are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, multiple contacts CC are arranged, for example, every two block regions BLK.

[0022] 1(b), in the block region BLK at the top of the page, a plurality of contacts CC are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page. Also, in the block regions BLK one block below the above-mentioned block region BLK and two blocks below, a plurality of contacts CC are arranged in the staircase region SR on the right side of the page, among the staircase regions SR at both ends in the X direction. Furthermore, in the block region BLK at the bottom of the page, a plurality of contacts CC are again arranged in the staircase region SR on the left side of the page.

[0023] Therefore, the contacts CC in the staircase regions SR at both ends in the X direction shown in FIG. 1(a) belong to different block regions BLK and are not actually located on the same cross section.

[0024] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL located at the same height as the memory cells.

[0025] The word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around these components.

[0026] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0027] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers a plurality of word lines WL, etc., a semiconductor memory device 1 is formed that includes a configuration of a plurality of word lines WL, select gate lines SGD, SGS, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0028] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view taken along the Y direction showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0029] More specifically, Fig. 2(a) is a cross-sectional view of the memory region MR of the semiconductor memory device 1. In Fig. 2(a), the structure below the insulating layer 60 and above the insulating layer 53 (described later) are omitted. Fig. 2(b) is an enlarged cross-sectional view of the pillar PL at the height of the select gate lines SGD and SGS. Fig. 2(c) is an enlarged cross-sectional view of the pillar PL at the height of the word lines WL.

[0030] 2(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. The intermediate source line BSL is disposed below the memory region MR of the stack LM.

[0031] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers, etc. Among them, at least the intermediate source line BSL may be a conductive polysilicon layer or the like in which impurities are diffused.

[0032] The source line SL is connected to the peripheral circuit CBA via the electrode film EL by a through contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA through the insulating layer 50 on the outside of the laminated body LM.

[0033] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0034] The stacked body LMa is disposed above the source line SL. One or more select gate lines SGS are disposed below the word line WL in the lowest layer of the stacked body LMa, with an insulating layer OL interposed therebetween. The stacked body LMb is disposed on the stacked body LMa. One or more select gate lines SGD are disposed above the word line WL in the top layer of the stacked body LMb, with an insulating layer OL interposed therebetween.

[0035] The number of stacked word lines WL and select gate lines SGD, SGS in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer. The uppermost insulating layer OL of each stacked body LMa, LMb may be formed thicker than the other insulating layers OL.

[0036] The upper surface of the laminate LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53, together with an insulating layer 51 described later, each constitute a part of the insulating layer 50 shown in FIG.

[0037] As described above, the multilayer body LM is divided in the Y direction by the plurality of plate-shaped contacts LI. That is, the plate-shaped contacts LI are aligned in the Y direction and extend in the stacking direction and the X direction of the multilayer body LM.

[0038] In this way, the plate-shaped contact LI extends continuously within the stack LM from one end to the other end in the X direction of the stack LM. The plate-shaped contact LI also penetrates the stack LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0039] The plate-shaped contact LI has a tapered shape in which the width in the Y direction decreases from the upper end to the lower end, or a bowing shape in which the width in the Y direction is maximized at a predetermined position between the upper end and the lower end.

[0040] Each of the plate-shaped contacts LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer, etc. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer, etc.

[0041] The insulating layer 54 covers side walls of the plate-shaped contacts LI facing each other in the Y direction. The conductive layer 24 is filled inside the insulating layer 54 and is electrically connected to the source lines SL including the intermediate source lines BSL. However, instead of the plate-shaped contacts LI, a plate-shaped member filled with an insulating layer may penetrate the laminated body LM and extend in the X direction, thereby dividing the laminated body LM in the Y direction.

[0042] Furthermore, a plurality of isolation layers SHE are disposed between the plate contacts LI adjacent in the Y direction, extending in the X direction and penetrating the upper layer portion of the stacked body LMb. These isolation layers SHE are insulating layers 56 such as silicon oxide layers that extend in the stacked body LMb and penetrating at least the select gate lines SGD.

[0043] In other words, these separation layers SHE that penetrate the upper part of the laminate LMb extend in the X direction between the plate-shaped contacts LI through the memory region MR and part of the staircase region SR, thereby dividing the upper part of the laminate LMb into select gate lines SGD.

[0044] Here, the separation layer SHE extends in the X direction through the laminate LM at a position overlapping the upper end portions of some of the pillars PL on one side in the Y direction in the stacking direction of the laminate LM. By being positioned to overlap with the separation layer SHE, one side of the upper end portions of these pillars PL in the Y direction is missing.

[0045] In the memory region MR, a plurality of pillars PL are distributed and arranged, passing through the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0046] The pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. As described above, by arranging the pillars PL so that the separation layer SHE and some of the pillars PL overlap each other, it is possible to maintain a periodic arrangement, such as a staggered pattern, of the pillars PL, and to arrange the pillars PL at a high density, thereby increasing the memory capacity.

[0047] Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval shape, in the direction along the layer direction of the laminate LM, that is, in the direction along the XY plane.

[0048] The pillars PL are composed of pillars PLa penetrating the laminate LMa and pillars PLb penetrating the laminate LMb. The pillars PLa and PLb each have a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, the pillars PLa and PLb each have a bowing shape in which the diameter and cross-sectional area are maximized at a predetermined position between the upper layer side and the lower layer side.

[0049] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0050] 2(b) and 2(c), the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is arranged on the side surface of the pillar PL except for the depth position of the intermediate source line BSL. The memory layer ME is also arranged on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0051] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa. More specifically, the channel layer CN is arranged on the side and bottom surfaces of the pillar PL via the memory layer ME. However, a portion of the channel layer CN contacts the intermediate source line BSL on the side, thereby electrically connecting to the source line SL including the intermediate source line BSL. A core layer CR is filled further inside the channel layer CN.

[0052] Each of the pillars PL has a cap layer CP at its upper end. The cap layer CP is disposed at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. The cap layer CP is connected to a bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in the Y direction so as to intersect with the leading direction of the word line WL.

[0053] 2(a), plugs CH are connected only to three of the five pillars PL that penetrate the three separated select gate lines SGD and are electrically connected to the bit lines BL shown in Fig. 2(a). The other pillars PL are connected to other bit lines BL that extend in the Y direction parallel to the bit lines BL shown in Fig. 2(a) at positions different from the cross section shown in Fig. 2(a), via plugs CH not shown in Fig. 2(a).

[0054] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer, etc. The channel layer CN and cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0055] As shown in Figure 2(c), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0056] 2(b), a select gate STD is formed on the side of each pillar PL where it faces a select gate line SGD above the word line WL, and a select gate STS is formed on the side of each pillar PL where it faces a select gate line SGS below the word line WL.

[0057] By applying a predetermined voltage from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD and STS belong can be selected or unselected.

[0058] In addition, in the pillar PL that is arranged at a position overlapping the separation layer SHE and has one side of its upper end missing, the remaining side on the other side in the Y direction functions as the select gate line SGD.

[0059] Next, a detailed configuration example of the isolation layer SHE included in the semiconductor memory device 1 will be described with reference to FIG.

[0060] 3A and 3B are diagrams illustrating an example of the configuration of the isolation layer SHE of the semiconductor memory device 1 according to the embodiment. More specifically, FIG. 3A is an enlarged cross-sectional view of the isolation layer SHE taken along the Y direction, and FIG. 3B is an enlarged cross-sectional view of the isolation layer SHE taken along the Y direction, which is different from the cross-section of FIG. 3A. FIG. 3C is an XY cross-sectional view at the height position of an arbitrary select gate line SGD.

[0061] As shown in Figures 3(a) and (b), the laminate LM has, as an upper layer wiring structure, one or more select gate lines SGD, a plurality of word lines WL, and one or more word lines WLd arranged between the bottom layer select gate line SGD and the top layer word line WL.

[0062] 3(a) and 3(b), the stacked body LM includes, from the top down, two select gate lines SGD0 and SGD1, three word lines WLd, and a plurality of word lines WL. However, the stacked body LM may have three or more select gate lines SGD, or may have two or less or four or more word lines WLd.

[0063] The word line WLd is a dummy word line and does not function as a gate electrode for driving the memory cells MC. Different voltages can be applied to the select gate STD and the memory cells MC, which have different functions, via the select gate line SGD and the word line WL. By placing the dummy word line WLd between the select gate line SGD and the word line WL, the influence of the electric fields between the select gate STD and the memory cells MC is reduced.

[0064] In the example of Figures 3(a) and (b), the isolation layer SHE penetrates the select gate lines SGD0 and SGD1, and also penetrates the upper two of the three word lines WLd, reaching a depth position of the insulating layer OL directly below.

[0065] Furthermore, the separation layer SHE has wing portions WG that protrude toward the word lines WLd at the height of the word lines WLd. More specifically, as shown in the cross section of Figure 3(a), in the portion where the separation layer SHE overlaps with one side of the upper end of the pillar PL in the Y direction, the wing portions WG protrude only on one side in the Y direction toward the word lines WLd. On the other hand, as shown in the cross section of Figure 3(b), in the portion where the separation layer SHE does not overlap with the pillar PL, the wing portions WG of the separation layer SHE protrude toward the word lines WLd on both sides of the separation layer SHE in the Y direction.

[0066] The separation layer SHE including the wing portion WG may have a void in a portion thereof. That is, the insulating layer 56 filled in the separation layer SHE may have an unfilled portion in a portion where the separation layer SHE penetrates the laminate LM to a predetermined depth, or in a portion of the wing portion WG. Figures 3(a) and 3(b) show an example of a wing portion WG having a void VD in a portion thereof.

[0067] 3(a) and 3(b), the upper portion SHEb corresponds to the portion from the top end of the separation layer SHE to the middle of the insulating layer OL immediately below the bottom select gate line SGD1, and the lower portion SHEa corresponds to the portion from the top end of the separation layer SHE to the middle of the insulating layer OL immediately below the second word line WLd.

[0068] The width in the Y direction at the upper end of the lower portion SHEa of the separation layer SHE is narrower than the width in the Y direction at the lower end of the upper portion SHEb, so that the separation layer SHE has a step SP at the boundary between the lower portion SHEa and the upper portion SHEb.

[0069] 3(c), as described above, the pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. If the arrangement of these pillars PL is regarded as multiple rows of pillars PL extending in the X direction, the pillars PL are arranged in a staggered pattern as a whole, so that pillars PL in two adjacent rows are arranged without overlapping in the X direction.

[0070] The separation layer SHE extends in the X direction between two adjacent rows of pillars PL among these multiple rows of pillars PL. As a result, the pillars PL belonging to the row on one side in the Y direction with respect to the separation layer SHE are missing at their upper ends on the side facing the row on the other side in the Y direction. Also, the pillars PL belonging to the row on the other side in the Y direction with respect to the separation layer SHE are missing at their upper ends on the side facing the row on one side in the Y direction.

[0071] As described above, pillars PL each having one upper end portion missing are alternately arranged on both sides in the Y direction of the separation layer SHE extending in the X direction.

[0072] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Figures 4 to 12. Figures 4 to 12 are cross-sectional views taken along the Y direction illustrating, in order, some steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0073] First, Figure 4 shows how the structure that will later become part of the pillar PL is formed.

[0074] As shown in FIG. 4(a), a lower source line DSLa, an intermediate sacrificial layer SCN, and an upper source line DSLb are formed in this order above a support substrate SS.

[0075] The support substrate SS may be, for example, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate, or a conductive substrate. The lower source line DSLa and the upper source line DSLb are, for example, a polysilicon layer. The intermediate sacrificial layer SCN is a layer that will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL.

[0076] A stack LMsa is formed on the upper source line DSLb, where multiple insulating layers NL and multiple insulating layers OL are alternately stacked one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers to be replaced with conductive materials that will later become the word lines WL or select gate lines SGS. The stack LMsa is the part that will later become the stack LMa through this replacement process.

[0077] At this stage, the insulating layers OL, including the uppermost insulating layer OL, may have approximately the same thickness.

[0078] After this, although not shown, for example, both end portions of the laminate LMsa in the X direction are processed into a staircase shape to form the lower layer portion of the staircase region SR. This processing of the laminate LMsa is performed by using a photoresist layer or the like covering part of the upper surface of the laminate LMsa as a mask, and alternately repeating etching of the pair of insulating layers ON, NL and slimming of the photoresist layer multiple times.

[0079] The lower layer portion of the formed staircase region SR is covered with an insulating layer such as a silicon oxide layer, which will form part of the insulating layer 50 (see FIG. 1) described above.

[0080] As shown in Fig. 4(b), a plurality of memory holes MHa are formed, which penetrate the stacked body LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN and reach the lower source line DSLa. These memory holes MHa will later become pillars PLa.

[0081] As shown in FIG. 4(c), the memory holes MHa are filled with a sacrificial layer such as an amorphous silicon layer to form a plurality of pillars PLc.

[0082] Next, the formation of the pillars PL is shown in FIGS.

[0083] As shown in Figure 5(a), a silicon oxide layer or the like is stacked on the top surface of the laminate LMsa. This makes the top insulating layer OL of the laminate LMsa thicker than the other insulating layers OL. Also, the top ends of the pillars PLc are buried in the top insulating layer OL.

[0084] Furthermore, a stack LMsb is formed on the stack LMsa, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one by one. The stack LMsb is the portion where the insulating layers NL will later be replaced with word lines WL or select gate lines SGD to become the stack LMb.

[0085] At this stage, the insulating layers OL of the laminated body LMsb, including the uppermost insulating layer OL, may have approximately the same thickness.

[0086] Thereafter, although not shown, for example, both ends of the laminate LMsb in the X direction are processed into a staircase shape so as to be continuous with the lower portion of the staircase region SR, thereby forming the upper portion of the staircase region SR. This processing of the laminate LMsb is performed, as with the lower portion of the staircase region SR, by using a photoresist layer or the like covering part of the upper surface of the laminate LMsb as a mask, and by alternately repeating etching of the pair of insulating layers ON, NL and slimming of the photoresist layer multiple times.

[0087] The upper layer side portion of the formed staircase region SR is covered with an insulating layer such as a silicon oxide layer, which will form part of the insulating layer 50 (see FIG. 1) described above.

[0088] As shown in Fig. 5(b), a plurality of memory holes MHb are formed that penetrate the stack LMsb and reach the upper ends of the plurality of pillars PLc arranged in the stack LMsa. These memory holes MHb will later become the pillars PLb.

[0089] 6(a), the sacrificial layer is removed from the pillars PLc connected to the bottom ends of the memory holes MHb, thereby forming memory holes MH that penetrate the stacks LMsa and LMsb and reach the source lines SL.

[0090] As shown in Figure 6(b), in each of the multiple memory holes MH, a memory layer ME having a stacked structure of a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN (see Figures 2(b) and 2(c)) is formed in order from the outer periphery of the memory hole MH.

[0091] Furthermore, a channel layer CN is formed on the sidewalls and bottom surfaces of the plurality of memory holes MH via a memory layer ME. Furthermore, a core layer CR is formed by filling the voids in the memory holes MH inside the channel layer CN with a silicon oxide layer or the like.

[0092] At this time, the memory layer ME, the channel layer CN, and the core layer CR are also formed on the top surface of the laminate LMsb, and these memory layer ME, the channel layer CN, and the core layer CR are removed from the top surface of the laminate LMsb by etching back or the like.

[0093] As shown in Figure 7(a), when the core layer CR on the upper surface of the laminate LMsb is etched back, the upper end of the core layer CR is further etched back in the depth direction of the memory hole MH, thereby forming a recess DN at the upper end of the memory hole MH.

[0094] As shown in FIG. 7(b), a semiconductor layer is filled into the recess DN at the upper end of the memory hole MH to form a cap layer CP.

[0095] Furthermore, a silicon oxide layer or the like is stacked on the top surface of the stacked body LMsb, which makes the topmost insulating layer OL of the stacked body LMsb thicker than the other insulating layers OL, and the top ends of the pillars PL are buried in the topmost insulating layer OL.

[0096] In this way, a plurality of pillars PL are formed. However, at this point, the memory layer ME covers the entire sidewalls of the plurality of pillars PL, and the channel layer CN is not exposed.

[0097] Next, the formation of the source lines SL, word lines WL, etc. is shown in FIGS.

[0098] As shown in FIG. 8(a), a slit ST is formed so as to pass through the stacked bodies LMsa, LMsb and the upper source line DSLb and reach the intermediate sacrificial layer SCN.

[0099] The slits ST extend in the X direction within the laminates LMsa and LMsb, i.e., perpendicular to the paper surface. The slits ST are used in the replacement process described below and will later become the plate-like contacts LI.

[0100] 8(b), an insulating layer 55s is formed on the side walls of the slit ST facing each other in the Y direction. The insulating layer 55s is, for example, a silicon oxide layer, and differs from the above-mentioned insulating layer 55 (see FIG. 2(a)) that will later constitute the plate contact LI, and is a temporary protective layer formed to protect the stacked bodies LMsa and LMsb in subsequent processing.

[0101] As shown in FIG. 9(a), a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through the slit ST whose sidewalls are protected by the insulating layer 55s to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0102] As a result, a gap layer GPn is formed between the lower source line DSLa and the upper source line DSLb. Also, a part of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPn.

[0103] At this time, since the side walls of the slits ST are protected by the insulating layer 55s, the insulating layer NL in the stacked bodies LMsa and LMsb is prevented from being removed as well.

[0104] As shown in Figure 9(b), a chemical solution is appropriately poured into the gap layer GPn through the slit ST to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and (c)) of the memory layer ME exposed in the gap layer GPn.

[0105] As a result, the memory layer ME is removed from part of the sidewall of the pillar PL, and part of the inner channel layer CN is exposed in the gap layer GPn.

[0106] 10(a), a raw material gas such as amorphous silicon is injected through the slit ST whose sidewalls are protected by the insulating layer 55s, and the gap layer GPn is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPn, thereby forming an intermediate source line BSL containing polysilicon, etc.

[0107] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0108] As shown in FIG. 10(b), the insulating layer 55s is removed from the sidewall of the slit ST.

[0109] 11(a), a remover for the insulating layers NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb through the slits ST to remove the insulating layers NL of the laminates LMsa and LMsb, thereby forming laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0110] The laminates LMga and LMgb, which include multiple gap layers GP, have a fragile structure. The multiple pillars PL support the fragile laminates LMga and LMgb. Support by these pillars PL prevents the remaining insulating layers OL from bending and prevents the laminates LMga and LMgb themselves from being distorted or broken.

[0111] As shown in FIG. 11(b), a source gas of a conductive material such as tungsten or molybdenum is injected into the stacks LMga and LMgb through the slits ST, and the gap layers GP of the stacks LMga and LMgb are filled with the conductive material to form a plurality of word lines WL, etc.

[0112] As a result, a stack LM is formed, which includes stacks LMa and LMb, each of which is formed by alternately stacking a plurality of word lines WL and a plurality of insulating layers OL. Fig. 11(b) shows that one or more conductive layers 29 are formed on the upper side of the stack LM. These conductive layers 29 are partitioned into the pattern of the select gate lines SGD by a separation layer SHE, which is formed in a subsequent process.

[0113] As described above, the process of forming the intermediate source lines BSL from the intermediate sacrificial layers SCN and the process of forming the word lines WL from the insulating layers NL are also called a replacement process.

[0114] Thereafter, the slits ST are filled with an insulating layer 55 to form plate-like contacts LI. Contacts CC (see FIG. 1) are also formed through the insulating layer covering the staircase region SR to be connected to individual word lines WL, etc. Grooves are also formed through the conductive layer 29 on the upper layer of the laminate LM, and are filled with an insulating layer 56 to form separation layers SHE, which also partition the conductive layer 29 into the pattern of the select gate lines SGD.

[0115] FIG. 12 shows how the separation layer SHE is formed.

[0116] 12, two select gate lines SGD0 and SGD1 are formed from the upper layer side of the stacked body LM, as in the above-described FIG. 3. Also, the stacked body LM has three dummy word lines WLd in the layer below the select gate lines SGD0 and SGD1.

[0117] 12(a), grooves GRs are formed in the upper layer of the laminate LM, penetrating the conductive layer 29 that is to function as the select gate line SGD and extending in the X direction through the laminate LM. The grooves GRs can be formed by dry etching such as reactive ion etching (RIE).

[0118] In this case, to ensure that the select gate lines SGD0 and SGD1 penetrate through the trenches GRs, it is preferable that the bottom of the trenches GRs reach partway through the insulating layer OL immediately below the select gate line SGD1. The bottom of the trenches GRs may also reach the word line WLd in the top layer. In this way, by placing the dummy word line WLd between the select gate line SGD and the word line WL, a margin can be obtained when forming the isolation layer SHE.

[0119] 12(b), an insulating layer 56 such as a silicon oxide layer is formed on the side surfaces of the grooves GRs facing each other in the Y direction. At this point, the insulating layer 56 does not completely fill the grooves GRs but covers the side walls of the grooves GRs with a predetermined thickness.

[0120] As shown in FIG. 12(c), additional dry etching is performed on the grooves GRs whose sidewalls are covered with the insulating layer 56 to form grooves GRd with a depth that reaches within the range of the three dummy word lines WLd. At this time, it is preferable not to penetrate the bottommost word line WLd immediately above the word line WL. The remaining word line WLd can mitigate the influence of the electric field between the memory cell MC and the select gate STD.

[0121] In the example of Figure 12(c), a trench GRd is formed that penetrates the two upper word lines WLd out of the three word lines WLd and reaches the middle of the insulating layer OL sandwiched between the second and third word lines WLd.

[0122] As shown in the enlarged view of FIG. 12(f), processing using dry etching or the like can cause unevenness on the bottom surface of the groove GRd due to the different material layer contained in the pillar PL.

[0123] More specifically, the charge storage layer CT is, for example, a silicon nitride layer, and the channel layer CN is, for example, a semiconductor layer, which are configured to include a material different from that of the block insulating layer BK, the tunnel insulating layer TN, and the core layer CR, which are, for example, a silicon oxide layer. Since the processing speed by dry etching differs between these different material layers, as described above, unevenness may occur on the bottom surface of the trench GRd.

[0124] 12(f) shows the charge storage layer CT and the channel layer CN protruding from the bottom surface of the trench GRd, assuming that they have a lower etching rate than the block insulating layer BK, the tunnel insulating layer TN, and the core layer CR. However, the relationship between the etching rates of different material layers can vary depending on the plasma source and etching conditions used in dry etching. Therefore, the bottom surface of the trench GRd can have an uneven shape different from that shown in FIG. 12(f).

[0125] As shown in Figure 12(d), after forming the groove GRd by dry etching or the like, the groove GRd is wet-etched using a chemical solution that dissolves metals such as tungsten or molybdenum. As a result, the dummy word line WLd exposed on the side wall of the groove GRd is set back a predetermined distance, and a wing portion WGw is formed. The wing portion WGw is formed on one side of the groove GRd in the Y direction in the portion where the pillar PL and the groove GRd overlap, and on both sides of the groove GRd in the Y direction in other portions.

[0126] Wet etching has higher selectivity between different materials than dry etching, for example. Therefore, only the word lines WLd on the sidewalls of the trenches GRd are retracted without substantially affecting other layers around the trenches GRd, including the select gate lines SGD0 and SGD1, which are covered by the insulating layer 56 even though the trenches GRd penetrate through them. Furthermore, wet etching proceeds isotropically, unlike dry etching, which has anisotropy. Therefore, the protruding distances of the wing portions WGw on both sides of the trenches GRd in the Y direction at least at the same height are approximately equal.

[0127] As shown in FIG. 12(e), an insulating layer 56 is filled into the groove GRd including the wing portion WGw.

[0128] As a result, a separation layer SHE is formed in the laminate LM, and the upper layer portion of the laminate LM is partitioned into the pattern of multiple select gate lines SGD0, SGD1 by the separation layer SHE. At this time, a part of the wing portion WGw may be left unfilled, and the wing portion WG may be formed with a void VD. Also, the separation layer SHE may be formed with a void in a portion corresponding to the groove GRd.

[0129] Thereafter, an insulating layer 52 is formed on the upper surface of the laminated body LMb, and plugs CH are formed through the insulating layer 52 to connect to the pillars PL. An insulating layer 53 is formed on the insulating layer 52, and bit lines BL connected to the pillars PL via the plugs CH are formed in the insulating layer 53. Plugs connected to the contacts CC in the staircase region SR and upper-layer wiring connected to the contacts CC via the plugs are also formed. Electrode pads PDb connected to the bit lines BL and upper-layer wiring are also formed.

[0130] Meanwhile, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw the peripheral circuit CBA out to the surface of the insulating layer 40, and are connected to electrode pads PDc, etc. formed on the surface of the insulating layer 40.

[0131] Furthermore, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads PDb, PDc in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is ground and removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0132] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0133] (Overview) In semiconductor memory devices such as 3D nonvolatile memories, a technique is known in which one or more conductive layers, including the top conductive layer of a stack, are partitioned into select gate line patterns by isolation layers, allowing memory cells to be independently controlled for each select gate line partition. Meanwhile, to increase memory capacity, pillars are densely arranged in a periodic pattern in the memory area. Therefore, isolation layers may be formed in positions that overlap some of these pillars, resulting in missing portions of the pillars.

[0134] A select gate on the drain side of a partially missing pillar may experience a decrease in threshold voltage. The inventors speculated that the unevenness that occurs on the bottom surface of the trench when forming the isolation layer is one of the factors that affects the threshold voltage of the select gate. That is, when a dummy word line or the like is located close to a channel layer that has unevenness with other components at the bottom surface of the isolation layer formed from the uneven trench, a voltage applied via the dummy word line causes electric field concentration near the uneven channel layer.

[0135] According to the embodiment of the semiconductor memory device 1, the separation layer SHE, which penetrates from the top layer select gate line SGD to a predetermined word line WLd, has a wing portion WG that protrudes toward the predetermined word line WLd at least at the height position of the predetermined word line WLd.

[0136] This allows the word line WLd near the bottom surface of the isolation layer SHE to be separated from the channel layer CN having an uneven bottom surface of the isolation layer SHE, thereby preventing the word line WLd from worsening the electric field concentration near the channel layer CN, thereby improving the electrical characteristics of the select gate STD belonging to the pillar PL.

[0137] According to the embodiment of the semiconductor memory device 1, the separation layer SHE has a wing portion WG at the height position of the lower word line WLd, including the specified word line WLd, from the top select gate line SGD to the specified word line WLd.

[0138] When forming the separation layer SHE, as described above, the upper side surface of the trench DRd is covered with the insulating layer 56, and then only the lower word lines WLd are set back to form the wing portions WG. This allows the word lines WLd, including the above-mentioned specified word line WLd close to the bottom surface of the separation layer SHE, to be kept away from the channel layer CN at the bottom surface of the separation layer SHE without damaging the select gate lines SGD.

[0139] In the semiconductor memory device 1 of the embodiment, the conductive layer below the protruding wing portion WG of the isolation layer SHE is the dummy word line WLd. In this way, even if the wing portion WG is protruding from the dummy word line WLd, the characteristics of the semiconductor memory device 1 are not affected.

[0140] According to the semiconductor memory device 1 of the embodiment, the layer immediately below the predetermined word line WLd that is penetrated by the isolation layer SHE is also a dummy word line WLd. By ensuring that at least one word line WLd does not penetrate the isolation layer SHE, the influence of the electric field between the select gate STD and the memory cell MC can be suppressed.

[0141] According to the semiconductor memory device 1 of the embodiment, the protruding distances of the wing portions WG protruding on both sides in the Y direction at the same height position are substantially equal to each other. When forming the separation layer SHE, as described above, the word lines WLd are recessed by isotropic wet etching to form the wing portions WG, so that the protruding distances of the wing portions WG at the same height position are approximately equal to each other. In this way, the wing portions WG can be easily formed using wet etching.

[0142] According to the semiconductor memory device 1 of the embodiment, some of the pillars PL overlap the separation layer SHE on one side in the Y direction in the stacking direction of the laminated body LM.

[0143] In this way, by allowing the separation layer SHE to interfere with some of the pillars PL, the pillars PL can be arranged at high density without disrupting the periodicity. Also, by limiting the missing portion of the pillar PL caused by the separation layer SHE to one side of the pillar PL in the Y direction, the select gate STD and memory cell MC belonging to the pillar PL with the missing portion can also function.

[0144] According to the semiconductor memory device 1 of the embodiment, the separation layer SHE extends in the X direction at a position between adjacent columns of pillars PL, overlapping with the stacking direction of the laminate LM on the side of the pillar PL belonging to one column facing the other column, and on the side of the pillar PL belonging to the other column facing the one column.

[0145] By adjusting the positional relationship between the separation layer SHE and the pillar PL in this way, the missing portion of the pillar PL caused by the separation layer SHE can be limited to one side of the pillar PL in the Y direction.

[0146] According to the semiconductor memory device 1 of the embodiment, the isolation layer SHE includes an insulating layer 56, and electrically isolates a predetermined word line WLd in the Y direction from the select gate line SGD in the uppermost layer through which the isolation layer SHE penetrates. This allows the upper conductive layer of the laminated body LM to be divided into a pattern of a plurality of select gate lines SGD, and allows several groups of memory cells MC to be driven independently.

[0147] According to the semiconductor memory device 1 of the embodiment, the wing portion WG of the separation layer SHE includes a void VD in part. In this way, even if the wing portion WG has the void VD, the effect of suppressing the electric field concentration near the channel layer CN due to the word line WLd can be obtained.

[0148] According to the embodiment of the semiconductor memory device 1, the separation layer SHE has a step SP at the boundary between a lower portion SHEa extending through the stack LM at the height position of the lower word line WLd having the wing portion WG, and an upper portion SHEb extending through the stack LM at the height position of the select gate line SGD above the lower portion SHEa.

[0149] Such a step SP is formed by additionally etching the trenches DRs after covering the side surfaces with the insulating layer 56 as described above when forming the separation layer SHE. In this way, since the side surfaces are covered with the insulating layer 56, the wing portions WG can be formed in the separation layer SHE without damaging the select gate lines SGD.

[0150] In the above-described embodiment, the pillar PL is connected to the source line SL at the side of the channel layer CN, but this is not limiting. For example, the pillar may be configured so that the memory layer at the bottom of the pillar is removed and the lower end of the channel layer is connected to the source line.

[0151] In the above-described embodiment, the staircase region SR and the like are arranged at the ends of the stack LM in the X direction. However, the arrangement position of the staircase region in the stack is not limited to this. The staircase region may be arranged, for example, in the center of the stack. In this case, the memory region may be arranged, for example, at the end of the stack LM.

[0152] In the above-described embodiment, the insulating layers NL and OL are stacked in two steps to form a two-tier stack LM including stacks LMa and LMb. However, the stack may have a one-tier structure, or a three-tier or more structure. By increasing the number of tiers, the number of stacked word lines WL can be further increased.

[0153] In the above-described embodiment, the semiconductor memory device 1 is configured by bonding together a stacked body LM on which pillars PL and contacts CC, etc. are formed and a semiconductor substrate SB on which peripheral circuits CBA are formed. However, the semiconductor memory device may also be obtained by forming peripheral circuits on a semiconductor substrate and forming a stacked body or other configuration above the peripheral circuits via source lines. Alternatively, the semiconductor memory device may be obtained by forming peripheral circuits on a semiconductor substrate and forming a stacked body or other configuration at a position on the same semiconductor substrate away from the peripheral circuits.

[0154] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0155] 1...semiconductor memory device, 56...insulating layer, CBA...peripheral circuit, CC...contact, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb...stacked body, MC...memory cell, MR...memory region, NL, OL...insulating layer, PL, PLa, PLb...pillar, SB...semiconductor substrate, SGD, SGS...select gate line, SHE...separation layer, SHEa...lower layer portion, SHEb...upper layer portion, SP...step, ST...slit, STD, STS...select gate, VD...void, WG...wing portion, WL, WLd...word line.

Claims

1. a laminate in which a plurality of conductive layers are stacked and spaced apart from one another; a plate-like portion extending through the laminate in a stacking direction of the laminate and a first direction intersecting the stacking direction, and penetrating through N-th (N is an integer of 1 or more) conductive layers from the uppermost layer among the plurality of conductive layers, The plate-shaped portion is a wing portion protruding toward the Nth conductive layer at a height position of at least the Nth conductive layer among the plurality of conductive layers; Semiconductor memory device.

2. The plate-shaped portion is the wing portion is provided at a height position of a lower conductive layer including the Nth conductive layer among the uppermost conductive layer to the Nth conductive layer, 2. The semiconductor memory device according to claim 1.

3. the lower conductive layer from which the wing portion protrudes is a dummy word line; 3. The semiconductor memory device according to claim 2.

4. Among the plurality of conductive layers, the (N+1)th conductive layer from the top layer is also a dummy word line.

4. The semiconductor memory device according to claim 3.

5. At the same height position, protruding distances of the wing portions protruding on both sides in a second direction intersecting the stacking direction and the first direction are substantially equal to each other.

2. The semiconductor memory device according to claim 1.

6. The stacked body further includes a plurality of pillars each having a semiconductor layer extending in the stacking direction, Some of the pillars of the plurality of pillars are the plate-shaped portion overlaps the plate-shaped portion in the stacking direction on one side of a second direction intersecting the stacking direction and the first direction; 2. The semiconductor memory device according to claim 1.

7. At least some of the pillars a first row extending in the first direction; a second row adjacent to the first row and extending in the first direction; The plate-shaped portion is a position between the first and second rows, a side of a pillar belonging to the first row facing the second row, and a position overlapping a side of a pillar belonging to the second row facing the first row in the stacking direction, the position extending in the first direction; 7. The semiconductor memory device according to claim 6.

8. The plurality of pillars are arranged in a staggered pattern when viewed from the stacking direction.

8. The semiconductor memory device according to claim 7.

9. The plate-shaped portion is It is configured to include an insulating layer, the conductive layers from the top layer through which the plate-shaped portion penetrates to the N-th conductive layer are electrically separated in a second direction intersecting the stacking direction and the first direction; 2. The semiconductor memory device according to claim 1.

10. The wing portion includes a void in a portion thereof.

10. The semiconductor memory device according to claim 9.

11. The plate-shaped portion is a first portion extending through the stack at a height position of the lower conductive layer having the wing portion; a second portion extending through the stack at a height position of a conductive layer above the first portion, a step is provided at a boundary between the first portion and the second portion; 3. The semiconductor memory device according to claim 2.

12. a width of an upper end of the first portion in a second direction intersecting the stacking direction and the first direction is narrower than a width of a lower end of the second portion in the second direction; 12. The semiconductor memory device according to claim 11.

13. forming a laminate in which a plurality of conductive layers are stacked and spaced apart from one another; forming a groove by dry etching, the groove extending through the stacked body in a stacking direction of the stacked body and a first direction intersecting the stacking direction, and penetrating through M-th (M is an integer of 1 or more) conductive layers from the uppermost layer among the plurality of conductive layers; forming a first insulating layer covering a side surface of the groove in a second direction intersecting the stacking direction and the first direction; additionally dry-etching the groove in which the first insulating layer is formed, to penetrate through up to N-th conductive layer (N is an integer greater than M) from the top layer among the plurality of conductive layers; among the plurality of conductive layers, conductive layers exposed on a side surface of the groove in the second direction and including the Nth conductive layer are recessed from the side surface of the groove by wet etching through the groove; filling the groove with a second insulating layer to form a plate-like portion having wing portions protruding toward the conductive layer including the N-th conductive layer at a height position of the conductive layer including the N-th conductive layer; A method for manufacturing a semiconductor memory device.

14. forming a plurality of pillars each having a semiconductor layer extending in the stacking direction from the stacked body; In some of the pillars, the groove is formed at a position that overlaps with one side of the stacking direction in a second direction that intersects with the stacking direction and the first direction. The method for manufacturing a semiconductor memory device according to claim 13.

15. a plurality of pillars each having a semiconductor layer extending in the stacking direction of the stacked body; a first row extending in the first direction; a second row adjacent to the first row and extending in the first direction; Formed to belong to a groove extending in the first direction is formed at a position between the first and second rows, the groove being overlapped in the stacking direction with a side of the pillar belonging to the first row facing the second row and a side of the pillar belonging to the second row facing the first row; The method for manufacturing a semiconductor memory device according to claim 13.

16. forming the plurality of pillars so as to have a staggered arrangement when viewed from the stacking direction; The method for manufacturing a semiconductor memory device according to claim 15.

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