Semiconductor memory device

Abstract

To provide a semiconductor memory device capable of replacing a defective main memory cell with a redundant memory cell even during use.SOLUTION: A semiconductor memory device includes: a main memory including a plurality of main memory cells; a redundant memory including a plurality of redundant memory cells; a word line group including a plurality of word lines that drive the main memory cells and a plurality of word lines that drive the redundant memory cells; a correction unit that corrects errors in data read from the main memory cells; and a management unit that outputs a request signal to request replacement of the main memory cells with the redundant memory cells when the number of times that the data read from the main memory cells has been corrected by the correction unit reaches or exceeds a predetermined number for each of a predetermined number of the word lines.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor memory device. [Background technology]

[0002] In semiconductor storage devices having nonvolatile memories, defects may occur in memory cells. When a defect in a main memory cell is detected during inspection before shipping, a technique is known in which the main memory cell is replaced with a redundant memory cell (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-59295 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional semiconductor memory devices have a problem that if a defect occurs in a main memory cell during use of the semiconductor memory device after shipment, the defective main memory cell cannot be replaced with a redundant memory cell.

[0005] An object of the present disclosure is to provide a semiconductor memory device that can replace a defective main memory cell with a redundant memory cell even during use. [Means for solving the problem]

[0006] In order to achieve the above object, the semiconductor memory device of the present disclosure comprises a main memory including a plurality of main memory cells, a redundant memory including a plurality of redundant memory cells, a word line group including a plurality of word lines that drive the main memory cells and a plurality of word lines that drive the redundant memory cells, a correction unit that corrects errors in data read from the main memory cells, and a management unit that outputs a request signal to request replacement of the main memory cells with the redundant memory cells when, for each of a predetermined number of the word lines, the number of times that the data read from the main memory cells has been corrected by the correction unit reaches or exceeds a predetermined number. [Effects of the Invention]

[0007] According to the present disclosure, a defective main memory cell can be replaced with a redundant memory cell even during use. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of a configuration of a semiconductor memory device according to an embodiment; [Figure 2] FIG. 2 is a circuit diagram illustrating an example of a configuration of a memory according to an embodiment. [Figure 3] FIG. 2 is a circuit diagram illustrating an example of a configuration of a correction count management unit according to the embodiment. [Figure 4] 10 is a flowchart illustrating an example of the flow of a correction management process executed by the semiconductor memory device of the embodiment. [Figure 5] FIG. 10 is a circuit diagram illustrating another example of the configuration of the correction count management unit according to the embodiment. [Figure 6] FIG. 10 is a circuit diagram illustrating another example of the configuration of the correction count management unit according to the embodiment. [Figure 7] 10 is a flowchart illustrating an example of the flow of a request process executed by a processing unit of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the following embodiments do not limit the technology of the present disclosure.

[0010] 1 shows a block diagram illustrating an example of the configuration of a semiconductor memory device 10 according to this embodiment. The semiconductor memory device 10 according to this embodiment includes a memory controller 12 and a memory 14. The semiconductor memory device 10 according to this embodiment may be, for example, a flash memory.

[0011] The memory controller 12 has a function of controlling the reading, writing, erasing, etc. of data from the memory 14 in response to commands from a CPU (Central Processing Unit) 2. For example, an LSI (Large Scale Integration) or the like is used as the memory controller 12. The memory controller 12 of this embodiment is an example of a control unit of the present disclosure.

[0012] The memory 14 includes a nonvolatile memory cell block 20 and a peripheral circuit 21. FIG. 2 shows a circuit diagram illustrating an example of the configuration of the memory 14. The memory 14 of this embodiment has a plurality of word lines WL and a plurality of bit lines (not shown), and includes a plurality of memory cells provided at intersections of the word lines WL and the bit lines. Note that the specific numbers of word lines WL and bit lines are not limited to the numbers exemplified in this embodiment, and can be set according to the storage capacity of the semiconductor storage device 10, the required performance, specifications, etc.

[0013] The peripheral circuit 21 includes address decoders 22 and 23 , a read circuit 24 , a multiplexer 25 , an ECC (Error Correction Code) circuit 26 , a test circuit 28 , a correction count management unit 30 , a defective address determination redundancy switching circuit 32 , and an OR circuit 33 .

[0014] The nonvolatile memory cell block 20 of the memory 14 includes a main memory 20A, a redundant memory 20B, and a replacement address storage memory 20C.

[0015] The main memory 20A has word lines WL1 to WL n The semiconductor memory device 10 of this embodiment is a memory having a capacity corresponding to n×the number of bit lines.

[0016] The redundant memory 20B is connected to the word line WL n+1 ~WL n+m The semiconductor memory device 10 of this embodiment includes a plurality of redundant memory cells driven by a word line WL. The redundant memory cells are used to repair defective memory cells. In the semiconductor memory device 10 of this embodiment, memory cells are replaced with redundant memory cells in units of word lines WL.

[0017] The replacement address storage memory 20C is connected to the word line WL s , W.L. s+1 The replacement address storage memory 20C stores the address of the main memory cell to be replaced by the redundant memory cell. s The address of a redundant memory cell that replaces a main memory cell of the main memory 20A that is detected as defective before the shipment of the semiconductor storage device 10 is stored in advance in a memory cell corresponding to the address.

[0018] In the semiconductor memory device 10 of this embodiment, before shipment, the test circuit 28 tests the memory cells of the main memory 20A. The test circuit 28 automatically generates addresses for the main memory 20A and writes data to the main memory cells corresponding to the generated addresses. The test circuit 28 also generates expected values, reads the written data, and compares the read data with the generated expected values ​​to determine whether they match. Unlike this embodiment, the main memory 20A may be tested without using the test circuit 28 by inputting addresses from outside the memory 14, writing data to the main memory cells of the main memory 20A, and then reading the written data and determining whether it matches the expected value using a tester or the like. In this case, the test circuit 28 is unnecessary. In either case, if the read data does not match the expected value, the main memory cell is deemed defective. The address of a main memory cell deemed defective is stored in the replacement address storage memory 20C so that it can be replaced with a redundant memory cell. In this embodiment, main memory cells are replaced with redundant memory cells in units of word lines WL. For example, if a main memory cell driven by word line WL1 is determined to be defective, all main memory cells driven by word line WL1 are replaced with redundant memory cells in units of word lines WL2. n+m The redundant memory cell is replaced by a redundant memory cell driven by .

[0019] The defective address determination redundancy switching circuit 32 has, for example, a plurality of registers. When the semiconductor memory device 10 is started up, the address of the main memory cell determined to be defective, which is stored in the replacement address storage memory 20C, is read out and stored in the register of the defective address determination redundancy switching circuit 32 as defective address information.

[0020] When an address is input from the memory controller 12, the defective address determination redundancy switching circuit 32 compares the input address with the stored defective address information, and if they match, outputs the address of the redundant memory cell generated by the defective address determination redundancy switching circuit 32 to the address decoder 22 and the address decoder 23 instead of the input address.

[0021] Specifically, the signal output from the test circuit 28 and the signal output from the defective address determination redundancy switching circuit 32 are input to the OR circuit 33. If either the signal input from the test circuit 28 or the signal input from the defective address determination redundancy switching circuit 32 is "1", the signal output from the OR circuit 33 becomes "1". As a result, the control signal input to the multiplexer 25 becomes "1", and the address output from the test circuit 28, i.e., the address of the redundant memory cell, is output to the address decoder 22 and the address decoder 23. As a result, the main memory cell which is the defective address is replaced with the redundant memory cell.

[0022] On the other hand, when both the signal input from the test circuit 28 and the signal input from the defective address determination redundancy switching circuit 32 are "0", the signal output from the OR circuit 33 is "0". As a result, the control signal input to the multiplexer 25 is "0", and the address input from the memory controller 12 is output to the address decoder 22 and the address decoder 23.

[0023] When data is read from the memory 14, a word line WL selected based on an address input to the address decoder 22 and a memory cell corresponding to a bit line selected by an address input to the address decoder 23 are driven, and data is read from the memory cell by the read circuit 24. Errors in the data read by the read circuit 24 are corrected by the ECC circuit 26, and the corrected data is output to the CPU 2 via the memory controller 12.

[0024] If the ECC circuit 26 detects a 1-bit error in the data read by the read circuit 24, it outputs the data after correcting the error to the memory controller 12. The ECC circuit 26 also outputs a signal SEC indicating that a 1-bit error has occurred to the correction count management unit 30. The ECC circuit 26 of this embodiment is an example of a correction unit of the present disclosure.

[0025] The correction count management unit 30 outputs a request signal RQ requesting replacement of the main memory cell with a redundant memory cell when the number of times data read from the main memory cell is corrected by the ECC circuit 26 reaches or exceeds a predetermined number for each of a predetermined number of word lines WL. The correction count management unit 30 of this embodiment is an example of a management unit of the present disclosure.

[0026] The correction count management unit 30 of this embodiment is an example in which the predetermined number of the present disclosure is "1", and the correction count management unit 30 counts the number of times a 1-bit error is detected by the ECC circuit 26 for each word line WL. FIG. 3 shows a circuit diagram illustrating an example of the configuration of the correction count management unit 30.

[0027] The correction count management unit 30 detects the word lines WL1 to WL n+m Each management circuit 40 (401 to 40 n+m ) are provided. In addition, the management circuits 401 to 40 n+m When these are controlled, the reference numerals 1 to n+m for distinguishing them from one another are omitted, and they are simply collectively referred to as "control circuits 40."

[0028] The management circuit 40 includes a count-up processing unit 40A, a boot loader unit 40B, and a register unit 40C. The count-up processing unit 40A includes a count-up circuit 41, an AND circuit 42, and a multiplexer 44. The boot loader unit 40B includes a multiplexer 46. The register unit 40C includes a flip-flop 48 and an AND circuit 49.

[0029] The AND circuit 42 receives the signal SEC output from the ECC circuit 26 and the signal output from the address decoder 22 to the word line WL. If either the signal SEC or the signal on the word line WL is "0," the signal output from the AND circuit 42 becomes "0." As a result, the control signal input to the multiplexer 44 becomes "0," and the multiplexer 44 outputs the output value of the flip-flop 48. In other words, if the word line WL is not selected by the address decoder 22, or if the word line WL is selected but a single-bit error has not been corrected by the ECC circuit 26, the current number of corrections held by the flip-flop 48 is output from the multiplexer 44.

[0030] On the other hand, when both the signal SEC and the signal of the word line WL are "1," the signal output from the AND circuit 42 becomes "1." As a result, the control signal input to the multiplexer 44 becomes "1," and the multiplexer 44 outputs a value counted up by the count-up circuit 41. In other words, when the word line WL is selected by the address decoder 22 and a one-bit error is corrected by the ECC circuit 26, the multiplexer 44 outputs the number of corrections counted up by +1.

[0031] The multiplexer 46 receives the output of the multiplexer 44 and information DATA on the number of corrections made to date stored in the replacement address storage memory 20C. The multiplexer 46 also receives a control signal boot_en from the memory controller 12 as a control signal. When power is applied, the control signal boot_en input from the memory controller 12 becomes "1," and information DATA on the number of corrections made to date is output to the flip-flop 48. This allows the flip-flop 48 to hold the number of corrections made to date as an initial value. When the semiconductor memory device 10 is used for the first time, for example, and the ECC circuit 26 has never performed a single-bit correction, the initial setting value pre-stored in the replacement address storage memory 20C is input as the information DATA on the number of corrections.

[0032] On the other hand, when the power is turned on, the control signal boot_en becomes “0”, and the output of the multiplexer 44 is output to the flip-flop 48 .

[0033] The flip-flops 48 include D flip-flops, the number of which corresponds to the upper limit of the count number. In the example shown in FIG. 3, the flip-flops 48 include k D flip-flops 48 (flip-flops 481 to 488). k ) Flip-flops 481-48 k holds the input D at the falling edge of the input read enable signal reb and outputs the held value. In other words, when reading data, it holds the input D output from the multiplexer 46 and outputs the input value.

[0034] When the power is turned on, as described above, the flip-flop 48 is set to the current number of corrections stored in the replacement address storage memory 20C or to an initial setting value. k Since the management circuit 40 is provided with the counter, it can count up to k times. In other words, the upper limit of the count for the number of corrections is "k times." When using this management circuit 40 with an upper limit of count less than k times, the difference between k and the desired upper limit is stored in the replacement address storage memory 20C as an initial setting value. For example, if k=100 and the actual upper limit of count is desired to be 40 times, the initial setting value is set to "60" and stored in the replacement address storage memory 20C. As a result, when the semiconductor memory device 10 is used for the first time, "60" is preset in the flip-flop 48 upon power-on, and the actual upper limit of count can be set to 100 - 60 = 40 times. Thereafter, upon power-on, the current number of corrections stored in the nonvolatile memory cell block 20 is set in the flip-flop 48, and counting is possible up to the upper limit of 100 times.

[0035] Flip-flops 481-48 kThe output of the flip-flops 481 to 488 is input to the AND circuit 49. k The flip-flops 481 to 484 output a request signal RQ to the memory controller 12 in response to the signal input from the flip-flops 481 to 484. k Until all the outputs of the flip-flops 481 to 488 become "1", that is, when the count value is less than the upper limit value, the request signal RQ output from the AND circuit 49 becomes "0". k When all outputs of the AND circuit 49 become "1," that is, after the count value reaches the upper limit, the request signal RQ output from the AND circuit 49 becomes "1." When the request signal RQ is "1," it indicates that a request is made to replace the main memory cell of the word line WL from which data has been read with a redundant memory cell. For example, when the request signal RQ output from the AND circuit 49 of the management circuit 401 is "1," it indicates that a request is made to replace the main memory cell corresponding to the word line WL1 with a redundant memory cell.

[0036] In this way, the memory controller 12 receives a request signal RQ from each management circuit 40 of the correction count management unit 30. In addition, the memory controller 12 receives information (address) from the management circuit 40 indicating the word line WL requesting replacement.

[0037] This allows the memory controller 12 to determine whether or not to replace a main memory cell with a redundant memory cell for each word line WL based on the value (level) of the request signal RQ input from the management circuit 40 of the correction count management unit 30.

[0038] When the request signal RQ input from the correction count management unit 30 changes from "0" to "1", the memory controller 12 of this embodiment stores the address of the word line WL corresponding to the request signal RQ as the address of the defective memory cell in the replacement address storage memory 20C. n The address of the word line WL to be replaced with the redundant memory cell is input to the word line WL of the replacement address storage memory 20C.s+1 is stored in the memory cell corresponding to the

[0039] The address of the defective memory cell stored in the replacement address storage memory 20C is stored as defective address information in a register of the defective address determination redundancy switching circuit 32. As a result, from that point on, the redundant memory cell will be used in place of the main memory cell for which the number of times 1-bit errors have been corrected by the ECC circuit 26 has reached the upper limit.

[0040] Furthermore, the memory controller 12 of this embodiment stores the value output from the flip-flop 48, i.e., the count value of the number of corrections made up to now, in the replacement address storage memory 20C of the nonvolatile memory cell block 20 before power is cut off to the semiconductor memory device 10. As a result, the count value of the number of corrections made up to now is stored for each word line WL, and from the next time onwards, counting can be restarted from the previous count value.

[0041] Next, a process for managing the number of corrections made when reading data and replacing defective memory cells with redundant memory cells (hereinafter referred to as a correction management process) performed by the semiconductor memory device 10 of this embodiment will be described. Fig. 4 shows a flowchart illustrating an example of the flow of the correction management process. In this embodiment, when power is turned on, the correction management process shown in Fig. 4 is performed.

[0042] When power is turned on, the memory controller 12 sets the initial setting value or the current number of corrections in the flip-flop 48 of the management circuit 40 of the correction count management unit 30 in step S100, as described above. Specifically, the memory controller 12 inputs the initial setting value or the current number of corrections stored in the replacement address storage memory 20C as information DATA to the multiplexer 46 of the correction count management unit 30. The memory controller 12 also sets the control signal boot_en of the multiplexer 46 of the management circuit 40 to "1." This causes the multiplexer 46 to output the information DATA to the flip-flop 48, and the flip-flop 48 enters a state in which the initial setting value or the current number of corrections is set.

[0043] Next, in step S102, the memory controller 12 determines whether or not a data read request has been received from the CPU 2. Until a data read request has been received, the determination in step S102 remains negative, and the process proceeds to step S114. On the other hand, if a data read request has been received, the determination in step S102 remains positive, and the process proceeds to step S104.

[0044] If the ECC circuit 26 has not corrected the 1-bit error, the determination in step S104 is negative, and the process proceeds to step S114. On the other hand, if the ECC circuit 26 has corrected the 1-bit error, the determination in step S104 is positive, and then, in step S106, the correction count management unit 30 counts up the number of corrections as described above. Specifically, the signal SEC output from the ECC circuit 26 becomes "1," and the counted-up value is output from the multiplexer 44 of the management circuit 40 of the correction count management unit 30, and is output to the flip-flop 48 via the multiplexer 46.

[0045] If the counted-up number of corrections has not yet reached the upper limit, the determination in step S108 is negative, and the process proceeds to step S114. On the other hand, if the counted-up number of corrections has reached the upper limit, the determination in step S108 is positive, and then, in step S110, the request signal RQ output from the AND circuit 49 becomes "1" as described above. Specifically, the flip-flops 481 to 48 k Since all of the outputs of the AND circuit 49 are "1", the request signal RQ output from the AND circuit 49 is "1".

[0046] Next, in step S112, the memory controller 12 stores the address of the defective memory cell in the replacement address storage memory 20C as described above. Specifically, the memory controller 12 stores the address of the word line WL, whose request signal RQ has become "1", in the nonvolatile memory cell block 20 as the address of the defective memory cell.

[0047] Until the power supply is cut off, the determination in step S114 is negative, and the processes in steps S102 to S112 are repeated. On the other hand, if the power supply is cut off, the determination in step S114 is positive, and the process proceeds to step S116.

[0048] In step S116, the memory controller 12 stores the number of corrections of each word line WL held in each management circuit 40 of the correction count management unit 30 in the replacement address storage memory 20C. When the processing by the memory controller 12 ends, the correction management processing shown in FIG. 4 ends.

[0049] As described above, the semiconductor memory device 10 of the embodiment includes a main memory 20A including a plurality of main memory cells, a redundant memory 20B including a plurality of redundant memory cells, and word lines WL1 to WL2 that drive the main memory 20A. n and the word line WL that drives the redundant memory 20B. n+1 ~WL n+mThe semiconductor memory device 10 also includes an ECC circuit 26 that corrects errors in data read from the main memory cells, and a correction count management unit 30 that outputs a request signal RQ for requesting replacement of the main memory cells with redundant memory cells when the number of times that the data read from the main memory cells has been corrected by the ECC circuit 26 reaches or exceeds a predetermined number, for each of a predetermined number of word lines WL.

[0050] With the above configuration, the semiconductor memory device 10 can replace a defective main memory cell with a redundant memory cell even during use, thereby improving the reliability of the semiconductor memory device 10 and contributing to extending the life of the semiconductor memory device 10.

[0051] In the semiconductor memory device 10 of the above embodiment, as shown in FIG. n+1 ~WL n+m For these, too, by counting the number of corrections by the management circuit 40, if a redundant memory cell corresponding to one of these word lines WL becomes defective, it can be replaced with another redundant memory cell. Therefore, even if a defect occurs in a redundant memory cell, it can be replaced with a memory cell that is not defective, thereby further improving the reliability of the semiconductor memory device 10.

[0052] The semiconductor memory device 10 is not limited to the above-described embodiment (see FIGS. 2 and 3). For example, as shown in FIG. 6, the correction count management unit 30 may be configured with a FIFO (First-In First-Out) memory 30A and a processing unit 30B such as a processor. The number of corrections is stored in a system RAM (Random Access Memory) 12A. When the power is turned on, the current number of corrections or an initial setting value read from the replacement address storage memory 20C is stored in the system RAM 12A.

[0053] Every time the ECC circuit 26 corrects a one-bit error, the FIFO memory 30A stores a SEC signal indicating that the error has been corrected and the address of the corresponding word line WL.

[0054] The processing unit 30B counts the number of corrections, and when the upper limit is reached, performs a request process to request replacement of the memory cell with a redundant memory cell. Figure 7 shows a flowchart illustrating an example of the request process executed by the processing unit 30B.

[0055] In step S200, the processing unit 30B obtains the address information of the corrected memory cell (word line WL) from the FIFO memory 30A.

[0056] In the next step S202, the processing unit 30B reads out the number of corrections corresponding to the acquired address information from the system RAM 12A.

[0057] In the next step S204, the processing unit 30B adds "1" to the value read from the system RAM 12A, and stores the added value again in the system RAM 12A as a new number of corrections.

[0058] Until the number of corrections after addition reaches the upper limit of the number of corrections, the determination in step S206 remains negative, and the process proceeds to step S210. On the other hand, if the number of corrections after addition reaches the upper limit of the number of corrections, the determination in step S206 remains positive, and the process proceeds to step S208.

[0059] In step S208, the processing unit 30B outputs a request signal RQ set to "1" to the memory controller 12 to request replacement of the memory cell with a redundant memory cell.

[0060] Until the power is cut off, the determination in step S210 is negative, and the processing in steps S200 to S208 is repeated. On the other hand, when the power is cut off, the determination in step S210 is positive, and the request processing shown in FIG. 7 ends.

[0061] In this way, by adopting the configuration shown in FIG. 6, it is not necessary to provide a management circuit 40 for each word line WL, and therefore the scale of the correction count management unit 30 can be reduced.

[0062] 6, the FIFO memory 30A is provided in consideration of the time required to manage the number of corrections and the occurrence of consecutive corrections, but the FIFO memory 30A is not essential. For example, the processing unit 30B may directly acquire the signal SEC etc. from the ECC circuit 26.

[0063] Furthermore, for example, in the above embodiment, the number of times the ECC circuit 26 has corrected one bit error is counted up, but it may be counted down from an upper limit. In this case, as shown in FIG. 5, the management circuit 40 includes a count down circuit 41A instead of the count up circuit 41 of the management circuit 40 (see FIG. 3) described above, and a NOR circuit 49A instead of the AND circuit 49. As a result, when the count down is completed, the flip-flops 481 to 48 k All of the outputs become "1", the request signal RQ output from the NOR circuit 49A becomes "1", and in response to the request signal RQ, the memory controller 12 stores the defective memory address in the replacement address storage memory 20C.

[0064] Furthermore, in the above embodiment, the number of corrections is counted for each word line WL, in other words, the number of corrections is counted for each word line WL. However, the number of corrections may be counted for two or more word lines WL at a time. That is, the predetermined number in the present disclosure is not limited to "1" and may be "2" or greater. For example, when the number of corrections is counted for two word lines WL, the number of management circuits 40 included in the correction count management unit 30 is (n + m) ÷ 2. Furthermore, two word lines WL are connected to the input of the AND circuit 42, for example, via a selector. In this way, by increasing the number of word lines WL per unit for which the number of corrections is counted, the number of management circuits 40 can be reduced, thereby reducing the size of the correction count management unit 30.

[0065] Furthermore, the memory controller 12 may perform part of the functions of the correction count management unit 30 in the above embodiment.

[0066] The following additional notes are provided regarding the above-described embodiments. (Appendix 1) a main memory including a plurality of main memory cells; a redundant memory including a plurality of redundant memory cells; a word line group including a plurality of word lines for driving the main memory cells and a plurality of word lines for driving the redundant memory cells; a correction unit that corrects an error in the data read from the main memory cell; a management unit that outputs a request signal for requesting replacement of the main memory cell with the redundant memory cell when the number of times that data read from the main memory cell has been corrected by the correction unit reaches or exceeds a predetermined number for each of the predetermined number of word lines; A semiconductor memory device comprising:

[0067] (Appendix 2) The management unit counts the number of corrections for each of the predetermined number of word lines. 2. The semiconductor memory device according to claim 1.

[0068] (Appendix 3) The management unit stores the count value of the number of corrections in a nonvolatile storage unit before power is cut off. 10. The semiconductor memory device according to claim 1 or 2.

[0069] (Appendix 4) the correction unit further corrects errors in the data read from the redundant memory cells; The request signal output by the management unit requests replacement of the redundant memory cell with another redundant memory cell when the number of times that data read from the redundant memory cell has been corrected by the correction unit reaches or exceeds a predetermined number for each of the predetermined number of word lines. 4. The semiconductor memory device according to claim 1, wherein the first and second memory cells are arranged in a first direction.

[0070] (Appendix 5) The memory cell storage device further includes a control unit that controls replacement of the main memory cell with the redundant memory cell based on the request signal output from the management unit. 5. The semiconductor memory device according to claim 1, wherein the first and second memory cells are arranged in a first direction. [Explanation of symbols]

[0071] 10. Semiconductor memory device 12 Memory Controller 14 Memory 20 nonvolatile memory cell block, 20A main memory, 20B redundant memory, 20c replacement address storage memory 21 Peripheral circuits 26 ECC circuit 28 Test Circuit 30 Correction count management section 32 Defective address determination redundancy switching circuit 40, 401-40 n+m management circuit WL, WL1~WL n , W.L. n+1 , W.L. n+m Word Line

Claims

1. a main memory including a plurality of main memory cells; a redundant memory including a plurality of redundant memory cells; a word line group including a plurality of word lines for driving the main memory cells and a plurality of word lines for driving the redundant memory cells; a correction unit that corrects an error in the data read from the main memory cell; a management unit that outputs a request signal for requesting replacement of the main memory cell with the redundant memory cell when the number of times that data read from the main memory cell has been corrected by the correction unit reaches or exceeds a predetermined number for each of the predetermined number of word lines; A semiconductor memory device comprising:

2. The management unit counts the number of corrections for each of the predetermined number of word lines.

2. The semiconductor memory device according to claim 1.

3. The management unit stores the count value of the number of corrections in a nonvolatile storage unit before power is cut off.

3. The semiconductor memory device according to claim 2.

4. the correction unit further corrects errors in the data read from the redundant memory cells; The request signal output by the management unit requests replacement of the redundant memory cell with another redundant memory cell when the number of times that data read from the redundant memory cell has been corrected by the correction unit reaches or exceeds a predetermined number for each of the predetermined number of word lines.

2. The semiconductor memory device according to claim 1.

5. The memory cell storage device further includes a control unit that controls replacement of the main memory cell with the redundant memory cell based on the request signal output from the management unit.

2. The semiconductor memory device according to claim 1.

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