Wiring board and method for manufacturing the same

Abstract

To provide a wiring board in which defects in via conductors are suppressed.SOLUTION: A wiring board 1 according to an embodiment includes a conductor layer 20 including a via land VL, a conductor film ACL formed on the via land VL, an insulating layer 11 covering the conductor layer 20 and the conductor film ACL, and a via conductor 30 that penetrates the insulating layer 11 and connects to the via land VL through the conductor film ACL. The ratio of the shortest distance between the top surface of the conductor film ACL and the end face of the via conductor 30 opposite to the end face connected to the conductor film ACL to the shortest distance between the top surface of the via land VL and the end face of the via conductor 30 opposite to the end face connected to the conductor film ACL is 0.4 or more and 0.7 or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a wiring board and a method for manufacturing the wiring board. An insulating layer is formed on a conductor layer, and through holes are formed in the insulating layer to penetrate the insulating layer. A conductor is filled in the through holes to form via conductors connected to the conductor layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-58472 Summary of the Invention [Problem to be solved by the invention]

[0004] In the wiring board manufacturing method of Patent Document 1, when the insulating layer is thick, the depth of the through hole increases, which may make it difficult to fill the conductor, and defects such as voids in the formed via conductor may occur. [Means for solving the problem]

[0005] The wiring board of the present invention includes a conductor layer including a via land, a conductor film formed on the via land, an insulating layer covering the conductor layer and the conductor film, and a via conductor that penetrates the insulating layer and connects to the via land through the conductor film, wherein the ratio of the shortest distance between the top surface of the via land and the end face of the via conductor opposite to the end face connected to the conductor film to the shortest distance between the top surface of the conductor film and the end face of the via conductor opposite to the end face connected to the conductor film is 0.4 or more and 0.7 or less.

[0006] A method for manufacturing a wiring board of the present invention includes forming a conductor layer including a via land, forming a resist layer including an opening exposing the upper surface of the via land, forming a conductor film in the opening by electrolytic plating, removing the resist layer, forming an insulating layer covering the conductor layer and the conductor film, forming a through hole that penetrates the insulating layer to expose the upper surface of the conductor film, and filling the through hole with a conductor to form a via conductor. Forming the conductor film and the insulating layer includes setting the ratio of the shortest distance from the upper surface of the conductor film to the shortest distance from the upper surface of the insulating layer to be 0.4 or more and 0.7 or less.

[0007] According to the embodiment of the present invention, a high-quality wiring board in which defects in via conductors are suppressed can be provided. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring substrate according to an embodiment of the present invention. [Figure 2A] FIG. 2 is a partially enlarged view of region II in FIG. 1. [Figure 2B] FIG. 10 is a cross-sectional view showing another example of the wiring board according to the embodiment of the present invention. [Figure 2C] FIG. 10 is a cross-sectional view showing another example of the wiring board according to the embodiment of the present invention. [Figure 2D] FIG. 10 is a cross-sectional view showing another example of the wiring board according to the embodiment of the present invention. [Figure 3A] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 3B] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 3C] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 3D] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 3E] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 3F] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] The wiring board of the present invention will be described below with reference to the drawings. Note that the drawings referred to below are not intended to show the exact proportions of the components, but are drawn to make the features of the present invention easier to understand. FIG. 1 shows a partial cross section of wiring board 1, which is an example of a wiring board according to an embodiment. Wiring board 1 is formed of insulating layers and conductor layers that are alternately stacked, and FIG. 1 shows some of the insulating layers and conductor layers.

[0010] 1 shows two insulating layers 10 and 11, two conductor layers 20 and 21, and a solder resist layer SR on one surface F of the wiring board 1, among the multiple insulating layers and conductor layers that the wiring board 1 may have. The conductor layer 20 and the conductor layer 21 are connected by a via conductor 30 that penetrates the insulating layer 11 in the thickness direction. An opening SRa is formed in the solder resist layer SR that constitutes the one surface F of the wiring board 1, and the surface of a conductor pad 21p included in the conductor layer 21 is exposed from the opening SRa.

[0011] The wiring board of the embodiment has at least an insulating layer 11, a conductor layer 20, and a via conductor 30. The number of insulating layers and conductor layers included in the wiring board 1 is not particularly limited and may be increased or decreased as appropriate. In the illustration, the insulating layer 11 is shown as the uppermost insulating layer in the wiring board 1, and the via conductor 30 is shown as the uppermost via conductor in the wiring board 1, but the arrangement of the insulating layer 11, the via conductor 30, and the conductor layer 20 in the wiring board of the embodiment is not limited to the illustrated example. An additional insulating layer may be stacked on top of the insulating layer 11 and the conductor layer 21, and via conductors penetrating the additional insulating layer and conductor layers on the additional insulating layer may be formed. In the description of the wiring board 1, the side of one surface F of the wiring board 1 will be referred to as the "top," "upper side," "outside," or simply "outside." The side of each element constituting the wiring board 1 on which the one surface F is formed will also be referred to as the "top," "upper side," "outside," or simply "outside."

[0012] One surface F of the illustrated wiring board 1 can be formed as a component mounting surface on which external electronic components such as semiconductor elements are mounted. The surface (not shown) of the wiring board 1 opposite to one surface F is formed as a connection surface used for connecting to a motherboard of an electronic device, a package substrate of a semiconductor device having a stacked structure, etc. One surface F of the wiring board 1 shown in FIG. 1 is composed of a solder resist layer SR and the surfaces of the conductor pads 21p exposed in the openings SRa of the solder resist layer SR.

[0013] The conductor layer 20 is formed in contact with the upper surface of the insulating layer 10. The conductor layer 20 includes a via land VL connected to a via conductor 30 formed thereon. The via land VL formed in the conductor layer 20 is electrically connected to the conductor layer 21 on the opposite side of the insulating layer 11 through the via conductor 30 formed in the insulating layer 11. The via conductor 30 is formed by a conductor filled in a through hole 11a penetrating the insulating layer 11. The via conductor 30 has a tapered shape whose diameter decreases from one surface F to the opposite side (bottom), but the shape of the via conductor 30 is not limited to this. The via conductor 30 may have a shape whose diameter decreases toward one surface F, or may be formed into a cylindrical shape that has the same diameter in the thickness direction of the insulating layer 11 and is approximately perpendicular to the conductor layer 20. Note that although the term "diameter" is used, the planar shapes of the through hole 11a and the via conductor 30 are not necessarily circular. The "diameter" refers to the distance between the longest two points on the periphery of the through hole 11a and the via conductor 30 in a horizontal cross section. Furthermore, for convenience, the term "reduced diameter" is used, but "reduced diameter" simply means that the distance between the longest two points on the outer periphery of the via conductor 30 in a horizontal cross section becomes smaller.

[0014] In the wiring board of the embodiment, a conductor film ACL is formed on the via land VL of the conductor layer 20. The via land VL of the conductor layer 20 and the via conductor 30 are connected through the conductor film ACL. As shown in the figure, the conductor film ACL can be formed only on the via land VL in the conductor pattern of the conductor layer 20.

[0015] The insulating layers 10 and 11 of the wiring board 1 are formed using any insulating resin, such as epoxy resin. Polyimide resin, BT resin (bismaleimide-triazine resin), polyphenylene ether resin, phenolic resin, etc. may also be used. The insulating layers 10 and 11 may contain an inorganic filler, such as silica. In the illustrated example of the wiring board 1, the insulating layers 10 and 11 do not contain a core material, but may contain a core material, such as glass fiber or aramid fiber, if necessary. The multiple insulating layers that may constitute the wiring board 1 may be made of different materials, or all may be made of the same material. The solder resist layer SR is formed using, for example, a photosensitive polyimide resin, epoxy resin, etc.

[0016] The conductor layers 20, 21, the conductor film ACL, and the via conductors 30 may be formed using any suitable conductive material, such as copper. The conductor layers 20, 21 and the via conductors 30 may be formed, for example, by sputtering, electroless plating, electrolytic plating, or a combination thereof. In the illustrated example, the conductor layers 20, 21 have a two-layer structure consisting of a metal film layer Ca, which may be, for example, an electroless copper plating film, and a plating film layer Cb, which may be, for example, an electrolytic copper plating film. However, the structure of each conductor layer 20, 21 constituting the wiring board 1 is not limited to the multilayer structure illustrated in FIG. 1. For example, they may have a three-layer structure consisting of copper foil, an electroless copper plating film layer, and an electrolytic copper plating film layer. Alternatively, the conductor layers 20, 21 may have a single-layer structure consisting of an electroless plating film.

[0017] As shown in the figure, the via conductor 30 can be formed integrally with the metal film layer Ca and plating film layer Cb that constitute the conductor layer 21. In the example shown, the via conductor 30 is a so-called filled via that fills the through hole 11a, and is composed of the metal film layer Ca and plating film layer Cb that cover the inner surface (bottom surface and inner wall surface) of the through hole 11a. Alternatively, the via conductor 30 may have a single-layer structure of electroless plating film.

[0018] The conductor film ACL formed on the via land VL is formed as an electrolytic plated film layer by electrolytic plating on the conductor layer 20. The conductor film ACL can be composed of a single layer of electrolytic plated film. The conductor layer ACL is preferably formed of the same conductor material as the conductor material constituting the plating film layer Cb constituting the conductor layer 20.

[0019] 2A, the configurations of the via land VL, the conductive film ACL on the via land VL, and the via conductor 30 provided in the wiring board of the embodiment will be described in detail. Fig. 2 is an enlarged view of an area II surrounded by a dashed line in Fig. 1.

[0020] 2A, the entire bottom surface of the through hole 11a is formed by the upper surface of the conductive film ACL. The entire bottom of the via conductor 30 is directly connected to the upper surface of the conductive film ACL. The via land VL and the via conductor 30 are not directly connected, but are indirectly connected via the conductive film ACL. Therefore, the depth of the via conductor 30 (the dimension of the via conductor 30 in the thickness direction of the insulating layer 11) is smaller than when the via conductor 30 is directly connected to the via land VL.

[0021] The conductive film ACL is formed so as to satisfy a predetermined dimensional condition for the shortest distance D1 between the upper surface of the via land VL and the upper surface of the via conductor 30. Note that the "upper surface of the via conductor 30" refers to the end surface opposite to the end surface connected to the upper surface of the conductive film ACL, of the two end surfaces extending perpendicular to the depth direction of the via conductor 30. In other words, the "upper surface of the via conductor 30" refers to the interface of the via conductor 30 with the conductive layer 21 along the upper surface of the insulating layer 11, and the upper surface of the via conductor 30 is located at the same level as the upper surface of the insulating layer 11 in the thickness direction of the insulating layer 11. Specifically, the conductive film ACL is formed to a thickness such that the ratio of the shortest distance D2 between the upper surface of the conductive film ACL and the upper surface of the via conductor 30 to the shortest distance D1 between the upper surface of the via land VL and the end surface of the via conductor 30 opposite to the end surface connected to the conductive film ACL is 0.4 or more and 0.7 or less.

[0022] By forming the conductor film ACL so that its thickness satisfies the above-described predetermined dimensional conditions, the through hole 11a can be formed with a relatively small depth. By forming the through hole 11a with a relatively small depth, the via conductor 30 can be formed in the through hole 11a with relatively fewer defects than when the through hole 11a is relatively deep. When the through hole 11a is relatively deep, voids may be more likely to occur in the process of forming the via conductor 30 (particularly when forming the plating film layer Cb). Furthermore, a downward recess may be formed in the region immediately above the via conductor 30 of the conductor layer 21 formed integrally with the via conductor 30. To address this problem, by forming the conductor film ACL so that it satisfies the above-described predetermined dimensional conditions, the through hole 11a can be formed with a relatively small depth, and the via conductor 30 can be formed without voids. Furthermore, a conductor layer 21 can be formed in which recesses in the region immediately above the via conductor 30 are suppressed.

[0023] From the viewpoint of suppressing voids in the via conductor 30 as described above, it is preferable that the thickness of the conductor film ACL is formed so that the shortest distance between the upper surface of the conductor film ACL and the upper surface of the via conductor 30 is 20 μm or more and 35 μm or less. From the same viewpoint, it is also preferable that the diameter UD of the via conductor 30 is 50 μm or more and 70 μm or less. Here, the "diameter of the via conductor 30" means the distance between the longest two points on the periphery of the upper surface of the via conductor 30 in a plan view.

[0024] Furthermore, from the viewpoint of suppressing voids as described above, it is preferable that the aspect ratio of the via conductor 30 (shortest distance D2 between the upper surface of the conductive film ACL and the upper surface of the via conductor 30 / diameter UD of the via conductor 30) is 1.4 or more and 2.5 or less. For example, as described above, when the diameter UD of the via conductor 30 is 50 μm or more and 70 μm or less, the shortest distance D1 from the upper surface of the via land VL to the upper surface of the via conductor 30 is about 40 μm to 50 μm, and the thickness of the conductive film ACL is about 15 μm to 20 μm. Therefore, the depth of the via conductor 30 (shortest distance D2 between the upper surface of the conductive film ACL and the upper surface of the via conductor 30) can be about 20 μm to 35 μm.

[0025] Next, with reference to FIG. 2B , a configuration different from that shown in FIG. 2A will be described regarding the connection between the via conductor 30, the via land VL, and the conductive film ACL. While FIG. 2A illustrates an example in which the via conductor 30 is directly connected to the conductive film ACL and indirectly connected to the via land VL via the conductive film ACL, the example shown in FIG. 2B illustrates an example in which the via conductor 30 is directly connected to the conductive film ACL and the via land VL. Specifically, the through hole 11a exposes the top surface of the via land VL and the side and top surfaces of the conductive film ACL at its bottom. That is, the bottom of the via conductor 30 is directly connected to the top surface of the via land VL and the side and top surfaces of the conductive film ACL. Note that in the examples shown in FIG. 2B and the subsequently referenced FIGS. 2C and 2D , the configurations other than the configuration regarding the connection between the via conductor 30, the via land VL, and the conductive film ACL are the same as the configuration described with reference to FIG. 2A , and therefore, their description will be omitted.

[0026] 2B, the via land VL is directly connected to the conductive film ACL and the via conductor 30, the conductive film ACL is directly connected to the via land VL and the via conductor 30, and the via conductor 30 is directly connected to the via land VL and the conductive film ACL. In addition to the above-mentioned void suppression in the via conductor 30, the direct connections between the via conductor 30, the conductive film ACL, and the via land VL may result in a more reliable connection structure that is less susceptible to peeling.

[0027] Next, with reference to Fig. 2C, a modified example of the configuration of the via conductor 30, via land VL, and conductive film ACL shown in Fig. 2B will be described. In the example shown in Fig. 2C, the entire upper and side surfaces of the conductive film ACL are directly connected to the via conductor 30, and the via conductor 30 is directly connected to the via land VL over the entire periphery of the conductive film ACL. With this configuration, in addition to suppressing voids in the via conductor 30 as described above, it is believed that peeling at the connections between the via conductor 30, conductive film ACL, and via land VL may be more effectively suppressed.

[0028] Next, with reference to Fig. 2D, a configuration example of the via conductor 30, via land VL, and conductive film ACL different from the example shown in Fig. 2A will be described. In the example shown in Fig. 2D, like the example shown in Fig. 2A, the entire bottom of the via conductor 30 is directly connected to the upper surface of the conductive film ACL, but it differs from the example shown in Fig. 2A in that the entire upper surface of the via land VL is covered by the conductive film ACL. In this way, by forming the conductive film ACL over a relatively wide area, the possibility of a state in which the upper surface of the conductive film ACL cannot be exposed at the bottom surface of the through hole 11a during the formation of the via conductor 30 (specifically, during the drilling of the through hole 11a) may be reduced. Therefore, the above-mentioned suppression of voids in the via conductor 30 may be more effectively achieved.

[0029] 1 as an example, a method for manufacturing a wiring board according to an embodiment will be described below with reference to FIGS. 3A to 3F. As in FIG. 1, the entire wiring board 1 is not shown in FIGS. 3A to 3F, but only a partial cross section of one surface F of the wiring board 1 is shown. In the following description, as in the description of the wiring board 1 described above, the side of each element constituting the wiring board 1 on which one surface F of the wiring board 1 is formed will be referred to as the "top," "upper side," "outside," or simply "outside."

[0030] First, a wiring board is prepared by a typical build-up method for manufacturing wiring boards, in which one or more pairs of insulating and conductor layers are stacked. A conductor layer 20 having a pattern including via lands VL is stacked on the insulating layer 10 of the prepared wiring board, forming a two-layer structure of, for example, a metal film layer Ca and a plating film layer Cb, resulting in the state shown in FIG. 3A . The metal film layer Ca can be formed, for example, by electroless copper plating, as an electroless copper plating film covering the entire upper surface of the insulating layer 10. The plating film layer Cb can be formed, for example, by electrolytic copper plating using the metal film layer Ca as a power supply layer. In the illustrated state, of the metal film layer Ca and plating film layer Cb that constitute the conductor layer 20, the plating film layer Cb is formed in the pattern that the conductor layer 20 should have. The metal film layer Ca covers the entire upper surface of the insulating layer 10 and is exposed from the pattern of the plating film layer Cb.

[0031] 3B, a resist film RL is formed on the surface of the conductor layer 20 (the upper and side surfaces of the plating film layer Cb and the upper surface of the metal film layer Ca exposed from the pattern of the plating film layer Cb). The resist film RL is formed to have an opening RLa corresponding to the position where the conductor film ACL (see FIG. 1) will be formed. The resist film RL can be formed, for example, by forming a resin layer containing a photosensitive polyhydroxyether resin, epoxy resin, phenolic resin, polyimide resin, or the like, and exposing and developing it using a mask having an opening pattern corresponding to the pattern of the opening RLa.

[0032] 3C, a conductor film ACL is formed in the opening RLa of the resist film RL by, for example, electrolytic plating using the conductor layer 20 as a power supply layer. In forming the conductor film ACL, electrolytic plating of the same conductor material as the plating film layer Cb constituting the conductor layer 20 may be performed.

[0033] Next, the resist film RL is removed. Removal of the resist film exposes the side surfaces of the conductor film ACL and the upper surface of the conductor layer 20. The metal film layer Ca exposed by removing the resist film RL is removed by etching, and the upper surface of the insulating layer 10 is exposed from the pattern of the conductor layer 20. The state shown in FIG. 3D is formed. The metal film layer Ca is removed by etching after the conductor film ACL is formed. That is, the formation of the plating film layer Cb and the formation of the conductor film ACL can be performed by electrolytic plating using the common metal film layer Ca as a power supply layer.

[0034] Next, as shown in FIG. 3E, an insulating layer 11 is formed to cover the surfaces (top and side surfaces) of the conductor film ACL, the surfaces (top and side surfaces) of the conductor layer 20, and the upper surface of the insulating layer 10 exposed from the pattern of the conductor layer 20. The insulating layer 11 can be formed by thermocompression bonding any insulating resin, such as polyimide resin, BT resin (bismaleimide-triazine resin), polyphenylene ether resin, or phenolic resin, formed into a film shape. Next, through holes 11a that penetrate the insulating layer 11 are formed at the positions where the via conductors 30 (see FIG. 1) will be formed in the insulating layer 11 by irradiation with laser light, such as a carbon dioxide laser beam or a YAG laser beam. The through holes 11a are formed so that the upper surface of the conductor film ACL is exposed at the bottom.

[0035] 3C and the insulating layer 11 described with reference to FIG. 3E, the thicknesses of the conductive film ACL and the insulating layer 11 are adjusted to satisfy predetermined dimensional conditions. Specifically, the thicknesses of the conductive film ACL and the insulating layer 11 are adjusted so that the ratio of the shortest distance between the top surface of the conductive film ACL and the top surface of the insulating layer 11 to the shortest distance between the top surface of the conductive layer 20 and the top surface of the insulating layer 11 is 0.4 or more and 0.7 or less. That is, the depth (dimension in the thickness direction of the insulating layer 11) of the through-hole 11a that penetrates the insulating layer 11 and exposes the conductive film ACL at the bottom surface is set smaller than that in the case where the top surface of the conductive layer 20 (top surface of the via land VL) is exposed at the bottom surface, in accordance with the above-mentioned conditions satisfied by the conductive film ACL and the insulating layer 11.

[0036] For example, in forming the conductive film ACL and the insulating layer 11, the shortest distance between the upper surface of the conductive film ACL and the upper surface of the insulating layer 11 is adjusted to be 20 μm or more and 35 μm or less. In forming the through hole 11a described with reference to FIG. 3E, the diameter of the through hole 11a (the distance between the longest two points on the periphery of the through hole 11a on the upper surface of the insulating layer 11) can be formed to be 50 μm or more and 70 μm or less.

[0037] 3F, via conductors 30 in through holes 11a and conductor layer 21 covering the upper surface of insulating layer 11 are integrally formed. A metal film layer Ca is formed by, for example, electroless plating of copper over the inner surfaces (bottom and sidewall surfaces) of through holes 11a and the entire upper surface of insulating layer 11. Subsequently, a plating resist for electrolytic plating having openings according to the conductor pattern that conductor layer 21 should have is formed on metal film layer Ca, and a plating film layer Cb is formed in the openings by, for example, electrolytic plating of copper.

[0038] The via conductor 30 is formed by forming a plating film layer Cb on the metal film layer Ca that covers the inner wall of the through hole 11a and is exposed in the opening of the plating resist. As described above, the thicknesses of the conductive film ACL and the insulating layer 11 are formed to satisfy predetermined dimensional conditions, and therefore the depth of the through hole 11a exposed in the opening is relatively small. Therefore, it is considered that voids are unlikely to be formed when the plating film layer Cb is formed in the through hole 11a. In addition, it is considered that a recess is unlikely to be formed in the region directly above the via conductor 30 in the conductor layer 21 that is formed integrally with the via conductor 30.

[0039] Subsequently, the plating resist is removed to expose the metal film layer Ca, and the exposed metal film layer Ca is removed by etching to expose the upper surface of the insulating layer 11. The conductor layer 21 including the conductor pads 21p is formed.

[0040] Next, a solder resist layer SR is formed by laminating a photosensitive epoxy resin or polyimide resin layer on the surfaces of the conductor layer 21 and the insulating layer 11. Openings SRa that define the conductor pads 21p are formed in the solder resist layer SR by photolithography. This completes the formation of the wiring board 1.

[0041] The wiring board of the embodiment is not limited to the structures illustrated in the drawings or the structures and materials illustrated in this specification. The wiring board of the embodiment includes at least a conductor layer including a via land, a conductor film formed on the via land, an insulating layer covering the conductor layer, and via conductors that penetrate the insulating layer and connect to the via land through the conductor film. The ratio of the shortest distance between the top surface of the conductor film and the top surface of the via conductor to the shortest distance between the top surface of the via land and the top surface of the via conductor is not limited to 0.4 or more and 0.7 or less. The number of insulating layers and conductor layers constituting the wiring board is not limited. Furthermore, a plating layer including, for example, a nickel layer and a tin layer may be formed on the surface of the conductor pad 21p included in the conductor layer 21 constituting one side F.

[0042] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to the drawings, and the conditions and order of the steps may be modified as appropriate. The method for manufacturing a wiring board according to the embodiment includes forming a conductor layer including a via land, forming a resist including an opening that exposes the via land, forming a conductor film by electrolytic plating, forming an insulating layer covering the conductor film, forming a through hole that exposes the upper surface of the conductor film, and forming a via conductor in the through hole. The formation of the conductor film and insulating layer may include setting the ratio of the shortest distance from the upper surface of the conductor film to the shortest distance from the upper surface of the insulating layer to the shortest distance from the upper surface of the via land to the shortest distance from the upper surface of the insulating layer to 0.4 or more and 0.7 or less. For example, after forming the conductor layer 21, a solder resist layer SR may not be formed on the conductor layer 21, and any number of insulating and conductor layers may be further stacked on top of the conductor layer 21. Depending on the structure of the wiring board to be manufactured, some steps may be omitted or other steps may be added. [Explanation of symbols]

[0043] 1. Wiring board 10, 11 Insulation layer 20, 21 Conductor layer 11a Through hole 30 Via conductor ACL Conductor Film VL Beerland Ca metal film layer Cb plating layer RL resist layer F One side

Claims

1. a conductor layer including a via land; a conductive film formed on the via land; an insulating layer covering the conductor layer and the conductor film; a via conductor that penetrates the insulating layer and connects to the via land through the conductive film; A wiring board comprising: the shortest distance between the top surface of the via land and the end surface of the via conductor opposite to the end surface connected to the conductive film, The ratio of the shortest distance between the top surface of the conductive film and the end face of the via conductor opposite to the end face connected to the conductive film is 0.4 or more and 0.7 or less.

2. 2. The wiring board according to claim 1, wherein the shortest distance between the upper surface of the conductive film and the end face of the via conductor opposite to the end face connected to the conductive film is 20 [mu]m or more and 35 [mu]m or less.

3. 2. The wiring board according to claim 1, wherein the via conductor has a diameter of 50 μm or more and 70 μm or less.

4. 2. The wiring board according to claim 1, wherein the aspect ratio of the via conductor is 1.4 or more and 2.5 or less.

5. 2. The wiring board according to claim 1, wherein the entire bottom of the via conductor is directly connected to the upper surface of the conductive film.

6. 2. The wiring board according to claim 1, wherein the bottom of the via conductor is directly connected to the upper surface of the conductive film and the upper surface of the via land.

7. 2. The wiring board according to claim 1, wherein the via land is made up of a metal film layer and a plated film layer, and the conductor film is made up of a plated film layer.

8. 2. The wiring board according to claim 1, wherein the conductive film is formed only on the via land.

9. 2. The wiring board according to claim 1, wherein the conductor layer comprises a metal film layer and a plated film layer, and the conductor film is formed from the same conductor material as that constituting the plated film layer.

10. 10. The wiring board according to claim 9, wherein the conductive material is copper.

11. forming a conductor layer including a via land; forming a resist layer including an opening exposing an upper surface of the via land; forming a conductive film in the opening by electrolytic plating; removing the resist layer; forming an insulating layer covering the conductor layer and the conductor film; forming a through hole that penetrates the insulating layer and exposes an upper surface of the conductor film; filling the through hole with a conductor to form a via conductor; A method for manufacturing a wiring substrate, comprising: Forming the conductive film and the insulating layer includes setting the ratio of the shortest distance from the top surface of the conductive film to the top surface of the insulating layer to 0.4 or more and 0.7 or less.

12. 12. A method for manufacturing a wiring board according to claim 11, wherein forming the conductor layer includes forming a metal film layer and forming a plating film layer by electrolytic plating using the metal film layer as a power supply layer.

13. 13. The method for manufacturing a wiring board according to claim 12, wherein forming the conductive film includes electrolytic plating using the metal film layer as a power supply layer.

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