Multilayer substrate, filter module, and communication device

Abstract

To stabilize electrical characteristics of an inductor in a multilayer substrate.SOLUTION: A multilayer substrate comprises: a plurality of dielectric layers laminated in a thickness direction of the multilayer substrate; and a first inductor and a second inductor consisting of a plurality of conductor patterns positioned on surfaces of the plurality of dielectric layers. When a rectangular, circular or elliptic virtual line enclosing the first inductor is assumed in a planar perspective view in the thickness direction, the first inductor includes a recess separated from the virtual line in a first direction, and a first distance which is a maximal value of a distance between the recess and the second inductor in the first direction within a range where the recess extends in a second direction across the first direction is larger than a second distance which is a maximal value of a distance between the recess and the virtual line in the first direction within the range where the recess extends in the second direction.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] One aspect of the present disclosure relates to a multilayer substrate having an inductor. [Background technology]

[0002] Patent Document 1 listed below discloses an example of a wiring pattern for an inductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-124373 Summary of the Invention [Problem to be solved by the invention]

[0004] It is desirable to stabilize the electrical characteristics of inductors in multilayer substrates. [Means for solving the problem]

[0005] A multilayer substrate according to one embodiment of the present disclosure has a first inductor and a second inductor each composed of a plurality of dielectric layers stacked in the thickness direction of the multilayer substrate and a plurality of conductor patterns located on the surface of each of the plurality of dielectric layers, and when viewed from a plane perspective in the thickness direction, when a rectangular, circular, or elliptical imaginary line surrounding the first inductor is imagined, the first inductor has a recess spaced from the imaginary line in the first direction, and a first distance, which is the maximum value of the distance between the recess and the second inductor in the first direction within the range in which the recess extends in a second direction intersecting the first direction, is greater than a second distance, which is the maximum value of the distance between the recess and the imaginary line in the first direction within the range in which the recess extends in the second direction. [Effects of the Invention]

[0006] According to one aspect of the present disclosure, it is possible to stabilize the electrical characteristics of an inductor in a multilayer substrate. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic perspective view showing an example of the configuration of a multilayer substrate according to a first embodiment. [Figure 2] 3 shows an example of the shape of the first inductor of the first embodiment in plan view. [Figure 3] FIG. 10 is a schematic perspective view showing a configuration example of a multilayer substrate as a comparative example. [Figure 4] 10 shows an example of the shape of a first inductor of a comparative example in planar perspective view. [Figure 5] 10 shows an example of the positional relationship between a first inductor and a second inductor in a comparative example in planar perspective view. [Figure 6] 3 shows an example of the positional relationship between a first inductor and a second inductor in a planar perspective view according to the first embodiment. [Figure 7] 10 is a schematic perspective view showing an example of the configuration of a multilayer substrate according to a second embodiment. FIG. [Figure 8] 10 shows an example of the shape of the second inductor of the second embodiment in plan view. [Figure 9] 10 shows an example of the positional relationship between a first inductor and a second inductor in a planar perspective view according to the second embodiment, and also exemplifies distances related to the first inductor. [Figure 10] 10 shows an example of the positional relationship between a first inductor and a second inductor in a planar perspective view according to the second embodiment, and also exemplifies distances related to the second inductor. [Figure 11] 10 shows an example of the configuration of a filter module according to a third embodiment. [Figure 12] 1 shows an example of the configuration of a filter module as a comparative example. [Figure 13] 10 shows an example of the configuration of a communication device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Embodiment 1] Embodiment 1 will be described below. For convenience of explanation, components having the same functions as those described in Embodiment 1 will be denoted by the same reference numerals in the following embodiments, and their description will not be repeated. For simplicity, descriptions of well-known technical matters will be omitted as appropriate. Each component, material, and numerical value described in this specification is merely exemplary unless there is a contradiction in the content. Therefore, for example, the positional relationship and connection relationship of each component are not limited to the examples in each figure unless there is a contradiction in the content. Furthermore, each figure is not necessarily drawn to scale.

[0009] (One example of the configuration of the multilayer substrate 1) Fig. 1 is a schematic perspective view showing an example of the configuration of a multilayer substrate 1 according to embodiment 1. For convenience of explanation, a Cartesian coordinate system (D1-D2-D3 coordinate system) shown in Fig. 1 is introduced in this specification. Of the components of the multilayer substrate 1, Fig. 1 shows only those components related to the first inductor LA, and other components are omitted from the illustration.

[0010] In this specification, planar perspective from the thickness direction of the multilayer substrate 1 (direction D3 described below) is simply referred to as "planar perspective." The direction D1 in the example of embodiment 1 represents a certain direction in planar perspective. In the example of FIG. 2 described below, the direction D1 is the horizontal direction (lateral direction) within the plane of the paper. The direction D1 may also be referred to as the first direction.

[0011] The D2 direction is a direction that intersects with the D1 direction in planar perspective. In the example of Fig. 2, the D2 direction is a vertical direction (lengthwise direction) in the plane of the paper. The D2 direction may also be referred to as a second direction.

[0012] The D3 direction is the thickness direction of the multilayer substrate 1. In this specification, the positive direction of the D3 direction is described as the upward direction. Therefore, the negative direction of the D3 direction is the downward direction. A support substrate (not shown) of the multilayer substrate 1 is located in the negative direction of the D3 direction. The D3 direction may also be referred to as a third direction.

[0013] The multilayer substrate 1 has a plurality of dielectric layers stacked in the D3 direction. The multilayer substrate 1 may be, for example, an LTCC (Low Temperature Co-fired Ceramics) multilayer substrate. That is, the multilayer substrate 1 may have LTCC layers as dielectric layers. In this case, the capacitors in the multilayer substrate 1 may be realized by the LTCC layers.

[0014] In the example of FIG. 1, four dielectric layers LY1 to LY4 are shown. In this specification, the dielectric layers LY1 to LY4 may be collectively referred to as dielectric layers LY. In the example of FIG. 1, the four dielectric layers LY are adjacent to each other at a constant interval (pitch) in the D3 direction. In this specification, the pitch of the dielectric layers LY is represented as pt. In the example of FIG. 1, the four dielectric layers LY are parallel to each other. The LYs extend in the D1 and D2 directions.

[0015] The dielectric layer LY1 is located at the top of the four dielectric layers LY. The dielectric layer LY2 is adjacent to the dielectric layer LY1 on its lower side. The dielectric layer LY3 is adjacent to the dielectric layer LY2 on its lower side. The dielectric layer LY4 is adjacent to the dielectric layer LY3 on its lower side. Therefore, the dielectric layer LY4 is located at the bottom of the four dielectric layers LY. In this way, in the example of FIG. 1, the numbers indicating the dielectric layers LY increase from top to bottom.

[0016] The multilayer substrate 1 has a first inductor LA and a second inductor LB, each of which is composed of a plurality of conductor patterns located on the surface of each of the dielectric layers LY1 to LY4. The second inductor LB is not shown in Fig. 1. Therefore, of the plurality of conductor patterns, only the conductor pattern constituting the first inductor LA is shown in Fig. 1.

[0017] 1 illustrates four conductor patterns PA1 to PA4 as conductor patterns that configure the first inductor LA. In this specification, the conductor patterns PA1 to PA4 may be collectively referred to as the conductor pattern PA. As will be described later, the conductor pattern PA forms a main body portion PP1 and a protrusion portion PP2 of the first inductor LA in a planar perspective view (see FIG. 2).

[0018] 1, the conductor pattern PA1 is located on the surface of the dielectric layer LY1. The conductor pattern PA2 is located on the surface of the dielectric layer LY2. The conductor patterns PA1 and PA2 are connected via a via-hole conductor BA12 that connects the dielectric layers LY1 and LY2.

[0019] Next, the conductor pattern PA3 is located on the surface of the dielectric layer LY3. The conductor patterns PA2 and PA3 are connected via a via-hole conductor BA23 that connects the dielectric layers LY2 and LY3. The conductor pattern PA4 is located on the surface of the dielectric layer LY4. The conductor patterns PA3 and PA4 are connected via a via-hole conductor BA34 that connects the dielectric layers LY3 and LY4.

[0020] The multiple conductor patterns PA have shapes that correspond to each other so as to form a first inductor LA. In the example of FIG. 1, the conductor pattern PA3 has the same shape as the conductor pattern PA1 in a planar perspective view. On the other hand, the conductor pattern PA2 has a different shape from the conductor pattern PA1 in a planar perspective view. And the conductor pattern PA4 has the same shape as the conductor pattern PA2 in a planar perspective view. The conductor patterns PA2 and PA4 may have shapes complementary to the conductor patterns PA1 and PA3.

[0021] In this specification, "shape A existing at one position is equivalent to shape B existing at another position" means "shape B can be superimposed on shape A by translating shape B in any direction without rotating shape B."

[0022] In this specification, any one of the multiple dielectric layers (e.g., dielectric layers LY1 to LY4) in the multilayer substrate 1 will be referred to as the first dielectric layer. Of the multiple conductor patterns constituting the first inductor LA, the conductor pattern located on the surface of the first dielectric layer will be referred to as the first conductor pattern.

[0023] Additionally, in this specification, a conductor pattern that is different from the first conductor pattern and has the same shape as the first conductor pattern in a planar perspective, among the multiple conductor patterns that make up the first inductor LA, is referred to as a second conductor pattern. And, a dielectric layer that is different from the first dielectric layer and on which the second conductor pattern is located, among the multiple dielectric layers, is referred to as a second dielectric layer.

[0024] Therefore, in the multilayer substrate 1, the second conductor pattern is not located on the same surface of the dielectric layer as the first conductor pattern. As can be seen from the example of Fig. 1, in the multilayer substrate 1, the distance between the first dielectric layer and the second dielectric layer in the D3 direction may be 2 pt or more. In other words, the distance between the first conductor pattern and the second conductor pattern in the D3 direction may be 2 pt or more.

[0025] That is, in the D3 direction, at least one dielectric layer different from the first dielectric layer and the second dielectric layer may be located between the first dielectric layer and the second dielectric layer. In other words, in the D3 direction, at least one conductor pattern different from the first conductor pattern and the second conductor pattern may be located between the first conductor pattern and the second conductor pattern.

[0026] The conductor pattern PA1 in Fig. 1 is an example of a first conductor pattern. Therefore, the dielectric layer LY1 is an example of a first dielectric layer. The conductor pattern PA3 is an example of a second conductor pattern corresponding to the conductor pattern PA1 as the first conductor pattern. Therefore, the dielectric layer LY3 is an example of a second dielectric layer corresponding to the dielectric layer LY1 as the first dielectric layer.

[0027] 1, the distance between the dielectric layer LY1 and the dielectric layer LY3 is 2 pt. Therefore, the dielectric layer LY2 is located between the dielectric layer LY1 and the dielectric layer LY3. Therefore, in the D3 direction, the conductive pattern PA2, which has a different shape from the conductive patterns PA1 and PA3, is located between the conductive patterns PA1 and PA3.

[0028] The conductor pattern PA2 in FIG. 1 is another example of a first conductor pattern. Therefore, the dielectric layer LY2 is another example of a first dielectric layer. The conductor pattern PA4 is an example of a second conductor pattern corresponding to the conductor pattern PA2 as the first conductor pattern. Therefore, the dielectric layer LY4 is an example of a second dielectric layer corresponding to the dielectric layer LY2 as the first dielectric layer.

[0029] 1, the distance between the dielectric layer LY2 and the dielectric layer LY4 is 2 pt. Therefore, the dielectric layer LY3 is located between the dielectric layer LY2 and the dielectric layer LY4. Therefore, in the D3 direction, the conductive pattern PA3, which has a different shape from the conductive patterns PA2 and PA4, is located between the conductive patterns PA2 and PA4.

[0030] 2 shows an example of the shape of the first inductor LA in a planar perspective view. In the description of FIG. 2 and the subsequent corresponding figures, unless otherwise specified, the shapes and positional relationships of the first inductor LA and corresponding components in a planar perspective view will be described.

[0031] The first inductor LA has a certain closed area. Therefore, as shown in FIG. 2, a virtual line VL surrounding the first inductor LA can be assumed. The virtual line VL forms a virtual figure identified by the outer edge shape of the first inductor LA in a planar perspective. The virtual figure is a figure that surrounds the outer edge shape of the first inductor LA in a planar perspective and is a figure that is maximally in contact with the main outer edge of the first inductor LA. The shape of the virtual figure may be, for example, a shape that is symmetrical in the D1 direction and the D2 direction. Therefore, for example, the shape of the virtual figure may be a rectangle, a circle, or an ellipse.

[0032] As described above, for example, a rectangular, circular, or elliptical virtual line may be assumed to surround the first inductor LA. The rectangle may be a square or a rectangle. For ease of explanation, FIG. 2 illustrates a virtual line VL that forms a rectangle as a virtual figure.

[0033] The first inductor LA has a recess CV1. As shown in Fig. 2, the recess CV1 is spaced apart from the imaginary line VL in the direction D1. In this way, the recess CV1 may be a portion of the first inductor LA that is defined with reference to the imaginary line VL.

[0034] The first inductor LA in the example of Fig. 2 has a body portion PP1 and a protrusion portion PP2. The body portion PP1 in the example of Fig. 2 has a substantially rectangular shape. In the example of Fig. 2, the area of ​​the body portion PP1 is larger than the area of ​​the protrusion portion PP2. The body portion PP1 may be referred to as a first portion.

[0035] 2, the protrusion PP2 protrudes from the main body PP1 toward the positive side of the D1 direction (to the right in the drawing in the example of FIG. 2). The protrusion PP2 may be referred to as a second portion. Alternatively, the protrusion PP2 may be referred to as a length adjustment portion of the first inductor LA.

[0036] In this specification, the side of the main body portion PP1 that is connected to the protrusion portion PP2 and extends in the D2 direction is referred to as the first side E1. In the example of Fig. 2, the first side E1 is located on the positive side of the main body portion PP1 in the D1 direction.

[0037] In this specification, the side of the protrusion PP2 that is connected to the main body PP1 and extends in the D1 direction is referred to as the second side E2. In the example of Fig. 2, the first side E1 and the second side E2 are connected. In this manner, the first side E1 and the second side E2 may define the recess CV1.

[0038] (Multilayer substrate 1R as a comparative example) Next, a multilayer substrate 1R will be described as a comparative example of the multilayer substrate 1. FIG. 3 is a schematic perspective view showing an example of the configuration of the multilayer substrate 1R. FIG. 3 is a paired view with FIG. 1. The multilayer substrate 1R has a first inductor LAR instead of the first inductor LA. In the example of FIG. 3, four conductor patterns PAR1 to PAR4 are shown as the conductor patterns that make up the first inductor LAR. In this specification, the conductor patterns PAR1 to PAR4 may be collectively referred to as the conductor pattern PAR.

[0039] 3, the conductor pattern PAR1 is located on the surface of the dielectric layer LY1. The conductor pattern PAR2 is located on the surface of the dielectric layer LY2. The conductor patterns PAR1 and PAR2 are connected via a via-hole conductor BAR12 that connects the dielectric layers LY1 and LY2.

[0040] Next, the conductive pattern PAR3 is located on the surface of the dielectric layer LY3. The conductive patterns PAR2 and PAR3 are connected via a via-hole conductor BAR23 that connects the dielectric layer LY2 and the dielectric layer LY3. The conductive pattern PAR4 is located on the surface of the dielectric layer LY4. The conductive patterns PAR3 and PAR4 are connected via a via-hole conductor BAR34 that connects the dielectric layer LY3 and the dielectric layer LY4.

[0041] The plurality of conductor patterns PAR have shapes corresponding to each other so as to form a first inductor LAR. In the example of Fig. 3, the plurality of conductor patterns PAR have rotational symmetry in a planar perspective. Therefore, unlike the multilayer substrate 1, the multilayer substrate 1R does not have conductor patterns having the same shape in a planar perspective.

[0042] 3, the shape of the conductor pattern PAR2 is equivalent to the shape of the conductor pattern PAR1 rotated 90 degrees counterclockwise in planar perspective. Next, the shape of the conductor pattern PAR3 is equivalent to the shape of the conductor pattern PAR2 rotated 90 degrees counterclockwise in planar perspective. And the shape of the conductor pattern PAR4 is equivalent to the shape of the conductor pattern PAR3 rotated 90 degrees counterclockwise in planar perspective.

[0043] FIG. 4 shows an example of the shape of the first inductor LAR in a planar perspective view. FIG. 4 is a diagram paired with FIG. 2. Unlike the first inductor LA, the first inductor LAR in the example of FIG. 4 does not have a recess. In other words, unlike the first inductor LA, the first inductor LAR does not have a protrusion. The first inductor LAR in the example of FIG. 4 has only a rectangular main body.

[0044] (Example of the positional relationship between the first inductor and the second inductor in the multilayer substrate 1R) FIG. 5 shows an example of the positional relationship between the first inductor LAR and the second inductor LB in a multilayer substrate 1R in a planar perspective view. In the first embodiment, a case where the second inductor LB does not have a recess is illustrated. Therefore, the second inductor LB in the first embodiment does not have a protrusion. The second inductor LB in the first embodiment has only a rectangular main body. As can be understood from this, the second inductor LB can be formed, for example, according to the configuration example of the first inductor LAR in FIG. 3 described above.

[0045] In the example of Fig. 5, the first inductor LAR and the second inductor LB are spaced apart by a distance d0 in the direction D1. As described above, neither the first inductor LAR nor the second inductor LB has a recess. Therefore, in the example of Fig. 5, in the range where the first inductor LAR and the second inductor LB overlap as viewed from the direction D1, d0 has a constant value regardless of the position in the direction D2.

[0046] (Example of Positional Relationship Between First Inductor and Second Inductor in Multilayer Substrate 1) Fig. 6 shows an example of the positional relationship between the first inductor LA and the second inductor LB in a multilayer substrate 1 in a planar perspective view. Fig. 6 is a diagram paired with Fig. 5. In the example of Fig. 6, unlike the example of Fig. 5, the first inductor LA has a recess CV1. Due to the presence of the recess CV1, it is easier to separate the first inductor from the second inductor in the D1 direction in the multilayer substrate 1 compared to the multilayer substrate 1R.

[0047] 6, distance d1 represents the maximum distance between recess CV1 and second inductor LB in the D1 direction within the range in which recess CV1 extends in the D2 direction. Meanwhile, distance d2 represents the maximum distance between recess CV1 and virtual line VL in the D1 direction within the same range. d1 may be referred to as the first distance, and d2 may be referred to as the second distance. As shown in FIG. 6, in multilayer substrate 1, d1 > d2.

[0048] (Effects of the first embodiment) As described above, the presence of the recess CV1 makes the first distance greater than the second distance in the multilayer substrate 1. As a result, in the first embodiment, the first inductor can generally be spaced further away from the second inductor in the D1 direction than in the comparative example.

[0049] Therefore, according to the first embodiment, the risk of an unintended increase in magnetic coupling between the first inductor and the second inductor can be reduced compared to the comparative example. As a result, according to the first embodiment, the electrical characteristics of the inductors (e.g., the first inductor and the second inductor) in the multilayer substrate can be made more stable compared to the comparative example.

[0050] Additionally, as described above, in the multilayer substrate 1, the distance between the first dielectric layer and the second dielectric layer in the D3 direction can be set to 2 pt or more. This can reduce the risk of an unintended increase in magnetic coupling between the first conductor pattern located on the surface of the first dielectric layer and the second conductor pattern located on the surface of the second dielectric layer. Therefore, according to the first embodiment, the electrical characteristics of the first inductor can be further stabilized.

[0051] In the first embodiment, the larger d1 is set, the more effectively the risk of an unintended increase in magnetic coupling between the first inductor and the second inductor can be reduced. Therefore, for example, d1 may be set to be larger than the line width of a predetermined conductor pattern constituting the first inductor in a planar perspective view. As an example, d1 may be set to be larger than the line width of the first conductor pattern in a planar perspective view.

[0052] [Embodiment 2] In the first embodiment, the second inductor LB does not have a recess. However, the second inductor according to one aspect of the present disclosure may also be formed according to the configuration example of the first inductor LA in FIG. 1 described above. That is, the second inductor may also have a recess. In the second embodiment, a second inductor having a recess will be described.

[0053] FIG. 7 is a schematic perspective view showing an example of the configuration of the multilayer substrate 2 of the second embodiment. The multilayer substrate 2 has a second inductor LB2 instead of the second inductor LB. FIG. 7 roughly corresponds to FIG. 1. Of the components of the multilayer substrate 2, FIG. 7 illustrates only those components related to the second inductor LB2, and does not illustrate other components. Therefore, unlike FIG. 1, FIG. 7 does not illustrate the first inductor LA. Of the multiple conductor patterns, FIG. 7 illustrates only the conductor pattern that constitutes the second inductor LB2.

[0054] 7, four conductor patterns PB1 to PB4 are shown as examples of the conductor patterns that make up the second inductor LB2. In this specification, the conductor patterns PB1 to PB4 may be collectively referred to as the conductor pattern PA. As will be described later, the conductor pattern PB forms the second body portion PP3 and the second protrusion portion PP4 of the second inductor LB2 in a planar perspective view (see FIG. 8).

[0055] 7, the conductor pattern PB1 is located on the surface of the dielectric layer LY1. The conductor pattern PB2 is located on the surface of the dielectric layer LY2. The conductor patterns PB1 and PAB are connected via a via-hole conductor BB12 that connects the dielectric layers LY1 and LY2.

[0056] Next, conductor pattern PB3 is located on the surface of dielectric layer LY3. Conductive patterns PB2 and PB3 are connected via a via-hole conductor BB23 that connects dielectric layer LY2 and dielectric layer LY3. Conductive pattern PB4 is located on the surface of dielectric layer LY4. Conductive patterns PB3 and PB4 are connected via a via-hole conductor BB34 that connects dielectric layer LY3 and dielectric layer LY4.

[0057] The multiple conductor patterns PB have shapes corresponding to each other so as to form a second inductor LB2. In the example of Fig. 7, the conductor pattern PB3 has the same shape as the conductor pattern PB1 in a planar perspective view. On the other hand, the conductor pattern PB2 has a different shape from the conductor pattern PB1 in a planar perspective view. And the conductor pattern PB4 has the same shape as the conductor pattern PB2 in a planar perspective view. The conductor patterns PB2 and PB4 may have shapes complementary to the conductor patterns PB1 and PB3.

[0058] In the example of the second embodiment, any one of the plurality of dielectric layers (e.g., dielectric layers LY1 to LY4) in the multilayer substrate 2 is referred to as the third dielectric layer. The third dielectric layer may be the same dielectric layer as the first dielectric layer described above, or may be a different dielectric layer. Of the plurality of conductor patterns constituting the second inductor LB2, the conductor pattern located on the surface of the third dielectric layer is referred to as the third conductor pattern.

[0059] Additionally, in this specification, a conductor pattern that is different from the third conductor pattern and has the same shape as the third conductor pattern in a planar perspective, among the multiple conductor patterns that make up the second inductor LB2, is referred to as a fourth conductor pattern. Furthermore, a dielectric layer that is different from the third dielectric layer and on which the fourth conductor pattern is located, among the multiple dielectric layers, is referred to as a fourth dielectric layer. The fourth dielectric layer may be the same dielectric layer as the second dielectric layer described above, or may be a different dielectric layer.

[0060] Therefore, in the multilayer substrate 2, the fourth conductor pattern is not located on the same surface of the dielectric layer as the third conductor pattern. As can be seen from the example of Fig. 7, in the multilayer substrate 2, the distance between the third dielectric layer and the fourth dielectric layer in the D3 direction may be 2 pt or more. In other words, the distance between the third conductor pattern and the fourth conductor pattern in the D3 direction may be 2 pt or more.

[0061] That is, at least one dielectric layer different from the third and fourth dielectric layers may be located between the third and fourth dielectric layers in the D3 direction. In other words, at least one conductor pattern different from the third and fourth conductor patterns may be located between the third and fourth conductor patterns in the D3 direction.

[0062] The conductor pattern PB1 in Fig. 7 is an example of a third conductor pattern. Therefore, the dielectric layer LY1 is an example of a third dielectric layer. The conductor pattern PB3 is an example of a fourth conductor pattern corresponding to the conductor pattern PB1 as the third conductor pattern. Therefore, the dielectric layer LY3 is an example of a fourth dielectric layer corresponding to the dielectric layer LY1 as the third dielectric layer.

[0063] 7, as in the example of Fig. 1, the dielectric layer LY2 is located between the dielectric layer LY1 and the dielectric layer LY3. Therefore, in the D3 direction, the conductor pattern PB2, which has a different shape from the conductor patterns PB1 and PB3, is located between the conductor patterns PB1 and PB3.

[0064] The conductor pattern PB2 in Fig. 7 is another example of a third conductor pattern. Therefore, the dielectric layer LY2 is another example of a third dielectric layer. The conductor pattern PB4 is an example of a fourth conductor pattern corresponding to the conductor pattern PB2 as the third conductor pattern. Therefore, the dielectric layer LY4 is an example of a fourth dielectric layer corresponding to the dielectric layer LY2 as the third dielectric layer.

[0065] In the example of Fig. 7, as in the example of Fig. 1, the dielectric layer LY3 is located between the dielectric layer LY2 and the dielectric layer LY4. Therefore, in the D3 direction, the conductor pattern PB3, which has a shape different from the conductor patterns PB2 and PB4, is located between the conductor patterns PB2 and PB4.

[0066] Fig. 8 shows an example of the shape of the second inductor LB2 in a planar perspective view. Fig. 8 roughly corresponds to Fig. 2. In the second embodiment, the second inductor LB2 has a shape that forms a pair with the first inductor LA. In the second embodiment, the second inductor LB2 has a shape that is inverted in the D2 direction from the first inductor LA in a planar perspective view.

[0067] 8 shows a second virtual line VL2 surrounding the second inductor LB2. In comparison with the second virtual line VL2, the above-mentioned virtual line VL may be referred to as a first virtual line. As is clear from the description of the first embodiment, the second virtual line VL2 surrounding the second inductor LB may be rectangular, circular, or elliptical. For clarity of description, FIG. 8 also shows an example of the second virtual line VL2 forming a rectangle as a virtual figure.

[0068] The second inductor LB2 has a second recess CV2. In terms of comparison with the second recess CV2, the recess CV1 described above may be referred to as a first recess. As shown in FIG. 8, the second recess CV2 is spaced apart from the second imaginary line VL2 in the direction D1. In this way, the second recess CV2 may be a portion of the second inductor LB2 that is defined with reference to the second imaginary line VL2.

[0069] 8 has a second body portion PP3 and a second protrusion portion PP4. In terms of comparison with the second body portion PP3 and the second protrusion portion PP4, the above-mentioned body portion PP1 and protrusion portion PP2 may be referred to as a first body portion and a first protrusion portion, respectively.

[0070] In the example of FIG. 8, the second body portion PP3 has a substantially rectangular shape. In the example of FIG. 8, the area of ​​the second body portion PP3 is larger than the area of ​​the second protrusion portion PP4. The second body portion PP3 may be referred to as a third portion. In the example of FIG. 8, the second protrusion portion PP4 protrudes from the second body portion PP3 toward the negative side of the D1 direction (to the left in the example of FIG. 8). The second protrusion portion PP4 may be referred to as a fourth portion. Alternatively, the second protrusion portion PP4 may be referred to as a length adjustment portion of the second inductor LB2.

[0071] In this specification, the side of the second main body portion PP3 that is connected to the second protrusion portion PP4 and extends in the D2 direction is referred to as the third side E3. In the example of Fig. 8, the third side E3 is located on the negative side of the second main body portion PP3 in the D1 direction.

[0072] In this specification, the side of the second protrusion portion PP4 that is connected to the second main body portion PP3 and extends in the D1 direction is referred to as the fourth side E4. In the example of Fig. 8, the third side E3 and the fourth side E4 are connected. In this manner, the third side E3 and the fourth side E4 may define the second recess CV2.

[0073] (Example of Positional Relationship Between First Inductor and Second Inductor in Multilayer Substrate 2) 9 and 10 each show, in a planar perspective view, an example of the positional relationship between the first inductor LA and the second inductor LB2 in the multilayer substrate 2. Fig. 9 illustrates examples of distances related to the first inductor LA, and Fig. 10 illustrates examples of distances related to the second inductor LB2.

[0074] 9 and 10, in the second embodiment, the second inductor LB2 has a second recess CV2, which is different from the example of the first embodiment. Due to the existence of the second recess CV2, it is easier to separate the first inductor from the second inductor in the D1 direction in the multilayer substrate 2 compared to the multilayer substrate 1.

[0075] First, refer to FIG. 9. In FIG. 9, distance d3 represents the minimum distance between the first inductor LA and the second inductor LB2 in the D1 direction within the range where the recess CV1 does not extend in the D2 direction. Distance d3 may be referred to as a third distance. As shown in FIG. 9, in the multilayer substrate 2, d2>d3.

[0076] In this way, outside the virtual line VL1, a part of the second inductor LB2 (e.g., the second protrusion PP4) may be close to the first inductor LA in the direction D1. This is because, if the main body portion PP1 and the second main body portion PP3 are separated by a distance (e.g., d1) greater than d2, there is little risk of an unintended increase in magnetic coupling between the first inductor LA and the second inductor LB2.

[0077] Next, refer to FIG. 10. Distance d4 in FIG. 10 represents the maximum distance between the second recess CV2 and the first inductor LA in the D1 direction within the range in which the second recess CV2 extends in the D2 direction. Distance d5 represents the maximum distance between the second recess CV2 and the second virtual line VL2 in the D1 direction within the same range. d4 may be referred to as the fourth distance, and d5 may be referred to as the fifth distance. d4 in the example of FIG. 10 is equal to d1 in the example of FIG. 9. As shown in FIG. 10, in the multilayer substrate 2, d4>d5.

[0078] (Effects of the second embodiment) As described above, the fourth distance is greater than the fifth distance in the multilayer substrate 2 due to the presence of the second recess CV2. That is, in the second embodiment, the first inductor can generally be spaced further away from the second inductor in the D1 direction than in the first embodiment.

[0079] Therefore, according to the second embodiment, it is possible to more effectively reduce the risk of an unintended increase in magnetic coupling between the first inductor and the second inductor than in the first embodiment. According to the second embodiment, it is possible to further stabilize the electrical characteristics of both the first inductor and the second inductor.

[0080] As can be understood from the description of the first embodiment, d4 in the second embodiment may be set to be larger than the line width of the predetermined conductor pattern constituting the second inductor in a planar perspective view. As an example, d4 may be set to be larger than the line width of the third conductor pattern in a planar perspective view.

[0081] [Embodiment 3] 11 shows an example configuration of a filter module 100 according to a third embodiment. The filter module 100 may include a multilayer substrate according to an aspect of the present disclosure. Accordingly, the filter module 100 may include a first inductor and a second inductor according to an aspect of the present disclosure.

[0082] 11 illustrates a configuration in which the filter module 100 includes a first inductor LA and a second inductor LB. That is, the filter module 100 of FIG. 11 is an example of a filter module including a multilayer substrate 1. In FIG. 11, a duplexer is illustrated as the filter module 100.

[0083] 11, the filter module 100 includes a first filter FL1 and a second filter FL2. The second filter FL2 is a different filter from the first filter FL1. For example, the second filter FL2 has a different frequency terminal from the first filter FL1. Therefore, the circuit configuration of the second filter FL2 in the example of FIG. 11 is different from the circuit configuration of the first filter FL1.

[0084] In the example of Fig. 11, the first terminal T1 is a terminal dedicated to the first filter FL1, and the second terminal T2 is a terminal dedicated to the second filter FL2. Therefore, the second terminal T2 is a terminal different from the first terminal T1. The common terminal TCOM is a terminal different from the first terminal T1 and the second terminal T2. In the example of Fig. 11, the common terminal TCOM is a terminal common to the first filter FL1 and the second filter FL2.

[0085] 11, the first filter FL1 is connected to the common terminal TCOM and the first terminal T1, while the second filter FL2 is connected to the common terminal TCOM and the second terminal T2. In the example of FIG. 11, the first filter FL1 has a first inductor LA, while the second filter FL2 has a second inductor LB.

[0086] (Filter module 100R as a comparative example) Next, a filter module 100R will be described as a comparative example to the filter module 100. Fig. 12 shows an example of the configuration of the filter module 100R. Fig. 12 is a paired view with Fig. 11.

[0087] A filter module 100R in Fig. 12 is an example of a filter module including a multilayer substrate 1R as a comparative example. As shown in Fig. 12, the filter module 100R includes a first filter FL1R instead of the first filter FL1. The first filter FL1R includes a first inductor LAR instead of the first inductor LA.

[0088] (Effects of the third embodiment) As described above, a multilayer substrate according to one embodiment of the present disclosure (e.g., multilayer substrate 1) can reduce the risk of an unintended increase in magnetic coupling between the first inductor and the second inductor compared to the comparative example multilayer substrate 1R.

[0089] As a result, a filter module (e.g., filter module 100) according to one embodiment of the present disclosure can reduce the risk of degradation of the isolation characteristics between (i) the first terminal T1 connected only to the first filter and (ii) the second terminal T2 connected only to the second filter, compared to the comparative example filter module 100R.

[0090] Furthermore, as described above, the multilayer substrate according to one aspect of the present disclosure can stabilize the electrical characteristics of each inductor in the multilayer substrate compared to the comparative example multilayer substrate 1R. As a result, in addition, the filter module according to one aspect of the present disclosure can also reduce the variation in the amount of pass attenuation between (i) the common terminal TC connected to the first filter and the second filter, and (ii) the second terminal T2 connected only to the second filter, compared to, for example, the comparative example filter module 100R.

[0091] As an example, the above-mentioned variation was ±0.6 dB in filter module 100R of Fig. 12. On the other hand, the variation was ±0.3 dB in filter module 100 of Fig. 11. As described above, a filter module according to one aspect of the present disclosure can achieve a filter module with more stable electrical characteristics than conventional filter modules.

[0092] [Embodiment 4] FIG. 13 illustrates an exemplary configuration of a communication device 900 according to the fourth embodiment. The communication device 900 performs wireless communication using radio waves. The communication device 900 may include a filter module (e.g., filter module 100) according to an aspect of the present disclosure. The filter module 100 in the example of FIG. 13 includes a transmit filter 109 and a receive filter 111. As an example, the transmit filter 109 may be a first filter FL1, and the receive filter 111 may be a second filter FL2.

[0093] In the communication device 900, a transmission information signal TIS containing information to be transmitted may be modulated and frequency-raised (converted into a high-frequency signal having a carrier frequency) by an RF-IC (Radio Frequency-Integrated Circuit) 153, and converted into a transmission signal TS. A bandpass filter 155 may remove unwanted components from the TS outside the transmission passband. Next, the TS after removing the unwanted components may be amplified by an amplifier 157 and input to the transmission filter 109.

[0094] The transmit filter 109 may remove unnecessary components outside the transmission passband from the input transmit signal TS. The transmit filter 109 may output the TS after removing the unnecessary components to the antenna 159 via an antenna terminal. As an example, the antenna terminal may be the above-mentioned common terminal TCOM. The antenna 159 may convert the TS, which is an electrical signal input thereto, into radio waves as a wireless signal and transmit the radio waves to the outside of the communication device 900.

[0095] Furthermore, the antenna 159 may convert the received external radio waves into a received signal RS, which is an electrical signal, and input the RS to the receiving filter 111 via the antenna terminal. The receiving filter 111 may remove unwanted components outside the receiving passband from the input RS. The receiving filter 111 may output the received signal RS after the unwanted components have been removed to the amplifier 161. The output RS may be amplified by the amplifier 161. The bandpass filter 163 may remove unwanted components outside the receiving passband from the amplified RS. The RS after the unwanted components have been removed may be frequency-downshifted and demodulated by the RF-IC 153, and converted into a received information signal RIS.

[0096] The TIS and RIS may be low-frequency signals (baseband signals) containing appropriate information. For example, the TIS and RIS may be analog audio signals or digitized audio signals. The passband of the wireless signals may be set appropriately, for example, as long as they comply with any standard.

[0097] 〔summary〕 A multilayer substrate according to a first aspect of the present disclosure has a first inductor and a second inductor each composed of a plurality of dielectric layers stacked in the thickness direction of the multilayer substrate and a plurality of conductor patterns located on the surface of each of the dielectric layers, and when viewed from a plane perspective in the thickness direction, when a rectangular, circular, or elliptical imaginary line surrounding the first inductor is imagined, the first inductor has a recess spaced from the imaginary line in the first direction, and a first distance, which is the maximum value of the distance between the recess and the second inductor in the first direction within the range in which the recess extends in a second direction intersecting the first direction, is greater than a second distance, which is the maximum value of the distance between the recess and the imaginary line in the first direction within the range in which the recess extends in the second direction.

[0098] In a multilayer substrate according to aspect 2 of the present disclosure, in aspect 1, the second distance, when viewed from above, may be greater than a third distance, which is the minimum distance between the first inductor and the second inductor in the first direction in the range where the recess does not extend in the second direction.

[0099] In a multilayer substrate according to aspect 3 of the present disclosure, in aspect 1 or 2, in the planar perspective view, the first inductor may have a main body portion and a protrusion portion protruding from the main body portion toward the positive side of the first direction, and a first side of the main body portion may be connected to a second side of the protrusion portion, and the recess may be defined by the first side extending in the second direction and the second side extending in the first direction.

[0100] A multilayer substrate according to aspect 4 of the present disclosure, in any one of aspects 1 to 3, may have, as the conductor patterns constituting the first inductor, a first conductor pattern located on the surface of a first dielectric layer among the plurality of dielectric layers, and a second conductor pattern located on the surface of a second dielectric layer among the plurality of dielectric layers that is different from the first dielectric layer, wherein, in the planar perspective view, the second conductor pattern may have a shape identical to that of the first conductor pattern, and at least one dielectric layer different from the first dielectric layer and the second dielectric layer may be located between the first dielectric layer and the second dielectric layer in the thickness direction.

[0101] In a multilayer board according to a fifth aspect of the present disclosure, in the fourth aspect, the first distance may be greater than the line width of the first conductor pattern in the planar perspective view.

[0102] In a multilayer substrate according to aspect 6 of the present disclosure, in any one of aspects 1 to 5, when a rectangular, circular, or elliptical second virtual line is assumed to surround the second inductor in the planar perspective view, the second inductor may have a second recess that is spaced apart from the second virtual line in the first direction, and a fourth distance, which is the maximum value of the distance between the second recess and the first inductor in the first direction within the range in which the second recess extends in the second direction, may be greater than a fifth distance, which is the maximum value of the distance between the second recess and the second virtual line in the first direction within the range in which the second recess extends in the second direction.

[0103] A filter module according to aspect 7 of the present disclosure may include a multilayer substrate according to any one of aspects 1 to 6, and the filter module may include a first filter and a second filter different from the first filter, the first filter may be connected to a common terminal between the first filter and the second filter and a first terminal, the second filter may be connected to the common terminal and a second terminal different from the first terminal, the first filter may include the first inductor, and the second filter may include the second inductor.

[0104] A communication device according to an eighth aspect of the present disclosure may include the filter module according to the seventh aspect.

[0105] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0106] 1,2 Multilayer board VL1 Virtual Line VL2 Second virtual line CV1 recess CV2 2nd recess LA First inductor LB: Second inductor (second inductor without second recess) LB2: Second inductor (second inductor having a second recess) PP1 Main body PP2 protrusion E1 First side E2 Second edge d1 First distance d2 2nd distance PP3 Second main body part PP4 2nd protrusion E3 Third side E4 Fourth side d3 Third distance d4 Fourth distance d5 5th distance LY1 Dielectric layer (an example of the first dielectric layer) LY2 Dielectric layer (an example of a dielectric layer different from the first dielectric layer and the second dielectric layer) LY3 Dielectric layer (an example of the second dielectric layer) PA1 Conductive pattern (example of the first conductive pattern) PA3 conductor pattern (example of second conductor pattern) 100 Filter Module FL1 First filter FL2 Second filter T1 Terminal 1 T2 Terminal 2 TCOM common terminal 900 Communication Equipment

Claims

1. A multilayer substrate, a plurality of dielectric layers stacked in a thickness direction of the multilayer substrate; a first inductor and a second inductor each formed of a plurality of conductor patterns located on the surface of each of the plurality of dielectric layers; In plan view from the thickness direction, When a virtual line of a rectangle, a circle, or an ellipse surrounding the first inductor is assumed, the first inductor has a recess spaced apart from the imaginary line in a first direction; A multilayer substrate, wherein a first distance, which is the maximum value of the distance between the recess and the second inductor in a second direction intersecting the first direction, in a range in which the recess extends in the second direction, is greater than a second distance, which is the maximum value of the distance between the recess and the virtual line in the first direction, in the range in which the recess extends in the second direction.

2. In the planar perspective, 2. The multilayer substrate of claim 1, wherein the second distance is greater than a third distance, which is the minimum value of the distance between the first inductor and the second inductor in the first direction in the range where the recess does not extend in the second direction.

3. In the planar perspective view, the first inductor is a main body; a protrusion protruding from the main body portion toward a positive side in the first direction, a first side of the main body portion is connected to a second side of the protrusion portion; The multilayer substrate according to claim 1 , wherein the recess is defined by the first side extending in the second direction and the second side extending in the first direction.

4. The multilayer substrate has the conductor pattern constituting the first inductor, a first conductor pattern located on a surface of a first dielectric layer among the plurality of dielectric layers; a second conductor pattern located on a surface of a second dielectric layer different from the first dielectric layer among the plurality of dielectric layers, In the planar perspective view, the second conductor pattern has a shape equivalent to that of the first conductor pattern, 2. The multilayer substrate according to claim 1, wherein at least one dielectric layer different from the first dielectric layer and the second dielectric layer is located between the first dielectric layer and the second dielectric layer in the thickness direction.

5. The multilayer board according to claim 4 , wherein the first distance is greater than a line width of the first conductor pattern in the planar perspective view.

6. In the planar perspective, When a second imaginary line having a rectangular, circular, or elliptical shape is assumed to surround the second inductor, the second inductor has a second recess spaced apart from the second imaginary line in the first direction; 2. The multilayer substrate of claim 1, wherein a fourth distance, which is the maximum value of the distance between the second recess and the first inductor in the first direction in the range in which the second recess extends in the second direction, is greater than a fifth distance, which is the maximum value of the distance between the second recess and the second virtual line in the first direction in the range in which the second recess extends in the second direction.

7. A filter module having the multilayer substrate according to claim 1, The filter module comprises: A first filter; a second filter different from the first filter, the first filter is connected to a common terminal between the first filter and the second filter and to a first terminal; the second filter is connected to the common terminal and a second terminal different from the first terminal; the first filter includes the first inductor, The second filter includes the second inductor.

8. A communication device comprising the filter module of claim 7.

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