Multilayer ceramic capacitor and circuit board

Abstract

To provide a thin multilayer ceramic capacitor with a suppressed amount of static electricity generated during handling.SOLUTION: A multilayer ceramic capacitor 100 includes: a cuboid element body 10 having a stack 20 in which ceramic layers 2 and internal electrodes 22 are alternately stacked, a protective portion 30 covering a surface of the stack, and a plurality of via conductors 23a, 23b arranged so as to pass through the ceramic layers in the stacking direction of the stack, electrically connected to the internal electrodes, and having one end portion reaching the surface of the protective portion while the other end portion is covered by the protective portion; and a plurality of terminal electrodes 40a, 40b that are arranged on at least a mounting face 11, which is a face facing a circuit board when the multilayer ceramic capacitor is mounted on the circuit board, among faces forming the surfaces of the element body, and that are connected electrically to the via conductors, respectively. An electrode is not arranged on the opposite face 12, which is the face opposing the mounting face, among the faces that form the surfaces of the element body, and a recess 121 is provided at a position where the side of an end portion of each via conductor covered by the protective portion is projected in the stacking direction of the stack.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a circuit board. [Background technology]

[0002] A wide variety of ceramic electronic components are used in high-frequency communication systems, such as mobile phones. These ceramic electronic components are required to be smaller and thinner, and efforts are being made to make them smaller and thinner in multilayer ceramic capacitors as well.

[0003] Patent Document 1 discloses a thin, break-resistant multilayer ceramic capacitor in which via-hole electrodes that electrically connect internal electrode layers to each other and between internal electrode layers and terminal electrodes have voids formed therein. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-72263 Summary of the Invention [Problem to be solved by the invention]

[0005] The multilayer ceramic capacitor disclosed in Patent Document 1 has opposing upper and lower surfaces, with terminal electrodes formed only on the upper surface. In a multilayer ceramic capacitor with this structure, the lower surface, where no terminal electrodes are formed, is flat across its entire surface because there are no protrusions due to external electrodes. Therefore, when handling singulated capacitor chips during the manufacturing process, if the lower surface comes into contact with manufacturing equipment, jigs, other capacitor chips, etc., the contact area increases, resulting in an increase in the amount of static electricity. This increases the likelihood of transport problems due to sticking, resulting in reduced manufacturing yields. Furthermore, the increase in static electricity due to the flat shape of the lower surface also occurs when the cover tape is peeled off from the carrier tape containing the capacitors. This increase in static electricity also causes capacitor chips to stick to the peeled cover tape, resulting in reduced assembly yields.

[0006] The present invention has been made to solve the above problems, and has an object to provide a thin multilayer ceramic capacitor that reduces the amount of static electricity generated during handling, and a circuit board on which the multilayer ceramic capacitor is mounted. [Means for solving the problem]

[0007] The inventors conducted various studies to solve the above-mentioned problems and found that the above-mentioned object can be achieved by providing a recess on the bottom surface, i.e., the surface on which no terminal electrodes are formed, in a multilayer ceramic capacitor in which internal electrodes are electrically connected to each other through via conductors, at a position corresponding to the via conductor, thereby completing the present invention.

[0008] That is, a first aspect of the present invention for solving the above problem is a multilayer ceramic capacitor comprising: a laminate in which ceramic layers and internal electrodes primarily composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a rectangular parallelepiped element body having a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, electrically connected to the internal electrodes, one end of which reaches the surface of the protective portion while the other end is covered by the protective portion; and a plurality of terminal electrodes arranged at least on a mounting surface that faces a circuit board when mounted on the circuit board, among each of the surfaces forming the surface of the element body, and electrically connected to the via conductors, wherein an opposing surface that faces the mounting surface among each of the surfaces forming the surface of the element body has no electrode arranged thereon, and wherein the opposing surface has a recess at a position where the side of the via conductor that is covered by the protective portion is projected in the stacking direction of the laminate.

[0009] A second aspect of the present invention for solving the above problem is a circuit board on which the multilayer ceramic capacitor according to the first aspect is mounted. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a thin multilayer ceramic capacitor that reduces the amount of static electricity generated during handling, and a circuit board on which the multilayer ceramic capacitor is mounted. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 2] 2 is a cross-sectional view taken along line AA (LT cross-sectional view) in FIG. 1. [Figure 3] 10A and 10B are diagrams for explaining a method for determining whether or not the opposing surfaces of a multilayer ceramic capacitor have a recess at a position where the end of a via conductor that is covered with a protective portion is projected in the stacking direction of the laminate, and a method for determining the depth of the center and peripheral portions of the recess. [Figure 4]FIG. 4 is a schematic view (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 5] FIG. 10 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] The configuration and effects of the present invention will be described below, along with the technical concept, with reference to the drawings. However, the mechanism of action includes assumptions, and the correctness of such assumptions does not limit the present invention.

[0013] [Multilayer ceramic capacitors] First Embodiment 1 and 2 show an embodiment of a multilayer ceramic capacitor according to a first aspect of the present invention as a first embodiment. Note that FIG. 1 is shown inverted in the height direction (T-axis direction) compared to FIG. 2 so that recesses formed on opposing surfaces, which will be described later, can be more clearly seen. The multilayer ceramic capacitor 100 according to the first embodiment has a rectangular parallelepiped shape and includes a pair of faces perpendicular to three mutually orthogonal axes, namely, the lengthwise L-axis, the widthwise W-axis, and the heightwise T-axis. The rectangular parallelepiped is not limited to a mathematically defined rectangular parallelepiped, and may have any shape that is recognized as a rectangular parallelepiped when observed as a whole. Therefore, a rectangular parallelepiped in the present disclosure also includes a capacitor with rounded edges and corners, a capacitor with curved edges, and a capacitor with small curved surfaces. The length (L), width (W), and height (T) dimensions of the ceramic capacitor 100 can each independently take any value.

[0014] The dimensions of the multilayer ceramic capacitor 100 are, for example, an L-direction dimension of 200 μm to 2000 μm, a W-direction dimension of 100 μm to 2000 μm, and a T-direction dimension of 30 μm to 220 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.3 to 1.0. It is preferable that the L-direction dimension be 400 μm to 1200 μm, the W-direction dimension be 400 μm to 1200 μm, and the T-direction dimension be 40 μm to 150 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.4 to 1.0. It is more preferable that the T-direction dimension be 100 μm or less, as this is less subject to design constraints on the circuit board on which it is mounted.

[0015] 2 (LT cross section), the multilayer ceramic capacitor 100 according to the first embodiment includes a laminate 20 in which ceramic layers 21 made of ceramic and internal electrodes 22 mainly composed of metal are alternately stacked in the T direction, and an element body 10 having a protective part 30 covering the surface of the laminate 20. The internal electrodes 22 include internal electrodes 22a of one polarity that are electrically connected to each other, and internal electrodes 22b of a polarity different from that of the internal electrodes 22a that are electrically connected to each other.

[0016] A protective portion 30 is arranged on the surface of the element body 10, covering the surface of the laminate 20. The protective portion 30 includes a cover portion 31 arranged on a plane perpendicular to the T direction, and margin portions 32 arranged on a plane perpendicular to the W direction and a plane perpendicular to the L direction, respectively.

[0017] The element body 10 has a plurality of via conductors 23 that are disposed so as to penetrate the ceramic layers 21 in the stacking direction of the laminate 20 and are electrically connected to the internal electrodes 22, with one end reaching the surface of the protective portion 30 (cover portion 31) and the other end being covered by the protective portion 30 (cover portion 31). The via conductors 23 include a via conductor 23a electrically connected to the internal electrode 22a and a via conductor 23b electrically connected to the internal electrode 22b. Note that although the multilayer ceramic capacitor 100 shown in FIGS. 1 and 2 includes two via conductors 23, the number of via conductors in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0018] The multilayer ceramic capacitor 100 according to the first embodiment is arranged at least on a mounting surface 11, which is the surface that faces the circuit board when mounted on the circuit board, among the surfaces that form the surface of the element body 10, and includes a plurality of terminal electrodes 40 electrically connected to via conductors 23 (23a, 23b). The terminal electrodes 40 include a terminal electrode 40a electrically connected to the via conductor 23a and a terminal electrode 40b electrically connected to the via conductor 23b. Note that although the multilayer ceramic capacitor 100 shown in FIGS. 1 and 2 includes two terminal electrodes 40, the number of terminal electrodes in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0019] On the other hand, among the surfaces forming the surface of the element body 10, no electrodes are arranged on an opposing surface 12, which is the surface facing the mounting surface 11. The opposing surface 12 has a recess 121 at a position where the end of the via conductor 23 (23a, 23b) that is covered by the protective portion 30 (cover portion 31) is projected in the stacking direction of the laminate 20.

[0020] The thickness of the element body 10, obtained by subtracting the thickness of the terminal electrodes 40 (40a, 40b) from the T-direction dimension of the multilayer ceramic capacitor 100 described above, is, for example, 20 μm to 200 μm, and preferably 30 μm to 180 μm.

[0021] Hereinafter, each component constituting the multilayer ceramic capacitor 100 according to the first embodiment will be described in detail.

[0022] (ceramic layer) The ceramic layer 21 is made of ceramic. The ceramic composition is not particularly limited as long as it forms a dense ceramic layer 21 by co-firing with the internal electrodes 22 described later, and may be appropriately selected depending on the properties required for the multilayer ceramic capacitor. Examples of ceramic compositions include those containing barium titanate (BaTiO3) as the main component, those containing strontium titanate (SrTiO3) as the main component, and those containing BaTiO3 having a perovskite structure. 1-x-y Ca x Sr y Ti 1-z Zr z Examples of such ceramics include those containing O3 as a main component. The ceramic may contain an additive element in addition to the main component. Examples of the additive element include at least one selected from Mo, Nb, Ta, W, Mg, Mn, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), and Co, Ni, Li, B, Na, K, and Si. The additive element may be contained as a simple element or in the form of a compound such as an oxide, nitride, or carbide. The additive element may exist in a solid solution state in the main component, or may form a different phase from the elements constituting the main component or other additive elements.

[0023] (Internal electrode) The internal electrodes 22 (22a, 22b) are primarily composed of a metal. The type of metal is not particularly limited, and nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof can be used. Among these, nickel (Ni) is preferred as the primary element because of its high heat resistance, which allows the firing temperature to be increased when co-firing with the ceramic layer 21 to form a dense ceramic layer 21, and it is relatively inexpensive. Here, the term "primary element" as used herein refers to the element with the highest content expressed in atomic percentage (atomic %).

[0024] The internal electrodes 22 (22a, 22b) may contain, in addition to metal, ceramic particles having the same composition as the ceramic constituting the ceramic layer 21, or a glass component.

[0025] (Protection Department) The protective part 30 has a function of protecting the ceramic layers 21 and the internal electrodes 22. The material of the protective part 30 is not limited as long as it has high electrical insulation and low permeability to deterioration factors such as moisture. From the viewpoints of making shrinkage during firing when manufacturing the multilayer ceramic capacitor 100 uniform and alleviating internal stress within the multilayer ceramic capacitor 100, it is preferable that the main component of the protective part 30 be the same as the ceramic that forms the ceramic layers 21.

[0026] (Via conductor) Like the internal electrodes 22 (22a, 22b), the via conductors 23 (23a, 23b) are primarily composed of metal. Usable metals include those similar to those of the internal electrodes 22 (22a, 22b) described above. The composition of the via conductors may be different from that of the internal electrodes 22 (22a, 22b), but is preferably the same as that of the internal electrodes 22 (22a, 22b). By making the via conductors (23a, 23b) and the internal electrodes 22 (22a, 22b) the same composition, the magnitude of shrinkage caused by firing during manufacturing of the multilayer ceramic capacitor 100 is uniform, suppressing deformation, and the resistivity of the conductive paths of the multilayer ceramic capacitor 100 is uniform, suppressing localized heat generation during use.

[0027] The diameter of the via conductors 23 (23a, 23b) is not particularly limited, but is preferably 5 μm to 100 μm, more preferably 10 μm to 50 μm, from the viewpoint of reducing electrical resistance and suppressing heat generation during circuit operation while ensuring the capacitance of the multilayer ceramic capacitor 100. These preferred diameters are also preferable because they enable the diameter of the recesses 121 formed in the opposing surface 12 to be effective in suppressing charging.

[0028] The via conductors 23 (23a, 23b) preferably have a recess at their end on the opposing surface 12 side in a cross section parallel to the stacking direction of the laminate 20, i.e., at their end on the side covered by the protective portion 30 (cover portion 31). The recess at the end of the via conductors 23 (23a, 23b) on the opposing surface 12 side is formed as a result of the end of the via conductors 23 (23a, 23b) following the deformation of the cover portion-forming green sheet when forming the recess 121 on the opposing surface 12 during the manufacturing process of the multilayer ceramic capacitor 100, which will be described later. Therefore, the presence of a recess at the end of the via conductors 23 (23a, 23b) on the opposing surface 12 side indicates high adhesion between the via conductors 23 (23a, 23b) and the adjacent cover portion 31, ceramic layer 21, and internal electrode 22 (22a, 22b), thereby obtaining a multilayer ceramic capacitor 100 with high mechanical strength.

[0029] (terminal electrode) The material of the terminal electrodes 40 (40a, 40b) is not limited as long as it is conductive, and examples of the material include metals such as nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), alloys containing any of these as a main component, and conductive resins.

[0030] The terminal electrodes 40 (40a, 40b) may have an underlying conductor 41 in contact with the element body 10 and a plated conductor 42 formed on the surface of the underlying conductor 41. The terminal electrodes 40 (40a, 40b) having such a structure can improve adhesion to the element body 10 by the underlying conductor 41, and can improve solder wettability by the plated conductor 42 when mounted on a circuit board.

[0031] Ni is an example of the material of the underlying conductor 41. The thickness of the underlying conductor 41 can be set to 0.1 μm or more and 10 μm or less, and preferably 0.5 μm or more and 5 μm or less.

[0032] The plated conductor 42 may be formed of a single layer or multiple layers. When the plated conductor 42 is formed of multiple layers, the number of layers is preferably two to four. An example of the material and structure of the plated conductor 42 is one formed of Cu, Ni, and Sn in this order. The thickness of the plated conductor 42 can be 1 μm to 20 μm, and preferably 3 μm to 10 μm.

[0033] (recess) The recesses 121 formed on the opposing surface 12 are positioned at positions where the ends of the via conductors 23 (23a, 23b) that are covered with the protective portion 30 (cover portion 31) are projected in the stacking direction of the laminate 20. This reduces the amount of static electricity generated on the opposing surface 12 when the multilayer ceramic capacitor 100 is handled. This is presumably because the presence of the recesses 121 reduces the area of ​​contact with other members or elements. Furthermore, since the via conductors 23 are arranged at appropriate intervals from the end faces of the multilayer ceramic capacitor 100 and other via conductors 23 to prevent short circuits, it is presumed that aligning the formation positions of the recesses 121 on the opposing surface 12 with the via conductors 23 also contributes to suppressing the generation of static electricity. In addition, the presence of the recesses 121 at the projected positions of the ends of the via conductors 23 (23a, 23b) makes it difficult for a force to be applied from the opposing surface 12 side to the mounting surface 11 side of the via conductors 23 (23a, 23b) to push the via conductors 23 (23a, 23b) outward when mounting the multilayer ceramic capacitor 100 on a circuit board, thereby suppressing the occurrence of cracks at the interface between the via conductors 23 (23a, 23b) and the ceramic layer 21 and at the interface between the via conductors 23 (23a, 23b) and the cover portion 31. Furthermore, the recesses 121 formed at the projected positions of the ends of the via conductors 23 (23a, 23b) also indicate the positions of the terminal electrodes 40 (40a, 40b) formed on the mounting surface 11 side. Therefore, when mounting the multilayer ceramic capacitor 100 on a circuit board, the recesses 121 can be used as markers to align the lands with the terminal electrodes 40 (40a, 40b).

[0034] Here, whether or not the opposing surface 12 has a recess 121 at a position where the end of the via conductor 23 (23a, 23b) covered by the protective portion 30 (cover portion 31) is projected in the stacking direction of the laminate 20 is determined by the following procedure. First, the terminal electrode 40 formed on the mounting surface 11 of the multilayer ceramic capacitor 100 is removed to expose the via conductor 23 on the mounting surface 11. Methods for removing the terminal electrode 40 include polishing and acid dissolution. Next, the multilayer ceramic capacitor 100 is cut along a plane that passes near the center of gravity of the via conductor 23 exposed on the mounting surface and is parallel to the stacking direction to obtain an observation sample. This observation sample may also be prepared by polishing a plane perpendicular to the mounting surface to near the center of gravity of the via conductor 23 exposed on the mounting surface. Next, the observation sample is embedded in resin so that the cut surface is exposed, and the cut surface is mirror-polished. Next, the mirror-polished cut surface is observed with an optical microscope or a scanning electron microscope (SEM) to obtain an image in which the opposing surface 12 and the via conductor 23 are in the same field of view, as shown in Fig. 3. Next, in the obtained image, line segments v1 and v2 defining both side surfaces of the via conductor 23 are drawn, and both obtained line segments are extended to the opposing surface 12. Next, the intersection of the line segment v1 and the opposing surface 12 is designated as V1, and the intersection of the line segment v2 and the opposing surface 12 is designated as V2, and the distance d between V1 and V2 is measured. Next, in the image, a line segment c1 is drawn that is parallel to the line segment v1, is located closer to the center of the via conductor 23 than the line segment v1, and is 0.05d away from the line segment v1, and a line segment c2 is drawn that is parallel to the line segment v2, is located closer to the center of the via conductor 23 than the line segment v2, and is 0.05d away from the line segment v2, and the intersection of the line segment c1 and the opposing surface 12 is designated as C1 and C2, respectively. Next, in the image, a line segment b is drawn that overlaps with a region of the opposing surface 12 that is located on the opposite side of point C1 with respect to point V1 and a region that is located on the opposite side of point C2 with respect to point V2. Then, since the area of ​​the opposing surface 12 located between points C1 and C2 is located closer to the via conductor 23 than line b, the opposing surface 12 is determined to have a recess 121 at a position where the side of the end of the via conductor 23 (23a, 23b) covered by the protective portion 30 (cover portion 31) is projected in the stacking direction of the laminate 20.When drawing the line segments v1, v2, and b, if the side surface or opposing surface 12 of the via conductor 23 observed in the image is curved, the curve is linearly approximated to form the line segments.

[0035] The number of recesses 121 formed on the opposing surface 12 is not limited, but in order to enhance the anti-static effect of the opposing surface 12, it is preferable that they are formed in three or more locations, and it is more preferable that they are formed in four or more locations.

[0036] The recess 121 preferably has a circular or elliptical shape when viewed from a direction perpendicular to the opposing surface 12. This suppresses the occurrence of cracks in the opposing surface 12 when stress is applied to the multilayer ceramic capacitor 100. This is presumably because stress is less likely to concentrate at a specific location on the periphery of the recess 121.

[0037] The recess 121 is preferably deeper at the center than at the periphery. This configuration can prevent cracks from occurring at the interface between the via conductor 23 (23a, 23b) and the ceramic layer 21 and at the interface between the via conductor 23 (23a, 23b) and the cover portion 31 when stress is generated near the via conductor 23 (23a, 23b) and the recess 121, for example, when a circuit board on which the multilayer ceramic capacitor 100 is mounted is deformed. This is presumably due to the fact that the contact area between the via conductor 23 (23a, 23b) and the cover portion 31 is larger than when the depth is constant, improving the adhesion between them. In this case, it is preferable for the recess 121 to have a shape in which the amount of protrusion increases from the center toward the periphery, as this significantly prevents the occurrence of cracks. This is presumably due to the fact that the direction of the normal to the surface of the recess 121 varies depending on the position, thereby preventing stress concentration at specific locations.

[0038] The depth of the center of the recess 121 is preferably 0.1 μm or more and 10 μm or less, and more preferably 0.2 μm or more and 1.0 μm or less. When the depth of the center is 0.1 μm or more, the above-mentioned effects of suppressing charging and cracking become significant. On the other hand, when the depth of the center is 10 μm or less, a decrease in the mechanical strength of the multilayer ceramic capacitor 100 is suppressed.

[0039] Here, the depths of the central and peripheral portions of the recess 121 are determined by the following procedure. First, a microscope image is acquired according to the procedure for determining the position of the recess 121 on the opposing surface 12 described above, and line segments v1, v2, points V1, V2, line segments c1, c2, points C1, C2, and line segment b are drawn in the image. Next, as shown in FIG. 3, a perpendicular bisector c of line segment C1C2 is drawn in the image. c Next, construct the line segment c c is parallel to the line segment c c Two line segments c3 and c4 are drawn at a distance of 0.05d from the line segment c1, and their intersections with the opposing surface 12 are designated as C3 and C4, respectively. Next, five points are arbitrarily selected from the area of ​​the opposing surface 12 located between point C3 and point C4, and the distance between each of the points and line segment b is measured. The average of the five measured values ​​is then calculated, and the value obtained by dividing the average by the magnification of the microscope image is designated as the depth of the center of the recess 121. Next, as shown in FIG. 3, a line segment c1 is drawn in the image, which is parallel to line segment c1 and is located deeper than line segment c1. c Line c5 is located to the side of line c1 and is 0.05d away from line c1, and line c5 is parallel to line c2 and is closer to line c2 than line c2. c A line segment c6 is drawn at a distance of 0.05d from line segment c2, and the intersection of line segment c5 and opposing surface 12 is designated as C5, and the intersection of line segment c6 and opposing surface 12 is designated as C6. Next, three points are arbitrarily selected from the area of ​​opposing surface 12 located between points C1 and C5, and three points are arbitrarily selected from the area of ​​opposing surface 12 located between points C2 and C6, and the distance between each of the points and line segment b is measured. The average of the six measured values ​​is then calculated, and the value obtained by dividing the average by the magnification of the microscope image is designated as the depth of the peripheral portion of recess 121.

[0040] <Second embodiment> In another embodiment (second embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, the internal electrodes are drawn out to a surface perpendicular to the mounting surface, and external electrodes are disposed on the surfaces (drawn-out surfaces) to which the internal electrodes are drawn out, and the internal electrodes are also electrically connected via the external electrodes. An example of a multilayer ceramic capacitor 200 according to the second embodiment is shown in FIG. 4. Note that FIG. 4 shows an example in which two opposing surfaces are drawn out as drawn-out surfaces 13, but the number of drawn-out surfaces is not limited to this. Also, FIG. 4 shows an example in which terminal electrodes 40 (40a, 40b) extending to the drawn-out surfaces 13 form external electrodes 50 (50a, 50b), but the external electrodes 50 (50a, 50b) may be formed separately from the terminal electrodes 40 (40a, 40b). In the multilayer ceramic capacitor 200, the current flowing through the internal electrodes 22 (22a, 22b) is divided between the via conductors 23 (23a, 23b) and the external electrodes 50 (50a, 50b), thereby reducing the current flowing through each of the via conductors 23 (23a, 23b) and the external electrodes 50 (50a, 50b). This reduces heat generation during operation.

[0041] <Third embodiment> In another embodiment (third embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, the number of terminal electrodes arranged on the mounting surface is four or more, and each terminal electrode has a polarity opposite to that of the nearest terminal electrode on the mounting surface. An example of a multilayer ceramic capacitor 300 according to the third embodiment is shown in FIG. 5. While FIG. 5 shows an example in which the number of terminal electrodes 40 arranged on the mounting surface 11 is four, the number of terminal electrodes arranged on the mounting surface is not limited to this. The multilayer ceramic capacitor 300 has the same number of via conductors 23 (23a, 23b) as the number of terminal electrodes, or more, and the same number of recesses 121 formed on the opposing surface 12 as the via conductors 23 (23a, 23b). This more effectively suppresses charging on the opposing surface 12. Furthermore, the multilayer ceramic capacitor 300 has the advantage that the currents flowing through the via conductors (not shown) electrically connected to the terminal electrodes 40 (40a, 40b) in the opposite directions between the nearest conductors, thereby canceling out the magnetic fields generated by the currents. This reduces the equivalent series inductance (ESL). The above-mentioned effects are remarkable when the multilayer ceramic capacitor 200 has two pairs of surfaces that are parallel to the stacking direction of the laminate and face each other, and when the spacing between one pair, i.e., the L-direction dimension, is L μm and the spacing between the other pair, i.e., the W-direction dimension, is W μm (where L≧W), and the value of W / L, which is the ratio of W to L, is 0.8 or more and 1 or less, i.e., when the mounting surface 11 has a shape close to a square.

[0042] [Manufacturing method for multilayer ceramic electronic components] The multilayer ceramic capacitor according to the first aspect of the present invention can be manufactured by the procedure described below.

[0043] (A) Preparation of ceramic powder First, ceramic powder is prepared. Commercially available ceramic powders can be used as appropriate. When producing ceramic powder in-house, various raw material powders containing the constituent elements are mixed in a predetermined ratio and pre-fired (calcined). When mixing the various raw material powders in a predetermined ratio, various additives such as the above-mentioned additive elements and sintering aids may be further added, or these various additives may be further added to the powder after calcination.

[0044] (B) Preparation of raw sheets Next, the ceramic powder is mixed with a binder and a dispersion medium to prepare a slurry, and the slurry is formed into a sheet to obtain a green sheet.

[0045] The binder used should be one that can maintain the shape of the green sheet and volatilizes without leaving behind carbon or other residues during the binder removal process prior to firing. Examples of binders that can be used include polyvinyl alcohol, polyvinyl butyral, cellulose, urethane, and vinyl acetate. There are no particular restrictions on the amount of binder used, but since it will be removed in a later process, it is preferable to use as little as possible within the range that achieves the desired formability and shape retention, in order to reduce raw material costs.

[0046] The dispersion medium used is one that does not cause aggregation of the calcined powder and binder and can be easily removed by volatilization or the like after forming into a green sheet, as described below. Examples of the dispersion medium that can be used include water and alcohol-based solvents.

[0047] Components for adjusting the properties of the slurry, such as dispersants, plasticizers, and thickeners, may be added to the slurry.

[0048] The method for mixing the mixed powder with the binder and the dispersion medium is not particularly limited as long as the components are mixed uniformly while preventing the inclusion of impurities. One example is ball mill mixing.

[0049] The prepared slurry can be formed into a sheet to obtain a green sheet by a commonly used method such as a doctor blade method or a die coating method.

[0050] ((C) Formation of internal electrode pattern) Next, an internal electrode pattern containing metal is formed on the green sheet. The internal electrode pattern can be formed by printing or applying an internal electrode paste in a predetermined pattern, or by forming a metal film in a predetermined pattern by vapor deposition or sputtering. The internal electrode pattern is formed with a sufficient margin to ensure electrical insulation with the via conductor patterns that will be formed later and that will not come into contact with the via conductor patterns.

[0051] When forming an internal electrode pattern using an internal electrode paste, the internal electrode paste used is obtained by mixing metal particles and a vehicle in a triple roll mill. The internal electrode paste may contain glass frit and ceramic powder in addition to the above-mentioned components.

[0052] The type and amount of binder and solvent contained in the vehicle used are not limited, and may be selected appropriately taking into consideration the viscosity of the internal electrode paste, ease of handling, compatibility with the green sheet, and the like.

[0053] The internal electrode paste can be printed on the green sheet using, for example, a screen mask on which a predetermined internal electrode pattern is formed. When printing, a space may be left to become a margin when the multilayer ceramic capacitor is completed.

[0054] (D) Preparation of green laminate Next, a predetermined number of green sheets on which the internal electrode patterns have been formed are stacked and the green sheets are pressure-bonded together to obtain a green laminate. The stacking and pressure-bonding can be performed by a conventional method, such as pressing the stacked green sheets together in the stacking direction while heating them, and thermo-compression bonding by the action of a binder.

[0055] During lamination and compression bonding, a green sheet that will become a cover when the multilayer ceramic capacitor is completed may be added to the end portion in the lamination direction. In this case, the green sheet to be added may have the same composition as the green sheet on which the internal electrode pattern is printed, or a different composition. From the viewpoint of making the shrinkage rate during firing uniform, it is preferable that the composition of the green sheet to be added is the same as or similar to the green sheet on which the above-mentioned internal electrode precursor is arranged.

[0056] ((E) Formation of via conductor pattern) Next, holes are formed in the green laminate, and the holes are filled with a conductive paste to form a via conductor pattern. The conductive paste is not filled to the full extent of the holes, but rather, an unfilled portion is left on the side that will become the opposing surface when the multilayer ceramic capacitor is completed. Commonly used methods such as drilling or lasers can be used to form the holes. Lasers are preferred because they can produce a smooth processed surface. Commonly used methods such as syringe injection and printing using a metal mask can be used to fill the holes with the conductive paste. Printing using a metal mask is preferred because it has excellent filling properties for small-diameter holes. The components of the conductive paste can be the same as those of the internal electrode paste described above, and the amount of each component can be determined taking into account the filling properties of the holes.

[0057] ((F) Pressing of raw sheet for forming cover part) Next, a cover-forming green sheet is pressed onto the exposed surface of the green laminate where the conductive paste non-filled portion is exposed. At this time, the cover-forming green sheet located on the conductive paste non-filled portion enters the hole, thereby forming a recess.

[0058] ((G) Formation of terminal electrode pattern) Next, a terminal electrode pattern is formed on the surface opposite to the surface to which the cover-forming green sheet is crimped. The terminal electrode pattern can be formed by printing or applying a terminal electrode paste, or by forming a metal film by vapor deposition or sputtering. The terminal electrode pattern can be formed using a mask with a predetermined pattern, or by forming a paste or metal film on the entire mounting surface of the green laminate and then removing the portions other than the terminal electrode pattern. Face milling and barrel polishing, etc., can be used to remove the portions other than the terminal electrode pattern. When a terminal electrode paste is used to form the terminal electrode pattern, the components can be the same as those of the internal electrode paste described above, and the blending amounts of each component can be determined so as to obtain a uniform pattern with the desired thickness.

[0059] (H) Preparation of pre-fired chips Next, the green laminate is divided into individual pieces to obtain pre-fired chips. For the division, a commonly used means such as a dicing saw or a laser cutting machine can be used. After dividing the green laminate into individual pieces to form surfaces on which the internal electrode precursors are exposed, the surfaces may be coated with a material for forming margins to obtain pre-fired chips.

[0060] (I) Removal of binder Next, the resulting pre-fired chips are heated to volatilize and remove the binder. The heating conditions can be set appropriately taking into account the volatilization temperature and content of the binder. For example, the chips are held in a nitrogen (N2) atmosphere at a temperature of 200 to 500°C for 5 to 20 hours.

[0061] (J) Firing of pre-fired chips Next, the pre-fired chip from which the binder has been removed is heated to a predetermined temperature and fired. When setting the firing conditions, it is preferable to consider the sinterability of the ceramic powder, as well as the heat resistance and oxidation resistance of the metals contained in the internal electrode pattern, via conductor pattern, and terminal electrode pattern. An example of firing conditions is holding the chip at a temperature of 1100°C to 1400°C for 10 minutes to 2 hours in a reducing atmosphere containing a mixture of nitrogen (N2), hydrogen (H2), and water vapor (H2O). After firing, a reoxidation treatment may be performed in which the chip is held at 600°C to 1000°C in a nitrogen (N2) gas atmosphere or a low-oxygen atmosphere.

[0062] The sintered body thus obtained may be used as a multilayer ceramic capacitor as it is, or may be used as a multilayer ceramic capacitor after forming a conductive layer on the surface of the terminal electrode pattern by plating.

[0063] [Circuit board] A circuit board according to a second aspect of the present invention is equipped with the multilayer ceramic capacitor according to the first embodiment. This circuit board can be installed in a small space because the multilayer ceramic capacitor is thin and does not have electrodes on opposing surfaces.

[0064] This specification also discloses the following techniques.

[0065] (Appendix 1) a laminate in which ceramic layers formed of ceramic and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a plurality of via conductors disposed to penetrate the ceramic layers in the stacking direction of the laminate, electrically connected to the internal electrodes, one end of which reaches the surface of the protective portion, and the other end of which is covered by the protective portion; A rectangular parallelepiped element having the following structure: A plurality of terminal electrodes are disposed at least on the mounting surface, which is the surface that faces the circuit board when mounted on the circuit board, among the surfaces that form the surface of the element body, and are electrically connected to the via conductors. Equipped with Among the surfaces forming the surface of the element body, the opposing surface that faces the mounting surface is No electrodes are placed, and The end of the via conductor on the side covered with the protective portion has a recess at a position when projected in the stacking direction of the laminate. Multilayer ceramic capacitor.

[0066] (Appendix 2) The multilayer ceramic capacitor according to (Supplementary Note 1), wherein the recessed portions are present in three or more places.

[0067] (Appendix 3) The multilayer ceramic capacitor according to (Supplementary Note 1) or (Supplementary Note 2), wherein the recess has a circular or elliptical shape when viewed from a direction perpendicular to the opposing surface.

[0068] (Appendix 4) The multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 3), wherein the via conductor has a recess at an end on the opposing surface side in a cross section parallel to the stacking direction of the laminate.

[0069] (Appendix 5) The multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 4), wherein the recessed portion of the opposing surface has a depth greater at the center than at the periphery.

[0070] (Appendix 6) The multilayer ceramic capacitor according to (Appendix 5), wherein the depth of the central portion is 0.1 μm or more and 10 μm or less.

[0071] (Appendix 7) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 6), wherein the dimension in the lamination direction is 100 μm or less.

[0072] (Appendix 8) A circuit board on which the multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 7) is mounted. [Industrial Applicability]

[0073] According to the present invention, it is possible to provide a thin multilayer ceramic capacitor that generates less static electricity during handling. Such a multilayer ceramic capacitor is useful in that it can improve alignment accuracy when mounted on a circuit board and suppress the occurrence of internal cracks, thereby achieving a high yield. [Explanation of symbols]

[0074] 100, 200, 300 Multilayer ceramic capacitors 10 Base 11 Mounting surface 12 Opposite surface 13 Drawer surface 121 recess 20 laminate 21 ceramic layer 22(22a, 22b) Internal electrode 23(23a, 23b) Via conductor 30 Protection Department 31 Cover 32 Margin 40(40a, 40b) terminal electrode 41 Undercoat conductor 42 Plated conductor 50(50a, 50b) External electrode

Claims

1. a laminate in which ceramic layers formed of ceramic and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a plurality of via conductors disposed to penetrate the ceramic layers in the stacking direction of the laminate, electrically connected to the internal electrodes, one end of which reaches the surface of the protective portion, and the other end of which is covered by the protective portion; A rectangular parallelepiped element having the following structure: A plurality of terminal electrodes are disposed at least on the mounting surface, which is the surface that faces the circuit board when mounted on the circuit board, among the surfaces that form the surface of the element body, and are electrically connected to the via conductors. Equipped with Among the surfaces forming the surface of the element body, the opposing surface that faces the mounting surface is No electrodes are placed, and The end of the via conductor on the side covered with the protective portion has a recess at a position when projected in the stacking direction of the laminate. Multilayer ceramic capacitor.

2. The multilayer ceramic capacitor according to claim 1 , wherein the recessed portions are present in three or more places.

3. 2. The multilayer ceramic capacitor according to claim 1, wherein the recess has a circular or elliptical shape when viewed from a direction perpendicular to the opposing surface.

4. 2. The multilayer ceramic capacitor according to claim 1, wherein the via conductor has a recess at an end on the opposing surface side in a cross section parallel to the stacking direction of the laminate.

5. 2. The multilayer ceramic capacitor according to claim 1, wherein the recessed portion of the opposing surface has a depth greater at the center than at the periphery.

6. 6. The multilayer ceramic capacitor according to claim 5, wherein the depth of the central portion is 0.1 μm or more and 10 μm or less.

7. 2. The multilayer ceramic capacitor according to claim 1, wherein the dimension in the lamination direction is 100 μm or less.

8. A circuit board having the multilayer ceramic capacitor according to any one of claims 1 to 7 mounted thereon.

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