Semiconductor storage device manufacturing method

Abstract

To provide a semiconductor storage device manufacturing method capable of easily manufacturing a semiconductor storage device.SOLUTION: A semiconductor storage device manufacturing method of an embodiment includes: forming a laminated film in which a plurality of first layers containing an oxide and a plurality of second layers containing a nitride, each having a greater film thickness than the first layers, are alternately stacked one layer at a time in a first direction; forming an opening penetrating the laminated film and extending in the first direction; and increasing the thickness of each of the plurality of first layers and decreasing the thickness of each of the plurality of second layers by oxidizing the laminated film having the opening.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor memory device. [Background technology]

[0002] Large-capacity nonvolatile memories have been developed, which are capable of low-voltage and low-current operation, high-speed switching, and miniaturization and high integration of memory cells.

[0003] The memory cell array of a large-capacity nonvolatile memory has an array of numerous metal wirings called bit lines and word lines. By applying a voltage to the bit line and word line connected to a cell, data is written to one memory cell corresponding to the bit line and word line. A semiconductor memory device has been proposed in which memory cells are arranged three-dimensionally and equipped with a laminated film in which conductive layers and insulating layers that serve as word lines are alternately stacked. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2010 / 0276743 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the embodiment is to provide a method for manufacturing a semiconductor memory device that allows for easy manufacturing of the semiconductor memory device. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor memory device according to an embodiment includes forming a laminated film in which a plurality of first layers containing an oxide and a plurality of second layers containing a nitride and each having a thickness greater than that of the plurality of first layers are alternately stacked one layer at a time in a first direction, forming openings that penetrate the laminated film and extend in the first direction, and oxidizing the laminated film having the openings, thereby increasing the thickness of each of the plurality of first layers and decreasing the thickness of each of the plurality of second layers. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a block diagram of a semiconductor memory device according to an embodiment; [Figure 2] 1 is an equivalent circuit diagram of a semiconductor memory device according to an embodiment; [Figure 3] 1 is a schematic cross-sectional view of a main part of a semiconductor memory device according to an embodiment; [Figure 4] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 5] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 10A to 10C are schematic cross-sectional views showing a modified example of the method for manufacturing the semiconductor memory device according to the embodiment. [Figure 9] 10A to 10C are schematic cross-sectional views showing a modified example of the method for manufacturing the semiconductor memory device according to the embodiment. [Figure 10] 10A to 10C are schematic cross-sectional views showing a modified example of the method for manufacturing the semiconductor memory device according to the embodiment.

[0008] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same or similar parts are denoted by the same or similar reference numerals.

[0009] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing will be described as "up" and the downward direction of the drawing will be described as "down." In this specification, the concepts of "up" and "down" do not necessarily refer to the direction of gravity.

[0010] (Embodiment) A method for manufacturing a semiconductor memory device according to an embodiment includes forming a laminated film in which a plurality of first layers containing an oxide and a plurality of second layers containing a nitride and each having a thickness greater than that of the plurality of first layers are alternately stacked one layer at a time in a first direction, forming openings that penetrate the laminated film and extend in the first direction, and oxidizing the laminated film having the openings, thereby increasing the thickness of each of the plurality of first layers and decreasing the thickness of each of the plurality of second layers.

[0011] The overall configuration of a semiconductor memory device 100 will be described. The semiconductor memory device 100 according to this embodiment is a NAND flash memory capable of storing data in a nonvolatile manner. Figure 1 is a block diagram of the semiconductor memory device 100 according to this embodiment.

[0012] The semiconductor memory device 100 includes a memory cell array 90, a row decoder 91, a column decoder 98, a sense amplifier 99, an input / output circuit 94, a command register 95, an address register 96, a sequencer (control circuit) 97, and the like.

[0013] The memory cell array 90 includes j blocks BLK0 to BLK(j-1), where j is an integer equal to or greater than 1. Each of the blocks BLK includes a plurality of memory cell transistors. The memory cell transistors include electrically rewritable memory cells. The memory cell array 90 includes a plurality of bit lines, a plurality of word lines, a source line, and the like, for controlling the voltages applied to the memory cell transistors. The specific configuration of the blocks BLK will be described later.

[0014] The row decoder 91 receives a row address from the address register 96 and decodes the row address. The row decoder 91 selects a word line or the like based on the decoded row address. The row decoder 91 then transfers to the memory cell array 90 a plurality of voltages required for write, read, and erase operations.

[0015] The column decoder 98 receives a column address from the address register 96 and decodes the column address, and performs a bit line selection operation based on the decoded column address.

[0016] The sense amplifier 99 detects and amplifies data read from the memory cell transistor to the bit line during a read operation, and transfers write data to the bit line during a write operation.

[0017] The input / output circuit 94 is connected to an external device (host device) via a plurality of input / output lines (DQ lines). The input / output circuit 94 receives a command CMD and an address ADD from the external device. The command CMD received by the input / output circuit 94 is sent to a command register 95. The address ADD received by the input / output circuit 94 is sent to an address register 96. The input / output circuit 94 also transmits and receives data DAT to and from the external device.

[0018] The sequencer 97 receives control signals CNT from an external device. The control signals CNT include a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn. The "n" added to a signal name indicates active low. The sequencer 97 controls the overall operation of the semiconductor memory device 100 based on the command CMD held in the command register 95 and the control signals CNT.

[0019] FIG. 2 is an equivalent circuit diagram of the semiconductor memory device 100 of this embodiment.

[0020] As shown in FIG. 2, the semiconductor memory device 100 includes a plurality of word lines WL, a common source line CSL, a source select gate line SGS, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of memory strings MS.

[0021] The memory string MS has a source select transistor STS, a plurality of memory cell transistors MT, and a drain select transistor STD connected in series between a common source line CSL and a bit line BL.

[0022] The number of word lines WL, the number of bit lines BL, the number of memory strings MS, and the number of drain select gate lines SGD are not limited to those shown in FIG.

[0023] FIG. 3 is a schematic cross-sectional view of a main part of the semiconductor memory device of this embodiment.

[0024] The substrate 11 is, for example, a semiconductor layer containing single crystal silicon, and may be, for example, a semiconductor wafer or an SOI wafer.

[0025] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X and Y directions are defined. The substrate 11 is disposed parallel to the XY plane. The Z direction is an example of a first direction.

[0026] A plurality of first layers 13 containing an oxide and a plurality of conductive layers 6b are alternately stacked one layer at a time in the Z direction on the substrate 11. In this way, a stacked film S2 is provided on the substrate 11. The oxide here is, for example, silicon oxide.

[0027] The memory pillar H1 penetrates the stacked film S2 in the Z direction. A core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage film 4, and an insulating film 5a are provided in the memory pillar H1.

[0028] The core insulating film 1 is provided in the memory pillar H1. The core insulating film 1 includes, for example, silicon oxide.

[0029] The channel semiconductor layer 2 is provided around the core insulating film 1 in the memory pillar H1. The channel semiconductor layer 2 functions as a channel of the memory pillar H1. The channel semiconductor layer 2 is a pillar including a semiconductor material such as polysilicon.

[0030] The tunnel insulating film 3 is provided around the channel semiconductor layer 2. The tunnel insulating film 3 is an insulating film that is insulating but allows current to flow when a predetermined voltage is applied. The tunnel insulating film 3 includes, for example, silicon oxynitride.

[0031] The charge storage film 4 is provided around the tunnel insulating film 3. The charge storage film 4 is a film containing a material capable of storing charges. The charge storage film 4 contains, for example, silicon nitride.

[0032] The insulating film 5a is provided around the charge storage film 4. The insulating film 5a includes, for example, silicon oxide.

[0033] The insulating film 5b, the barrier metal layer 6a, and the conductive layer 6b are provided between the first layers 13 adjacent to each other.

[0034] The insulating film 5b is provided on the lower surface of the first layer 13 adjacent to the upper side, the upper surface of the first layer 13 adjacent to the lower side, and the side surfaces of the insulating film 5a. The insulating film 5b includes, for example, a metal insulating material such as aluminum oxide.

[0035] The barrier metal layer 6a is provided on the lower surface of the upper insulating film 5b, the upper surface of the lower insulating film 5b, and the side surfaces of the insulating film 5b provided on the side surfaces of the insulating film 5a. The barrier metal layer 6a includes, for example, titanium nitride.

[0036] The conductive layer 6b is provided in the barrier metal layer 6a. The conductive layer 6b includes, for example, tungsten (W). The conductive layer 6b corresponds to the word line WL.

[0037] The film thickness L1 of each first layer 13 in the Z direction is, for example, 17 nm. The distance L2 between adjacent first layers 13 in the Z direction is, for example, 22 nm. Note that the film thickness L1 of each first layer 13 in the Z direction and the distance L2 between adjacent first layers 13 in the Z direction are not limited to those described above.

[0038] A memory cell MC is provided in each memory pillar H1 in a portion facing the conductive layer 6b. A plurality of memory cells MC provided in one memory pillar H1 are included in one memory string MS. Each memory cell MC includes a memory cell transistor MT.

[0039] Note that Fig. 3 shows one memory string MS out of the memory strings MS shown in Fig. 2. The semiconductor memory device 100 includes a plurality of memory pillars H1.

[0040] Between the laminated film S2 and the substrate 11, for example, a common source line CSL, a source selection gate line SGS, and a plurality of source selection transistors STS (not shown) are provided.

[0041] Moreover, on the laminated film S2, for example, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of drain select transistors STD (not shown) are provided.

[0042] 4 to 7 are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of this embodiment.

[0043] 4, a common source line CSL, a source select gate line SGS, and a plurality of source select transistors STS (not shown) are formed on a substrate 11. The substrate 11 is placed, for example, on a stage T in a reaction chamber in which a semiconductor memory device is manufactured.

[0044] Next, a plurality of first layers 13 containing oxide and a plurality of second layers 14 containing nitride are alternately stacked one by one in the Z direction by, for example, a CVD (Chemical Vapor Deposition) method. This forms a stacked film S1. Here, the oxide is, for example, silicon oxide. The nitride is, for example, silicon nitride. In FIG. 4, the film thickness L3 of each of the first layers 13 in the Z direction is, for example, 5.6 nm. The film thickness L4 of each of the second layers 14 in the Z direction is, for example, 30.6 nm. Thus, the film thickness L4 of the second layer 14 is thicker than the film thickness L3 of the first layer. Next, openings H2 (through holes) are formed by, for example, a RIE (Reactive Ion Etching) method, penetrating the stacked film S1 in the Z direction and extending in the Z direction (FIG. 4). Here, when forming the openings H2, the temperature of the stage T on which the stacked film S1 is placed is preferably 70° C. or less.

[0045] Next, as shown in Fig. 5, a fifth layer 17 (an example of a third layer) containing a nitride such as silicon nitride is formed on the side surfaces of the first layers 13 and the second layers 14 exposed in the openings H2 by, for example, ALD (Atomic Layer Deposition). The fifth layer 17 has, for example, a cylindrical shape having the openings H2. In Fig. 5, the fifth layer 17 is formed on the side surfaces of the openings H2, but it may also be formed on the bottom surface of the openings H2.

[0046] Next, as shown in FIG. 6, the stacked film S1 having the opening H2 is oxidized. Here, a portion of the second layer 14, including the lower surface of the second layer 14, is oxidized, thereby forming a third layer 15 containing an oxide between the second layer 14 and the first layer 13 adjacent below the second layer 14. Also, a portion of the second layer 14, including the upper surface of the second layer 14, is oxidized, thereby forming a fourth layer 16 containing an oxide between the second layer 14 and the first layer 13 adjacent above the second layer 14. Also, by oxidizing the stacked film S1 having the opening H2, the fifth layer 17 is oxidized, thereby forming a sixth layer 18 (an example of the fourth layer) containing an oxide. (Hereinafter, the oxidation process shown in FIG. 6 may be referred to as "oxidation.")

[0047] As a result, the thickness of each of the plurality of second layers 14 containing nitride is reduced by oxidation.

[0048] Here, by oxidizing the stacked film S1 having the opening H2, a third layer 15 containing an oxide and a fourth layer 16 containing an oxide are formed as described above. If each first layer 13 is considered to include a fourth layer 16 formed below the corresponding first layer 13 and a third layer 15 formed on the corresponding first layer 13, the film thickness of the plurality of first layers 13 containing an oxide can be considered to have increased by the film thickness of the third layer 15 and the fourth layer 16, respectively.

[0049] In Figure 3, each of the first layers 13 in Figure 6, the fourth layer 16 formed below each of the first layers 13, and the third layer 15 formed on each of the first layers 13 are collectively illustrated as the "first layer 13."

[0050] In other words, by oxidizing the stacked film S1 having the opening H2, the portion of the second layer 14 in contact with the first layer 13 is oxidized. As a result, the thicknesses of the first layers 13 containing oxide are increased by the thicknesses of the third layer 15 and the fourth layer 16. Also, the thicknesses of the second layers 14 containing nitride are decreased.

[0051] It should be noted that the process by which the thickness of each of the plurality of first layers 13 increases and the process by which the thickness of each of the plurality of second layers 14 decreases are not limited to those described above.

[0052] Here, the film thickness L5 of the third layer 15 in the Z direction is, for example, 5.7 nm. The film thickness L6 of the fourth layer 16 in the Z direction is, for example, 5.7 nm. The film thickness L7 of the second layer 14 after oxidation in the Z direction is smaller than the film thickness L4 of the second layer 14 shown in FIGS. 4 and 5. The film thickness L7 of the second layer 14 in the Z direction is, for example, 22 nm.

[0053] The sum (L5+L6+L7) of the thickness L5 of the third layer 15 in the Z direction, the thickness L6 of the fourth layer 16 in the Z direction, and the thickness L7 of the second layer 14 in the Z direction shown in FIG. 6 is greater than the thickness L4 of the second layer 14 in the Z direction shown in FIGS. 4 and 5. This is because the volume increases when silicon nitride is oxidized to silicon oxide. As a result, the thickness (L 10 ) and the difference in the thickness of the oxidized laminated film S1 before the oxidation (L 10 -L 11 For example, in the case of a laminated film S1 formed by repeating the first layer 13 and the second layer 14 320 times, the difference in film thickness (L 10 -L 11 ) is about 2 μm.

[0054] As another example, the thickness L3 of the first layer 13 in the Z direction before oxidation is, for example, 2.3 nm. The thickness L4 of the second layer 14 in the Z direction before oxidation is, for example, 30.6 nm. The thickness L5 of the third layer 15 in the Z direction after oxidation is, for example, 7.35 nm. The thickness L6 of the fourth layer 16 in the Z direction after oxidation is, for example, 7.35 nm. The thickness L7 of the second layer 14 in the Z direction after oxidation is, for example, 22 nm.

[0055] As another example, the thickness L3 of the first layer 13 in the Z direction before oxidation is, for example, 4.4 nm. The thickness L4 of the second layer 14 in the Z direction before oxidation is, for example, 30.6 nm. The thickness L5 of the third layer 15 in the Z direction after oxidation is, for example, 6.3 nm. The thickness L6 of the fourth layer 16 in the Z direction after oxidation is, for example, 6.3 nm. The thickness L7 of the second layer 14 in the Z direction after oxidation is, for example, 22 nm.

[0056] In this embodiment, the thickness L3 of the first layer 13 in the Z direction before oxidation is preferably, for example, 0.3 nm or more and 10 nm or less, and the thickness L4 of the second layer 14 in the Z direction before oxidation is preferably, for example, 25 nm or more and 45 nm or less. The ratio of the thickness L3 of the first layer 13 in the Z direction before oxidation to the total thickness of the thickness L3 of the first layer 13 and the thickness L4 of the second layer 14 in the Z direction before oxidation is 0.5% or more and 30% or less.

[0057] In this embodiment, the thickness L1 (L3+L5+L6) of the first layer 13 in the Z direction after oxidation increases to a ratio of 35% to 45% of the total thickness of the thickness L1 of the first layer 13 in the Z direction and the thickness L7 of the second layer 14 after oxidation.

[0058] The oxidation of the stacked film S1 having the opening H2 is preferably performed by wet oxidation (e.g., H2O annealing) under high pressure conditions. Here, such wet oxidation is performed by using, for example, hydrogen gas and oxygen gas, and supplying water vapor (H2O) generated by a combustion reaction of the hydrogen gas and the oxygen gas into a reaction chamber in which the semiconductor memory device is manufactured.

[0059] Here, the partial pressure of water vapor (H2O) in the reaction chamber is preferably 10 atmospheres or more, which is a high-pressure condition, and may be 20 atmospheres or more. The temperature in the reaction chamber is preferably 400 degrees or more. The time for oxidizing the stacked film S1 is preferably, for example, 10 minutes to 1 hour, for example, about 30 minutes.

[0060] Next, the charge storage film 4, the tunnel insulating film 3, and part of the channel semiconductor layer 2 are formed in this order in the opening H2, for example, by ALD (Atomic Layer Deposition). The sixth layer 18 is used as the insulating film 5a shown in FIG. 3. Next, the sixth layer 18, the charge storage film 4, the tunnel insulating film 3, and part of the channel semiconductor layer 2 are removed from the bottom of the opening H2, for example, by etching. Next, the remaining part of the channel semiconductor layer 2 and the core insulating film 1 are formed in this order in the opening H2, for example, by ALD (Atomic Layer Deposition). As a result, the sixth layer 18, the charge storage film 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are formed in this order in the opening H2 (FIG. 7).

[0061] Next, slits (not shown) are formed in the laminated film S1. Next, a chemical solution such as phosphoric acid is supplied using the slits to remove the plurality of second layers 14. Next, an insulating film 5b, a barrier metal layer 6a, and a conductive layer 6b are formed in this order in the areas where the plurality of second layers 14 have been removed. This forms the laminated film S2.

[0062] Next, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of drain select transistors STD (not shown) are formed on the laminated film S2, thereby obtaining the semiconductor memory device 100 of the embodiment.

[0063] 8 to 10 are schematic cross-sectional views showing a modified example of the method for manufacturing a semiconductor memory device according to the embodiment.

[0064] The steps of forming a common source line CSL, a source select gate line SGS, and a plurality of source select transistors STS (not shown) on a substrate 11, forming a stacked film S1, and forming an opening H2 (through hole) (Figure 3) are the same as those in the manufacturing method of the semiconductor memory device of the embodiment.

[0065] Next, the stacked film S2 having the opening H2 is oxidized without forming the fifth layer 17. Here, the third layer 15 and the fourth layer 16 are formed, and the side surfaces of the first layers 13 exposed to the opening H2 are oxidized, forming a seventh layer 19 containing an oxide (e.g., silicon (Si) oxide) (FIG. 8).

[0066] Next, the seventh layer 19, part of the second layer 14, part of the third layer 15, and part of the fourth layer 16 are removed by, for example, RIE, thereby exposing the unoxidized side surface of the second layer 14 (FIG. 9).

[0067] Next, the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, and a portion of the channel semiconductor layer 2 are formed in this order in the opening H2, for example, by ALD (Atomic Layer Deposition). Next, the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, and a portion of the channel semiconductor layer 2 are removed from the bottom of the opening H2, for example, by etching. Next, the remaining portion of the channel semiconductor layer 2 and the core insulating film 1 are formed in this order in the opening H2, for example, by ALD (Atomic Layer Deposition). As a result, the insulating film 5a, the charge storage film 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are formed in this order in the opening H2 (FIG. 10). Note that the subsequent manufacturing process is the same as the manufacturing process of the semiconductor manufacturing apparatus of the embodiment.

[0068] Next, the effects of the method for manufacturing a semiconductor memory device according to the embodiment will be described.

[0069] As the thickness of the laminated film S1 increases, the depth of the opening H2 in the Z direction increases, which makes it difficult to form the opening H2.

[0070] Furthermore, when forming opening H2, processing of first layer 13 and processing of second layer 14 are performed alternately. Therefore, the conditions for optimal processing differ depending on, for example, the film thickness of first layer 13, the film thickness of second layer 14, and the ratio of the film thickness of first layer 13 to the film thickness of second layer 14. This point also makes it difficult to form opening H2.

[0071] Therefore, in the manufacturing method of a semiconductor memory device of the embodiment, a laminated film is formed in which a plurality of first layers containing an oxide and a plurality of second layers containing a nitride and each having a thickness thicker than the thickness of the plurality of first layers are alternately stacked one layer at a time in a first direction, openings are formed that penetrate the laminated film and extend in the first direction, and the laminated film having the openings is oxidized, thereby increasing the thickness of each of the plurality of first layers and decreasing the thickness of each of the plurality of second layers.

[0072] When the nitride-containing portion of second layer 14 is oxidized to form a layer containing oxide, the thickness of the oxidized portion of second layer 14 increases compared to the thickness before oxidation because the volume of silicon oxide per Si atom is larger than the volume of silicon nitride per Si atom.

[0073] Therefore, when the opening H2 is formed before oxidizing the stacked film S1, the thickness of the stacked film S1 as a whole in the Z direction is thinner, and therefore the opening H2 can be easily formed. Furthermore, by oxidizing the stacked film S1 after forming the opening H2, the thickness of the first layer 13 containing oxide can be increased. Therefore, for example, it becomes possible to easily prevent data corruption between adjacent memory cells MC and ensure insulation between adjacent word lines WL.

[0074] Furthermore, when forming opening H2, the film thickness of second layer 14 containing nitride can be increased. Therefore, by setting processing conditions for forming opening H2 to be more suitable for processing second layer 14 than for processing first layer 13, processing opening H2 can be easily performed.

[0075] The oxidation of the stacked film S1 is preferably performed by wet oxidation under high-pressure conditions. Normally, it is difficult to form the first layer 13 containing oxide by oxidizing the second layer 14 containing nitride without using a highly reactive manufacturing method such as radical oxidation. However, a problem arises in that the oxidizing power decreases due to the deactivation of radicals. On the other hand, when wet oxidation under high-pressure conditions is used, the oxidizing power does not decrease due to the deactivation of radicals. Therefore, for example, an increase in the oxidation rate and an improvement in the coverage of the formed oxide layer can be expected.

[0076] Here, the partial pressure of water vapor (H2O) in the reaction chamber is preferably 10 atmospheres or more to promote the wet oxidation, and the temperature in the reaction chamber is preferably 400 degrees or more to promote the wet oxidation.

[0077] When forming the processed portion, the temperature of the stage T on which the stacked film S1 is placed is preferably 70° C. or less. The processing speed of the nitride-containing second layer 14 is particularly increased when the temperature of the stage T is 70° C. or less. This allows the opening H2 to be formed more quickly.

[0078] According to the method for manufacturing a semiconductor memory device of this embodiment, it is possible to provide a method for manufacturing a semiconductor memory device that allows for easy manufacturing of the semiconductor memory device.

[0079] Although several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0080] 1: Core insulating film 2: Channel semiconductor layer 3: Tunnel insulating film 4: Charge storage film 5a: Insulating film 5b: Insulating film 6a: Barrier metal layer 6b: Conductive layer 11: Substrate 13: First layer 14: Second layer 15: Third layer 16: Fourth layer 17: Fifth layer (third layer) 18: Sixth layer (fourth layer) 19: Seventh layer 100: Semiconductor memory device Stage: T Opening: H2 Stacked film: S1 Stacked film: S2

Claims

1. forming a laminated film in which a plurality of first layers containing an oxide and a plurality of second layers containing a nitride and each having a thickness greater than that of the plurality of first layers are alternately stacked one layer at a time in a first direction; forming an opening extending in the first direction through the stacked film; oxidizing the stacked film having the openings to increase the thickness of each of the first layers and decrease the thickness of each of the second layers; A method for manufacturing a semiconductor memory device.

2. The oxidation is a wet oxidation.

2. The method for manufacturing a semiconductor memory device according to claim 1.

3. The wet oxidation is performed using hydrogen gas and oxygen gas.

3. The method for manufacturing a semiconductor memory device according to claim 2.

4. When the wet oxidation is performed, the amount of water vapor (H ２ O) is at least 10 atmospheres in partial pressure; 3. The method for manufacturing a semiconductor memory device according to claim 2.

5. When the wet oxidation is performed, the temperature in the reaction chamber in which the semiconductor memory device is manufactured is 400° C. or higher.

3. The method for manufacturing a semiconductor memory device according to claim 2.

6. when forming the opening that penetrates the stacked film and extends in the first direction, the temperature of a stage on which the stacked film is placed is 70° C. or less.

2. The method for manufacturing a semiconductor memory device according to claim 1.

7. a difference between the thickness of the laminated film after the oxidation and the thickness of the laminated film before the oxidation is greater than 0.1 μm; 2. The method for manufacturing a semiconductor memory device according to claim 1.

8. 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein, before the oxidation, a thickness of one of the plurality of first layers in the first direction is 0.3 nm or more and 10 nm or less, and a thickness of the second layer in contact with one of the plurality of first layers in the first direction is 25 nm or more and 45 nm or less.

9. 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein after the oxidation, a film thickness of one of the plurality of first layers is 35% or more and 45% or less of a total film thickness of one of the plurality of first layers and the second layer in contact with one of the plurality of first layers.

10. forming a third layer containing a nitride on side surfaces of the first layers and the second layers exposed in the openings after forming the openings that penetrate the stacked film and extend in the first direction and before oxidizing the stacked film having the openings; When oxidizing the stacked film having the opening, the third layer is oxidized.

2. The method for manufacturing a semiconductor memory device according to claim 1.

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