Oscillation circuit

Abstract

To output oscillation frequency that is stable not depending on power source voltage.SOLUTION: An oscillation circuit according to the present invention includes a reference capacitor, a reference resistor, a constant current circuit that feeds constant current, and an inverter circuit and the oscillation frequency is determined depending on the reference capacitance, the reference resistance, and the time constant determined based on the constant current. The constant current circuit includes a first transistor having one end connected to a first node, a second transistor having one end connected to the first node and connected by current mirror to the first transistor, a reference resistor connected between the first transistor and the second node, and a differential amplifier circuit that differentially amplifies the reference voltage and the voltage at a third node as a connection point of the reference resistor on the first transistor side, and outputs an output signal to the gates of the first and second transistors.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to an oscillator circuit. [Background technology]

[0002] Oscillator circuits that output signals at a specific oscillation frequency are used in communication devices, etc. For communication applications, fluctuations in the oscillation frequency must be kept within 1% regardless of fluctuations in power supply voltage and temperature. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-142964 Summary of the Invention [Problem to be solved by the invention]

[0004] In an RC oscillator circuit, the oscillation frequency is determined by the RC time constant of the circuit. The RC time constant varies depending on the values ​​of the reference resistor and reference capacitor, as well as the threshold voltage of the transistors that make up the inverter. The reference voltage input to the oscillator circuit varies greatly depending on the power supply voltage, so when the power supply voltage fluctuates, the oscillation frequency of the oscillator circuit also fluctuates. For this reason, there is a demand for an oscillator circuit that can output a stable oscillation frequency independent of the power supply voltage. The present invention provides an oscillator circuit that can output a stable oscillation frequency independent of the power supply voltage. [Means for solving the problem]

[0005] According to a first aspect of the present invention, there is provided an oscillator circuit including a reference capacitance, a reference resistor, a constant current circuit for supplying a constant current, and an inverter circuit, and the oscillation frequency is determined by a time constant determined by the reference capacitance, the reference resistor, and the constant current. The constant current circuit includes a current mirror circuit connected to a first node and configured by a plurality of transistors connected in a current mirror configuration, a reference resistor connected between the current mirror circuit and a second node, and a differential amplifier circuit that differentially amplifies a reference voltage and a voltage at a connection node of the reference resistor on the side of the current mirror circuit, and outputs an output signal to the gates of the transistors that configure the current mirror circuit.

[0006] According to a second aspect of the present invention, there is provided an oscillator circuit including a reference capacitance, a reference resistor, a constant current circuit for supplying a constant current, and an inverter circuit, and the oscillation frequency is determined by a time constant determined by the reference capacitance, the reference resistor, and the constant current. The constant current circuit includes a current mirror circuit connected to a first node and configured with a plurality of transistors connected in a current mirror configuration, and a reference resistor connected between the current mirror circuit and a second node. The current mirror circuit includes a first transistor having one end connected to the first node, a second transistor having one end connected to the first node and connected in a current mirror configuration with the first transistor, a third depletion-type transistor connected in series with the first transistor and having a gate connected to the second node, and a fourth depletion-type transistor connected in series with the second transistor and having a gate connected to the second node. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide an oscillation circuit that can output a stable oscillation frequency independent of the power supply voltage. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram illustrating an oscillator circuit 1 according to a first embodiment. [Figure 2]2 is a waveform diagram illustrating the oscillator circuit 1 according to the first embodiment. FIG. [Figure 3] FIG. 2 is a circuit diagram illustrating an example of the configuration of a constant current circuit 11 of a comparative example. [Figure 4] 10 is a graph illustrating fluctuations in reference voltage Vth relative to fluctuations in power supply voltage Vdd in a comparative example. [Figure 5] 10 is a graph illustrating fluctuations in the current mirror ratio with respect to fluctuations in the power supply voltage Vdd in a comparative example. [Figure 6] 1 is a circuit diagram illustrating an example of the configuration of a constant current circuit 11 according to a first embodiment. [Figure 7] 4 is a graph illustrating fluctuations in a reference voltage Vth relative to fluctuations in a power supply voltage Vdd in the first embodiment. [Figure 8] 4 is a graph illustrating a change in a current mirror ratio in response to a change in a power supply voltage Vdd in the first embodiment. [Figure 9] FIG. 10 is a circuit diagram illustrating an example of the configuration of a constant current circuit 11 according to a second embodiment. [Figure 10] FIG. 10 is a circuit diagram illustrating an example of the configuration of a constant current circuit 11 according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, functionally identical elements may be designated by the same numerals. Note that the accompanying drawings show embodiments and implementation examples according to the principles of the present disclosure, but these are for understanding the present disclosure and are not to be used to interpret the present disclosure in a limiting manner. The descriptions in this specification are merely typical examples and are not intended to limit the scope or application of the present disclosure in any way.

[0010] Although the present embodiment has been described in sufficient detail to enable those skilled in the art to implement the present disclosure, it should be understood that other implementations and forms are possible, and that changes in configuration and structure and substitutions of various elements are possible without departing from the scope and spirit of the technical ideas of the present disclosure. Therefore, the following description should not be interpreted as being limited thereto.

[0011] [First embodiment] An oscillator circuit 1 according to a first embodiment will be described with reference to FIG. 1. The oscillator circuit 1 includes, as an example, a constant current circuit 11, a reference resistor 12, a switch circuit 13, a capacitive element 14 (reference capacitance C), an operational amplifier 15, a switch circuit 16, a capacitive element 17, an operational amplifier 18, transistors 19A and 19B, a latch circuit 20, a D flip-flop circuit FF1, a buffer circuit BF1, and inverters IN1 to IN3. The constant current circuit 11 is configured to supply a charging current Irefc generated by mirroring a constant current Irefr to the switch circuits 13 and 16, and also to supply a reference voltage Vth. Details of the configuration will be described later. The reference resistor 12 is connected between the constant current circuit 11 and a ground potential node (Vss).

[0012] The switch circuit 13 is configured by connecting, for example, a P-type MOS transistor M1 and an N-type MOS transistor M2 in series, and is supplied with a charging current Irefc from the constant current circuit 11. A capacitive element 14 is connected between its output terminal (the connection node between the transistors M1 and M2) and a ground potential node (Vss). An output voltage Vc1 from the output terminal of the switch circuit 13 is input to an inverting input terminal (-) of an operational amplifier 15. The operational amplifier 15 receives a reference voltage Vth from the constant current circuit 11 at its non-inverting input terminal (+), and outputs a differentially amplified signal between the reference voltage Vth and the output voltage Vc1.

[0013] The switch circuit 16 is configured by connecting, for example, a P-type MOS transistor M3 and an N-type MOS transistor M4 in series, and is supplied with a charging current Irefc from the constant current circuit 11. A capacitive element 17 is connected between its output terminal (the connection node between the transistors M3 and M4) and a ground potential node (Vss). An output voltage Vc2 from the output terminal of the switch circuit 16 is input to an inverting input terminal (-) of an operational amplifier 18. The operational amplifier 18 receives a reference voltage Vth from the constant current circuit 11 at its non-inverting input terminal (+), and outputs a differentially amplified signal between the reference voltage Vth and the output voltage Vc2.

[0014] A P-type MOS transistor 19A, which is switched between conductive and non-conductive states by an enable signal en, is connected between the output terminal of the OP amplifier 15 and a power supply voltage node (Vdd), and an N-type MOS transistor 19B, which is switched between conductive and non-conductive states by an enable signal en_n (an inverted signal of the enable signal en), is connected between the output terminal of the OP amplifier 18 and a ground potential node. When the enable signals en and en_n switch between "H" and "L", the oscillation circuit 1 starts oscillating.

[0015] Latch circuit 20 is an RS flip-flop circuit that receives the output signals of OP amplifier 15 and OP amplifier 18 and latches the signal states. Inverter IN1 receives the output signal Sr of latch circuit 20 and supplies its inverted signal to the input terminal of switch circuit 13. Inverters IN2 and IN3 are connected in series, and the input terminal of inverter IN2 receives the output signal of latch circuit 20. The output terminal of inverter IN2 is connected to the input terminal of switch circuit 16.

[0016] The D flip-flop circuit FF1 holds the output signal of the latch circuit 20, delays it by a predetermined delay time, and outputs it. The output signal of the D flip-flop circuit FF1 is further delayed by the buffer circuit BF1 and is output as the clock signal ck0.

[0017] The operation of this oscillator circuit 1 will be described with reference to FIG. 2. When the enable signal en goes high, the oscillator circuit 1 begins operating. The output voltages Vc1 and Vc2 of the switch circuits 13 and 16 rise as the capacitors 14 and 17 are charged via the transistors M1 and M3. When the output voltages Vc1 and Vc2 reach the reference voltage Vth, the output signals of the operational amplifiers 15 and 18 are inverted and latched by the latch circuit 20. The output signal Sr of the latch circuit 20 is input to the switch circuits 13 and 16 via the inverters IN1 to IN3, switching the output signals Vc1 and Vc2 of the switch circuits 13 and 16 from high to low. The above operation is repeated, allowing the clock signal ck0 to continue oscillating at a predetermined frequency. The constant current circuit 11 supplies a constant current Irefr to the reference resistor 12 and also supplies a mirror current, the charging current Irefc, to the switch circuits 13 and 16. The oscillation frequency fck0 of the clock signal ck0 is determined by fcko = Irefc / (4Vth·C). When the power supply voltage Vdd fluctuates, the current mirror ratio fluctuates as described below, and therefore the oscillation frequency fck0 also fluctuates. In other words, the oscillation frequency fck0 fluctuates depending on the power supply voltage Vdd.

[0018] An example of the configuration of a constant current circuit 11 of the comparative example will be described with reference to FIG. 3. The constant current circuit of this comparative example includes P-type MOS transistors Mp1 and Mp2 connected in a current mirror configuration. The sources of the transistors Mp1 and Mp2 are connected to a node (first node) of a power supply voltage Vdd. A reference resistor 12 (resistance value R) is connected between the transistor Mp1 and a ground potential node (second node). A constant current Irefr flowing through the transistor Mp1 is mirrored to the transistor Mp2, causing a charging current Irefc to flow. A voltage Vth at the connection node between the transistor Mp1 and the reference resistor 12 is used as the output voltage.

[0019] However, in the configuration of this comparative example, the oscillation frequency fck0 is affected not only by the RC time constant, but also by the current mirror ratio of transistors Mp1 and Mp2, the comparator response time of OP amplifiers 15 and 18, and logic circuit delay time. As shown in FIG. 4, the reference voltage Vth output by constant current circuit 11 also varies with the power supply voltage Vdd. As shown in FIG. 5, the current mirror ratio (Irefc / Irefr) of transistors Mp1 and Mp2 also varies with the power supply voltage Vdd. Fluctuations in the power supply voltage Vdd cause fluctuations in the reference voltage Vth and the current mirror ratio, which in turn affects the oscillation frequency fck0.

[0020] A constant current circuit 11 according to a first embodiment will be described with reference to FIG. 6. The constant current circuit 11 includes transistors Mp1 and Mp2 connected in a current mirror configuration, as well as an operational amplifier 22. The operational amplifier 22 receives a reference voltage Vths at its inverting input terminal, and a voltage at a connection node N1 between the transistor Mp1 and the reference resistor 12 directly at its non-inverting input terminal. The reference voltage Vths is set as a target value for the reference voltage Vth, and is supplied from a constant voltage generating circuit (not shown). The output signal of the operational amplifier 22 is supplied to the gates of the transistors Mp1 and Mp2.

[0021] To suppress changes in the oscillation frequency fck0 due to fluctuations in the power supply voltage Vdd, the constant current circuit 11 compares the reference voltage Vth at the connection node N1 of the reference resistor 12 with a reference voltage Vths in an operational amplifier 22, and supplies the output signal as a differentially amplified signal to the gates of the transistors Mp1 and Mp2 that form the current mirror circuit. That is, by feeding back the reference voltage Vth, determined by the constant current Irefr, to the operational amplifier 22, the constant current Irefr can be controlled to be constant, and the reference voltage Vth can be kept constant regardless of fluctuations in the power supply voltage Vdd (see FIG. 7). Furthermore, the current mirror ratio Irefc / Irefr can also be kept constant regardless of fluctuations in the power supply voltage Vdd (see FIG. 8). This suppresses fluctuations in the oscillation frequency fck0 regardless of fluctuations in the power supply voltage Vdd.

[0022] [Second embodiment] Next, an oscillator circuit 1 according to a second embodiment will be described with reference to Fig. 9. The oscillator circuit 1 according to the second embodiment differs from the first embodiment (Fig. 6) in the configuration of the constant current circuit 11. In Fig. 9, the same components as those in Fig. 6 are given the same reference numerals, and therefore, redundant description will be omitted.

[0023] This constant current circuit 11 includes p-type MOS transistors Mp1 and Mp2 as well as n-type MOS transistors Mn1 and Mn2 (hereinafter referred to as transistors Mn1 and Mn2). The transistors Mn1 and Mn2 are current-mirror connected to form a current mirror circuit. The transistor Mn1 is connected in series with the transistor Mp1 between the transistor Mp1 and the reference resistor 12 to form a current path for the constant current Irefr. The transistor Mn2 is connected in series with the transistor Mp2 at the drain of the transistor Mp2 to form a current path for the charging current Irefc together with the transistor Mp2. The output signal of the operational amplifier 22 is supplied to the gates of these transistors Mn1 and Mn2. As with the first embodiment, this configuration maintains the constant current Irefr constant regardless of fluctuations in the power supply voltage Vdd, and also maintains the current mirror ratio Irefc / Irefr constant, resulting in suppression of fluctuations in the oscillation frequency fck0. In the configuration example of FIG. 9, the output signal of the OP amplifier 22 is input to the gates of the transistors Mn1 and Mn2, but instead of or in addition to this, the output signal of the OP amplifier 22 may be input to the gates of the transistors Mp1 and Mp2.

[0024] [Third embodiment] Next, an oscillator circuit 1 according to a third embodiment will be described with reference to Fig. 10. The oscillator circuit 1 according to the third embodiment differs from the oscillator circuit 1 according to the first embodiment (Fig. 6) in the configuration of the constant current circuit 11.

[0025] This constant current circuit 11 includes depletion-type n-type MOS transistors Md1 and Md2 (hereinafter referred to as transistors Md1 and Md2) in addition to current-mirror-connected transistors Mp1 and Mp2. The transistor Md1 is connected in series with the transistor Mp1 between the transistor Mp1 and the reference resistor 12 to form a current path for the constant current Irefr. The transistor Md2 is connected in series with the transistor Mp2 at the drain of the transistor Mp2 to form a current path for the charging current Irefc. The gates of the transistors Md1 and Md2 are connected to the ground potential node (Vss).

[0026] The drain-source voltage Vds of transistor Md1 is constant, which keeps the constant current Irefr approximately constant regardless of fluctuations in the power supply voltage Vdd. Although the threshold voltages of transistors Md1 and Md2 fluctuate slightly with fluctuations in the power supply voltage Vdd, this does not have a significant effect on the oscillation frequency fck0. Therefore, similar to the first embodiment, the configuration of the third embodiment also keeps the constant current Irefr constant regardless of fluctuations in the power supply voltage Vdd, and also keeps the current mirror ratio Irefc / Irefr constant, thereby suppressing fluctuations in the oscillation frequency fck0.

[0027] [others] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0028] 1...Oscillation circuit 11... Constant current circuit 12...Reference resistor 13, 16...Switch circuit 14, 17...Capacitor element 15, 18, 22...OP amps 19A, 19B...Transistor 20...Latch circuit FF1...flip-flop circuit IN1~3...Inverter

Claims

1. An oscillation circuit comprising a reference capacitance, a reference resistance, a constant current circuit for supplying a constant current, and an inverter circuit, wherein an oscillation frequency is determined by a time constant determined by the reference capacitance, the reference resistance, and the constant current, The constant current circuit is a current mirror circuit connected to the first node and configured by connecting a plurality of transistors in a current mirror configuration; a reference resistor connected between the current mirror circuit and a second node; a differential amplifier circuit that differentially amplifies a reference voltage and a voltage at a connection node of the reference resistor on the side of the current mirror circuit, and outputs an output signal to a gate of a transistor that constitutes the current mirror circuit; An oscillator circuit comprising:

2. The current mirror circuit is a first transistor having one end connected to the first node; a second transistor having one end connected to the first node and connected to the first transistor in a current mirror configuration; 2. The oscillator circuit of claim 1, comprising:

3. The current mirror circuit is a first transistor having one end connected to the first node; a second transistor having one end connected to the first node and connected to the first transistor in a current mirror configuration; a third transistor connected in series with the first transistor; a fourth transistor connected in series with the second transistor and connected in a current mirror with the third transistor; Equipped with the reference resistor is connected between the third transistor and the second node; 2. The oscillation circuit according to claim 1, wherein the differential amplifier circuit differentially amplifies a reference voltage and a voltage at a connection node of the reference resistor on the side of the third transistor, and outputs an output signal to the gates of the first and second transistors or the gates of the third and fourth transistors.

4. An oscillation circuit comprising a reference capacitance, a reference resistance, a constant current circuit for supplying a constant current, and an inverter circuit, wherein an oscillation frequency is determined by a time constant determined by the reference capacitance, the reference resistance, and the constant current, The constant current circuit is a current mirror circuit connected to the first node and configured by connecting a plurality of transistors in a current mirror configuration; a reference resistor connected between the current mirror circuit and a second node; Equipped with The current mirror circuit is a first transistor having one end connected to the first node; a second transistor having one end connected to the first node and connected to the first transistor in a current mirror configuration; a third depletion-mode transistor connected in series with the first transistor and having a gate connected to the second node; a fourth depletion-type transistor connected in series with the second transistor and having a gate connected to the second node; An oscillator circuit comprising:

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