Semiconductor device

Abstract

To provide a semiconductor device at low cost, which reduces manufacturing processes and has good productivity; and provide a semiconductor device which requires less power consumption and has high reliability.SOLUTION: In a semiconductor device manufacturing method, a photolithography process for forming an island-shaped semiconductor layer is omitted, and the semiconductor device is manufactured by at least four photolithography processes including a process of forming a gate electrode (including wiring and the like formed in the same layer), a process of forming a source electrode and a drain electrode (including wiring and the like formed in the same layer), a process of forming contact holes, and a process of forming pixel electrodes. In the process of forming the contact holes, formation of a groove prevents formation of a parasitic channel. The groove and the wiring overlap each other across an insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to transistors, semiconductor circuits, memory devices, imaging devices, display devices, and electro-optical devices All electronic devices and other devices can be considered semiconductor devices. [Background technology]

[0003] Recently, a thin film having a thickness of several nanometers to several hundred nanometers formed on a substrate having an insulating surface such as a glass substrate has been developed. Transistors made of thin semiconductor films of about I C (Integrated Circuit) and electronic devices including electro-optical devices Transistors are widely used in devices, especially active matrix liquid crystal displays. These are represented by display devices such as LEDs and EL (Electro Luminescence) display devices. Development is being rushed for use as a switching element in image display devices. In the switch-type liquid crystal display device, a pixel electrode connected to a selected switching element and a When a voltage is applied between the opposing electrodes corresponding to the pixel electrodes, a voltage is applied between the pixel electrodes and the opposing electrodes. The liquid crystal layer is optically modulated, and this optical modulation is recognized by the viewer as a display pattern. Here, an active matrix display device is a display device in which pixels are arranged in a matrix. By driving the element electrodes with switching elements, a display pattern is formed on the screen. This refers to a display device that uses a method of

[0004] The applications of the above-mentioned active matrix display devices are expanding, and the screen size is becoming larger. There is a growing demand for larger area, higher definition, and higher aperture ratio. High reliability is required for the display device, and the manufacturing method must be highly productive and cost-effective. One way to increase productivity and reduce production costs is to simplify the process. Examples include:

[0005] In active matrix display devices, transistors are mainly used as switching elements. In the fabrication of transistors, the photolithography process is reduced or simplified. For example, in the photolithography process, When one more mask is used, the resist coating, pre-baking, exposure, development, and post-baking steps are required. The process includes the steps of forming a coating and etching, as well as the steps before and after the steps. Therefore, photolithography in the manufacturing process is required. Just adding one more mask to the roughing process significantly increases the number of steps. Numerous techniques have been developed to reduce or simplify the photolithography steps in the fabrication process. Development is being done.

[0006] The transistor is a top-gate type in which the channel formation region is provided below the gate electrode. and bottom gate type in which the channel forming region is provided above the gate electrode. In an active matrix liquid crystal display device using these transistors, at least 5 It is fabricated through at least five photolithography steps using a single photomask. This is common.

[0007] In addition, in active matrix EL display devices, a partition is used to separate the EL layer for each pixel. Since it is necessary to form a wall layer, one more photomask is used to form at least a total of It is generally fabricated using six photolithography steps.

[0008] Conventional techniques for simplifying the photolithography process include backside exposure (see, for example, Many of them use complex techniques such as resist reflow or lift-off. Many of these require special equipment. This causes various problems and is one of the causes of the decrease in yield. This often results in a decrease in performance. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 05-203987 Summary of the Invention [Problem to be solved by the invention]

[0010] However, reducing or simplifying the photolithography process can result in unnecessary areas. A channel may be formed in the unintended area, causing the area to function as a transistor. .

[0011] For example, if a semiconductor layer overlaps the pixel electrode via an insulating layer, the voltage supplied to the pixel electrode Depending on the potential, a channel may be formed in the semiconductor layer that overlaps with the pixel electrode. A channel formed in a place where it is not actually needed is called a parasitic channel.

[0012] Also, for example, a common wiring A (for example, , gate wiring), a parasitic When the channel is formed, the wiring B of the first pixel, which is formed in contact with the semiconductor layer, (for example, the image signal wiring of the first pixel) and the wiring C of the second pixel (for example, the When the image signal wiring of the pixel in 2) is electrically connected by a parasitic channel That is, the wiring A functions as a gate electrode, and the wiring B functions as a source or drain electrode. The wiring C functions as one of the source and drain electrodes. In this way, unintentionally formed transistors can be prevented. The resistor is called a parasitic transistor.

[0013] In addition, when the distance between adjacent wirings is short, even if there is no layer that functions as a gate electrode, The electric field generated between adjacent wirings forms a parasitic channel in the semiconductor layer, and the adjacent wirings The operator may be electrically connected.

[0014] When a parasitic channel or a parasitic transistor is formed, the signals between the wires interfere with each other, preventing accurate signal transmission. This makes it difficult to transmit signals, which can lead to a decrease in display quality and reliability.

[0015] Furthermore, semiconductor devices are made up of multiple thin films with complex structures, and require a wide variety of materials, methods and processes. Therefore, depending on the manufacturing process used, the shape of the resulting semiconductor device may be irregular. This may result in deterioration of the electrical properties.

[0016] In view of such problems, it is an object of the present invention to provide a highly reliable semiconductor device.

[0017] One embodiment of the present invention is to reduce the number of photolithography steps used in manufacturing a semiconductor device compared to conventional methods. One of the challenges is to make this easier.

[0018] One embodiment of the present invention is to reduce the number of photomasks used in manufacturing a semiconductor device compared to conventional methods. One of the challenges is to

[0019] An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

[0020] An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. [Means for solving the problem]

[0021] The photolithography process for forming the island-shaped semiconductor layer is omitted, and the gate electrode (in the same layer) is a step of forming a source electrode and a drain electrode (including wiring formed in the same layer); a step of forming a contact hole and a groove; Four photolithography processes for forming electrodes (including wiring formed on the same layer) In this process, a semiconductor device to be used in a liquid crystal display device is manufactured.

[0022] Furthermore, the semiconductor device used in the liquid crystal display device manufactured by the above method has a parasitic channel or a parasitic To prevent the transistor from being generated, a second wiring is provided which is electrically connected to the source electrode of the transistor. For example, a first groove is formed along the line. and the first wiring is electrically connected to the first wiring. The second groove is formed so as to extend across both ends of the capacitance wiring in the line width direction. The third groove is formed so as to extend beyond the first groove and cross at least a part of the capacitance wiring. The second wiring is disposed between the second wiring and the pixel electrode, and the second wiring extends in a direction that the second wiring extends, and the second wiring extends beyond the edge of the pixel electrode. The third groove overlaps the pixel electrode and is formed along the direction in which the second wiring extends. The insulating film 11 may be formed so as to extend beyond the edge of the pixel electrode.

[0023] The first groove, the second groove, and the third groove may be formed independently of each other, or may be formed as a single groove. The groove may serve as a plurality of or all of the first to third grooves.

[0024] The first trench has a region that overlaps with the first wiring and a region that does not overlap with the first wiring. When the first wiring is exposed on the surface, the semiconductor layer exposed on the side surface of the groove and the semiconductor layer exposed on the bottom surface of the groove are There is a risk of leakage current occurring between the first wirings. This prevents leakage current from occurring in the groove. The trench to be formed in the region where the first wiring is to be formed is formed on the first wiring via an insulating layer.

[0025] The second groove has a region that overlaps with the capacitor wiring and a region that does not overlap with the capacitor wiring. When the capacitor wiring is exposed, the semiconductor layer exposed on the side of the groove and the capacitor layer exposed on the bottom of the groove are There is a risk of leakage current occurring between the wiring. For this reason, the capacitance wiring is not exposed at the bottom of the groove. This prevents leakage current from occurring in the trench. The grooves are formed on the capacitance wiring via an insulating layer.

[0026] One embodiment of the present invention is a semiconductor device including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer. a first wiring electrically connected to the gate electrode; a second wiring for connection, a pixel electrode electrically connected to the drain electrode, a capacitance wiring, and a groove portion The semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, and has a trench. The portion is formed on the first wiring and across the first wiring, and the groove portion is formed on the capacitor wiring and across the capacitor. The groove is formed across the second wiring, and the groove is formed along the direction in which the second wiring extends. The groove is formed beyond the end of the first wiring and the semiconductor layer is removed at the bottom of the groove. The capacitor wiring is overlapped with the insulating layer.

[0027] In one embodiment of the present invention, a gate electrode is formed by a first photolithography process, and A gate insulating layer is formed on the electrode, a semiconductor layer is formed on the gate insulating layer, and a second photolithography is performed. A source electrode and a drain electrode are formed on the semiconductor layer by a lithography process. A protective layer is formed on the source electrode and the drain electrode, and a third photolithography process is performed. Alternatively, a first contact is formed by selectively removing a portion of the protective layer that overlaps one of the drain electrodes. The process involves forming a gate hole and selectively removing a portion of the protective layer, semiconductor layer, and gate insulating layer. The formation of the second contact hole and the trench formed by selectively removing a portion of the protective layer and the semiconductor layer. A pixel electrode is formed on the protective layer by a fourth photolithography process. It is characterized by:

[0028] The resist mask in the third photolithography process is formed using a multi-tone mask. By performing the above steps, a first contact hole, a second contact hole, and a groove are formed. This can be done in a single photolithography process.

[0029] One aspect of the present invention is to form a first electrode, form a first layer on the first electrode, and A semiconductor layer is formed on the semiconductor layer, a second electrode and a third electrode are formed on the semiconductor layer, and the second electrode and the third electrode are formed on the semiconductor layer. A second layer is formed over the third electrode, and a second layer overlapping the second electrode or the third electrode is formed over the second layer. Formation of a contact hole by removing a portion, a portion of the first layer, and a portion of the semiconductor layer; and forming a contact hole by removing a part of the second layer, and forming a contact hole by removing a part of the second layer and a semi-conductor. The formation of the grooves, which is performed by removing a part of the conductor layer, is performed in the same photolithography process. It is characterized by:

[0030] The first layer functions as a gate insulating layer, and the second layer functions as a protective layer. The electrode acts as a gate electrode, and the second electrode acts as either a source or drain electrode. The third electrode functions as the other of the source electrode and the drain electrode.

[0031] The photolithography process for forming the island-shaped semiconductor layer is omitted, and the gate electrode (in the same layer) is a step of forming a source electrode and a drain electrode (including wiring formed in the same layer); a step of forming a contact hole and a groove; Five processes: a process for forming electrodes (including wiring formed on the same layer), and a process for forming a partition layer. A semiconductor device to be used in an EL display device is manufactured by the photolithography process.

[0032] The semiconductor device used in the EL display device manufactured by the above method has a parasitic channel or a parasitic a second transistor electrically connected to the source electrode of the first transistor to prevent generation of a second transistor; A groove is provided along the wiring of the first transistor. The first wiring extends beyond both ends in the line width direction of the first wiring that is electrically connected to the gate electrode of the first wiring. The second groove is formed so as to cross at least a part of the second wiring and the pixel. Between the electrodes, the second wiring is formed in the direction in which it extends, beyond the edge of the pixel electrode. The second groove overlaps the pixel electrode and is formed at the edge of the pixel electrode along the direction in which the second wiring extends. The third groove may be formed between adjacent pixels, so that the second groove is formed beyond the second groove. Grooves are formed along the direction in which the wire extends.

[0033] The first groove, the second groove, and the third groove may be formed independently of each other, or may be formed as a single groove. The groove may serve as a plurality of or all of the first to third grooves.

[0034] Furthermore, when the first wiring is exposed at the bottom of the first trench, the semiconductor exposed on the side surface of the trench A leakage current (hereinafter also referred to as "leak current") flows between the layer and the first wiring exposed at the bottom of the trench. Therefore, the first wiring is not exposed at the bottom of the groove, and To prevent the occurrence of leakage current in the first wiring, the first groove is provided on the first wiring via an insulating layer. and form.

[0035] One aspect of the present invention is a semiconductor device including a first wiring, a second wiring, a semiconductor layer, a pixel electrode, and a first groove portion. and a second groove portion, the semiconductor layer overlapping the first wiring and the pixel electrode, the first groove portion The second groove is formed on the first wiring and across the first wiring, and the second groove is formed in a region where the second wiring extends. The first wiring is formed between the second wiring and the pixel electrode and beyond the edge of the pixel electrode along the first direction. The semiconductor layer is removed from the bottom surfaces of the trench and the second trench, and the first trench is provided with a first wiring. The stacking is characterized by being performed via an insulating layer.

[0036] One aspect of the present invention is a liquid crystal display device having a first pixel and a second pixel adjacent to the first pixel. The first wiring, the second wiring, the semiconductor layer, the pixel electrode, the first groove portion, and the second groove portion The semiconductor layer overlaps the first wiring and the pixel electrode, and the first groove is formed on the first wiring. , is formed across the first wiring, and the second groove is formed along the direction in which the second wiring extends, A first groove portion and a second groove portion are formed between the second wiring and the pixel electrode and beyond the edge of the pixel electrode. The semiconductor layer is removed at the bottom of the second trench, and the first trench is connected to the first wiring and the insulating layer. a third groove portion, the bottom surface of which is removed from the semiconductor layer, between the first pixel and the second pixel; and the third groove portion is formed beyond an end of the first pixel.

[0037] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first wiring, and a second wiring. a first wiring, a third wiring, a pixel electrode, a first groove, and a second groove, The first transistor and the second transistor each include a gate electrode, a source electrode, a drain electrode, and a semiconductor a gate electrode of the first transistor electrically connected to the first wiring; One of the source electrode and the drain electrode of the transistor is electrically connected to the second wiring. The other of the source electrode or the drain electrode of the first transistor is connected to the the source electrode or the drain electrode of the second transistor. One of the terminals is electrically connected to the third wiring and is connected to the source electrode or the drain electrode of the second transistor. The other of the line electrodes is electrically connected to the pixel electrode, and the semiconductor layer is connected to the first wiring and the second wiring. The third wiring overlaps the pixel electrode, and the first groove is between the second wiring and the third wiring. The second groove is formed on the first wiring and across the first wiring, and the second groove is formed in a region where the second wiring extends. the second wiring and the third wiring are formed along the direction of the pixel electrode, between the second wiring and the third wiring, and beyond the edge of the pixel electrode; The semiconductor layer is removed at the bottom surfaces of the first and second grooves, and the first groove is It is characterized by being superimposed on the wiring via an insulating layer.

[0038] In one embodiment of the present invention, a gate electrode is formed by a first photolithography process, and A gate insulating layer is formed on the electrode, a semiconductor layer is formed on the gate insulating layer, and a second photolithography is performed. A source electrode and a drain electrode are formed on the semiconductor layer by a lithography process. An insulating layer is formed on the drain electrode, and a third photolithography process is performed to form the source electrode. A first contact is made by selectively removing a portion of the insulating layer that overlaps with one of the drain electrodes. The process is performed by forming a hole and selectively removing a portion of the insulating layer, the semiconductor layer, and the gate insulating layer. Formation of a second contact hole and a trench formed by selectively removing a portion of the insulating layer and semiconductor layer A pixel electrode is formed on the insulating layer by a fourth photolithography process, and a third The method is characterized in that a partition wall layer is formed by the photolithography process of 5.

[0039] The resist mask in the third photolithography process is formed using a multi-tone mask. By performing the above steps, a first contact hole, a second contact hole, and a groove are formed. This can be done in a single photolithography process.

[0040] One aspect of the present invention is to form a first electrode, form a first layer on the first electrode, and A semiconductor layer is formed on the semiconductor layer, a second electrode and a third electrode are formed on the semiconductor layer, and the second electrode and the third electrode are formed on the semiconductor layer. A second layer is formed to cover the third electrode, and a portion of the second layer overlapping the second electrode or the third electrode is A contact hole is formed by removing a portion of the second layer, a portion of the semiconductor layer, and the first layer. A contact hole is formed by removing a part of the first layer, a part of the second layer, and a semiconductor layer. The grooves are formed by removing a portion of the second layer in the same photolithography process. The method is characterized by forming a third layer.

[0041] The first layer acts as a gate insulating layer, the second layer acts as a protective layer, and the third layer acts as a barrier layer. The first electrode functions as a gate electrode, and the second electrode functions as a source electrode. The third electrode functions as either a source or drain electrode. It functions as the other of the two.

[0042] The first layer, the semiconductor layer, and the portion of the second layer are removed by a dry etching method or a wet etching method. Dry etching or a combination of dry and wet etching methods is used. It is possible to do so.

[0043] The gate electrode, source electrode, drain electrode, or the wiring connecting to these electrodes is made of copper or By forming the wiring from a material containing aluminum, the wiring resistance is reduced and signal delay is prevented. You can do this.

[0044] In addition, after the source and drain electrodes are formed, the surface and side surfaces of the exposed semiconductor layer are It is preferable to carry out a washing treatment to remove impurities that have been deposited.

[0045] The semiconductor layer may be made of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like. Examples of semiconductor materials include silicon, germanium, and silicon germanium. Examples of suitable materials include silicon, silicon carbide, and gallium arsenide.

[0046] In addition, by using an oxide semiconductor for the semiconductor layer, it is possible to achieve a highly reliable EL display with low power consumption. It is possible to realize a display device. [Effects of the Invention]

[0047] According to one embodiment of the present invention, a photolithography process used for manufacturing a transistor is performed more efficiently than in the past. Therefore, the film used in manufacturing a display device having a transistor can be The number of photomasks can be reduced compared to conventional methods, resulting in low-cost, highly productive semiconductor manufacturing. Locations can be provided.

[0048] According to one embodiment of the present invention, an oxide semiconductor is used for a semiconductor layer in which a channel is formed. Therefore, a semiconductor device with low power consumption and high reliability can be provided. [Brief explanation of the drawings]

[0049] [Figure 1] 1A to 1C illustrate one embodiment of the present invention. [Figure 2] 1A to 1C illustrate one embodiment of the present invention. [Figure 3] 1A to 1C illustrate one embodiment of the present invention. [Figure 4] 1A to 1C illustrate one embodiment of the present invention. [Figure 5] 1A to 1C illustrate one embodiment of the present invention. [Figure 6] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 7] 1A to 1C illustrate one embodiment of the present invention. [Figure 8] 1A to 1C illustrate one embodiment of the present invention. [Figure 9] 1A to 1C are diagrams illustrating a manufacturing method. [Figure 10] 1A to 1C are diagrams illustrating a manufacturing method. [Figure 11] 1A to 1C are diagrams illustrating a manufacturing method. [Figure 12] 1A to 1C are diagrams illustrating a manufacturing method. [Figure 13] FIG. 10 is a diagram illustrating a multi-tone mask. [Figure 14] 1A to 1C illustrate one embodiment of the present invention. [Figure 15] 1A to 1C illustrate one embodiment of the present invention. [Figure 16] 1A to 1C illustrate one embodiment of the present invention. [Figure 17] 1A to 1C illustrate one embodiment of the present invention. [Figure 18] 1A to 1C illustrate one embodiment of the present invention. [Figure 19] 1A to 1C illustrate one embodiment of the present invention. [Figure 20] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 21] 1A to 1C are diagrams illustrating a manufacturing method. [Figure 22] 1A to 1C are diagrams illustrating a manufacturing method. [Figure 23] 1A to 1C are diagrams illustrating a manufacturing method. [Figure 24] 1A to 1C illustrate one embodiment of the present invention. [Figure 25] 1A to 1C illustrate one embodiment of the present invention. [Figure 26] 1A to 1C illustrate one embodiment of the present invention. [Figure 27] 1A to 1C illustrate one embodiment of the present invention. [Figure 28] 1A and 1B are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0050] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. It should be noted that the following description of the invention is not intended to be limiting. In this case, the same reference numerals are used in common between different drawings to designate the same parts or parts having similar functions. Therefore, the repeated explanation will be omitted.

[0051] In addition, ordinal numbers such as "first," "second," and "third" in this specification may be used to avoid confusion of elements. The numbers are added to avoid confusion and are not intended to limit the number.

[0052] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual device for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0053] A transistor is a type of semiconductor device that amplifies current and voltage and controls conduction or non-conduction. In this specification, the transistor can be IGFET(Insulated Gate Field Effect Transi) stor) and thin film transistor (TFT) Includes:

[0054] Also, the functions of the "source" and "drain" of a transistor are different when transistors of different polarities are used. This may be reversed when using a current source or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It shall be possible to use it.

[0055] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0056] (Embodiment 1) In this embodiment, a semiconductor device is manufactured by reducing the number of photomasks and photolithography steps. As an example of the device, a semiconductor device that can be used in an active matrix liquid crystal display device is An example of the device and a method for manufacturing the device will be described with reference to FIGS.

[0057] A configuration example of a semiconductor device 100 that can be used in a liquid crystal display device will be described with reference to FIG. 6(A). The semiconductor device 100 includes a pixel region 102 and m (m is an integer of 1 or more) pixel regions on a substrate 101. a terminal section 103 having n (n) terminals 105_1 to 105_m and a terminal 107; The terminal unit 104 has terminals 106_1 to 106_n (each of which is an integer equal to or greater than 1). In addition, the semiconductor device 100 includes m wirings 212_1 to 212_2 electrically connected to the terminal portion 103. 2_m, the wiring 203, and n wirings 216_1 to 216_21 electrically connected to the terminal portion 104. The pixel area 102 has a matrix of m vertical rows by n horizontal columns. The pixel 110 (i, j) (i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less) are the wiring 212_i, the wiring 216_j Each pixel functions as a capacitance electrode or capacitance wiring. The wiring 203 is electrically connected to the terminal 107 and the counter electrode connection part 225. The wiring 212_i is electrically connected to the terminal 105_i. 16_j is electrically connected to the terminal 106_j.

[0058] The liquid crystal display device formed using the semiconductor device 100 is formed by arranging the liquid crystal layer perpendicular to the surface of the substrate 101. When used as a liquid crystal display device that operates with an electric field in the axial direction, the substrate 101 is set opposite to the substrate 101. An electrode (hereinafter also referred to as a "counter electrode") is attached to a substrate (hereinafter also referred to as a "counter substrate") that is In addition, the counter electrode is connected to a counter electrode connecting portion 22 formed on the substrate 101. 5, and is supplied with the same potential as the wiring 203. The pole connection portion 225 can be connected via a conductive paste or conductive particles.

[0059] The liquid crystal display device formed using the semiconductor device 100 is a device in which the liquid crystal layer is disposed on the surface of the substrate 101. When used as a liquid crystal display device operated by a parallel electric field, a counter electrode is provided on the counter substrate. Since the counter electrode connecting portion 225 is not formed, the formation of the counter electrode connecting portion 225 can be omitted.

[0060] The terminals 103 and 104 are external input terminals, and are connected to an external control circuit and It is connected using a PC (Flexible Printed Circuit) or similar. A signal supplied from a control circuit provided in the terminal 103 is transmitted to the terminal 104 via the terminal 103. 6A, the terminal portion 103 is located on the left side of the pixel region 102. The terminal portion 104 is formed on the right outer side, and signals are input from two points. The structure is shown in which the signal is input from two points, formed on the upper and lower outer sides of the element region 102. By inputting a signal from the Furthermore, the increase in wiring resistance due to the increase in size and high definition of the semiconductor device 100 can be prevented. In addition, the semiconductor device 100 can be provided with redundancy, thereby reducing the influence of signal delays. This makes it possible to improve the reliability of the semiconductor device 100. In FIG. 6A, the terminal portion 103 and the terminal portion 104 are provided at two locations. However, it is also possible to provide one of each.

[0061] 6B shows the circuit configuration of the pixel 110. The pixel 110 includes a transistor 111 The transistor 111 includes a gate electrode, a liquid crystal element 112, and a capacitor element 113. is electrically connected to the wiring 212_i, and is connected to the source electrode or drain electrode of the transistor 111. One of the electrodes is electrically connected to the wiring 216_j. The other of the source electrode and the drain electrode is connected to one electrode of the liquid crystal element 112 and the capacitor element 113. The other electrode of the liquid crystal element 112 is electrically connected to the electrode 114. The potential of the electrode 114 can be set to GND, a common potential, or any fixed potential. However, the potential of the electrode 114 may be changed as needed. The other electrode of the capacitor 113 is electrically connected to the wiring 203. The potential of the wiring 203 and the potential of the electrode 114 are preferably set to the same potential.

[0062] The transistor 111 receives an image signal supplied from a wiring 216_j to the liquid crystal element 112. The wiring 212_i has a function of selecting whether to turn on the transistor 111. When a signal is supplied to the wiring 216_j, an image signal is supplied to the wiring 216_j through the transistor 111. The liquid crystal element 112 responds to the supplied image signal (electric potential). The capacitor 113 controls the potential supplied to the liquid crystal element 112. The capacitor 113 has a function as a storage capacitor (also referred to as a Cs capacitor) for storing data. Although it is not necessarily required, the capacitor 113 can be provided to reduce the When 1 is in the off state, the current (off current) flows between the source and drain electrodes. Fluctuations in the potential applied to the liquid crystal element 112 can be suppressed.

[0063] The semiconductor layer in which the channel of the transistor 111 is formed may be a single crystal semiconductor, a polycrystalline semiconductor, or a Examples of the semiconductor material include: Silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. In addition, the display device described in this embodiment has a semiconductor Since the layer remains, the display device using the semiconductor is used as a transmission type display device. In this case, it is preferable to increase the transmittance of visible light by making the semiconductor layer as thin as possible.

[0064] In addition, an oxide semiconductor is used for a semiconductor layer in which a channel of the transistor 111 is formed. The oxide semiconductor has a large energy gap of 3.0 eV or more, and is resistant to visible light. In addition, the transistor obtained by processing the oxide semiconductor under appropriate conditions has a high transmittance. In the case of a transistor, the off-state current is 100 Ω or less under the temperature conditions in use (e.g., 25°C). A(1×10 -19 A) or less, or 10zA (1 x 10 -20 A) The following, and further 1 zA(1×10 -21A) or less. Therefore, it is possible to use semiconductors with low power consumption. Furthermore, the liquid crystal element 112 can be printed without providing the capacitor element 113. Since the applied potential can be maintained, the aperture ratio of the pixel can be increased, resulting in improved display quality. Furthermore, by increasing the aperture ratio of the pixels, it is possible to provide a liquid crystal display device with low backlight. This allows efficient use of light from light sources such as LEDs, thereby reducing the power consumption of liquid crystal displays. It is possible.

[0065] The oxide semiconductor used for the semiconductor layer has reduced impurities such as moisture and hydrogen. By reducing oxygen deficiencies in the body, i-type (intrinsic) or substantially i-type oxide semiconductors can be obtained. Preferably, the body is used.

[0066] Highly purified acid with reduced impurities such as water or hydrogen, which act as electron donors The oxide semiconductor (purified OS) then supplies oxygen to the oxide semiconductor, By reducing oxygen vacancies in the oxide semiconductor, it is possible to obtain an i-type (intrinsic) oxide semiconductor or an i-type The oxide semiconductor can be made to be substantially i-type. A transistor using an i-type or substantially i-type oxide semiconductor for a semiconductor layer to be formed is Specifically, a highly purified oxide semiconductor has the following characteristics: , Secondary Ion Mass Spectrometry (SIMS) The hydrogen concentration measured by ionospheric spectrometry was 5×10 19 / cm 3 Below, preferably 5×10 18 / cm 3 Less than or equal to 5 × 10 17 / cm 3 The following applies.

[0067] In addition, the i-type or substantially i-type oxide semiconductor that can be measured by Hall effect measurement The carrier density is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than, More preferably, 1×10 11 / cm 3 The band gap of oxide semiconductors is less than is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an i-type or substantially i-type oxide semiconductor for the semiconductor layer in which the hole is formed, As a result, the off-state current of the transistor can be reduced.

[0068] Here, we will discuss SIMS analysis of the hydrogen concentration in oxide semiconductors. In principle, it is difficult to obtain accurate data near the sample surface or near the interface between layers of different materials. Therefore, the distribution of hydrogen concentration in the film in the thickness direction is known to be difficult. When analyzing fabrics with SIMS, extreme fluctuations in values ​​occur in the areas where the target film is present. The average value in the region where a substantially constant value is obtained without any change is adopted as the hydrogen concentration. When the thickness of the film to be measured is small, the hydrogen concentration in the adjacent film is affected, and the In some cases, it may not be possible to find a region where a constant value is obtained. In this case, The maximum or minimum value of the hydrogen concentration is adopted as the hydrogen concentration in the film. In the region where the film exists, a mountain-shaped peak having a maximum value and a valley-shaped peak having a minimum value are If no peak is present, the value at the inflection point is taken as the hydrogen concentration.

[0069] In this embodiment, the transistor 111 is described as an n-channel transistor. However, a p-channel transistor may be used.

[0070] Next, an example of the configuration of the pixel 110 shown in FIG. 6 will be described with reference to FIGS. 1 and 2. FIG. 1 is a top view showing the planar configuration of the pixel 110, and FIG. 2 shows the stacked configuration of the pixel 110. The dashed lines A1-A2, B1-B2, C1-C2, and D1-D2 in FIG. 2A to 2D, the cross sections A1-A2, B1-B2, and C1-C2 , corresponds to the cross section D1-D2. In order to make the drawing easier to see, some components are shown in FIG. The description of the elements is omitted.

[0071] In the transistor 111 described in this embodiment, the drain electrode 206b is U-shaped (C-shaped, The source electrode 206a is U-shaped or horseshoe-shaped. By doing so, it is possible to ensure a sufficient channel width even if the transistor area is small. This allows the amount of current that flows when the transistor is turned on (also called on-state current) to be increased. When the on-current of the transistor 111 increases, the signal can be input more quickly. This makes it possible to:

[0072] In addition, the drain electrode 206b electrically connected to the pixel electrode 210 and the gate electrode 202 If the parasitic capacitance between the liquid crystal element and the liquid crystal display is large, the liquid crystal element is more susceptible to feedthrough. The potential supplied to the pixel 112 cannot be accurately maintained, which causes a deterioration in display quality. As shown in the figure, the source electrode 206a is U-shaped and surrounds the drain electrode 206b. By doing so, a sufficient channel width can be secured while the drain electrode 206b and the gate electrode 20 This reduces the parasitic capacitance between the two, improving the display quality of the liquid crystal display device. It can be done.

[0073] The wiring 203 functions as a capacitance electrode or a capacitance wiring. and the drain electrode 206b overlap each other to form a capacitor element 113.

[0074] In addition, the semiconductor device described in this embodiment has an island-shaped semiconductor layer formed thereon to simplify the process. Since the photolithography process for the semiconductor layer 205 is not performed, the semiconductor layer 205 remains in the entire pixel area. As a result, the wiring 212_i functions as a gate electrode, and the wiring 216_j functions as a switch. The wiring 216_j of the adjacent pixel functions as either a source electrode or a drain electrode. +1 acts as the other of the source and drain electrodes. There is a risk of this happening.

[0075] In addition, the wiring 203 functions as a gate electrode, and the wiring 216_j functions as a source electrode or a drain electrode. The wiring 216_j+1 of the adjacent pixel functions as a source electrode or There is a risk of a second parasitic transistor occurring, which functions as the other of the drain electrodes.

[0076] The pixel electrode 210 functions as a gate electrode, and the insulating layer 207 functions as a gate insulating layer. The wiring 216_j functions as either a source electrode or a drain electrode, and the wiring 216_j functions as either a source electrode or a drain electrode. The wiring 216_j+1 of the element functions as the other of the source electrode and the drain electrode. There is a risk of a parasitic transistor of 3 occurring.

[0077] When a potential that turns on the transistor 111 is supplied to the wiring 212_i, the first parasitic The transistor is also turned on, and the wiring 216_j of the pixel adjacent to the wiring 216_j +1 is electrically connected to the wiring 216_j by the first parasitic transistor. When the wiring 216_j+1 is electrically connected, the image signals from both sides interfere with each other, and an accurate image signal is not obtained. It becomes difficult to supply the liquid crystal element 112 with the liquid crystal.

[0078] When the second parasitic transistor functions as an n-type transistor, the wiring 203 The potential of the wiring 216_j or the wiring 216_j+1 of the adjacent pixel is higher than the supplied potential. The potential becomes lower, and the absolute value of the potential difference becomes larger than the threshold value of the second parasitic transistor. As a result, a parasitic channel is formed in the semiconductor layer 205 overlapping the wiring 203, and a second parasitic channel The transistor is turned on.

[0079] When the second parasitic transistor is turned on, the wiring 216_j and the wiring of the adjacent pixel The line 216_j+1 is electrically connected. When the wiring 216_j and the wiring 216_j+1 are electrically connected, the image signals of both interfere with each other, and the correct It becomes difficult to supply accurate image signals to the liquid crystal element 112.

[0080] When the third parasitic transistor functions as an n-type transistor, the pixel electrode 21 The potential of the wiring 216_j or the adjacent pixel is higher than the potential supplied or held at 0. The potential of the wiring 216_j+1 connected to the third parasitic transistor 216_j+1 becomes lower, and the absolute value of the potential difference becomes When the voltage Vcc exceeds the threshold voltage Vcc, a parasitic channel is generated in the semiconductor layer 205 overlapping the pixel electrode 210. A parasitic transistor is formed, and the third parasitic transistor is turned on.

[0081] When the third parasitic transistor is turned on, the wiring 216_j and the wiring of the adjacent pixel The line 216_j+1 is electrically connected. When the wiring 216_j and the wiring 216_j+1 are electrically connected, the image signals of both interfere with each other, and the correct It becomes difficult to supply accurate image signals to the liquid crystal element 112. For reasons such as reducing the size of the pixel electrode 210, the pixel electrode 210 is located close to the wiring 216_j and the wiring 216_j+1. As the temperature rises, the effect of the third parasitic transistor becomes stronger.

[0082] Therefore, in this embodiment, a groove portion 230 is provided in the pixel 110 by removing the semiconductor layer 205. The groove 230 is formed to have a width equal to or smaller than the width of the wiring 212_i, so that the parasitic transistor described above does not occur. By providing the wiring so as to cross over both ends of the direction, the generation of the first parasitic transistor can be prevented. In addition, the groove 230 is designed to cross over both ends of the wiring 203 in the line width direction. By doing so, it is possible to prevent the generation of the second parasitic transistor. A plurality of upper grooves 230 or grooves 230 on the wiring 203 may be provided.

[0083] The groove 230 is formed between the pixel electrode 210 and the wiring 216_j or between the pixel electrode 210 and the wiring 216_j. The wiring 216 is connected to at least one of the wirings 216_j+1 of the adjacent pixels. The end 231 of the pixel electrode 210 and the end 232 of the pixel electrode 210 are aligned in the direction in which the wiring 216_j or the wiring 216_j+1 extends. and beyond the edge 232. This prevents the formation of a third parasitic transistor. It should be noted that the wiring 216_j or the wiring 216_j+1 is set along the extending direction. The groove 230 is parallel to the direction in which the wiring 216_j or the wiring 216_j+1 extends. The conductor need not necessarily be provided with a bent or curved portion, but may have a bent or curved portion.

[0084] In FIG. 1, the groove 230 is interrupted in the region sandwiched between the wiring 212_i and the wiring 203. However, the groove 230 provided beyond the end of the wiring 212_i in the line width direction is extended, and the wiring 2 Alternatively, the groove 230 may be connected to the end of the wiring 03 in the line width direction.

[0085] Furthermore, the groove 230 is not provided on the wiring 203, and the potential of the wiring 203 is is set to a potential lower than the potential supplied to the wiring 216_j+1, However, in this case, the potential is applied to the wiring 203. A separate power source must be provided to supply the power.

[0086] There is no particular limitation on the size of the groove 230 where the semiconductor layer 205 is removed. In order to reliably prevent the generation of a resistor, the direction in which the wiring 216_j or the wiring 216_j+1 extends is The width of the portion of the groove 230 where the semiconductor layer is removed in the direction perpendicular to the direction of the groove 230 is 1 μm or more. It is preferable that the thickness is 2 μm or more, and more preferable that the thickness is 2 μm or more.

[0087] The cross section A1-A2 shows the stacked structure of the transistor 111 and the capacitor element 113. The transistor 111 is a bottom gate structure transistor called a channel etching type. The cross section B1-B2 shows the wiring 216_j including the pixel electrode 210 and the groove portion 230. The cross section C1-C2 shows the laminated structure from the wiring 216_j+1 to the wiring 216_j+2. 16_j and the laminated structure at the intersection of the wiring 212_i. D2 indicates a stacked structure of the interconnect 216_j+1, the intersection of the interconnect 212_i, and the groove 230. is doing.

[0088] In the cross section A1-A2 shown in FIG. 2(A), an underlayer 201 is formed on a substrate 200. A gate electrode 202 and a wiring 203 are formed on the earth layer 201. A gate insulating layer 204 and a semiconductor layer 205 are formed on the gate electrode 202 and the wiring 203 . In addition, a source electrode 206a and a drain electrode 206b are formed on the semiconductor layer 205. In addition, a source electrode 206a and a drain electrode 206b are in contact with a part of the semiconductor layer 205. An insulating layer 207 is formed on the insulating layer 207. A pixel electrode 210 is formed on the insulating layer 207. The drain electrode 206b is electrically connected to the insulating layer 207 through a contact hole 208 formed in the insulating layer 207. are electrically connected.

[0089] The wiring 203 and the drain electrode 206b sandwich the gate insulating layer 204 and the semiconductor layer 205 therebetween. The overlapping portion functions as a capacitor element 113. The dielectric layer 05 functions as a dielectric layer. By using a multi-layer structure for the dielectric layers, even if a pinhole occurs in one dielectric layer, the pinhole Since it is covered with another dielectric layer, the capacitive element 113 can function normally. Since the relative dielectric constant of the oxide semiconductor is as high as 14 to 16, the oxide semiconductor is used as the semiconductor layer 205. By using the above, the capacitance value of the capacitor 113 can be increased.

[0090] In the cross section B1-B2 shown in FIG. 2(B), an underlayer 201 is formed on a substrate 200. A gate insulating layer 204 is formed on the earth layer 201, and a semiconductor layer 205 is formed on the gate insulating layer 204. The wiring 216_j and the wiring 216_j+1 are formed on the semiconductor layer 205. An insulating layer 207 is formed on the semiconductor layer 205, the wiring 216_j, and the wiring 216_j+1. In addition, a pixel electrode 210 is formed on the insulating layer 207.

[0091] Between the wiring 216_j+1 and the pixel electrode 210, a part of the semiconductor layer 205 and the insulating layer 20 7 is removed to form a groove 230. The groove 230 has at least a bottom surface The semiconductor layer is not included in the structure.

[0092] In the cross section C1-C2 shown in FIG. 2(C), a base layer 201 is formed on a substrate 200. A wiring 212_i is formed on the earth layer 201. A gate insulating film is formed on the wiring 212_i. An insulating layer 204 and a semiconductor layer 205 are formed on the semiconductor layer 205. An insulating layer 207 is formed on the wiring 216_j.

[0093] In the cross section D1-D2 shown in FIG. 2(D), an underlayer 201 is formed on a substrate 200. A wiring 212_i is formed on the earth layer 201. A gate insulating film is formed on the wiring 212_i. An insulating layer 204 and a semiconductor layer 205 are formed on the semiconductor layer 205. j+1 is formed on the wiring 216_j+1, and an insulating layer 207 is formed on the wiring 216_j+1. A groove 230 is formed by removing a part of the body layer 205 and a part of the insulating layer 207. In addition, the gate insulating layer 204 is exposed at the bottom of the groove 230, and the wiring 2 below it is 12_i is not exposed.

[0094] Next, examples of pixel configurations different from the configuration shown in FIG. 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a top view showing the planar configuration of the pixel 120. The cross sections A1-A2, E1-E2, and F1-F2 are the same as those in FIG. -E2, F1-F2 correspond to the cross section of the part indicated by the chain line. ,In Figure 3, the illustration of some components is omitted.

[0095] The pixel 120 shown in FIG. 3 differs from the pixel 110 shown in FIG. 1 in the planar shape of the groove 230. 3. The structure of the portion indicated by the chain line A1-A2 in FIG. 3 corresponds to the cross section A1 described in FIG. 2(A). The cross section E1-E2 has the same structure as the cross section B1-B2. This is the same as the configuration in which a groove 230 is provided between the element electrode 210 and the wiring 216_j. The configuration of the plane F1-F2 is the same as the configuration of the cross section D1-D2 with the left and right sides swapped.

[0096] The pixel 120 has a groove 230 between the pixel electrode 210 and the wiring 216_j, and between the pixel electrode 210 and the wiring 216_j. 10 and the wiring 216_j+1 of the adjacent pixel. The groove 230 is set so as to cross over the ends of the wiring 212_i and the wiring 203 in the width direction. The wiring 212_i is not only provided in the area between the wiring 212_i and the wiring 203, but also in the area between the wiring 212_i and the wiring 203. As described above, by widely arranging the groove portion 230, the generation of a parasitic channel or a parasitic transistor can be prevented. can be more reliably prevented.

[0097] Next, an example of a pixel configuration different from the configurations shown in FIGS. 1 to 4 will be described with reference to FIG. 5. 5A is a top view showing the planar configuration of the pixel 130. -G2 corresponds to the cross section of the region indicated by the chain line G1-G2 in FIG. 5(A). The pixel 130 uses a conductive layer with high light reflectivity for the pixel electrode 211, and thus the pixel 130 is a reflective liquid crystal display. 1 shows an example of a pixel configuration that can be applied to a display device.

[0098] In the pixel 130, the grooves 251 and 252 where the semiconductor layer 205 has been removed are connected to the wiring 212. The wiring 212_i is provided so as to extend across both ends of the wiring 212_i in the line width direction. By providing a plurality of grooves that cross over both ends of the wiring 212_i, the wiring 212_i is formed to overlap with the wiring 212_i. The influence of parasitic channels can be more reliably suppressed.

[0099] In addition, in the pixel 130, the grooves 253 and 254 where the semiconductor layer 205 has been removed are used as wiring. The wiring 203 is provided so as to extend across both ends of the wiring 203 in the line width direction. By providing a plurality of grooves that cross over both ends, parasitic circuits formed by overlapping with the wiring 203 can be prevented. This can more reliably suppress the influence of the channel.

[0100] In addition, in the pixel 130, the grooves 255 and 256 where the semiconductor layer 205 has been removed are used as wiring. The pixel 216_j or the adjacent pixel 216_j+1 has a wiring extending direction. The wiring 216_j is provided beyond the end 233 and the end 234 of the element electrode 211. or along the direction in which the wiring 216_j+1 extends, the end 233 and the end 234 of the pixel electrode 211 By providing a plurality of grooves beyond the portion 234, a parasitic circuit formed by overlapping with the pixel electrode 211 can be prevented. The influence of the channel can be more reliably suppressed. The grooves 255 and 256 provided along the direction in which the wiring 216_j+1 extends are Alternatively, the wiring 216_j+1 does not need to be provided parallel to the extending direction, and may be provided at the bend or Alternatively, the slit may have a curved portion.

[0101] The grooves 255 and 256 of the pixel 130 have curved portions, and a part of the grooves 255 and 256 is connected to the pixel electrode 21. 1. The pixel 130 is formed to overlap with the pixel electrode 211. In this way, the grooves 257 and 258 overlap the pixel electrode 211. By providing the portions 255 and the grooves 258, it is possible to provide irregularities on the surface of the pixel electrode 211. By providing the surface of the pixel electrode 211 with irregularities, incident external light is diffused and a better image can be obtained. Therefore, the visibility of the display is improved.

[0102] The grooves 255 to 258 formed to overlap the pixel electrode 211 have side surfaces A tapered shape is preferable because it improves coverage of the pixel electrode 211 .

[0103] Next, regarding the configuration example of terminals 105_1 to 105_m and terminals 106_1 to 106_n, 7A1 and 7A2 show the terminals 105_1 to 105_m. 7A and 7B show a top view and a cross-sectional view of the same, respectively. The dashed line corresponds to the cross section J1-J2 in FIG. 7(A2). B2) shows a top view and a cross-sectional view of the terminals 106_1 to 106_n, respectively. The dashed line K1-K2 in FIG. 7(B1) corresponds to the cross section K1-K2 in FIG. 7(B2). In the cross section J1-J2 and the cross section K1-K2, J2 and K2 are the substrate ends. In order to make the drawing easier to understand, some components are omitted in FIG. is doing.

[0104] In the cross section J1-J2, an underlayer 201 is formed on a substrate 200, and a layer 202 is disposed on the underlayer 201. A line 212_i is formed on the wiring 212_i. In addition, a gate insulating layer 204, a semiconductor A dielectric layer 205 and an insulating layer 207 are formed on the dielectric layer 205. An electrode 221 is formed on the insulating layer 207. The electrode 221 is formed on the gate insulating layer 204, the semiconductor layer 205, and the insulating layer 207. The wiring 212_i is electrically connected to the wiring 212_i through a contact hole 219 formed therein.

[0105] In the cross section K1-K2, a base layer 201, a gate insulating layer 204, and A semiconductor layer 205 is formed. A wiring 216_j is formed on the semiconductor layer 205. An insulating layer 207 is formed on the insulating layer 207. An electrode 222 is formed on the insulating layer 207. The electrode 222 is connected to the wiring 216 via a contact hole 220 formed in the insulating layer 207. _j is electrically connected to

[0106] The configuration of the terminal 107 is also the same as that of the terminals 105_1 to 105_m or the terminals 106_1 to 106_m. _n can be configured in the same way.

[0107] The pixel region 102 and the terminal section 104 are connected by n wires 216_1 to 216_n. However, from the pixel region 102 to the terminals 106_1 to 106_n of the terminal section 104, In the routing of the wiring 216_1 to 216_n, the adjacent wirings 216_1 to 216 When adjacent wirings 216_1 to 216_n are close to each other, the potential difference between the adjacent wirings 216_1 to 216_n A parasitic channel is formed in the semiconductor layer 205 between the wirings 216_1 to 216_n. Therefore, there is a risk that adjacent wirings 216_1 to 216_n may be electrically connected to each other unintentionally. be.

[0108] This phenomenon occurs in the entire area from the pixel area 102 to the terminal area 104 or in the adjacent areas. A conductive layer is provided on the semiconductor layer 205 between the wirings 216_1 to 216_n via an insulating layer, By setting the potential of the conductive layer to a potential at which a parasitic channel is not formed in the semiconductor layer 205, It can be prevented.

[0109] For example, when an oxide semiconductor is used for the semiconductor layer 205, most oxide semiconductors are n-type semiconductors. Therefore, the potential of the conductive layer is set higher than the potential supplied to the wirings 216_1 to 216_n. The potential may be set to a low level.

[0110] In the contact hole forming step described later, the adjacent wirings 216_1 to 216_2 By removing the semiconductor layer 205 between the adjacent wirings 216_1 to 216_n, Unintentional electrical connections can be prevented.

[0111] In FIG. 8, a groove 240 is formed between adjacent wirings 216_j, 216_j+1, and 216_j+2. 8A shows a structure in which the terminals 106_j, 106_j are formed and the semiconductor layer 205 is removed. Wiring 216_j, 216_j+1, 216_j+ connected to 6_j+1, 106_j+2 8(A). The cross section L1-L2 shown in FIG. 8(B) is a top view showing the planar configuration of the semiconductor device 2. 8A, the wiring 21 corresponds to the cross section of the portion indicated by the dashed line L1-L2 in FIG. 6_j is connected to the terminal 106_j, and the wiring 216_j+1 is connected to the terminal 106_j+1. The wiring 216_j+2 is connected to the terminal 106_j+2. 8A, the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 205 are The edge layer 207 is not shown.

[0112] In the cross section L1-L2 shown in FIG. 8(B), a base layer 201, a gate insulating film 202, and a gate insulating film 204 are formed on a substrate 200. A layer 204 and a semiconductor layer 205 are formed on the semiconductor layer 205. 6_j, wiring 216_j+1, and wiring 216_j+2 are formed. An insulating layer 207 is formed on the wiring 216_j, the wiring 216_j+1, and the wiring 216_j+2. It is being done.

[0113] In addition, the semiconductor layer 205 is removed between the adjacent wiring 216_j and wiring 216_j+1. In addition, a groove portion 240 is formed between the adjacent wiring 216_j+1 and the wiring 216_j+ 2, a groove portion 240 is formed by removing the semiconductor layer 205 (FIG. 8(A), FIG. 8(B)). In this way, the semiconductor layer 205 is formed between the adjacent wirings 216_1 to 216_n. By providing the removed groove portion 240, the adjacent wirings 216_1 to 216_n can be separated from each other. The groove 240 is formed in the same process as the groove 230. It is possible.

[0114] There is no particular limitation on the size of the groove 240 where the semiconductor layer 205 is removed. In order to reliably prevent the generation of a loop, the direction in which the wiring 216_j or the wiring 216_j+1 extends is The width of the portion of the groove 240 where the semiconductor layer is removed in the perpendicular direction is set to 1 μm or more. It is preferable that the thickness is 2 μm or more, and more preferable that the thickness is 2 μm or more.

[0115] Next, the pixel portion of the liquid crystal display device described with reference to FIGS. 1 and 2 and the pixel portion of the liquid crystal display device described with reference to FIG. A method for manufacturing the terminals 105 and 106 will be described with reference to FIGS. 9 and 10 is taken along the dashed line A1-A2 in FIG. 1. 11 and 12. Also, the cross section D1-D2 in FIG. J1-J2 and cross section K1-K2 correspond to D1-D2 and J1-J2 in FIGS. 1 and 7. 1 and K1-K2 are cross-sectional views of the areas indicated by the dashed dotted lines.

[0116] First, an insulating layer to be the underlayer 201 is formed on the substrate 200 to a thickness of preferably 50 nm to 300 nm. The thickness of the film is usually between 100 nm and 200 nm (see FIG. 9(A) and FIG. 11(A)). The substrate 200 may be a glass substrate, a ceramic substrate, or any other substrate that can withstand the processing temperature of this manufacturing process. A plastic substrate or the like having a high degree of heat resistance can be used. If this is not the case, a metal substrate such as a stainless steel alloy with an insulating layer on its surface may be used. The glass substrate may be, for example, barium borosilicate glass or aluminoborosilicate glass. It is advisable to use a non-alkali glass substrate such as glass or aluminosilicate glass. The substrate 200 may be a silicon substrate, a sapphire substrate, or the like. (550mm x 650mm), 3.5th generation (600mm x 720mm, or 620mm m x 750 mm), 4th generation (680 mm x 880 mm, or 730 mm x 920 mm ), 5th generation (1100mm x 1300mm), 6th generation (1500mm x 1850mm ), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 2400mm ), 9th generation (2400mm x 2800mm, 2450mm x 3050mm), 10th generation A glass substrate of a size of 2950 mm×3400 mm or the like can be used. In this example, aluminoborosilicate glass is used for the substrate 200.

[0117] The underlayer 201 is made of aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, or the like. silicon, silicon oxide, silicon nitride oxide, or silicon oxynitride It can be formed by a laminated structure of multiple insulating layers, and impurity elements from the substrate 200 It should be noted that in this specification, silicon nitride oxide refers to a compound The composition is preferably a mixture of nitrogen and oxygen, and preferably a mixture of Rutherford back-flow and Rutherford Backscattering Spec (RBS) Hydrogen Forward Scattering Spectroscopy (HFS) When measured using Scattering Spectrometry (RDScattering Spectrometry), the composition The range is 5 atomic % or more and 30 atomic % or less of oxygen, 20 atomic % or more and 55 atomic % or less of nitrogen, Silicon is contained in the range of 25 atomic % to 35 atomic % and hydrogen is contained in the range of 10 atomic % to 30 atomic %. The underlayer 201 is formed by a method such as sputtering, CVD, coating, or printing. It can be used as appropriate.

[0118] Furthermore, by making the underlayer 201 contain halogen elements such as chlorine and fluorine, the substrate 200 The function of preventing or reducing the diffusion of impurity elements from the underlayer can be further enhanced. The concentration of halogen elements contained in 201 is determined by the concentration peak obtained by SIMS analysis. In the case of 15 / cm 3 More than 1×10 20 / cm 3 The following would suffice.

[0119] In this embodiment, a base layer 201 is formed on a substrate 200 using a plasma CVD method. The silicon oxynitride layer 201 is formed to a thickness of 200 nm. For example, the substrate 200 is heated to 350°C or higher. The underlayer 201 is formed while heating the substrate to a temperature of 450° C. or less. For example, the substrate is heated to 350° C. This is done by heating.

[0120] After the formation of the underlayer 201, the underlayer 201 may be heated under reduced pressure, a nitrogen atmosphere, a rare gas atmosphere, or an ultra-dry atmosphere. Heat treatment may be performed under an atmosphere. The concentration of hydrogen, moisture, hydrides, hydroxides, etc. can be reduced. The temperature is preferably higher than the temperature that the substrate 200 can withstand. For this purpose, it is preferable to perform the treatment at a temperature equal to or higher than the deposition temperature of the underlayer 201 and equal to or lower than the strain point of the substrate 200 .

[0121] The hydrogen concentration in the underlayer 201 is 5×10 18 atoms / cm 3 Less than, preferably 1×10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 It is desirable to do the following:

[0122] After the formation of the underlayer 201, oxygen (at least oxygen radicals, oxygen atoms) is added to the underlayer 201. The underlayer 201 is made to have a stoichiometric composition by introducing oxygen ions or oxygen ions. The introduction of oxygen may be performed by using an ion-rich region (an oxygen-excess region). Ion implantation, ion doping, plasma immersion ion implantation, etc. In addition, heat treatment under an oxygen atmosphere or It can also be performed by plasma treatment or the like.

[0123] Furthermore, the introduction of oxygen can also cause the formation of bonds between the elements constituting the underlayer 201 and hydrogen, or the bonds between the elements The bond between the hydrogen and the hydroxyl group is broken, and these hydrogen or hydroxyl groups react with oxygen. Since water is generated by the addition of oxygen, if heat treatment is performed after the introduction of oxygen, the impurities hydrogen or hydroxide Therefore, after introducing oxygen into the underlayer 201, the heat treatment Thereafter, oxygen may be further introduced into the underlayer 201, and the underlayer 201 may be subjected to an oxygen permeation treatment. The introduction of oxygen into the underlayer 201 and the heat treatment may be performed alternately. The oxygen introduction and the heat treatment may be carried out simultaneously.

[0124] Next, a 100% silicon dioxide film is formed on the underlayer 201 by sputtering, vacuum deposition, or plating. The conductive layer is formed to a thickness of 200 nm to 300 nm, preferably 200 nm to 300 nm. A resist mask is formed by a first photolithography process, and a part of the conductive layer is Selective etching is performed to form the gate electrode 202, the wiring 203, and the wiring 212_i. (See Figure 9(A) and Figure 11(A)).

[0125] The conductive layer for forming the gate electrode 202, the wiring 203, and the wiring 212_i is made of molybdenum. (Mo), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (A l), copper (Cu), chromium (Cr), neodymium (Nd), scandium (Sc), and other metals It can be formed as a single layer or a laminate using a material or an alloy material containing these as the main component. do.

[0126] For example, a single layer structure using aluminum containing silicon, or titanium layered on aluminum Two-layer structure with titanium on titanium nitride, two-layer structure with titanium on titanium nitride, tungsten on titanium nitride Two-layer structure with tungsten laminated on tantalum nitride, two-layer structure with Cu-Mg- Two-layer structure with Cu layered on Al alloy, copper layered on titanium nitride, and titanium layered on top of that. Examples include a three-layer structure in which stainless steel is laminated.

[0127] The conductive layer may be formed of indium tin oxide, indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, acid Indium tin oxide containing titanium dioxide, indium zinc oxide, indium with silicon dioxide added Alternatively, a conductive material having a light-transmitting property such as zinc tin oxide may be used. It is also possible to use a laminated structure of a conductive material having optical properties and a material containing the above metal element.

[0128] The conductive layer may be made of a metal oxide containing nitrogen, specifically, an In-Ga- Zn-based oxides, nitrogen-containing In-Sn-based oxides, nitrogen-containing In-Ga-based oxides, In-Zn oxides containing nitrogen, Sn oxides containing nitrogen, and In oxides containing nitrogen Alternatively, metal nitrides (InN, SnN, etc.) can be used.

[0129] These materials have a work function of 5 eV (electron volts) or more, and when used as a gate electrode, In this case, the threshold voltage of the electrical characteristics of the transistor can be made positive, and the so-called normal It is possible to realize an n-type transistor in the off state.

[0130] Since the conductive layer will be used as wiring, it is preferable to use low resistance materials such as Al and Cu. By using u, it is possible to reduce signal delay and achieve high image quality. It has low heat resistance and is prone to defects due to hillocks, whiskers, or migration. To prevent Al migration, Mo, Ti, W, and other metals are added to Al. It is preferable to laminate a metal material with a high melting point.

[0131] The conductive layer can be etched by a dry etching method or a wet etching method. In addition, the conductive layer is etched by both dry etching and wet etching. The resist mask formed on the conductive layer may be formed by photolithography. A printing method, an ink-jet method, or the like can be used as appropriate. When the film is formed by the PET method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0132] When etching the conductive layer by dry etching, halogen is used as the etching gas. A gas containing a halogen element can be used. An example of a gas containing a halogen element is chlorine ( Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4) or carbon tetrachloride (C Chlorine gases such as chlorine (Cl4), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6 ), nitrogen trifluoride (NF3) or trifluoromethane (CHF3) are typical examples. Fluorine-based gas, hydrogen bromide (HBr) or oxygen can be used as appropriate. An inert gas may be added to the etching gas. The horizontal plate type RIE (Reactive Ion Etching) method and the ICP (Inductively Coupled Plasma) method are Inductively Coupled Plasma (Inductively Coupled Plasma) etching method The etching conditions (coil) can be adjusted to allow etching to a desired processed shape. The amount of power applied to the electrode on the substrate side, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc. ) and adjust accordingly.

[0133] In this embodiment, a conductive layer is formed on the underlayer 201 by sputtering to a thickness of 100 nm. A tungsten film having a thickness of 1000 nm is formed. Then, a conductive layer is selected by a first photolithography process. The gate electrode 202, the wiring 203, and the wiring 212_i are formed (FIG. 9(A)). In addition, the ends of the formed gate electrode 202, wiring 203, and wiring 212_i are tapered. The bar shape is preferable because it improves the coverage of the insulating layer and conductive layer to be laminated later.

[0134] Specifically, the cross-sectional shapes of the gate electrode 202, the wiring 203, and the wiring 212_i are trapezoidal or triangular. The ends of the gate electrode 202, the wiring 203, and the wiring 212_i are tapered to form an angular shape. Here, the taper angles of the ends of the gate electrode 202, the wiring 203, and the wiring 212_i are The angle θ is set to 60° or less, preferably 45° or less, and more preferably 30° or less. The taper angle θ is the angle at which a layer having a tapered shape is formed on its cross section (a plane perpendicular to the surface of the substrate). When observed from a vertical direction, it indicates the inclination angle between the side and bottom surfaces of the layer. If the angle is less than 90°, it is called a forward taper, and if the taper angle is 90° or more, it is called a reverse taper. By making the edge of each layer tapered, the layer formed on top of it is discontinuous. This prevents the phenomenon of the film breaking apart (step discontinuity) and improves the coating properties.

[0135] In addition, the gate electrode 202, the wiring 203, and the wiring 212_i are formed into a laminated structure consisting of multiple layers. As a result, the ends of the gate electrode 202, the wiring 203, and the wiring 212_i can be formed in a stepped shape. This can prevent the layer formed thereon from being cut off, improving coverage.

[0136] Unless otherwise specified, the photolithography process referred to in this specification includes resist masking. a step of forming a resist mask, a step of etching a conductive layer or an insulating layer, and a step of removing the resist mask shall be included.

[0137] Next, a gate insulating layer 204 is formed on the gate electrode 202, the wiring 203, and the wiring 212_i. (See FIG. 9B and FIG. 11B.) The gate insulating layer 204 is made of silicon oxide, nitride, or the like. Silicon, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride , aluminum oxide nitride, aluminum oxide nitride, tantalum oxide, gallium oxide, iridium oxide Tritium, lanthanum oxide, hafnium oxide, hafnium silicate, and nitrogen were introduced. Hafnium silicate, hafnium aluminate with nitrogen introduced, etc. can be used. The gate insulating layer can be formed by a plasma CVD method, a sputtering method, or the like. 204 is not limited to a single layer and may be a laminate of different layers. For example, as the gate insulating layer A, Silicon nitride is formed by CVD and oxidized as gate insulating layer B on top of gate insulating layer A. The gate insulating layer 204 may be formed of silicon.

[0138] Generally, a capacitance element has a structure in which a dielectric is sandwiched between two opposing electrodes, and the thickness of the dielectric is The thinner the electrode (the shorter the distance between the two opposing electrodes) and the higher the dielectric constant of the dielectric, However, if the dielectric is made thinner to increase the capacitance of the capacitive element, The leakage current between the two electrodes is likely to increase, and the dielectric strength of the capacitance element is reduced. It becomes easier.

[0139] The overlapping portion of the gate electrode, gate insulating layer, and semiconductor layer of the transistor is the capacitance element described above. The gate insulating layer of the semiconductor layer functions as a capacitor (hereinafter also referred to as "gate capacitance"). A channel is formed in the region overlapping the gate electrode via the gate electrode. The channel forming region functions as two electrodes of the capacitor element, and the gate insulating layer functions as the dielectric of the capacitor element. It is preferable that the gate capacitance is large, but in order to increase the capacitance, Furthermore, if the gate insulating layer is made thinner, problems such as an increase in leakage current and a decrease in dielectric strength voltage will occur. is likely to occur.

[0140] On the other hand, the gate insulating layer 204 is made of hafnium silicate (HfSi x O y (x>0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y >0, z>0), nitrogen-doped hafnium aluminate (HfAl x O y N z (x >0, y>0, z>0), high-k materials such as hafnium oxide and yttrium oxide When the gate insulating layer 204 is thick, the thickness of the gate electrode 202 and the semiconductor layer 205 is It is possible to ensure a sufficient capacitance value.

[0141] For example, if a high-k material with a large dielectric constant is used as the gate insulating layer 204, Even if the insulating layer 204 is made thick, the capacitance is the same as when silicon oxide is used for the gate insulating layer 204. Since the amount of the gate electrode 202 can be reduced, the leakage current generated between the gate electrode 202 and the semiconductor layer 205 can be reduced. In addition, a wiring formed using the same layer as the gate electrode 202 and a wiring overlapping the wiring can be formed. This reduces the leakage current that occurs between other wiring. Silicon oxide nitride, silicon nitride, silicon oxide nitride, aluminum oxide, oxynitride It may also have a laminated structure with at least one of aluminum oxide and gallium oxide. The thickness of the insulating layer 204 is 10 nm or more and 300 nm or less, and more preferably 50 nm or more and 200 nm or less. For example, the gate insulating layer 204 may have a thickness of 10 nm to 50 nm. A laminated structure of silicon nitride and silicon oxynitride with a thickness of 100 nm to 300 nm. It may also be constructed as such.

[0142] The temperature during the formation of the gate insulating layer 204 is set to the temperature of the substrate 200 and the gate electrode 202 (the same layer). The higher the temperature, the better, as long as it is within the temperature that the device (including wiring formed by The substrate 200 is heated to 350° C. or more and 450° C. or less to form the insulating layer 204. A silicon oxynitride film with a thickness of 100 nm is formed by plasma CVD. It is preferable that the temperature during the formation of the insulating layer 204 is constant. The deposition is carried out by heating the substrate 200 to 350°C.

[0143] After the gate insulating layer 204 is formed, the gate insulating layer 204 is heated under reduced pressure, a nitrogen atmosphere, a rare gas atmosphere, or a superheated atmosphere. Heat treatment may be performed in a dry air atmosphere. The concentration of hydrogen, moisture, hydrides, or hydroxides contained in 4 can be reduced. The temperature of the heat treatment is preferably higher than the temperature that the substrate 200 can withstand. Specifically, the temperature is set to be equal to or higher than the temperature at which the gate insulating layer 204 is formed and equal to or lower than the strain point of the substrate 200. It is preferable that:

[0144] The hydrogen concentration in the gate insulating layer 204 is 5×10 18 atoms / cm 3 Less than preferred Or 1 x 10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 It is desirable to do the following: .

[0145] When an oxide semiconductor is used for the semiconductor layer 205, the gate insulating layer 204 is It is preferable that the gate insulating layer 204 contains oxygen in the portion in contact with the layer 05. It is preferable that oxygen is present in the bulk in an amount exceeding the stoichiometric ratio, e.g. For example, when silicon oxide is used as the gate insulating layer 204, SiO 2+α (just and α>0).

[0146] The gate insulating layer 204 can be formed by a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, or the like. It can be formed by appropriately using an ALD method or the like. z) can be applied. 204 is a plate on which a plurality of substrate surfaces are set approximately perpendicular to the sputtering target surface. Alternatively, the film may be formed using a sputtering device that forms a film in a heated state.

[0147] After the gate insulating layer 204 is formed, the gate insulating layer 204 is The gate insulating layer 204 is chemically doped with silicon dioxide (containing any of chlorine, oxygen atoms, and oxygen ions). It may be in a state where there is a region where there is more oxygen than in the stoichiometric composition (where there is an oxygen excess region). The introduction of elements is performed by ion implantation, ion doping, plasma immersion ion implantation, etc. It can be done by heat treatment in an oxygen atmosphere or by using an oxygen atmosphere. It can also be performed by plasma treatment in a nitrogen atmosphere.

[0148] Furthermore, the introduction of oxygen can also cause a bond between the elements constituting the gate insulating layer 204 and hydrogen, or The bond between the element and the hydroxyl group is broken, and the hydrogen or hydroxyl group reacts with oxygen. Therefore, if the heating process is performed after the introduction of oxygen, the impurities hydrogen or Therefore, when oxygen is introduced into the gate insulating layer 204, the hydroxyl group is easily released as water. After that, oxygen may be further introduced into the gate insulating layer 204, and the gate insulating layer 204 may be heated. The gate insulating layer 204 may be in an oxygen-excess state. The introduction and the heat treatment may be alternately repeated several times. Heat treatment may be carried out simultaneously.

[0149] When an oxide semiconductor is used for the semiconductor layer 205, a large amount of oxygen (excessive oxygen) is used as an oxygen supply source. The gate insulating layer 204 containing the gate insulating layer 204 is provided in contact with the semiconductor layer 205. Oxygen can be supplied from the gate insulating film 4 to the semiconductor layer 205. The semiconductor layer 205 is heated with the edge layer 204 in contact with at least a portion of the edge layer 204. By supplying oxygen to the semiconductor layer 205, the semiconductor layer It can compensate for the oxygen deficiency in 205.

[0150] In this embodiment, silicon oxynitride is used for the gate insulating layer 204. Specifically, A silicon oxynitride film is formed on the gate electrode 202 to a thickness of 100 nm.

[0151] Next, a semiconductor that will become the semiconductor layer 205 is formed on the gate insulating layer 204 (FIG. 9(B), (See FIG. 11B.) In this embodiment, an oxide semiconductor is used for the semiconductor layer 205. In addition, prior to the formation of the oxide semiconductor, the semiconductor layer 205 is formed in contact with the gate insulating layer 204. The area to be flattened may be subjected to flattening treatment. The flattening treatment is not particularly limited, but may be performed by Polishing treatment (e.g., Chemical Mechanical Polishing) Chemical Mechanical Polishing (CMP), dry etching, and plasma treatment can be used. do.

[0152] The plasma treatment may be, for example, a reverse plasma treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma near the substrate, thereby modifying the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the cleaning is performed, powdery substances (particles, dust, etc.) adhering to the surface of the gate insulating layer 204 are removed. (also called) can be removed.

[0153] In addition, polishing, dry etching, and plasma treatment are performed multiple times as planarization processes. In addition, when the steps are combined, the order of the steps may be There are no particular limitations on the thickness, and it may be set appropriately according to the unevenness of the surface of the gate insulating layer 204.

[0154] Oxide semiconductors can be grown by sputtering, evaporation, PCVD, PLD, ALD, or M The oxide semiconductor can be formed by a BE method or the like. For example, deposition by sputtering in an atmosphere of 100% oxygen is performed under conditions that include The film is formed by using a method containing a large amount of oxygen (preferably an oxide semiconductor in a crystalline state). It is preferable to form a film containing a region in which the oxygen content is excessive relative to the stoichiometric composition. stomach.

[0155] The target for producing an oxide semiconductor by sputtering is, for example, In, Ga, and Zn-containing metal oxides were prepared by the following method: In2O3:Ga2O3:ZnO=1:1:1 [mol A target having a composition of In2O3:Ga2O3 can be used. :ZnO=1:1:2 [molar ratio], In2O3:Ga2O 3:ZnO=1:1:4 [molar ratio], or In2O3: Use a target with a composition of Ga2O3:ZnO=2:1:8 [molar ratio] It is also possible.

[0156] The relative density of the metal oxide target is 90% or more and 100% or less, preferably 95% or more. By using a metal oxide target with a high relative density, The deposited oxide semiconductor can be made into a dense film.

[0157] The oxide semiconductor film was formed by holding the substrate in a processing chamber maintained in a reduced pressure state and raising the substrate temperature to 10 The temperature is 0°C or higher and 600°C or lower, preferably 300°C or higher and 500°C or lower.

[0158] By forming the film while heating the substrate, hydrogen, moisture, and It is possible to reduce the concentration of impurities such as hydrides or hydroxides. Damage caused by heating is reduced. A sputtering gas from which the oxide has been removed is introduced, and an oxide semiconductor is formed using the target.

[0159] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions are suitable for a direct current (DC) power supply of 0.5 kW and an oxygen (oxygen flow rate 100%) atmosphere. When a pulsed DC power supply is used, the powdery substances (particles) generated during film formation are This is preferable because it can reduce the amount of dust (also called dust) and make the film thickness distribution uniform.

[0160] Even when the above sputtering apparatus is used, the oxide semiconductor formed contains at least a small amount of nitrogen. For example, nitrogen may be present in an oxide semiconductor at a concentration of 5×10 18 atoms / cm 3 May be present at concentrations less than

[0161] Here, a sputtering apparatus for forming an oxide semiconductor will be described in detail below.

[0162] The process chamber for forming the oxide semiconductor has a leak rate of 1×10 -10 Pa·m 3 / sec or less It is preferable to do so, so that impurities are prevented from being introduced into the film when the film is formed by sputtering. Contamination can be reduced.

[0163] To reduce the leak rate, it is necessary to reduce not only external leaks but also internal leaks. An external leak is when gas enters the vacuum system from outside due to a small hole or poor seal. Internal leaks are leaks from partitions such as valves in the vacuum system or leaks from internal components. Leak rate is 1×10 -10 Pa·m 3 / sec or less Therefore, measures must be taken to prevent both external and internal leaks.

[0164] To reduce external leakage, it is advisable to seal the opening and closing parts of the processing chamber with metal gaskets. Tal gaskets are coated with iron fluoride, aluminum oxide, or chromium oxide. It is preferable to use a metal material. Metal gaskets have a higher adhesion than O-rings, and they are In addition, passivation such as iron fluoride, aluminum oxide, and chromium oxide can reduce the By using a metal material coated with a fluorine-based compound, the released gas, including hydrogen, generated from the metal gasket can be prevented. This suppresses the internal leakage and reduces the internal leakage.

[0165] The inner wall of the processing chamber is made of aluminum and chromium, which emit less gas, including hydrogen. , titanium, zirconium, nickel or vanadium. It may be used by coating an alloy material containing chromium and nickel. The alloy material containing nickel is rigid, heat-resistant, and suitable for processing. If the surface roughness of the component is reduced by polishing or other methods to reduce the surface area, the released gas Alternatively, the components of the film forming apparatus may be replaced with iron fluoride, aluminum oxide, or crystalline oxide. It may be coated with a passivating material such as ROM.

[0166] Furthermore, a sputtering gas refiner may be installed immediately before the sputtering gas is introduced into the processing chamber. In this case, the length of the piping from the refiner to the treatment chamber is 5 m or less, preferably 1 m or less. By keeping the length of the piping at 5m or less or 1m or less, the influence of the gas emitted from the piping can be reduced. The reverberation can be reduced depending on the length.

[0167] The exhaust from the processing chamber is performed by a roughing pump such as a dry pump, a sputter ion pump, and a turbo pump. It is advisable to use a suitable combination of a sub-pump and a high vacuum pump such as a cryopump. In addition, to remove residual moisture in the processing chamber, an adsorption type vacuum pump, for example, a cryopump It is preferable to use a pump, an ion pump, or a titanium sublimation pump. While the sub-pump excels at pumping out large molecules, it has poor pumping ability for hydrogen and water. , a cryopump with high water pumping capacity or a sputter ion pump with high hydrogen pumping capacity It is also effective to combine a turbomolecular pump with a cold trap. The processing chamber may be evacuated using an adsorption type vacuum pump such as a cryopump. For example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably carbon atoms Since impurities contained in the oxide semiconductor film formed in the treatment chamber (including compounds containing impurities) are exhausted, The concentration of pure substances can be reduced.

[0168] Adsorbates present inside the processing chamber are adsorbed to the inner wall and do not affect the pressure in the processing chamber. This causes gas emission when the processing chamber is evacuated. Although there is no correlation, a pump with high exhaust capacity is used to remove as much of the adsorbed matter as possible from the treatment chamber. It is important to evacuate the treatment chamber in advance. Baking is also possible. Baking increases the desorption rate of adsorbed substances by about 10 times. Baking can be performed at a temperature between 100°C and 450°C. By removing adsorbed substances while adding gas, it is possible to remove water and other substances that are difficult to remove by exhausting only. The speed can be further increased.

[0169] In the sputtering method, the power supply for generating plasma is an RF power supply, A A C power supply, a DC power supply, etc. can be used as appropriate. Note that a pulse DC power supply is used. This reduces the amount of powdery material (also called particles or dust) that is generated during film formation, and also improves film thickness distribution. This is preferable because it is uniform.

[0170] The thickness of the semiconductor layer 205 is 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. In this embodiment, the semiconductor layer 205 is formed by a sputtering device having an AC power supply. A 35 nm thick In-Ga-Zn oxide ( IGZO) is formed (see FIG. 9(B)). In-Ga-Zn oxide ternary oxide with an atomic ratio of 1:1:1 (=1 / 3:1 / 3:1 / 3) The film formation conditions are oxygen and argon atmosphere (oxygen flow rate 50%). ), pressure 0.6 Pa, power supply power 5 kW, and substrate temperature 170°C. The speed is 16 nm / min.

[0171] In addition, sodium (Na), lithium (Li), potassium (K) and other elements in oxide semiconductors The concentration of alkali metals is 5 x 10 16 cm -3 Less than 1 × 10 16 cm -3 or less, more preferably 1 × 10 15 cm -3 Below, Li is 5 × 10 15 cm -3 Below Below, preferably 1 x 10 15 cm -3 In the following, K is 5×10 15 cm -3 Below, preferably 1×10 15 cm -3 It is preferable to do the following:

[0172] Oxide semiconductors are insensitive to impurities, and there are many metal impurities in oxide semiconductors. It is not a problem if it contains a large amount of alkali metals such as sodium. It has been pointed out that d-lime glass can also be used (Kamiya, Nomura, Hosono, "Amorphous Oxide Semiconductors" "Physical properties of the body and the current status of device development," Solid State Physics, September 2009, Vol. 44, p. 6 21-633) However, this is not an appropriate indication. Alkali metals do not form oxide semiconductors. Alkaline earth metals are also impurities because they are not elements that form oxide semiconductors. In particular, Na, among alkali metals, is an impurity when it is not an element. When the insulating layer in contact with the conductor layer is an oxide, Na diffuses into the insulating layer. + Also, In the oxide semiconductor layer, Na breaks the bond between the metal and oxygen that constitute the oxide semiconductor. As a result, for example, the threshold voltage shifts in the negative direction. This leads to deterioration of transistor characteristics, such as normally-on and reduced mobility, due to the softening of the In addition, the characteristics of the transistors are also affected by impurities. The deterioration and variation of characteristics occur when the hydrogen concentration in the oxide semiconductor layer is sufficiently low. Therefore, when the hydrogen concentration in the oxide semiconductor is 5×10 19 cm -3 Below Below, especially 5x10 18 cm -3 If the concentration of the alkali metal in the oxide semiconductor is It is strongly recommended that the above values ​​be used.

[0173] The oxide semiconductor used for the semiconductor layer 205 is at least indium (In) or It is preferable that zinc (Zn) is contained. It is particularly preferable that both In and Zn are contained. A stabilizer for reducing variations in electrical characteristics of a transistor using the oxide semiconductor It is preferable that the stabilizer contains gallium (Ga) in addition to the above. It is preferable to have tin (Sn) as the catalyst, and hafnium as the stabilizer. It is preferable to use aluminum (Al) as a stabilizer. It is preferable that the stabilizer contains zirconium (Zr). is preferred.

[0174] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0175] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. , In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also known as IGZO) (Indicated as In-Al-Zn oxide, In-Sn-Zn oxide, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides Oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides , In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn -Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide Compounds can be used.

[0176] In addition, as an oxide semiconductor, the chemical formula InMO3(ZnO) containing element M is used. m (m>0) The element M may be Zn, Ga, Al, Fe, Mn, or C. o. In addition, the oxide semiconductor may be one or more metal elements selected from the following: In2SnO5(ZnO) n Materials expressed as (n>0) may also be used.

[0177] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 In-Ga-Zn oxides with atomic ratios of (=1 / 2:1 / 6:1 / 3) and their neighboring compositions Alternatively, an oxide of In:Sn:Zn=1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or is In-Sn with an atomic ratio of In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8). It is preferable to use a -Zn-based oxide or an oxide having a composition close to that.

[0178] However, oxide semiconductors containing indium are not limited to these, and may have the required semiconductor properties ( It is sufficient to use an appropriate composition depending on the characteristics (mobility, threshold, variation, etc.). In order to obtain the desired semiconductor characteristics, the carrier density, impurity concentration, defect density, metal element and oxygen It is preferable to make the atomic ratio, interatomic distance, density, etc., appropriate.

[0179] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0180] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), the oxide composition is close to (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 The above expression means that r satisfies the above condition, and r can be set to, for example, 0.05. The same is true for monsters.

[0181] The oxide semiconductor used for the semiconductor layer 205 may be single-crystal or polycrystalline (also referred to as polycrystalline). Or it may be in an amorphous state.

[0182] The oxide semiconductor used for the semiconductor layer 205 is preferably CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) Let's say.

[0183] CAAC-OS is neither completely single crystalline nor completely amorphous. The oxide semiconductor has a crystalline-amorphous mixed phase structure in which a crystalline portion is present in the amorphous phase. The part is often small enough to fit inside a cube with a side of less than 100 nm. Transmission Electron Microscope (TEM) In the observation image by pe), the boundary between the amorphous and crystalline parts in CAAC-OS is clear. In addition, grain boundaries (also called grain boundaries) were observed in the CAAC-OS by TEM. Therefore, the decrease in electron mobility due to grain boundaries is not observed in CAAC-OS. be suppressed.

[0184] The crystalline parts contained in the CAAC-OS have c-axes perpendicular to the surface on which the CAAC-OS is formed or to the surface. The atoms are aligned in a certain direction and have a triangular or hexagonal atomic arrangement when viewed from the direction perpendicular to the ab plane. When viewed from the direction perpendicular to the c-axis, metal atoms or metal atoms and oxygen atoms are arranged in layers. The orientation of the a-axis and b-axis may differ between different crystal parts. In this specification, when simply referring to a vertical angle, the angle also includes an angle between 85° and 95°. It will be decided.

[0185] In the CAAC-OS, the distribution of the crystal parts does not have to be uniform. In the process of forming an OS, when crystals are grown from the surface side of the oxide semiconductor film, The proportion of crystalline parts near the surface may be higher than that near the bottom. By adding impurities to the -OS, the crystalline portion in the impurity-doped region becomes amorphous. This may also occur.

[0186] The c-axis of the crystalline part of the CAAC-OS is perpendicular to the surface on which the CAAC-OS is formed or the surface. The shape of the CAAC-OS (cross-sectional shape of the surface to be formed or cross-sectional shape of the surface) The c-axis direction of the crystal part may be different depending on the CAAC. The direction perpendicular to the surface on which the -OS is formed. Alternatively, the film is formed by carrying out a crystallization treatment such as a heat treatment after the film is formed.

[0187] The electrical characteristics of transistors using CAAC-OS are stable when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0188] Note that part of oxygen contained in the oxide semiconductor film may be substituted with nitrogen.

[0189] In addition, in oxide semiconductors with crystalline parts such as CAAC-OS, defects in the bulk can be further reduced. By improving the surface flatness, the movement can be reduced more than that of an amorphous oxide semiconductor. To improve the flatness of the surface, it is necessary to deposit an oxide semiconductor on a flat surface. Specifically, it is preferable to form a surface having an average surface roughness (Ra) of 1 nm or less, preferably 0 It is preferable to form the surface on a surface with an interatomic thickness of 0.3 nm or less, more preferably 0.1 nm or less. It can be evaluated using an atomic force microscope (AFM). be.

[0190] However, since the transistor 111 described in this embodiment is a bottom-gate transistor, The gate electrode 202 is located below the gate insulating layer 204. After forming a gate insulating layer 204 on the gate electrode 202 to obtain The surface of the gate insulating layer 204 overlapping the electrode 202 is subjected to a planarization process such as a CMP process. It is also possible.

[0191] In addition, a semiconductor layer 205 is formed by sputtering an In-Ga-Zn oxide material. In this case, the atomic ratio is preferably In:Ga:Zn=1:1:1, 4:2:3, 3:1: In-Ga-Zn oxide tantalum with a ratio of 2, 1:1:2, 2:1:3, or 3:1:4 An In-Ga-Zn oxide target having the above atomic ratio can be used. By forming the semiconductor layer 205 using the target, a polycrystalline oxide semiconductor or CAAC- OS is more likely to form.

[0192] Before forming the oxide semiconductor to be the semiconductor layer 205, the oxide semiconductor is heated under reduced pressure, a nitrogen atmosphere, a rare gas atmosphere, or a nitrogen atmosphere. The heat treatment may be carried out in an atmosphere of nitrogen or ultra-dry air. Heat treatment may be performed in an atmosphere at a temperature of 350°C or higher and 450°C or lower. The heat treatment is carried out for 1 hour. The water adhering to the surface of the gate insulating layer 204 is removed by the heat treatment. It is possible to reduce impurities such as hydrogen, moisture, and hydrocarbons. It is preferable to form the oxide semiconductor layer successively without exposing the substrate 101 to the air. .

[0193] In addition, the process from the formation of the gate insulating layer 204 to the formation of the semiconductor layer 205 is not exposed to the atmosphere during the process. It is preferable to perform the steps in succession without exposing the gate insulating layer 204 and the oxide semiconductor layer to heat treatment. If the gate insulating layer 204 is formed continuously without being exposed to the air, hydrogen, moisture, and hydrogen may be generated on the surface of the gate insulating layer 204. This prevents impurities such as hydrocarbons from being adsorbed on the gate insulating layer. Since the interface between the oxide semiconductor layer and the oxide semiconductor layer can be kept clean, the reliability of the semiconductor device is improved. It is possible to improve the performance.

[0194] In addition, the semiconductor layer 205 is subjected to a process for removing (dehydrating or dehydrogenating) excess hydrogen (including water and hydroxyl groups). The temperature of the heat treatment is 300°C or more and 700°C or less. The heat treatment is carried out under reduced pressure, a nitrogen atmosphere, a rare gas atmosphere, or the like. This can be done anywhere.

[0195] In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the semiconductor layer 205 is The material was then heat treated for 1 hour at a temperature between 350°C and 450°C in a nitrogen atmosphere. Further, the mixture was heated at a temperature of 350°C to 450°C for 1 hour in a nitrogen and oxygen atmosphere. Heat treatment is performed, for example, at 350°C for 1 hour.

[0196] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device that heats the object to be treated by radiation may be used. For example, a GRTA (Gas Reactor Tank Apparatus) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp or other lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment An active gas is used.

[0197] For example, as a heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650 to 700°C. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0198] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0. It is preferable to keep the concentration at 1 ppm or less.

[0199] Furthermore, by heat treatment for dehydration or dehydrogenation, a main component material constituting an oxide semiconductor can be In oxide semiconductors, oxygen, which is the source of the oxide, may be released and reduced at the same time. Oxygen vacancies exist at the locations where the atoms are desorbed, and the electrical characteristics of the transistor deteriorate due to the oxygen vacancies. This results in donor levels that lead to sexual variation.

[0200] Therefore, after the semiconductor layer 205 is heated by the heat treatment, high-purity oxygen gas and high-purity Nitrous oxide gas or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. , preferably 1 ppm or less, more preferably 10 ppb or less) of air may be introduced. It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. The purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device is preferably 6N or more. The impurity concentration in oxygen gas or nitrous oxide gas is 7N or more (i.e., the impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less, preferably It is preferable to set the concentration to 0.1 ppm or less. By using this method, impurities are simultaneously removed by dehydration or dehydrogenation treatment. By supplying oxygen, which is the main component of oxide semiconductors, 205 can be highly purified and made into i-type (intrinsic)

[0201] Furthermore, the semiconductor layer 205 that has been subjected to the dehydration or dehydrogenation treatment is treated with oxygen (at least oxygen radicals). Oxygen may be supplied to the film by introducing oxygen atoms or oxygen ions. stomach.

[0202] Oxygen can be introduced by ion implantation, ion doping, plasma immersion ion implantation, etc. The lamination method, plasma treatment in an oxygen atmosphere, or the like can be used.

[0203] Furthermore, the introduction of oxygen can improve the bonding between hydrogen and elements constituting the oxide semiconductor, or The bond between the element and the hydroxyl group is broken, and these hydrogens or hydroxyl groups react with oxygen. This produces water, and the subsequent heating process removes the impurities hydrogen or The hydroxyl group can be easily released as water. After introducing oxygen, a heat treatment is performed, and then oxygen is introduced into the semiconductor layer 205. The oxygen-excessive state of the semiconductor layer 205 may be used. Alternatively, the heat treatment and the introduction of oxygen may be carried out simultaneously. good.

[0204] Oxygen is introduced into the semiconductor layer 205 that has been subjected to dehydration or dehydrogenation treatment (heat treatment). By supplying oxygen, the semiconductor layer 205 can be made i-type (intrinsic). The transistor having the (intrinsic) semiconductor layer 205 has suppressed fluctuations in electrical characteristics. , and is electrically stable.

[0205] In this way, the oxide semiconductor used for the semiconductor layer 205 is an oxide semiconductor from which impurities such as hydrogen are sufficiently removed. By doing so, the water is highly purified, and sufficient oxygen is supplied to make it supersaturated with oxygen. It is preferable that the polymer is i-type (intrinsic) or substantially i-type (intrinsic) by the addition of the polymer. Specifically, the hydrogen concentration in the oxide semiconductor is 5×10 19 atoms / cm 3 below, Preferably 5 x 10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atom s / cm 3 In addition, in order to ensure that sufficient oxygen is supplied and the oxygen is supersaturated, An insulating layer containing excess oxygen is provided to surround and be in contact with the oxide semiconductor.

[0206] The hydrogen concentration in the insulating layer containing excess oxygen is also important because it affects the characteristics of the transistor. The hydrogen concentration in the insulating layer containing excess oxygen is 7.2 × 1020 atoms / cm 3 That's all In some cases, the variation in the initial characteristics of the transistor increases, the L length dependency increases, and the B The hydrogen concentration in the insulating layer containing excess oxygen is 7. 2×10 20 atoms / cm 3 That is, the hydrogen concentration in the oxide semiconductor layer is set to be less than 5×1 0 19 atoms / cm 3 The hydrogen concentration of the insulating layer containing excess oxygen is 7.2×1 0 20 atoms / cm 3 It is preferable that it is less than 1000 kJ / s.

[0207] The hydrogen concentration is sufficiently reduced and highly purified, and sufficient oxygen is supplied to prevent oxygen deficiency. In oxide semiconductors with reduced defect levels in the energy gap, the carrier density is 1×1 0 12 / cm 3 Less than 1×10 11 / cm 3 Less than, preferably 1.45 x10 10 / cm 3 For example, the off-state current (here, unit: The value per channel width (1 μm) is 100 zA (1 zeptoampere is 1 × 1 0 -21 A) or less, preferably 10zA or less. At 85°C, it is 100zA ( 1×10 -19 A) or less, preferably 10zA (1 x 10 -20 A) The following is true: As shown above, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, Therefore, a transistor with excellent off-state current characteristics can be obtained.

[0208] Further, a transistor having an i-type (intrinsic) or substantially i-type oxide semiconductor In this case, electrical characteristics such as threshold voltage and on-current show almost no temperature dependence. In addition, there is little change in transistor characteristics due to photodegradation.

[0209] In this way, the oxide is highly purified and made i-type (intrinsic) by reducing oxygen vacancies. Transistors using compound semiconductors have suppressed fluctuations in electrical characteristics and are electrically stable. Therefore, it is possible to provide a highly reliable liquid crystal display device having stable electrical characteristics. do.

[0210] Next, a source electrode 206a, a drain electrode 206b, and wiring are formed on the semiconductor layer 205. 216 (in FIGS. 9 to 12, these are represented as wiring 216_j and wiring 216_j+1) A conductive layer is formed to serve as the source electrode 206a (see FIG. 9(C) and FIG. 11(C)). The conductive layer used for the gate electrode 202, the drain electrode 206b, and the wiring 216 is the same as that used for the gate electrode 202. The source electrode 206a and the drain electrode 206b can be formed by the above materials and methods. The conductive layer used for the wiring 216 and the wiring 216 may be formed of a conductive metal oxide. Conductive metal oxides include indium oxide, tin oxide, zinc oxide, and indium tin oxide. (abbreviated as ITO), indium zinc oxide or these metal oxide materials with silicon oxide It is possible to use a material containing kon.

[0211] In this embodiment, the conductive layer is formed by sputtering titanium with a thickness of 100 nm. A 400 nm thick aluminum layer and a 100 nm thick titanium layer are then formed. By a photolithography process, the source electrode 206a, the drain electrode 206b, and the wiring A line 216 is formed.

[0212] The conductive layer can be etched in the same manner as in the formation of the gate electrode 202. In this embodiment, two layers of titanium and aluminum are etched under the first etching condition. After that, the remaining titanium film single layer is removed under the second etching conditions. The etching conditions were as follows: etching gas (BCl3:Cl2 = 750 sccm:150 sccm) The bias power is set to 1500 W, the ICP power supply power is set to 0 W, and the pressure is set to 2.0 Pa. The second etching condition is etching gas (BCl3:Cl2 = 700 sccm: 1 00 sccm), bias power was set to 750 W, ICP power supply power was set to 0 W, and pressure is set to 2.0 Pa.

[0213] At this time, the formation of the source electrode 206a, the drain electrode 206b, and the wiring 216 exposes the The surface of the exposed semiconductor layer 205 contains elements that make up the conductive layer, elements present in the processing chamber, The elements that make up the etching gas or etching solution used in etching are added as impurities. It may be worn.

[0214] When impurities are attached, the off-state current of the transistor increases or the electrical characteristics of the transistor deteriorate. Furthermore, a parasitic channel is easily generated in the semiconductor layer 205, and the electric Electrodes and wiring that should be electrically isolated from each other are easily electrically connected via the semiconductor layer 205. .

[0215] In addition, some impurities may be mixed in the vicinity of the surface of the semiconductor layer 205 (in the bulk), The oxygen in the semiconductor layer 205 is extracted, and oxygen vacancies occur on the surface of the semiconductor layer 205 and in the vicinity of the surface. For example, chlorine and boron contained in the etching gas, and ethylene Aluminum, which is the material of the etching chamber, reduces the resistance of the semiconductor layer 205 (to n-type). It could be one of the factors.

[0216] Therefore, in one embodiment of the present invention, the source electrode 206a, the drain electrode 206b, and the wiring After the etching for forming 216 is completed, impurities adhering to the surface of the semiconductor layer 205 are removed. A cleaning process (impurity removal process) is carried out to remove impurities.

[0217] The impurity removal treatment can be performed by plasma treatment or treatment with a solution. As the plasma treatment, oxygen plasma treatment or nitrous oxide plasma treatment may be used. Alternatively, a rare gas (typically, argon) may be used for the plasma treatment.

[0218] In addition, cleaning with solutions includes alkaline solutions such as TMAH solution and diluted hydrofluoric acid. This can be done using any acidic solution, water, etc. For example, when using dilute hydrofluoric acid, 5 0% by weight hydrofluoric acid, 1 / 10 with water 2 ~1 / 10 5 About 1 / 10, preferably 3 ~1 / 10 5 Dilute hydrofluoric acid diluted to about 0.5 wt % to 5×10 -4 % by weight of diluted hydrofluoric acid, preferably 5×10 -2 Weight% to 5×10 -4 % by weight of diluted fluorine It is preferable to use an acid for the cleaning process. In addition, the above impurities can be removed.

[0219] Furthermore, when impurity removal treatment is performed using a dilute hydrofluoric acid solution, the surface of the semiconductor layer 205 is etched. That is, impurities attached to the surface of the semiconductor layer 205 and the semiconductor layer 2 Impurities mixed in the vicinity of the surface of the semiconductor layer 205 can be removed together with a part of the semiconductor layer 205. As a result, the source electrode 206a, the drain electrode 206b, and the The film thickness of the region overlapping with the wiring 216_j may be larger than the film thickness of the region not overlapping with the wiring 216_j. Yes. For example, 1 / 10 3 The IGZO film was treated with diluted hydrofluoric acid (0.05% by weight). When the film thickness is increased, the film thickness decreases by 1 to 3 nm per second, and the film thickness decreases by 2 / 10. 5 Diluted hydrofluoric acid (0.0025 wt.% When an IGZO film is treated with hydrofluoric acid, the film thickness decreases by about 0.1 nm per second.

[0220] By performing impurity removal treatment, the peak concentration obtained by SIMS analysis was The chlorine concentration on the surface of the semiconductor layer is 1×10 19 / cm 3 or less (preferably 5 × 10 18 / cm 3 or less, more preferably 1 × 10 18 / cm 3 (See below). In addition, the boron concentration on the semiconductor layer surface is set to 1×10 19 / cm 3 Less than or equal to (preferably 5 x 1 0 18 / cm 3 or less, more preferably 1 × 10 18 / cm 3 (below) In addition, the aluminum concentration on the semiconductor layer surface is set to 1 × 10 19 / cm 3 Below (preferably is 5 x 10 18 / cm 3 or less, more preferably 1 × 1018 / cm 3 (below) can be done.

[0221] By performing impurity removal processing, highly reliable transistors with stable electrical characteristics can be realized. It can be realized.

[0222] Next, an insulating layer is formed on the source electrode 206a, the drain electrode 206b, and the wiring 216_j. The insulating layer 207 functions as a protective layer. The insulating layer 204 can be formed by the same material and method as the gate insulating layer 204 or the base layer 201. In addition, when an oxide semiconductor is used for the semiconductor layer 205, the insulating layer 207 is The state in which there is a region in the gas (in the gas) where there is more oxygen than in the stoichiometric composition (having an oxygen excess region) It is preferable to do so.

[0223] After the insulating layer 207 is formed, oxygen (at least any of oxygen radicals, oxygen atoms, and oxygen ions) is The insulating layer 207 can be kept in an oxygen-excess state by introducing oxygen into the film. Oxygen may be introduced directly into the insulating layer 207 or through another layer. When oxygen is introduced through other layers, ion implantation, ion doping, and proton implantation are used. Alternatively, a laser ion implantation method or the like may be used. When oxygen is introduced directly into 07, plasma treatment in an oxygen atmosphere is also performed in addition to the above method. Also, the following can be used.

[0224] By introducing oxygen, the bond between the element constituting the insulating layer 207 and hydrogen or the bond between the element and hydrogen The bond between the hydroxyl groups is broken and these hydrogens or hydroxyl groups react with oxygen. In order to generate water, the impurities hydrogen and In other words, the hydroxyl group in the insulating layer 207 can be easily released as water. Therefore, after oxygen is introduced into the insulating layer 207, the impurity concentration can be further reduced. After that, oxygen is further introduced into the insulating layer 207, and the insulating layer 207 The introduction of oxygen into the insulating layer 207 and the heat treatment may be performed in an oxygen-excess state. These steps may be repeated alternately multiple times. Alternatively, oxygen introduction and heat treatment may be performed simultaneously.

[0225] Before forming the insulating layer 207, oxygen plasma treatment or nitrous oxide plasma treatment may be performed. It is preferable to carry out the above-mentioned process to remove moisture and organic substances adhering to the surface. After plasma treatment or nitrous oxide plasma treatment, etc., the It is preferable to form it as follows.

[0226] In this embodiment, silicon oxide having a thickness of 200 nm is deposited as the insulating layer 207 by sputtering. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide layer is formed by sputtering using a rare gas. (typically argon) atmosphere, oxygen atmosphere, or a mixture of rare gas and oxygen atmosphere The target can be silicon oxide or silicon. For example, silicon can be used as a target and sputtered in an atmosphere containing oxygen. By carrying out the above, silicon oxide can be formed.

[0227] After the insulating layer 207 is formed, the insulating layer 207 is annealed in a nitrogen atmosphere, a rare gas atmosphere, an oxygen atmosphere, a mixture of nitrogen and oxygen, or Alternatively, the heat treatment may be performed in a mixed gas atmosphere of a rare gas and oxygen. The material is then heat treated at 300°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.

[0228] Next, a resist mask is formed by a third photolithography process, and a drain electrode A part of the insulating layer 207 on 206b is selectively removed to form a contact hole 208. In addition, in the cross section D1-D2, the insulating layer 207 and a part of the semiconductor layer 205 are selectively In the cross section J1-J2, the portion on the wiring 212_i is removed to form a groove 230. The insulating layer 207, the semiconductor layer 205, and a portion of the gate insulating layer 204 are selectively removed, and A contact hole 219 is formed. In addition, in the cross section K1-K2, A part of the insulating layer 207 is selectively removed to form a contact hole 220. Although not shown, the groove 240 is also formed in the same manner as the groove 230.

[0229] In the third photolithography process, first, a resist is formed on the insulating layer 207 using a multi-tone mask. A mask 261 is formed (see FIG. 9(E) and FIG. 11(E)).

[0230] Here, a multi-tone mask will be explained with reference to FIG. The mask is capable of three exposure levels: a partially exposed portion, a semi-exposed portion, and an unexposed portion. This is an exposure mask that allows the transmitted light to have multiple intensities. It is possible to form a resist mask having regions of multiple (typically two) thicknesses. Therefore, by using a multi-tone mask, the number of exposure masks (photomasks) can be reduced. It is possible to reduce it.

[0231] A typical example of a multi-tone mask is a gray-tone mask 304 shown in FIG. , there is a halftone mask 314 as shown in FIG. 13(B1).

[0232] As shown in FIG. 13(A1), the gray-tone mask 304 is made of a transparent substrate 301 and its The light-shielding portion 302 and the diffraction grating 303 are formed on the light-shielding portion 302. On the other hand, the diffraction grating 303 has slits, dots, meshes, etc. By setting the interval between the light transmitting portions to be equal to or less than the resolution limit of the light used for exposure, the light transmission The diffraction grating 303 can be formed by periodic slits, dots, meshes, etc. Either periodic slits, dots, or meshes can be used.

[0233] The light-transmitting substrate 301 may be a light-transmitting substrate such as quartz. The diffraction grating 303 is formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. This can be done.

[0234] When the gray-tone mask 304 is irradiated with exposure light, as shown in FIG. 13(A2), In the portion 302, the light transmittance is 0%, and neither the light shielding portion 302 nor the diffraction grating 303 is provided. In the area where the light is not incident, the light transmittance is 100%. The light transmittance of the diffraction grating 303 can be adjusted in the range of 10 to 70%. This is possible by adjusting the spacing and pitch of the slits, dots, or meshes of the diffraction grating. do.

[0235] As shown in FIG. 13(B1), the halftone mask 314 is made of a transparent substrate 311 and its The semi-transmitting portion 312 is formed on the M oSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light-shielding portion 313 may be formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. can.

[0236] When the halftone mask 314 is irradiated with exposure light, as shown in FIG. 13(B2), In the portion 313, the light transmittance is 0%, and neither the light-shielding portion 313 nor the semi-transmitting portion 312 is provided. In the non-transparent area, the light transmittance is 100%. The light transmittance of the semi-transmitting portion 312 can be adjusted in the range of 10 to 70%. This can be adjusted by changing the material used for 12.

[0237] The resist mask 261 formed using a multi-tone mask is made up of multiple regions with different thicknesses. The resist mask has two regions (thick and thin regions). In the resist mask 261, the thick regions are called convex portions of the resist mask 261, and the thin regions are called convex portions of the resist mask 261. are sometimes called recesses of the resist mask 261.

[0238] The resist mask 261 covers the contact holes 208, 220, and the grooves. The contact hole 219 has a recess at a position overlapping the area where the contact hole 230 is to be formed. The resist mask 261 is not provided on the region where the film is to be formed.

[0239] Next, a first etching process is performed. By the first etching process, the resist mask 26 1 as a mask, a part of the insulating layer 207 on the wiring 212_i in the cross section J1-J2, A part of the semiconductor layer 205 and a part of the gate insulating layer 204 are etched, and a contact hole is formed. On the side of the contact hole 219, the insulating layer 207 and the semiconductor layer 2 05, and the side surfaces of the gate insulating layer 204 are exposed, and the wiring 212_i is exposed on the bottom surface ( See Figure 12(A).

[0240] The insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204 are etched by dry etching. Dry etching or wet etching may be used, or both may be used. The etching gas used is a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), trichloride boron tetrachloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc. It is possible.

[0241] As dry etching, parallel plate type RIE (Reactive Ion Etching) ng) method and ICP (Inductively Coupled Plasma) In addition, a combined plasma etching method can be used. D2, the cross section K1-K2 is not etched because it is covered with the resist mask 261. (See Figure 10(A) and Figure 12(A)).

[0242] Next, the resist mask 261 is shrunk by ashing using oxygen plasma or the like, and the A resist mask 262 is formed. At this time, the resist mask 262 is formed in a thin region (a recess ) is removed, and the insulating layer 207 is exposed (see FIG. 10(B) and FIG. 12(B)). .

[0243] Next, a second etching process is performed. By the second etching process, the resist mask 26 2 as a mask, the insulating layer 20 overlapping the drain electrode 206b in the cross section A1-A2 is 7 is etched to form a contact hole 208. In this step, a part of the insulating layer 207 and a part of the semiconductor layer 205 are etched to form a groove 230. In addition, a part of the insulating layer 207 overlapping with the wiring 216_j in the cross section K1-K2 is formed. is etched to form a contact hole 220. At this time, in the cross section J1-J2 Also, a part of the insulating layer 207 that is not covered with the resist mask 262 and the semiconductor layer 205 A part of the surface is etched (see FIG. 12(C)).

[0244] The side surface of the insulating layer 207 is exposed at the side surface of the contact hole 208, and the drain electrode is exposed at the bottom surface. The electrode 206b is exposed on the side surface of the groove 230. The side surface of the contact hole 220 is exposed, and the gate insulating layer 204 is exposed at the bottom surface. At this point, the side surfaces of the insulating layer 207 are exposed, and the wiring 216_j is exposed at the bottom surface.

[0245] The second etching process may be dry etching or wet etching, or both. At this time, the wiring 212_i may be formed so as not to be exposed at the bottom of the groove 230. When the wiring 212_i is exposed at the bottom of the groove 230, the side of the groove 230 Leak current is likely to occur between the semiconductor layer 205 exposed on the surface and the wiring 212_i, which reduces the display quality. This is one of the causes of deterioration in the display area and reliability. The display quality is significantly degraded by the groove portion 230 and the wiring 212_i. By overlapping the semiconductor layer 205 and the wiring 21 through the wiring 21, the occurrence of a parasitic channel is prevented. 2_i, and can improve the display quality of the display device. do.

[0246] Generally, the contact hole 219 and the groove 230 have the same laminated structure. When forming openings of different depths in a region, the formation of the openings may be performed using multiple photolithography processes. However, according to the manufacturing process described in this embodiment, Forming openings of different depths in a layered structure using a single photolithography process That is, it is possible to achieve this at low cost with fewer photolithography steps. A display device can be manufactured with high productivity.

[0247] In addition, according to the manufacturing process shown in this embodiment, a photoresist is formed in the channel formation region of the semiconductor layer 205. In particular, when an oxide semiconductor is used as the semiconductor layer 205, a resist is not formed directly on the semiconductor layer 205. In this case, the channel formation region of the semiconductor layer 205 is protected by the insulating layer 207. In the photoresist peeling and cleaning process, moisture is not present in the channel forming region of the semiconductor layer 205. Since there is no adhesion of dust, the characteristic variations of the transistor 111 are reduced, and reliability is improved. To rise.

[0248] Next, the pixel electrode 21 is formed on the insulating layer 207 by using a sputtering method, a vacuum deposition method, or the like. 0, a light-transmitting conductive layer (also referred to as a transparent conductive layer) to be the electrode 221 and the electrode 222 The thickness of the film is 30 nm or more and 200 nm or less, preferably 50 nm or more and 100 nm or less. do.

[0249] Examples of the light-transmitting conductive layer include indium oxide containing tungsten oxide, tungsten oxide, and Indium zinc oxide containing stainless steel, indium oxide containing titanium oxide, titanium oxide Contains indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc Conductive materials with transparency, such as indium tin oxide and silicon oxide, are used. Alternatively, a material consisting of 1 to 10 graphene sheets may be used. stomach.

[0250] In addition, although the present embodiment has exemplified a method for manufacturing a pixel portion of a transmission type liquid crystal display device, The present invention is not limited to the transmissive type, but can also be applied to the pixel portion of a reflective or semi-transmissive liquid crystal display device. When obtaining a pixel portion of a reflective liquid crystal display device, a conductive layer with high light reflectivity (reflective layer) is used as the pixel electrode. (also called conductive layer), for example, aluminum, titanium, silver, rhodium, nickel, etc. Metals with high reflectivity of visible light, or alloys containing at least one of these metals, or When obtaining a pixel portion of a semi-transmissive liquid crystal display device, one pixel electrode The electrode is formed of a transparent conductive layer and a reflective conductive layer, and has a transmissive portion and a reflective portion.

[0251] In this embodiment, an ITO layer having a thickness of 80 nm is formed as a light-transmitting conductive layer. A resist mask is formed by the photolithography process, and a light-transmitting conductive layer is selected. Selective etching is performed to form the pixel electrode 210, the electrode 221, and the electrode 222 (see FIG. 10(D), see Fig. 12(D).

[0252] The pixel electrode 210 is electrically connected to the drain electrode 206b through a contact hole 208. The electrode 221 is electrically connected to the wiring 212_i through a contact hole 219. The electrode 222 is connected to the wiring 216_j through the contact hole 220. electrically connected.

[0253] In addition, the contact holes 219 and contacts formed in the terminal portions 103 and 104 are In the contact hole 220, the wiring 212_i and the wiring 216_j are left exposed. It is important to cover the wiring 212_i and the wiring 212_i with an oxide conductive material such as ITO. Since the wiring 212_i and the wiring 216_j are metal layers, the wiring 212_i and the wiring 216_j are exposed. If left in this state, the exposed surface will oxidize, increasing the contact resistance with FPCs, etc. An increase in the input signal frequency can cause delays and distortion of the waveform of externally input signals, making it difficult to accurately receive external signals. The reliability of the semiconductor device is reduced. By covering the exposed surface of the j with a conductive oxide material such as ITO, the increase in contact resistance can be reduced. This can prevent the occurrence of defects and improve the reliability of the semiconductor device.

[0254] According to this embodiment, a semiconductor device can be fabricated using fewer photolithography steps than in the past. Therefore, it is possible to manufacture a liquid crystal display device at low cost and with high productivity. This can be done.

[0255] In this embodiment, a bottom-gate transistor has been described as an example. It is also possible to apply this to transistors with a gate structure.

[0256] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0257] (Embodiment 2) FIG. 14 shows one mode of a liquid crystal display device using the semiconductor device described in the above-described Embodiment 1 as an example.

[0258] FIG. 14A shows a transistor 4010 and a liquid crystal element 4013 mounted on a first substrate 400. 4005 and a second substrate 4006. Therefore, FIG. 14(B) corresponds to a cross-sectional view taken along line M1-M2 in FIG. 14(A). A groove 4040 is provided on the substrate 4001 .

[0259] A sealing material 4005 is formed so as to surround a pixel portion 4002 provided on a first substrate 4001. A second substrate 4006 is provided on the pixel portion 4002. 002 is a liquid crystal display device formed by a first substrate 4001, a sealing material 4005, and a second substrate 4006. It is sealed together with the crystal layer 4008.

[0260] In addition, the area outside the area surrounded by the sealing material 4005 on the first substrate 4001 In the area, there is an input terminal 4020, and FPC (Flexible Printed Circuit FPC4018a and FPC4018b are connected. FPC4018a is a separate The FPC 4018b is electrically connected to a signal line driver circuit 4003 formed on a substrate. The pixel electrodes are electrically connected to a scanning line driver circuit 4004 which is fabricated on a different substrate. Various signals and potentials are applied to the FPC 4018a and FPC 4018b. The signals are supplied from the signal line driver circuit 4003 and the scanning line driver circuit 4004 via b.

[0261] The method of connecting the drive circuit fabricated on a separate substrate is not particularly limited. , COG (Chip On Glass), Wire Bonding, TCP (Tape C Methods such as the ARRIER Package can be used.

[0262] Although not shown, the signal line driver circuit 4003 or the scanning line driver circuit 4004 is The transistors disclosed in this specification may be formed on the first substrate 4001 .

[0263] A liquid crystal element (also called a liquid crystal display element) is used as a display element provided in the display device. In addition, display media such as electronic ink, which changes contrast through electrical effects, are also available. can be applied.

[0264] The display device shown in FIG. 14 has an electrode 4016 and a wiring 4015. The wiring 4015 is connected to the terminal of the FPC 4018a via the anisotropic conductive layer 4019. are electrically connected.

[0265] The electrode 4016 is formed from the same conductive layer as the first electrode 4030. The source electrode and drain electrode of the transistor 4010 are formed from the same conductive layer.

[0266] In this embodiment, the transistor described in Embodiment 1 is used as the transistor 4010. The transistor 4010 provided in the pixel portion 4002 is a display element. The display element is not particularly limited as long as it can display an image. Various display elements can be used.

[0267] FIG. 14 shows an example of a display device using a liquid crystal element as a display element. The liquid crystal element 4013, which is a display element, includes a first electrode 4030, a second electrode 4031, and a and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between two layers that function as alignment films. An insulating layer 4032 and an insulating layer 4033 are provided. The second electrode 4032 is also provided on the groove 4040. The second electrode 4031 is formed on the second substrate 40. The first electrode 4030 and the second electrode 4031 are connected via a liquid crystal layer 4008. The structure is such that the layers are stacked.

[0268] The spacers 4035 are columnar spacers formed on the second substrate 4006 by an insulating layer. The sensor is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. A spherical spacer may also be used.

[0269] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0270] Alternatively, a liquid crystal exhibiting a blue phase, which does not require an alignment film, may be used. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer, a liquid crystal composition containing 5% by weight or more of a chiral agent is used. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec or less. It is short and optically isotropic, so alignment treatment is not required and the viewing angle dependency is small. Since no film is required, rubbing treatment is also unnecessary. This prevents electrostatic damage that can be caused by electrostatic discharge, reducing defects and damage to liquid crystal display devices during the manufacturing process. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0271] The specific resistivity of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 1 1 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The specific resistivity values ​​in the specification are those measured at 20°C.

[0272] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. The setting is made so that the charge can be held for a predetermined period, taking into consideration the current and the like. The semiconductor layer in which the channel is formed is made i-type (intrinsic) or substantially i-type. When a transistor using an oxide semiconductor is used, the size of the storage capacitance (capacitance value) can be reduced. , it can be set to 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel.

[0273] The transistor disclosed in the above embodiment includes an oxide semiconductor in a semiconductor layer in which a channel is formed. The transistor can reduce the current value in the off state (off current value). The retention time of electrical signals such as image signals can be extended, and the input interval can also be extended when the power is on. This allows the frequency of refresh operations to be reduced, resulting in reduced power consumption. In addition, the semiconductor layer in which the channel is formed is made i-type (intrinsic) or In other words, a transistor using an i-type oxide semiconductor can be used without providing a storage capacitor. This makes it possible to maintain the potential applied to the liquid crystal element.

[0274] In addition, a transistor using an oxide semiconductor for a semiconductor layer in which a channel is formed has a relatively high Since a high field effect mobility can be obtained, the liquid crystal display device can be driven at high speed. By using this transistor in the pixel area of ​​a display device, the vertical synchronization frequency can be increased by 1.5 times. Preferably, set it to double or more to reduce the afterimage phenomenon and blurring of moving images that can be a problem when displaying moving images. This makes it easier to apply a driving technique called double speed driving, which reduces the display quality. Therefore, it is possible to provide a liquid crystal display device.

[0275] In addition, the transistors are separately formed in a driver circuit portion and a pixel portion on the same substrate. Therefore, the number of components in the liquid crystal display device can be reduced. The productivity of the device can be improved.

[0276] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS(Fringe Field Switching) mode, ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0277] Furthermore, normally black type liquid crystal display devices, for example, vertical alignment (VA) It may also be a transmissive liquid crystal display device that employs a (alignment) mode. Vertical alignment mode is a method of controlling the alignment of liquid crystal molecules in a liquid crystal display panel. When no pressure is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. There are several types of direct alignment modes, such as MVA (Multi-Doma in Vertical Alignment mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Supe) You can also use the r-View mode. It is a multi-layer structure that is divided into regions (sub-pixels) and designed to tilt the molecules in different directions in each region. A method known as domaining or multi-domain design can be used.

[0278] In addition, in a liquid crystal display device, a black matrix (light-shielding layer), a polarizing member, a phase difference member, Optical members (optical substrates) such as anti-reflection members are provided as appropriate. Circularly polarized light produced by a retardation substrate may also be used. Either may be used.

[0279] In addition, multiple light-emitting diodes (LEDs) are used as backlights, and a time-division display system is used. It is also possible to perform field sequential driving. By applying the color drive method, color display can be achieved without using a color filter. This can be done.

[0280] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may differ for each dot of the color element. The present invention is not limited to liquid crystal display devices with monochromatic display, but is also applicable to liquid crystal display devices with monochrome display. It is also possible to do so.

[0281] In FIG. 14, the first substrate 4001 and the second substrate 4006 are glass substrates. In addition, a flexible substrate can also be used, for example, a light-transmitting plastic substrate. As for plastic, FRP (Fiberglass-R Reinforced Plastics (PVF) sheet, PVF (Polyvinyl Fluoride) film A film made of a polyester or acrylic resin can be used. It uses a sheet with a structure in which aluminum foil is sandwiched between PVF film or polyester film. It is also possible to do so.

[0282] A transmissive liquid crystal display device transmits light from a light source or a display element to display an image. The thin films such as the substrate, insulating layer, and conductive layer provided in the pixel area through which light passes are all in the wavelength range of visible light. It is preferable that the film is translucent to light in the region.

[0283] A first electrode and a second electrode (a pixel electrode, a common electrode, a counter electrode) that apply a voltage to the display element In the case of a reflective electrode, the direction of the light to be extracted, the location of the electrodes, and the pattern of the electrodes are all determined by the The translucency or reflectivity can be selected depending on the turn structure.

[0284] The first electrode 4030 and the second electrode 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium dioxide, ITO, indium zinc oxide, silicon dioxide A light-transmitting conductive material such as doped indium tin oxide can be used. Alternatively, a material consisting of 1 to 10 graphene sheets may be used.

[0285] In addition, either the first electrode 4030 or the second electrode 4031 is made of tungsten (W), Molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), Niobium (Nb), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (N i), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) It can be formed by using one or more of the following metals, their alloys, or their nitrides. This can be done.

[0286] The first electrode 4030 and the second electrode 4031 are made of a conductive polymer (conductive polymer The conductive polymer can be formed using a conductive composition containing a conductive polymer. A so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or The copolymer may be a copolymer of two or more of aniline, pyrrole and thiophene, or a derivative thereof. Examples include:

[0287] In addition, since transistors are easily damaged by static electricity, it is preferable to provide a protection circuit. It is preferable that the protection circuit is configured using a non-linear element.

[0288] As described above, by using the transistor exemplified in the above embodiment, a highly reliable liquid crystal display (LCD) can be obtained. Note that the transistors described in the above embodiments can be used in a liquid crystal display device. Not only semiconductor devices with display functions, but also power devices mounted on power supply circuits, LSIs, etc. semiconductor integrated circuits, semiconductor devices with image sensor functions that read information from objects, etc. The present invention can be applied to semiconductor devices having various functions.

[0289] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0290] (Embodiment 3) In this embodiment, a semiconductor device is manufactured by reducing the number of photomasks and photolithography steps. As an example of the device, a semiconductor device that can be used in an active matrix EL display device is An example of the device and a method for manufacturing the same will be described with reference to FIGS.

[0291] First, referring to FIG. 20(A), the structure of a semiconductor device 150 that can be used in an EL display device will be described. The semiconductor device 150 has a pixel region 102 on a substrate 101 and m (m is 1) a terminal section 103 having terminals 105_1 to 105_m (number of terminals 105_1 to 105_m is an integer greater than or equal to 105_m) and a terminal 107; A terminal having n (n is an integer of 1 or more) terminals 106_1 to 106_n and a terminal 108 The semiconductor device 150 has a terminal portion 104 electrically connected to the terminal portion 103. The wirings 212_1 to 212_m, the wiring 224, and n wirings electrically connected to the terminal portion 104 The pixel region 102 has the wirings 216_1 to 216_n and the wiring 217. It has a plurality of pixels 160 arranged in a matrix of m vertical (rows) x n horizontal (columns). The pixel 160(i, j) in the i-th row and j-th column (i is an integer between 1 and m, and j is an integer between 1 and n) ) is the wiring 212_i (the i-th wiring 212), the wiring 216_j (the j-th wiring 216) Each pixel is electrically connected to either the anode or the cathode. a wiring 224 that functions as a wiring to which the other potential of the anode or cathode is supplied; The wiring 224 is electrically connected to the terminal 107. The wiring 212_i is electrically connected to the terminal 108. The wiring 216_j is electrically connected to the terminal 106_j. are.

[0292] The terminals 103 and 104 are external input terminals, and are connected to an external control circuit and The signal supplied from the external control circuit is input to the terminal 1. 20A, the signal is input to the semiconductor device 150 via the terminal 103 and the terminal 104. The sub-units 103 are formed on the left and right outer sides of the pixel region 102, and signals are input from two points. In addition, terminal sections 104 are formed on the upper and lower outer sides of the pixel region 102, and signals are input from two points. By inputting signals from two locations, the signal supply capacity is improved. This facilitates high-speed operation of the semiconductor device 150. This can reduce the effect of signal delay caused by the increase in wiring resistance that accompanies higher resolution. Since it is possible to provide redundancy to the semiconductor device 150, the reliability of the semiconductor device 150 can be improved. In FIG. 20(A), the terminal portion 103 and the terminal portion 104 are Although the configuration is such that two of each are provided, it is also possible to provide one of each.

[0293] 20B shows the circuit configuration of the pixel 160. The pixel 160 includes a transistor 11 1, a transistor 121, an EL element 116, and a capacitor element 113. The gate electrode of the transistor 111 is electrically connected to the wiring 212_i. One of the source electrode and the drain electrode is electrically connected to the wiring 216_j. The other of the source electrode and the drain electrode of the transistor 111 is connected to the The gate electrode and one electrode of the capacitor element 113 are electrically connected to a node 115. In addition, one of the source electrode and the drain electrode of the transistor 121 is connected to E The other of the source electrode and the drain electrode is electrically connected to one of the electrodes of the L element 116. The other electrode of the capacitor 113 is electrically connected to the wiring 217. The other electrode of the wiring 217 is electrically connected to the wiring 224. The potential difference is the sum of the threshold voltage of the transistor 121 and the threshold voltage of the EL element 116. Set it to be larger than the voltage.

[0294] The transistor 111 has a gate electrode of the transistor 121 connected to a line 216_j. The wiring 212_i has a function of selecting whether or not to input an image signal to be input. When a signal that turns on the transistor 111 is supplied, the signal is transmitted to the wiring 216 via the transistor 111. The image signal of _j is supplied to node 115 .

[0295] The transistor 121 supplies a current corresponding to the potential (image signal) supplied to the node 115 as E The capacitor 113 has a function of supplying a current to the L element 116. The transistor 121 has a function of keeping the difference constant. It functions as a current source for supplying current to 116.

[0296] The semiconductor layer in which the channels of the transistors 111 and 121 are formed is A crystalline semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used. Examples of the body material include silicon, germanium, silicon germanium, and silicon carbide. Examples of the display device described in this embodiment include gallium arsenide and gallium arsenide. Since the device has a structure in which the semiconductor layer remains in the pixel region, the display device using the semiconductor can be When used in an emission type display device, the semiconductor layer should be made as thin as possible to minimize visible light It is preferable to increase the transmittance of the

[0297] In addition, in the semiconductor layer in which the channels of the transistors 111 and 121 are formed, The oxide semiconductor described in the above embodiment is preferably used. The energy gap is large at 3.0 eV or more, and the transmittance to visible light is high. In transistors obtained by processing semiconductors under appropriate conditions, the off-state current Under temperature conditions (e.g., 25°C), 100 zA (1 x 10 -19 A) The following or is 10zA(1×10 -20 A) or less, and even 1zA (1×10 -21 A) The following Therefore, the gate voltage of the transistor 121 can be reduced without providing the capacitor 113. In addition, the power consumption of the semiconductor device can be reduced. can.

[0298] In this embodiment, the transistor 111 and the transistor 121 are both n-channel transistors. Although the explanation will be given assuming that one or both of the transistors are p-channel transistors, It may also be a transistor.

[0299] The capacitor 113 is a capacitor for holding an image signal supplied to the gate electrode of the transistor 121. The capacitor 113 is not necessarily provided, but it is preferable to provide the transistor 11 The transistor is turned off when the current (off-state current) flows between the source and drain. This makes it possible to suppress fluctuations in the potential applied to the gate electrode of the transistor 121.

[0300] The EL element 116 has an EL layer sandwiched between one electrode serving as an anode and the other electrode serving as a cathode. The luminance is controlled according to the amount of current flowing through the EL layer. The brightness of 116 is controlled according to the amount of current flowing between the source and drain of transistor 121. To be controlled.

[0301] Next, an example of the configuration of the pixel 160 shown in FIG. 20 will be described with reference to FIGS. 15 to 18. 15 and 16 are top views showing the planar configuration of the pixel 160. 16 is a top view of the state in which the pixel electrode 210 is formed on the insulating film 210. FIG. 15 and 16 are top views of the state in which the L layer 271 has been formed. 16, some components are omitted. For example, in FIG. 16, The counter electrode 226 formed on the substrate 221 is not shown.

[0302] 17 and 18 are cross-sectional views showing the stacked structure of the pixel 160. 15 and 16, and FIG. 17(B) corresponds to the cross section taken along the dashed line P1-P2. , corresponds to the cross section taken along the dashed line Q1-Q2 in FIGS. 15 and 16, and FIG. 18 is This corresponds to the cross section taken along the dashed line R1-R2 in FIGS.

[0303] A drain electrode 206b electrically connected to the node 115 (see FIG. 20B) If the parasitic capacitance occurring between the gate electrodes 202 is large, the node 115 may Since the transistor 111 is easily affected by the potential fluctuation, it changes from the ON state to the OFF state. When this happens, the potential supplied to the node 115 cannot be accurately maintained, which is a factor that causes a decrease in display quality. As described in the above embodiment, the source electrode 206a is U-shaped, and the drain electrode By making the shape surrounding the drain electrode 206b, a sufficient channel width is ensured. Since the parasitic capacitance generated between the gate electrode 202 and the gate electrode 6b can be reduced, the EL display device This can improve the display quality of the device.

[0304] In addition, in the semiconductor device described in this embodiment, the island-shaped semiconductor layer is formed to simplify the process. Since no photolithography process is performed to form the semiconductor layer 20 in the entire pixel area, As a result, as in the above embodiment, the semiconductor device described in this embodiment Parasitic transistors can also occur in semiconductor devices.

[0305] In the semiconductor device described in this embodiment, the wiring 212_i functions as a gate electrode, and the wiring The line 216_j functions as either a source electrode or a drain electrode, and the wiring 217 functions as a source electrode. A first parasitic transistor may be created that functions as the other of the source and drain electrodes. do.

[0306] Note that the semiconductor device described in this embodiment mode does not have the wiring 203. The second parasitic transistor described above does not occur, but the pixel electrode 210 functions as a gate electrode. The insulating layer 207 functions as a gate insulating layer, and the wiring 216_j functions as a source electrode or a drain electrode. The wiring 217 functions as the other of the source and drain electrodes. There is a risk of a third parasitic transistor functioning, especially when increasing the pixel aperture ratio. For these reasons, if the pixel electrode 210 is brought closer to the wiring 216_j and the wiring 217, the third The influence of parasitic transistors becomes stronger.

[0307] Furthermore, when the potential difference between the wiring 217 and the wiring 216_j+1 of the adjacent pixel increases, There is a risk that a parasitic channel will be generated in the semiconductor layer 205 between the two wirings due to an electric field generated between the two wirings. There is.

[0308] When a potential that turns on the transistor 111 is supplied to the wiring 212_i, the first parasitic The transistor is also turned on, and the wiring 216_j and the wiring 217 are electrically connected to each other. When the wiring 216_j and the wiring 217 are electrically connected by the parasitic transistor 1, It becomes difficult to supply a clear image signal to the node 115.

[0309] When the third parasitic transistor functions as an n-type transistor, the pixel electrode 21 The potential of the wiring 216_j becomes lower than the potential supplied to or held at 0. When the absolute value of the potential difference becomes larger than the threshold value of the third parasitic transistor, the pixel electrode 21 A channel is formed in the semiconductor layer 205 located under the gate electrode 200, and the third parasitic transistor is turned on. This is the state.

[0310] When the third parasitic transistor is turned on, the wiring 216_j and the wiring 217 are electrically connected. The wiring 216_j and the wiring 217 are electrically connected by a third parasitic transistor. If the pixel aperture is too large, it becomes difficult to supply an accurate image signal to the node 115. For reasons such as increasing the efficiency, the pixel electrode 210 is located close to the wiring 216_j and the wiring 217. As the temperature rises, the effect of the third parasitic transistor becomes stronger.

[0311] In addition, a parasitic channel is generated between the wiring 217 and the wiring 216_j+1 of the adjacent pixel. When this is done, the wiring 217 and the wiring 216_j+1 are electrically connected, and the correct image signals are transmitted to the wiring 216_j+1. It becomes difficult to supply the voltage to the node 115 of each pixel.

[0312] Therefore, a groove 230 is provided in the pixel 160 where the semiconductor layer 205 is removed, and the above-mentioned parasitic transistor The groove 230 is located between the wiring 216_j and the wiring 217. By providing the first parasitic transistor so as to cross over both ends of the wiring 212_i in the line width direction, The groove 230 can prevent the generation of a transistor and a parasitic channel. Multiple entries may be placed on _i.

[0313] In addition, the groove 230 is formed between the wiring 216_j and the pixel electrode 210, or between the wiring 217 and the pixel electrode 210. The wiring 216_j or the wiring 217 extends between at least one of the electrodes 210. The electrode 210 is formed in the direction of the pixel electrode 210, beyond the edge 231 and the edge 232 of the pixel electrode 210. This can prevent the generation of the third parasitic transistor. The groove 230 provided along the direction in which the wiring 217 extends is It does not have to be strictly parallel to the line 217, and may have bends or curves. It's fine.

[0314] In addition, between the wiring 217 and the wiring 216_j+1 of the adjacent pixel, a wiring that crosses the edge of the pixel is provided. In addition, by providing the groove portion 230, a parasitic channel is formed between the wiring 217 and the wiring 216_j+1. It can be prevented from being generated.

[0315] There is no particular limitation on the size of the groove 230 where the semiconductor layer 205 is removed. To ensure that no resistors or parasitic channels are generated, the wiring 216_j or the wiring 217 The width of the portion of the groove 230 where the semiconductor layer has been removed in the direction perpendicular to the extending direction is It is preferably 1 μm or more, and more preferably 2 μm or more.

[0316] The cross section P1-P2 shown in FIG. 17(A) shows the transistor 111, the transistor 121, and The transistor 111 and the capacitor 113 are stacked in a stacked structure. Figure 17 shows a transistor with a bottom gate structure called a channel-etched type. The cross section Q1-Q2 shown in (B) shows the wiring 216, including the pixel electrode 210 and the groove portion 230. j to the wiring 216_j+1. R2 is the product at the intersection of the wiring 212_i, the wiring 217, and the wiring 216_j+1. The layer structure is shown.

[0317] In the cross section P1-P2 shown in FIG. 17(A), a base layer 201 is formed on a substrate 200, A gate electrode 202, a gate electrode 243, and a capacitance electrode 215 are formed on an underlayer 201. In addition, a gate insulating layer 204 and a semiconductor layer 205 are formed on the gate electrode 202. In addition, a source electrode 206a and a drain electrode 206b are formed on the semiconductor layer 205. In addition, a source electrode 206a, a drain electrode 206b, and a An insulating layer 207 is formed on the source electrode 236a and the drain electrode 236b. A pixel electrode 210 is formed on the insulating layer 207, and a contact hole 210 is formed in the insulating layer 207. 1. It is electrically connected to the source electrode 236a of the transistor 121 via .

[0318] In addition, a contact hole in which the insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204 are partially removed is formed. A contact hole 209 is formed, and a wiring 213 is formed so as to overlap the contact hole 209. The wiring 213 connects the drain electrode 206b of the transistor 111 and the The gate electrode 243 of the gate electrode 121 is electrically connected. However, the insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204 are removed. A contact hole 214 is formed, and a wiring 22 is formed overlapping the contact hole 214. The capacitance electrode 215 and the wiring 217 are electrically connected by the wiring 213. The contact hole 208 is formed in the same layer as the pixel electrode 210. The contact holes 209, 214, and the groove 230 are formed in the same process. is formed.

[0319] Although not shown in FIG. 17A, the drain electrode 236b of the transistor 121 is electrically connected to the wiring 217. Note that in this embodiment, a part of the wiring 217 is An example is shown in which it functions as a drain electrode 236b (see FIG. 15).

[0320] Moreover, a partition layer 218 for separating the EL layer 271 for each pixel is formed on the insulating layer 207. In addition, an EL layer 271 is formed on the pixel electrode 210 and the partition wall layer 218. A counter electrode 226 is formed on the wall layer 218 and the EL layer 271. The portion where the EL layer 271 and the counter electrode 226 overlap functions as the EL element 116. do.

[0321] The capacitance electrode 215 and the drain electrode 206b connect the gate insulating layer 204 and the semiconductor layer 205. The overlapping portion sandwiched between them functions as a capacitor 113. The conductor layer 205 functions as a dielectric layer. By forming a multi-layered dielectric layer, even if a pinhole occurs in one dielectric layer, The pinhole is covered with another dielectric layer, so that the capacitive element 113 can function normally. In addition, since the relative dielectric constant of the oxide semiconductor is as high as 14 to 16, the semiconductor layer 205 When an oxide semiconductor is used, the capacitance of the capacitor 113 can be increased.

[0322] In the cross section Q1-Q2 shown in FIG. 17(B), a base layer 201 is formed on a substrate 200, A gate insulating layer 204 is formed on the base layer 201, and a semiconductor layer 20 is formed on the gate insulating layer 204. 5 are formed on the semiconductor layer 205. The wiring 217 is formed, and the semiconductor layer 205, the wiring 216_j, the wiring 216_j+1, and An insulating layer 207 is formed on the wiring 217. In addition, a pixel electrode 210 is formed on the insulating layer 207. is formed.

[0323] Between the wiring 216_j and the pixel electrode 210, the semiconductor layer 205 and a part of the insulating layer 207 are A removed groove 230 is formed. A groove 230 is formed by removing a part of the semiconductor layer 205 and the insulating layer 207. The groove 230 is configured so that at least its bottom surface does not have a semiconductor layer. do.

[0324] In the cross section R1-R2 shown in FIG. 18, an underlayer 201 is formed on a substrate 200. A wiring 212_i is formed on the wiring 212_i. A gate insulating layer 204 and a semiconductor layer 205 are formed on the semiconductor layer 205. In addition, wiring 217 and The wiring 216_j+1 of the adjacent pixel is formed, and the semiconductor layer 205, the wiring 217, and An insulating layer 207 is formed on the wiring 216_j+1. A wall layer 218 is formed, and a counter electrode 226 is formed on the partition layer 218. A groove 230 is formed by removing a portion of the insulating layer 207 and the body layer 205. 230 has a structure in which at least the bottom surface does not have a semiconductor layer. The wiring 212_i is not exposed at the bottom of the groove 230.

[0325] Next, an example of a pixel having a planar configuration different from that of FIG. 15 will be described with reference to FIG. 19 is a top view showing the planar configuration of the pixel 120. Note that, for ease of viewing the drawing, In FIG. 19, the underlayer 201, the gate insulating layer 204, the semiconductor layer 205, the insulating layer 207, the partition wall The layer 218, the EL layer 271, and the counter electrode 226 are omitted. The pixel 120 differs from the pixel 160 shown in FIGS. 15 and 16 in the planar configuration of the groove 230. The layer structure of the portion indicated by the dashed line P1-P2 in FIG. 19 is the same as that shown in FIG. 17(A). The configuration is the same as that described above.

[0326] The pixel 120 has a groove 230 between the wiring 217 and the pixel electrode 210, and between the wiring 216_j. and the pixel electrode 210. The width of the pixel 160 is not only extended beyond the edge of the pixel 160 but also wider than the pixel 160. The contact holes 209 and 214 are formed as grooves 230. The capacitor electrode 215 and the gate electrode 243 are integrally formed, and the grooves 230 are formed as much as possible around the capacitor electrode 215 and the gate electrode 243. In this way, by disposing the grooves 230 over a wide range, the parasitic transistor This makes it possible to more reliably prevent the formation of resistors.

[0327] Next, a semiconductor device that can be used in the EL display device described with reference to FIGS. 15 to 18 will be described. A method for manufacturing the device will be described with reference to FIGS. 21 to 23. The cross section P1-P2 in FIG. 15 corresponds to the part indicated by the dashed line P1-P2 in FIG. 16. The semiconductor device described in this embodiment is a cross-sectional view of the pixel electrode 210. Up to this step, the semiconductor device can be formed by the same steps as those of the semiconductor device shown in the first embodiment. Furthermore, at least the parts denoted by the same reference numerals as those used in the above embodiment are the same as those in the embodiment. It can be formed using the same materials and methods as those described in the first embodiment. , and detailed description thereof will be omitted in this embodiment.

[0328] First, an insulating layer that will become the base layer 201 is formed on the substrate 200, and a conductive layer is formed on the base layer 201. (See FIG. 21(A)). Then, a first photolithography process is performed on the conductive layer. A resist mask is formed on the conductive layer, and a part of the conductive layer is selectively removed to form a gate electrode 202 and a gate The electrode 243, the capacitance electrode 215, and the wiring 212_i (not shown in FIG. 21) are formed (FIG. 21 In this embodiment, aluminoborosilicate glass is used for the substrate 200, and the base Silicon oxynitride is used for the layer 201, and tungsten is used as the conductive layer.

[0329] Next, a gate electrode 202, a gate electrode 243, a capacitance electrode 215, and a wiring 212_i are formed on the gate electrode 202, the gate electrode 243, the capacitance electrode 215, and the wiring 212_i. A gate insulating layer 204 is formed, and a semiconductor layer 205 is formed on the gate insulating layer 204 (FIG. 21 In this embodiment, silicon oxynitride is used as the gate insulating layer 204. The semiconductor layer 205 is formed using an oxide semiconductor.

[0330] Next, a source electrode 206a, a drain electrode 206b, and a source electrode 206c are formed on the semiconductor layer 205. 236a, the drain electrode 236b, and the wiring 216_j (not shown in FIG. 21). In this embodiment mode, a conductive layer is formed using a multilayer of titanium, aluminum, and titanium. Then, a second photolithography process is performed to selectively remove a portion of the conductive layer. The source electrode 206a, the drain electrode 206b, the source electrode 236a, and the drain electrode The pole 236b and the wiring 216_j are formed (see FIG. 21(C)).

[0331] Next, the source electrode 206a, the drain electrode 206b, the source electrode 236a, and the drain electrode An insulating layer 207 is formed on the electrode 236b and the wiring 216_j (see FIG. 21(D)). In this embodiment, silicon oxide is formed as the insulating layer 207.

[0332] Next, a resist mask is formed by a third photolithography process, and a source electrode 2 is formed. A portion of the insulating layer 207 on the surface 36a is selectively removed to form a contact hole 208.

[0333] In the third photolithography process, first, a resist is formed on the insulating layer 207 using a multi-tone mask. A mask 261 is formed (see FIG. 22(A) and FIG. 13(A)).

[0334] The resist mask 261 covers the contact hole 208 and the groove 230 (not shown in FIG. 22). The recessed portion is located at a position overlapping the region where the contact hole 209 is formed. The resist mask 261 is not provided on the region where the resist mask 261 is to be formed.

[0335] Next, a first etching process is performed. Using the resist mask 261 as a mask, By performing the coating process, a part of the insulating layer 207, a part of the semiconductor layer 205, and the gate electrode 206 are removed. A part of the insulating layer 204 is etched to form a contact hole 209 (FIG. 22(B)). )). At the side of the contact hole 209, the insulating layer 207, the semiconductor layer 205, and The side surface of the gate insulating layer 204 is exposed. A part of the gate electrode 243 and a part of the gate electrode 206b are exposed.

[0336] Next, the resist mask 261 is shrunk by ashing using oxygen plasma or the like, and the A resist mask 262 is formed. At this time, the resist mask 262 is formed in a thin region (a recess ) is removed, and the insulating layer 207 is exposed (see FIG. 22(C)).

[0337] Next, a second etching process is performed. By the second etching process, the resist mask 26 2 is used as a mask to form the insulating layer 207 overlapping the source electrode 236a in the cross section P1-P2. A part of the contact hole 208 is formed by etching. 209, a part of the insulating layer 207 that is not covered with the resist mask 262, and A part of the semiconductor layer 205 is etched (see FIG. 23(A)). Although not shown, the groove 230 and the contact hole 208 are also formed by the second etching process. is formed in the same way.

[0338] The side surface of the insulating layer 207 is exposed at the side surface of the contact hole 208, and the source electrode 206 is formed at the bottom surface. On the side surface of the groove 230, the insulating layer 207 and the semiconductor layer 205 are exposed. The top surface is exposed, and the gate insulating layer 204 is exposed on the bottom surface.

[0339] Next, the pixel electrode 21 is formed on the insulating layer 207 by using a sputtering method, a vacuum deposition method, or the like. In this embodiment, ITO is formed as the transparent conductive layer. .

[0340] Subsequently, a resist mask is formed by a fourth photolithography process, and a conductive layer is selected. The pixel electrode 210, the wiring 213, and the wiring 223 (not shown in FIG. 23) are selectively etched. (See FIG. 23(B)).

[0341] The pixel electrode 210 is connected to the source electrode 2 of the transistor 121 through the contact hole 208. 36a. In addition, in the contact hole 209, The drain electrode 206b and the gate electrode 243 are electrically connected to each other. In the hole 214, the capacitance electrode 215 and the wiring 217 are electrically connected via the wiring 223. The terminal portion 103 and the terminal portion 104 are also formed in the same manner as in the above embodiment. can be done.

[0342] Next, a partition layer 218 is provided on the pixel region 102 (see FIG. 23(C)). The material for forming the partition wall may be an organic insulating material or an inorganic insulating material. The layer 218 is provided with an opening 2 that overlaps with the pixel electrode 210 by a fifth photolithography process. 16 and 17(B)). The sidewall shape of the partition layer 218 is It is preferable that the partition layer 218 has a rectangular shape or a shape having a curvature. If a photosensitive material is used, the partition wall layer 218 can be formed without using a photoresist. Furthermore, the sidewall shape of the partition wall layer 218 can be made to have a curved shape. Materials for forming 18 include acrylic resin, phenolic resin, polystyrene, In this embodiment, a photosensitive polymer such as polyethyleneimide can be used as the partition layer 218. Polyimide is used.

[0343] The partition wall layer 218 is formed between the contact hole 208, the contact hole 209, and the contact The barrier layer 218 is also formed on the hole 214 and the groove 230. 08, the contact hole 209, the contact hole 214, and the groove portion 230 are filled. The end portions of the semiconductor layer and the insulating layer exposed when the contact holes and the grooves are formed are then By adopting this configuration, the exposed portion can be protected. Therefore, the reliability of the semiconductor device can be improved. It is not formed on the portion 103 and the terminal portion 104 .

[0344] Next, the EL layer 271 is formed in the area of ​​the opening 272 that contacts the pixel electrode 210. The counter electrode 226 is formed on the EL layer 271 and the partition layer 218 (see FIG. 23(C)). .

[0345] The pixel electrode 210 functions as one electrode of the EL element 116. The counter electrode 226 It functions as the other electrode of the EL element 116. The EL layer 271 includes a hole injection layer, a hole A transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, etc. may be laminated. When the layer 10 is used as an anode, the pixel electrode 210 is made of a material having a work function larger than that of the hole injection layer. In addition, when the pixel electrode 210 has a multi-layered structure, at least a hole injection material is used. The pixel electrode 210 is made of a material having a large work function. When the counter electrode 226 is used as a cathode, the counter electrode 226 is provided with a layer having a work function smaller than that of the electron injection layer. Specifically, the counter electrode 226 is made of a material containing aluminum and lithium. An alloy of the following can be used.

[0346] Note that in this embodiment, one embodiment of the present invention is described as An example of application to a bottom emission structure in which light is extracted from the surface on the substrate 200 side is shown. However, one embodiment of the present invention is a top-emission type in which light is extracted from the surface of the EL element 116 opposite to the substrate 200. The display device has a top emission structure, and the display device has a double emission structure that emits light from both sides. The present invention can also be applied to a display device having a dual emission structure. In the case of a surface emission structure, the pixel electrode 210 is used as a cathode and the counter electrode 226 is used as an anode. The injection layer, transport layer, and light-emitting layer that make up the EL layer 271 are arranged in the reverse order to that of the bottom emission structure. It is sufficient to stack them.

[0347] According to this embodiment, a semiconductor device can be fabricated using fewer photolithography steps than in the past. Therefore, an EL display device can be produced at low cost and with good productivity. Furthermore, according to this embodiment, a semiconductor device with excellent reliability and little deterioration in electrical characteristics can be obtained. Therefore, it is possible to manufacture an EL display device with excellent reliability. can be done.

[0348] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0349] (Fourth embodiment) FIG. 24 illustrates one mode of an EL display device using the transistor described in Embodiment 1 as an example.

[0350] FIG. 24A shows a structure in which a transistor 4010 and an EL element 4113 are disposed on a first substrate 4001. 4 is a plan view of a panel sealed between a first substrate 4006 and a second substrate 4006 by a sealing material 4105; FIG. 24(B) corresponds to a cross-sectional view taken along line N1-N2 in FIG. 24(A). A groove 4040 is provided on the plate 4001 .

[0351] A sealing material 4105 is formed so as to surround a pixel portion 4002 provided on a first substrate 4001. A second substrate 4006 is provided on the pixel portion 4002. 02 is sealed by a first substrate 4001, a sealing material 4105, and a second substrate 4006. The sealing material 4105 can be formed using a known sealing material, glass frit, or the like. Specifically, materials such as organic resins such as thermosetting resins or photocurable resins, and low-melting-point glass are used. The sealing material may also contain a desiccant.

[0352] A space 400 surrounded by a first substrate 4001, a second substrate 4006, and a sealing material 4105. 7 is filled with a gas, particularly a gas that is inert to the EL element 4113. For example, it is preferable to use a rare gas or nitrogen as the gas. It's nice.

[0353] In addition, the area outside the area surrounded by the sealing material 4105 on the first substrate 4001 The input terminal 4020 is provided on the FPC 4018a (Flexible Printed Circuit) FPC4018a is a separate, different The FPC 4018b is electrically connected to a signal line driver circuit 4003 formed on a substrate. The pixel portion is electrically connected to a scanning line driver circuit 4004 that is fabricated on a different substrate. Various signals and potentials are applied to 4002 via FPC4018a and FPC4018b. Then, the signals are supplied from a signal line driver circuit 4003 and a scanning line driver circuit 4004 .

[0354] The method of connecting the drive circuit fabricated on a separate substrate is not particularly limited. , COG, wire bonding, TCP, etc. can be used.

[0355] Although not shown, the signal line driver circuit 4003 or the scanning line driver circuit 4004 is The transistors disclosed in this specification may be formed on the first substrate 4001 .

[0356] The display device shown in FIG. 24B includes a wiring 4015 and an electrode 4016. 15 and the electrode 4016 are connected to the terminal of the FPC 4018a via the anisotropic conductive layer 4019. , are electrically connected.

[0357] The wiring 4015 is formed from the same conductive layer as the source electrode and the drain electrode of the transistor 4010. The electrode 4016 is connected to a first electrode 4130 which is one of the electrodes of the EL element 4113. They are formed from the same conductive layer.

[0358] In this embodiment, the transistor 4010 is the transistor shown in the above embodiment. The transistor 4010 provided in the pixel portion 4002 is an EL element. and electrically connect them to form a display panel.

[0359] The display device shown in FIG. 24B is an example in which an EL element is used as a display element. In FIG. 24B, the EL element 4113 has a first electrode 4130, a second electrode 4131, and a and an EL layer 4108. The EL element 4113 and other EL elements 4113 are electrically connected to each other. A partition wall layer 4009 is also provided on the groove 4040 to effectively separate the layers.

[0360] By filling the groove 4040 with the partition layer 4009, the semiconductor exposed when the groove 4040 is formed is prevented from being damaged. By adopting this configuration, the side surfaces of the body layer and the insulating layer can be covered. Since the portion can be protected, the reliability of the semiconductor device can be improved.

[0361] In addition, by using an oxide semiconductor for the semiconductor layer of the transistor described in this embodiment, Compared to transistors using ruthenium silicon, this provides a high field-effect mobility. Therefore, the use of the above transistor in the pixel portion of an EL display device allows for high-speed driving. In addition, the transistors can be mounted on the same substrate. It can be manufactured separately into a driver circuit section or a pixel section, so the components of an EL display device can be The number can be reduced.

[0362] As described above, by applying the transistors exemplified in the above embodiments, the transistors The number of photomasks used in the manufacturing process of a display device with high reliability can be reduced. Therefore, an EL display device with improved performance can be manufactured at low cost and with high productivity. Therefore, it is possible to provide an EL display device with excellent reliability.

[0363] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0364] (Embodiment 5) In this embodiment, a structural example of a transistor will be described. A part or a part having the same function and a step can be performed in the same manner as in the above embodiment. Therefore, the repeated explanation in this embodiment will be omitted. do.

[0365] A transistor 2450 shown in FIG. 25A has a gate electrode 2401 formed on a substrate 2400. A gate insulating layer 2402 is formed on the gate electrode 2401, and a gate insulating layer 240 2, an oxide semiconductor layer 2403 is formed on the source electrode 2 The oxide semiconductor layer 240 is formed on the gate electrode 405a and the drain electrode 2405b. 3. An insulating layer 2407 is formed on the source electrode 2405a and the drain electrode 2405b. A protective insulating layer 2409 may be formed on the insulating layer 2407. A base layer may be formed between the gate electrode 2401 and the semiconductor layer 400. It is a type of bottom-gate transistor and also an inverted staggered transistor. .

[0366] A transistor 2460 shown in FIG. 25B has a gate electrode 2401 formed on a substrate 2400. A gate insulating layer 2402 is formed on the gate electrode 2401, and a gate insulating layer 240 An oxide semiconductor layer 2403 is formed on the insulating film 2, and a channel protection layer 2404 is formed on the oxide semiconductor layer 2403. 2406 is formed on the channel protection layer 2406 and the oxide semiconductor layer 2403. A source electrode 2405a and a drain electrode 2405b are formed on the gate electrode 2405. A protective insulating layer 2409 may be formed over the gate electrode 2405a and the drain electrode 2405b. A base layer may be formed between the substrate 2400 and the gate electrode 2401. 0 is a transistor with a bottom gate structure called a channel protection type (also called a channel stop type). It is also a type of inverted staggered transistor. The insulating layer 06 can be formed using the same materials and methods as the other insulating layers. The cross-sectional shape of the end of the layer 2406 is tapered or stepped, so that the source electrode 2405 a, or occurs near the end of the channel protection layer 2406 overlapping with the drain electrode 2405b. This can reduce the electric field concentration that may occur, thereby suppressing the deterioration of the electrical characteristics of the transistor 2460. can.

[0367] A transistor 2470 shown in FIG. 25C is a transistor in which a base layer 2436 is formed over a substrate 2400. The oxide semiconductor layer 2403 is formed over the base layer 2436. A source electrode 2405a and a drain electrode 2405b are formed on the base layer 2436. The oxide semiconductor layer 2403, the source electrode 2405a, and the drain electrode 2405b are A gate insulating layer 2402 is formed, and a gate electrode 2401 is formed on the gate insulating layer 2402. A protective insulating layer 2409 may be formed over the gate electrode 2401. Transistor 2470 is one of the top-gate structure transistors.

[0368] The transistor 2480 shown in FIG. 25(D) has a first gate electrode 24 11 is formed, and a first gate insulating layer 2413 is formed on the first gate electrode 2411. The oxide semiconductor layer 2403 is formed over the first gate insulating layer 2413. 2403 and the first gate insulating layer 2413, a source electrode 2405a and a drain electrode The oxide semiconductor layer 2403 and the source electrode 2405 are formed on the oxide semiconductor layer 2403. A second gate insulating layer 2414 is formed on the gate electrode 2405a and the drain electrode 2405b. A second gate electrode 2412 is formed on the gate insulating layer 2414. The pixel electrode 2412 may be formed using the same layer as the pixel electrode shown in the above embodiment mode. A protective insulating layer may be formed on the second gate electrode 2412. A base layer may be formed between the gate electrodes 2411 .

[0369] The transistor 2480 is a combination of the transistors 2450 and 2470. The first gate electrode 2411 and the second gate electrode 2412 are electrically connected to each other. The first gate electrode 2411 and the second gate electrode 2412 can function as one gate electrode. The two gate electrodes 2412 may be supplied with different potentials.

[0370] Either the first gate electrode 2411 or the second gate electrode 2412 is simply used as a gate electrode. The back gate electrode has a gate The same potential as the target electrode may be applied, or a fixed potential such as ground potential or common potential may be applied. In addition, by controlling the potential applied to the back gate electrode, The threshold voltages of transistor 2480 and transistor 2570 can be controlled.

[0371] The back gate electrode is formed of a conductive material having a light-shielding property. By covering the channel formation region of the oxide semiconductor layer 2403 with Therefore, the light can be prevented from entering the oxide semiconductor layer 2403. 403, which causes deterioration of characteristics such as a shift in the threshold voltage of the transistor. This can prevent rubbing.

[0372] The transistor 2550 shown in FIG. 26A has a gate electrode 2401 formed on a substrate 2400. A gate insulating layer 2402 is formed on the gate electrode 2401, and a gate insulating layer 240 2, a source electrode 2405a and a drain electrode 2405b are formed, and a gate insulating layer 2 402, the oxide semiconductor layer 240 is formed on the source electrode 2405a and the drain electrode 2405b. 3 is formed. In addition, the oxide semiconductor layer 2403, the source electrode 2405a, and the drain electrode 2405b are formed. An insulating layer 2407 is formed on the inner electrode 2405b. A protective insulating layer 2409 may be formed between the substrate 2400 and the gate electrode 2401. The transistor 2550 is a type of transistor with a bottom gate structure. It is also one of the inverted staggered transistors.

[0373] In the transistor 2560 shown in FIG. 26B, a base layer 2436 is formed over a substrate 2400. A source electrode 2405a and a drain electrode 2405b are formed on the base layer 2436. , an oxide semiconductor layer is formed on the underlayer 2436, the source electrode 2405a, and the drain electrode 2405b. The oxide semiconductor layer 2403, the source electrode 2405a, and the drain electrode 2405b are formed on the semiconductor layer 2403. A gate insulating layer 2402 is formed on the gate electrode 2405b, and a gate insulating layer 2402 is formed on the gate insulating layer 2402. A protective insulating layer 2409 is formed on the gate electrode 2401. The transistor 2560 is one of the top-gate transistors. do.

[0374] The transistor 2570 shown in FIG. 26C has a first gate electrode 24 11 is formed, and a first gate insulating layer 2413 is formed on the first gate electrode 2411. , a source electrode 2405a and a drain electrode 2405b are formed on the first gate insulating layer 2413. The first gate insulating layer 2413, the source electrode 2405a, and the drain electrode 2405b are formed. The oxide semiconductor layer 2403 is formed on the source electrode 405b. A second gate insulating layer 2414 is formed on the gate electrode 2405a and the drain electrode 2405b. A second gate electrode 2412 is formed on the second gate insulating layer 2414. The port electrode 2412 may be formed using the same layer as the pixel electrode shown in the above embodiment mode. A protective insulating layer may be formed on the second gate electrode 2412. An underlying layer may be formed between the first gate electrode 2410 and the first gate electrode 2411.

[0375] Transistor 2570 is a combination of transistors 2550 and 2560. The first gate electrode 2411 and the second gate electrode 2412 are electrically connected to each other. The first gate electrode 2411 and the second gate electrode 2412 can function as one gate electrode. One of the two gate electrodes 2412 is simply called the gate electrode, and the other is called the back gate. It is sometimes called a port electrode.

[0376] As mentioned above, the threshold voltage of the transistor can be controlled by changing the potential of the back gate electrode. The voltage can be changed. In addition, the back gate is made of a conductive material with light blocking properties. By covering the channel formation region of the oxide semiconductor layer 2403 with the back electrode, Light can be prevented from entering the oxide semiconductor layer 2403 from the electrode side. The semiconductor layer 2403 is prevented from light degradation and the deterioration of characteristics such as a shift in the threshold voltage of the transistor is prevented. This can prevent the occurrence of catastrophic changes.

[0377] An insulating layer in contact with the oxide semiconductor layer 2403 (in this embodiment, the gate insulating layer 240 2, insulating layer 2407, channel protection layer 2406, underlayer 2436, first gate insulating layer 2 413, and the second gate insulating layer 2414.) contains a group 13 element and oxygen. It is preferable to use an insulating material. Many oxide semiconductor materials contain elements of Group 13. Insulating materials containing Group 13 elements are compatible with oxide semiconductors, and when they are bonded to oxide semiconductors, By using the oxide semiconductor as an insulating layer, the state of the interface with the oxide semiconductor can be kept good.

[0378] An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of insulating materials containing Group 13 elements include gallium oxide and aluminum oxide. gallium oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Aluminum gallium is a material that has a higher aluminum content (atomic %) than the gallium content (atomic %). Gallium aluminum oxide refers to the gallium content (atomic %) of indicates an aluminum content (atomic %) of 100 or more.

[0379] For example, when an insulating layer is formed in contact with an oxide semiconductor layer containing gallium, By using a material containing gallium oxide, the interface characteristics between the oxide semiconductor layer and the insulating layer can be maintained good. For example, an oxide semiconductor layer and an insulating layer containing gallium oxide can be provided in contact with each other. This can reduce the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating layer. When an element of the same group as the component element of the oxide semiconductor layer is used for the insulating layer, For example, it is possible to obtain a similar effect by using an insulating layer made of a material containing aluminum oxide. It is also effective to form a film of aluminum oxide, which has the characteristic of being difficult for water to pass through. Therefore, the use of this material is effective in preventing water from entering the oxide semiconductor layer. This is also preferable in this respect.

[0380] In addition, the insulating layer in contact with the oxide semiconductor layer 2403 is formed by introducing oxygen into the bulk. to have a region with more oxygen than the stoichiometric composition (having an oxygen excess region) The term "bulk" means that oxygen is added not only to the surface of the layer but also to the inside of the layer. The introduction of oxygen can be achieved by ion implantation, ion doping, or proton implantation. This can be done using a plasma implantation ion implantation method or the like. It can also be performed by heat treatment in an oxygen atmosphere or plasma treatment in an oxygen atmosphere. can.

[0381] When the insulating layer having an oxygen-excess region is in contact with the oxide semiconductor layer, the excess oxygen in the insulating layer is The element is supplied to the oxide semiconductor layer and is deposited in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and the insulating layer. The oxide semiconductor layer can be made i-type or substantially i-type by reducing oxygen vacancies in the surface. can.

[0382] A transistor having an i-type or substantially i-type oxide semiconductor exhibits fluctuations in electrical characteristics. Therefore, it is a highly reliable material with stable electrical characteristics. Therefore, a semiconductor device with a high resistance can be provided.

[0383] Note that the insulating layer having an oxygen-excess region is an insulating layer in contact with the oxide semiconductor layer 2403, It may be used for only one of the upper insulating layer or the lower insulating layer. It is preferable to use it for both insulating layers. The insulating layers are used as upper and lower insulating layers in contact with the oxide semiconductor layer 2403. By sandwiching the oxide semiconductor layer 2403, the above effect can be further enhanced. .

[0384] The insulating layers used as the upper and lower layers of the oxide semiconductor layer 2403 have the same structure. The insulating layer may have one constituent element, or may have a different constituent element.

[0385] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0386] (Embodiment 6) The display device described in the above embodiment can be applied to a semiconductor device that displays 3D images. In this embodiment, a display device that switches between a left-eye image and a right-eye image at high speed is used. Using a device, you can view 3D videos or still images using special glasses that synchronize with the image on the display device. An example of viewing an image is shown in FIG.

[0387] In FIG. 27A, a display device 2711 and dedicated eyeglasses 2701 are connected by a cable 2703. The display device 2711 uses the display device disclosed in this specification. The dedicated eyeglasses body 2701 has a left eye panel 2702a and a right eye panel 2702b. The shutters provided on the display device 27 are alternately opened and closed to allow the user to 11 images can be recognized as 3D.

[0388] Also, a block diagram of the main configuration of the display device 2711 and the dedicated eyeglasses body 2701 is shown. Shown in Figure 27(B).

[0389] The display device 2711 shown in FIG. 27(B) includes a display control circuit 2716, a display portion 2717, a timer 2718, a timer 2719, a timer 2720, a timer 2721, a timer 2722, a timer 2723, a timer 2724, a timer 2725, a timer 2726, a timer 2727, a timer 2728, a a timing generator 2713, a source line side driving circuit 2718, an external operating means 2722, and a gate It has a line side driving circuit 2719. It is possible to operate it by an external operating means 2722 such as a keyboard. The output signal is varied depending on the

[0390] The timing generator 2713 generates a start pulse signal and the like, and also generates the left eye image signal. a signal for synchronizing the image for the right eye with the shutter of the left-eye panel 2702a; The signal for synchronizing with the shutter of the display panel 2702b is generated.

[0391] A synchronization signal 2731a for the left-eye image is input to a display control circuit 2716 and displayed on a display unit 2717. At the same time, a synchronization signal 2730a that opens the shutter of the left eye panel 2702a is sent to the left. The right-eye video synchronization signal 2731b is input to the display control circuit 2702a. The image is input to the path 2716 and displayed on the display unit 2717, and at the same time, the right eye panel 2702b A synchronization signal 2730b that opens the shutter is input to the right eye panel 2702b.

[0392] In addition, in order to switch between the image for the left eye and the image for the right eye at high speed, the display device 2711 is equipped with a light-emitting diode. Using diodes (LEDs), a time-division additive color mixing method (field It is preferable to use a sequential method.

[0393] In addition, since the field sequential method is used, the timing generator 2713 is A signal synchronized with the synchronization signals 2730a and 2730b is also input to the backlight section of the diode. It is preferable that the backlight section has R, G, and B LEDs. .

[0394] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0395] (Embodiment 7) In this embodiment mode, examples of electronic devices including the display device described in the above embodiment mode will be described. explain.

[0396] FIG. 28(A) shows a notebook personal computer, which includes a main body 3001 and a housing 300 2, a display unit 3003, a keyboard 3004, etc. By applying the display device shown in the above, a highly reliable notebook-type personal computer can be realized. It can be used as a data.

[0397] FIG. 28(B) shows a portable digital assistant (PDA), and a main body 3021 includes a display unit 3023 and a An external interface 3025 and operation buttons 3024 are provided. The display device shown in the above embodiment mode is applied to the stylus 3022. This makes it possible to make a highly reliable personal digital assistant (PDA).

[0398] FIG. 28C shows an example of an electronic book. For example, the electronic book is made up of a housing 2706 and The housing 2706 and the housing 2704 are made up of two housings. The opening and closing operation can be performed with the shaft portion 2712 as an axis. This configuration allows the device to function like a paper book.

[0399] The housing 2706 incorporates a display unit 2705, and the housing 2704 incorporates a display unit 2707. The display unit 2705 and the display unit 2707 are configured to display continuous images. Alternatively, a different image may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 28C), and An image can be displayed on the display unit (display unit 2707 in FIG. 28(C)). By applying the display device shown in the above form, a highly reliable e-book reader can be obtained. .

[0400] FIG. 28C shows an example in which an operating unit and the like are provided in the housing 2706. For example, In the housing 2706, a power terminal 2721, operation keys 2723, a speaker 2725, etc. The operation key 2723 can be used to turn pages. A keyboard and a pointing device may be provided on the same surface. External connection terminals (earphone terminal, USB terminal, etc.) and recording medium insertion port are located on the back and sides of the body. Furthermore, the electronic book may have a function as an electronic dictionary. This may also be configured as follows.

[0401] The electronic book may be configured to be capable of transmitting and receiving information wirelessly. It is also possible to purchase and download desired book data from the server. be.

[0402] FIG. 28(D) shows a mobile phone, which is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 contains a display panel 2802, a speaker 2803, a microphone, and 2804, pointing device 2806, camera lens 2807, external connection terminal The housing 2800 also includes a solar panel for charging the portable information terminal. It is equipped with a battery cell 2810, an external memory slot 2811, etc. The antenna is also attached to the case. It is built into the body 2801.

[0403] The display panel 2802 is equipped with a touch panel, and the image displayed on the display panel 2802 is shown in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0404] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera lens 2802, so video calls are possible. The speaker 2803 and microphone 2804 are not limited to voice calls, but also to video calls, Recording and playback are possible. Furthermore, the housing 2800 and the housing 2801 can be slid apart. As shown in 28(D), it can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0405] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. do.

[0406] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. By applying the display device described in the above embodiment mode, a highly reliable mobile phone can be provided. It is possible.

[0407] FIG. 28(E) shows a digital video camera, which includes a main body 3051, a display unit (A) 3057, Eyepiece 3053, operation switch 3054, display unit (B) 3055, battery 3056, etc. By applying the display device described in the above embodiment, This makes it possible to make a highly reliable digital video camera.

[0408] FIG. 28(F) shows an example of a television device. The television device has a housing 96 The display unit 9603 is incorporated in the camera body 9601. The display unit 9603 can display images. In this example, the housing 9601 is supported by a stand 9605. By applying the display device described in the above embodiment, a highly reliable television It can be a vision device.

[0409] The television set can be operated using an operation switch on the housing 9601 or a separate remote control. In addition, the remote control device can be configured to output the A display unit for displaying information may be provided.

[0410] The television device is assumed to be equipped with a receiver, modem, etc. It can receive television broadcasts and can also communicate by wire or wireless via a modem. By connecting to a network, you can send and receive data in one direction (sender to receiver) or two directions (sender to receiver). It is also possible to communicate information between the recipient and the receiver, or between receivers themselves.

[0411] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Explanation of symbols]

[0412] 100 Semiconductor device 101 Substrate 102 pixel area 103 Terminal section 104 Terminal section 105 terminal 106 terminals 107 terminal 108 terminals 110 pixels 111 Transistor 112 Liquid crystal element 113 Capacitor element 114 Electrode 115 nodes 116 EL element 120 pixels 121 Transistor 130 pixels 150 Semiconductor devices 160 pixels 200 boards 201 Base layer 202 gate electrode 203 Wiring 204 Gate insulating layer 205 Semiconductor layer 207 Insulating layer 208 Contact Hole 209 Contact Hole 210 pixel electrode 211 Pixel electrode 212 Wiring 213 Wiring 214 Contact Hole 215 Capacitive electrode 216 Wiring 217 Wiring 218 Partition layer 219 Contact Hole 220 Contact Hole 221 Electrode 222 Electrode 223 Wiring 224 Wiring 225 Counter electrode connection part 226 Counter electrode 230 Groove 231 End 232 End 233 End 234 End 240 Groove 243 Gate electrode 251 Groove 252 Groove 253 Groove 254 Groove 255 Groove 256 Groove 257 Groove 258 Groove 261 Resist Mask 262 Resist mask 271 EL layer 272 Opening 301 Transparent substrate 302 Light blocking section 303 Diffraction Grating 304 Gray Tone Mask 311 Transparent substrate 312 Semi-transparent part 313 Light-shielding part 314 Halftone Mask 2400 board 2401 Gate electrode 2402 Gate insulating layer 2403 Oxide semiconductor layer 2406 Channel Protection Layer 2407 Insulation layer 2409 Protective insulation layer 2411 Gate electrode 2412 Gate electrode 2413 Gate insulating layer 2414 Gate insulating layer 2436 Base layer 2450 transistor 2460 transistor 2470 transistor 2480 transistor 2550 transistor 2560 transistors 2570 transistor 2701 Glasses 2703 Cable 2704 Housing 2705 ​​Display section 2706 Housing 2707 Display section 2711 Display device 2712 Shaft 2713 Timing Generator 2716 Display control circuit 2717 Display section 2718 Source line side driver circuit 2719 Gate line side driving circuit 2721 Power terminal 2722 External operation means 2723 Operation Key 2725 Speaker 2800 chassis 2801 Case 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 External Memory Slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main Unit 3022 stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3056 Battery 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4007 Space 4008 Liquid crystal layer 4009 Partition layer 4010 transistor 4013 Liquid crystal element 4015 Wiring 4016 Electrode 4019 Anisotropic conductive layer 4020 Input terminal 4030 Electrode 4031 Electrode 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4040 Groove 4105 Sealing materials 4108 EL layer 4113 EL element 4130 Electrode 4131 Electrode 9601 Housing 9603 Display section 9605 Stand 105_i terminal 106_j terminal 206a Source electrode 206b Drain electrode 212_i wiring 216_j Wiring 236a Source electrode 236b Drain electrode 2405a Source electrode 2405b Drain electrode 2702a Left eye panel 2702b Right eye panel 2730a sync signal 2730b sync signal 2731a Sync signal 2731b Sync signal 4018a FPC 4018b FPC

Claims

[Claim 1] a transistor having a gate electrode, a source electrode, a drain electrode, and a semiconductor layer; a first wiring electrically connected to the gate electrode; a second wiring electrically connected to the source electrode; a pixel electrode electrically connected to the drain electrode; Capacitive wiring, A groove portion; and the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring; the groove is formed on the first wiring so as to cross the line width direction of the first wiring, the trench is formed on the capacitance line across a line width direction of the capacitance line, the groove is formed in a direction in which the second wiring extends, beyond an end of the pixel electrode; The semiconductor device has a bottom surface in which the semiconductor layer is removed, and the groove overlaps the first wiring and the capacitor wiring with an insulating layer interposed therebetween.

Images