Memory system

Abstract

To provide a memory system that efficiently reads data.SOLUTION: A memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of memory cells. The memory controller reads first data from a plurality of memory cells using a first voltage and stores the first data in a memory circuit, reads second data from a bit group including each bit of the plurality of memory cells using a first read voltage group, performs an error correction process for the second data, and when error correction for the second data is successful and third data is obtained, determines a second read voltage group based on the first data, second data, and third data stored in the memory circuit.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD Embodiments generally relate to memory systems. [Background technology]

[0002] 2. Description of the Related Art Memory systems including a memory and a controller for controlling the memory are known, and are required to store data with high reliability. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,892,799 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a memory system that efficiently reads data. [Means for solving the problem]

[0005] According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller reads first data from the plurality of memory cells using a first voltage and stores the first data in a memory circuit. The memory controller reads second data from a bit group including respective bits of the plurality of memory cells using a first set of read voltages. The memory controller performs an error correction process on the second data. When the error correction on the second data is successful and third data is obtained, the memory controller determines a second set of read voltages based on the first data, the second data, and the third data stored in the memory circuit. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 shows an example of components and connections of the components in a memory system according to the first embodiment. [Figure 2] FIG. 2 shows components of a block of semiconductor memory in the memory system of the first embodiment and connections of the components. [Figure 3] FIG. 3 shows an example of the structure of a part of the memory cell array of the memory system according to the first embodiment. [Figure 4] FIG. 4 shows an example of the distribution of threshold voltages of memory cell transistors and data mapping in the memory system of the first embodiment. [Figure 5] FIG. 5 shows an example of functional blocks during operation of the memory system of the first embodiment. [Figure 6] FIG. 6 shows the flow of the operation of the memory system of the first embodiment. [Figure 7] FIG. 7 shows the concept of the first type shift amount estimation by the memory system of the first embodiment. [Figure 8] FIG. 8 shows data obtained by the operation of the memory system of the first embodiment. [Figure 9] FIG. 9 shows the flow of the operation of the memory system of the first embodiment. [Figure 10] FIG. 10 shows an example of data obtained during operation of the memory system of the first embodiment. [Figure 11] FIG. 11 shows another example of data obtained during operation of the memory system of the first embodiment. [Figure 12] FIG. 12 shows the concept of second-type shift amount estimation by the memory system of the first embodiment. [Figure 13] FIG. 13 shows the flow of the operation of the memory system of the first embodiment. [Figure 14] FIG. 14 shows the concept of second-type shift amount estimation by the memory system of the second embodiment. [Figure 15] FIG. 15 shows the concept of second-type shift amount estimation by the memory system of the second embodiment. [Figure 16] FIG. 16 shows the concept of second-type shift amount estimation by the memory system of the second embodiment. [Figure 17]FIG. 17 shows the concept of second-type shift amount estimation by the memory system of the second embodiment. [Figure 18] FIG. 18 shows the concept of second-type shift amount estimation by the memory system of the second embodiment. [Figure 19] FIG. 19 shows the concept of second-type shift amount estimation by the memory system of the second embodiment. [Figure 20] FIG. 20 shows the flow of operations in the memory system of the second embodiment. [Figure 21] FIG. 21 shows the concept of second-type shift amount estimation by the memory system according to the modified example of the second embodiment. [Figure 22] FIG. 22 shows the concept of second-type shift amount estimation by the memory system according to the modified example of the second embodiment. [Figure 23] FIG. 23 shows the concept of second-type shift amount estimation by the memory system according to the modified example of the second embodiment. [Figure 24] FIG. 24 shows the concept of second-type shift amount estimation by the memory system according to the modified example of the second embodiment. [Figure 25] FIG. 25 shows the concept of second-type shift amount estimation by the memory system according to the modified example of the second embodiment. [Figure 26] FIG. 26 shows the concept of second-type shift amount estimation by the memory system according to the modified example of the second embodiment. [Figure 27] FIG. 27 shows the flow of operations in a memory system according to a modification of the second embodiment. [Figure 28] FIG. 28 shows an example of functional blocks during operation of the memory system of the third embodiment. [Figure 29] FIG. 29 shows a flow of an operation of the memory system of the third embodiment. [Figure 30] FIG. 30 shows the concept of the operation of the memory system of the third embodiment, and shows an example of combined page data. [Figure 31] FIG. 31 shows the flow of operations in the memory system of the third embodiment. [Figure 32]FIG. 32 shows the flow of operations in a memory system according to a modification of the third embodiment. [Figure 33] FIG. 33 shows the concept of the first type shift amount estimation by the memory stem of the fourth embodiment. [Figure 34] FIG. 34 shows the concept of the first type shift amount estimation by the memory stem of the fourth embodiment. [Figure 35] FIG. 35 shows the concept of the first type shift amount estimation by the memory stem of the fourth embodiment. [Figure 36] FIG. 36 shows the concept of the first type shift amount estimation by the memory stem of the fourth embodiment. [Figure 37] FIG. 37 shows the concept of operation of the memory cell of the fourth embodiment, and shows an example of combined page data. [Figure 38] FIG. 38 shows the flow of operations in the memory system of the fourth embodiment. [Figure 39] FIG. 39 shows the flow of operations in the memory system of the fourth embodiment. [Figure 40] FIG. 40 shows the flow of operations in the memory system of the fourth embodiment. [Figure 41] FIG. 41 shows the concept of the first type shift amount estimation by the memory system according to the second modified example of the fourth embodiment. [Figure 42] FIG. 42 shows the concept of the first type shift amount estimation by the memory system of the third modified example of the fourth embodiment. [Figure 43] FIG. 43 shows the flow of operations in a memory system according to the fourth modified example of the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In some embodiments or different embodiments, components having substantially the same functions and configurations may be distinguished from one another by adding an additional number or letter to the end of the reference numeral. In the embodiment following a certain described embodiment, differences from the described embodiment will be mainly described. All descriptions of one embodiment also apply to descriptions of other embodiments, unless explicitly or obviously excluded.

[0008] Any steps in the method flows of the embodiments are not limited to the illustrated order and may occur in an order different from the illustrated order and / or in parallel with other steps unless otherwise indicated.

[0009] 1. First embodiment 1.1.Structure (composition) Memory System Fig. 1 shows an example of components and connections of the components in a memory system according to the first embodiment. Fig. 1 shows the hardware configuration.

[0010] As shown in FIG. 1, an information processing system 1 includes a host device 2 and a memory system 3.

[0011] The host device 2 is a device that processes data using the memory system 3. Examples of the host device 2 include a personal computer and a server in a data center.

[0012] The memory system 3 is a device for storing data. An example of the memory system 3 is an SD TM The memory system 3 includes a memory card such as a card, a Universal Flash Storage (UFS), and a Solid State Drive (SSD). The memory system 3 stores, reads, and erases data in response to a request from the host device 2. The memory system 3 can also store, read, and erase data without a request from the host device 2.

[0013] The memory system 3 includes a memory controller 10 , a non-volatile memory 20 , and a volatile memory 30 .

[0014] An example of the nonvolatile memory 20 includes a NAND flash memory. The nonvolatile memory 20 includes a plurality of blocks BLK (BLK0 to BLK3). Each block BLK includes a plurality of memory cells. Each memory cell stores data in a nonvolatile manner. In one example, the block BLK is a unit of data erasure.

[0015] An example of the volatile memory 30 includes a dynamic random access memory (DRAM). The volatile memory 30 stores information such as information about a read voltage used when reading data from the nonvolatile memory 20.

[0016] The memory controller 10 is a controller that controls the nonvolatile memory 20. An example of the form of the memory controller 10 includes an integrated circuit such as a System-on-a-Chip (SoC). The memory controller 10 controls the nonvolatile memory 20 to perform processing requested by the host device 2. Specifically, the memory controller 10 writes write data to the nonvolatile memory 20 based on a write request from the host device 2. The memory controller 10 reads read data from the nonvolatile memory 20 based on a read request from the host device 2, and transmits data based on the read data to the host device 2.

[0017] The memory controller 10 includes a CPU 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a host interface (host I / F) 14, a non-volatile memory interface (NVMI / F) 15, a volatile memory interface (VMI / F) 16, and an error correction circuit 17.

[0018] The CPU 11 is a circuit that controls the overall operation of the memory controller 10. The memory controller 10 performs various operations by having the CPU 11 execute programs stored in the ROM 12 and loaded onto the RAM 13. The firmware is configured to enable the CPU 11 to perform the operations described in each embodiment and to realize the functional blocks described in each embodiment.

[0019] The ROM 12 is a non-volatile memory. An example of the ROM 12 is an EEPROM (Electrically Erasable Programmable Read Only Memory). The ROM 12 stores programs including firmware.

[0020] The RAM 13 is a volatile memory. The RAM 13 temporarily stores data and stores the programs stored in the ROM 12 while the memory system 3 is powered. Examples of the RAM 13 include a dynamic random access memory (DRAM) and a static random access memory (SRAM). The RAM 13 also functions as a buffer memory.

[0021] The host interface 14 is an interface through which the memory controller 10 communicates with the host device 2. The host interface 14 includes hardware or a combination of hardware and software. The host interface 14 is connected to the host device 2 by a wire that enables communication in a format that the memory controller 10 and the host device 2 comply with. In one example, the memory controller 10 is configured to support SD TM Interface: SAS (Serial Attached SCSI (Small Computer System Interface)), SATA (Serial ATA (Advanced Technology Attachment)), or PCIe TM(Peripheral Component Interconnect express) compliant.

[0022] The nonvolatile memory interface 15 is an interface through which the memory controller 10 communicates with the nonvolatile memory 20. The nonvolatile memory interface 15 includes hardware or a combination of hardware and software. The nonvolatile memory interface 15 is connected to the nonvolatile memory 20 by wiring to enable communication in a manner based on the type of nonvolatile memory 20. The nonvolatile memory interface 15 transmits commands, address information, and write data to the nonvolatile memory 20 and receives read data from the nonvolatile memory 20. The nonvolatile memory interface 15 transmits various control signals to the nonvolatile memory 20 for controlling the nonvolatile memory 20.

[0023] The volatile memory interface 16 is an interface through which the memory controller 10 communicates with the volatile memory 30. The volatile memory interface 16 includes hardware or a combination of hardware and software. The volatile memory interface 16 is connected to the volatile memory 30 by wiring to enable communication in a manner based on the type of volatile memory 30. In one example, the volatile memory interface 16 complies with the DRAM interface standard.

[0024] The error correction circuit 17 includes an encoder 171 and a decoder 172, and uses an error correction code (ECC) to detect and correct errors in data to be written to the nonvolatile memory 20 and in data read from the nonvolatile memory 20. The error correction circuit 17 may be implemented as an independent dedicated semiconductor chip, a circuit formed on a semiconductor substrate, or firmware executed by the CPU 11. The encoder 171 generates an error correction code from data to be written to the nonvolatile memory 20 (actual write data). Based on a method for generating the error correction code, the error correction code generated from the actual write data is added to the actual write data. The actual write data and the error correction code generated from the actual write data are written to the nonvolatile memory 20. The decoder 172 decodes the read data using the error correction code. The decoder 172 detects fail bits in the data read from the nonvolatile memory 20. A fail bit is a bit (including one or more bits) read from a memory cell that differs from the data written to the memory cell. When a fail bit is detected, the decoding unit 172 identifies the position of the fail bit and corrects the fail bit. Examples of correction methods include hard bit decoding and soft bit decoding. Examples of hard-decision decoding codes used in hard-decision decoding include BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes. Examples of soft-decision decoding codes used in soft-decision decoding include LDPC (Low Density Parity Check) codes.

[0025] 2 shows components and connections of components in a block of a semiconductor memory in the memory system of the first embodiment. A plurality of blocks BLK, for example, all blocks BLK, include the components and connections shown in FIG.

[0026] One block BLK includes a plurality of string units SU. Figure 2 shows an example of five string units SU_0 to SU_4.

[0027] 2, m bit lines BL_0 to BL_m-1 are each connected to one NAND string NS from each of the string units SU_0 to SU_4 in each block BLK, where m is a positive integer.

[0028] Each NAND string NS includes one select gate transistor ST, n cell transistors MT (MT_0 to MT_n-1), and one select gate transistor DT (DT0, DT1, DT2, DT3, or DT4). Each cell transistor MT functions as a memory cell, where n is a positive integer. The cell transistor MT is an element that stores data in a nonvolatile manner. The cell transistor MT includes a control gate electrode or gate electrode (word line WL) and a charge storage film insulated from the surroundings, and stores data in a nonvolatile manner based on the charge in the charge storage film. Data is written to the cell transistor MT by injecting electrons into the charge storage film.

[0029] The select gate transistor ST, the cell transistors MT_0 to MT_n-1, and the select gate transistor DT are connected in series in this order between the source line SL and one bit line BL.

[0030] A plurality of NAND strings NS connected to different bit lines BL respectively constitute one string unit SU. In each string unit SU, the control gate electrodes of the cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. A set of cell transistors MT sharing a word line WL in one string unit SU is called a cell unit CU.

[0031] The select gate transistors DT0 to DT4 belong to the string units SU_0 to SU_4, respectively. The select gate transistors DT2, DT3, and DT4 are omitted from FIG. 2. The gate of the select gate transistor DT0 of each of the multiple NAND strings NS in the string unit SU_0 is connected to a select gate line SGDL0. Similarly, the gates of the select gate transistors DT1, DT2, DT3, and DT4 of each of the multiple NAND strings NS in the string units SU_1, SU_2, SU_3, and SU_4 are connected to select gate lines SGDL1, SGDL2, SGDL3, and SGDL4, respectively.

[0032] The gate of the select gate transistor ST is connected to a select gate line SGSL.

[0033] Each block BLK may have any structure as long as the circuit shown in Fig. 2 is realized. As an example, each block BLK may have the structure shown in Fig. 3. Fig. 3 schematically shows an example of the structure of a portion of the memory cell array of the memory system of the first embodiment.

[0034] 3, an insulator INS is provided on the upper surface of a substrate sub. A conductor CC is provided on the upper surface of the insulator INS. The conductor CC functions as a part of the source line SL.

[0035] Above the conductor CC, one conductor CS, multiple (e.g., eight) conductors CW, and conductor CD are provided. The conductors CS, CW, and CD are arranged in this order at intervals along the z-axis and extend along the y-axis. The conductors CS, CW, and CD function as the select gate line SGSL, word lines WL0 to WL7, and select gate line SGDL for each NAND string NS, respectively.

[0036] A memory pillar MP is provided above the conductor CC. The memory pillar MP penetrates the conductors CS, CW, and CD. The lower surface of the memory pillar MP is located in the conductor CC. The memory pillar MP includes an insulator IC, a semiconductor (layer) SF, a tunnel insulator (layer) IT, a charge storage layer IA, a block insulator (layer) IB, and a conductor (layer) CT.

[0037] The insulator IC has a columnar shape extending along the z-axis and is located at the center of the memory pillar MP. The semiconductor SF covers the side surface of the insulator IC. The semiconductor SF is in contact with the conductor CC at a portion of its bottom surface. The semiconductor SF functions as the channel region and body of the cell transistor MT and the select gate transistors DT and ST. The channel region is the region where the channel is formed.

[0038] A tunnel insulator IT covers the side surface of the semiconductor SF. A charge storage layer IA is an insulator or a conductor and covers the side surface of the tunnel insulator IT. A block insulator IB covers the side surface of the tunnel insulator IT.

[0039] The conductor CT covers the top surface of the insulator IC and the top surface of the semiconductor SF.

[0040] The upper surfaces of some of the conductors CT are connected to the conductors CB via conductive plugs CP. The conductors CB extend along the x-axis and are aligned along the y-axis. The conductors CB function as bit lines BL.

[0041] The portions of each memory pillar MP that intersect with the conductors CS, CW, and CD function as a select gate transistor ST, a cell transistor MT, and a select gate transistor DT, respectively.

[0042] The nonvolatile memory 20 can store two or more bits of data in one cell transistor MT. FIG. 4 shows an example of the threshold voltage distribution and data mapping of cell transistors MT storing three bits of data in the memory system of the first embodiment. The threshold voltage of each cell transistor MT varies depending on the amount of electrons in its charge storage layer IA and the data stored therein. In the case of three-bit storage, each cell transistor MT is in one of the states “S0”, “S1”, “S2”, “S3”, “S4”, “S5”, “S6”, and “S7” depending on its threshold voltage. The cell transistors MT in the “S0”, “S1”, “S2”, “S3”, “S4”, “S5”, “S6”, and “S7” states have higher threshold voltages in this order. When the threshold voltage of a cell transistor MT is lowered by data erasure, it is transitioned to the “S0” state.

[0043] When data is written, the cell transistor MT to be written is either maintained in the "S0" state or moved to one of the "S1", "S2", "S3", "S4", "S5", "S6", and "S7" states depending on the data to be written. Even multiple cell transistors MT that store the same 3-bit data may have different threshold voltages. A set of threshold voltages in a single state is called a threshold voltage lobe.

[0044] Three bits of data can be assigned to each state in any way. In one example, each state is treated as having the following three bits of data: In the following description, "ABC" means that A, B, and C represent the upper, middle, and lower bit values, respectively. “S0” state: “111” “S1” state: “110” “S2” state: “100” “S3” state: “000” “S4” state: “010” “S5” state: “011” “S6” state: “001” “S7” state: “101” Data reading is based on determining the state of the cell transistor MT to be read. To determine the state, multiple read voltages VCGR having different magnitudes are used. If the cell transistor MT has a threshold voltage equal to or greater than the read voltage VCGR, it is turned off even when the control gate electrode receives the read voltage VCGR. If the cell transistor MT has a threshold voltage less than the read voltage VCGR, it is turned on when the control gate electrode receives the read voltage VCGR. Based on this, it is determined whether the threshold voltage of the target cell transistor MT exceeds the read voltage VCGR.

[0045] The determination of whether the cell transistor MT to be read is in a state higher than the "S0", "S1", "S2", "S3", "S4", "S5", "S6", and "S7" states is performed using read voltages V1, V2, V3, V4, V5, V6, and V7, respectively. The read voltages V1, V2, V3, V4, V5, V6, and V7 are higher in this order. Obtaining a set of bits indicating whether the cell transistor MT is on or off by applying the read voltages V1, V2, V3, V4, V5, V6, and V7 (data reading) may be referred to as 1R, 2R, 3R, 4R, 5R, 6R, and 7R, respectively.

[0046] A set of data bits at the same position (digit) of the cell transistors MT of one cell unit CU constitutes one page. The set (or bit string) of the least significant (first digit from the bottom) bits (lower bits) of the cell transistors MT of each cell unit CU is called the lower page. The set (or bit string) of the second least significant bit (middle bits) of the cell transistors MT of each cell unit CU is called the middle page. The set (or bit string) of the third least significant bit (upper bits) of the cell transistors MT of each cell unit CU is called the upper page.

[0047] The read voltages V1 and V5 are used to read data from the lower page. The set of read voltages V1 and V5 used in reading the lower page may be referred to as a read voltage group Vth_0.

[0048] The read voltages V2, V4, and V6 are used to read data from the middle page. The set of read voltages V2, V4, and V6 used in reading the middle page may be referred to as a read voltage group Vth_1.

[0049] The read voltages V3 and V7 are used to read the data of the upper page. The set of read voltages V3 and V7 used in reading the upper page may be referred to as a read voltage set Vth_2.

[0050] The memory controller 10 specifies the read voltages V1 to V7 used in data read using DAC (Digital to Analog Converter) values ​​that represent shift amounts ΔV1 to ΔV7 from default values. A set of shift amounts ΔV1 and ΔV5 that are added to the read voltages V1 and V5, respectively, of the read voltage group Vth_0 may be referred to as a shift amount group ΔVth0. A set of shift amounts ΔV2, ΔV4, and ΔV6 that are added to the read voltages V2, V4, and V6, respectively, of the read voltage group Vth_1 may be referred to as a shift amount group ΔVth1. A set of shift amounts ΔV3 and ΔV7 that are added to the read voltages V3 and V7, respectively, of the read voltage group Vth_2 may be referred to as a shift amount group ΔVth2.

[0051] The data written to the page can be randomized by the memory controller 10 so as to suppress bias in the distribution of “1” data bits and “0” data bits. By randomization, it is expected that the number of transistors to which the cell transistors MT in each state belong in the cell unit CU into which data is written will be nearly uniform.

[0052] 1.2.Operation 5 shows an example of functional blocks during operation of the memory system of the first embodiment. As shown in FIG. 5, the memory system 3 includes functional blocks such as a read control unit 31, a shift amount estimation unit 32, a shift amount estimation unit 33, an error correction unit 34, a page data storage unit 35, a single-state read data storage unit 36, a post-separation page data storage unit 37, and a shift amount storage unit 38 during operation of the memory system 3. Some functions may be performed by functional blocks other than the illustrated functional blocks, or may be divided into smaller functional sub-blocks.

[0053] Each of the read control unit 31, the shift amount estimation unit 32, the shift amount estimation unit 33, the page data storage unit 35, the single-state read data storage unit 36, the post-separation page data storage unit 37, and the shift amount storage unit 38 is realized by part of one or more resources of the CPU 11, the ROM 12, the RAM 13, the non-volatile memory interface 15, the volatile memory interface 16, and the volatile memory 30.

[0054] In one example, the error correction unit 34 is the decoding unit 172 itself.

[0055] The read control unit 31 controls all types of data reads from the non-volatile memory 20. The read control unit 31 identifies data to be read from the non-volatile memory 20 to execute a read request from the host device 2, controls the reading of the data, generates an instruction to read the data, and sends the generated instruction to the non-volatile memory 20.

[0056] The shift amount estimation unit 32 controls the first type shift amount estimation described below. The first type shift amount estimation refers to estimating the shift amount (or adjustment amount) of the read voltage that is expected to lead to reading of page data containing fewer errors (fail bits). Hereinafter, *** data (*** is an arbitrary character string) may be simply referred to as data.

[0057] The shift amount estimation unit 33 controls the second-type shift amount estimation described below. The second-type shift amount estimation refers to estimating a shift amount of a read voltage that is expected to lead to reading of page data containing fewer errors. The second-type shift amount estimation is different from the first-type shift amount estimation. The second-type shift amount estimation is an estimation that can be performed when data containing errors (or data before error correction) and data after the errors are corrected (or data after error correction) of a certain page are available.

[0058] The page data storage unit 35 stores data read from a page of the nonvolatile memory 20 (page data).

[0059] The single-state read data storage unit 36 ​​stores data obtained by a single-state read on a cell unit CU of the nonvolatile memory 20. Unlike a page read, a single-state read refers to reading page data, i.e., obtaining a set of bits having values ​​indicating whether a cell transistor MT is on or off due to application of only one read voltage to one cell unit CU.

[0060] The post-separation page data storage unit 37 stores the post-separation page data. The post-separation page data is data generated from the page data using single-state read data, and includes only bits of the page data that meet a specific condition.

[0061] The shift amount storage unit 38 stores the shift amount.

[0062] 6 shows a flow of operation of the memory system of the first embodiment. The flow of FIG. 6 starts when the memory controller 10 receives a read request for certain data from the host device 2 and identifies a page from which data is to be read to execute the data read request. The page to be read may be referred to as a selected page. The cell unit CU providing the selected page may be referred to as a selected cell unit CUw hereinafter.

[0063] 6, the memory controller 10 instructs the nonvolatile memory 20 to read data from a selected page using a set of shift amounts ΔVtha (St1). The data read instruction includes information instructing a page read, address information specifying the page from which data is to be read, and a set of shift amounts ΔVtha. There are also cases where the set of shift amounts ΔVtha is zero, i.e., the default set of read voltages Vth is used.

[0064] Upon receiving the instruction, the nonvolatile memory 20 reads data from the selected page using the set of shift amounts ΔVtha (St2). The nonvolatile memory 20 transmits the read data Da to the memory controller 10.

[0065] Upon receiving the data Da, the memory controller 10 attempts to correct the error in the data Da using the error correction unit 34 (St3).

[0066] If the error correction is successful (St4; Yes), the memory controller 10 transmits data based on the data Da to the host device 2 as the data subject to the read request (St5). This ends the flow. Cases in which the error correction is successful include cases in which no error is detected.

[0067] If the error correction fails (St4; No), the memory controller 10 performs a first-type shift amount estimation (St7). The first-type shift amount estimation includes multiple page reads using different sets of shift amounts ΔVth for the selected page and calculations by the memory controller 10. The first-type shift amount estimation will be described further below. The first-type shift amount estimation allows the memory controller 10 to obtain a set of shift amounts ΔVthb that is expected to lead to reading of page data containing fewer errors.

[0068] The memory controller 10 instructs the nonvolatile memory 20 to read data from the selected page using the set of shift amounts ΔVthb (St11).

[0069] Upon receiving the instruction, the nonvolatile memory 20 reads data from the selected page using the set of shift amounts ΔVthb (St12). The nonvolatile memory 20 transmits the read data Db to the memory controller 10.

[0070] Upon receiving the data Db, the memory controller 10 attempts to correct the error in the data Db using the error correction unit 34 (St13).

[0071] If the error correction fails (St14; No), the memory controller 10 attempts to correct the error in the selected page using another technique (St15). An example of the other technique includes using a more advanced error correction method. When step St15 is completed, the flow of FIG. 6 ends.

[0072] If the error correction is successful (ST14; Yes), the memory controller 10 transmits data based on the data Dc as the data subject to the read request to the host device 2 (St16). The data Dc is the data after the error correction of the data Db.

[0073] The memory controller 10 performs second-type shift amount estimation (St17). In the process of step St17, the pre-error-correction data Db and the post-error-correction data Dc are used. The second-type shift amount estimation will be described in more detail later. By the second-type shift amount estimation, the memory controller 10 obtains a set of shift amounts ΔVthc that are expected to lead to reading data containing fewer errors.

[0074] The memory controller 10 stores the shift amount group ΔVthc for the selected page as the latest value in the shift amount storage unit 38 (St18). This ends the flow of Fig. 6. The shift amount group ΔVthc is used in the next data read from the selected page, and in one example, is used as the shift amount group ΔVtha.

[0075] 1.2.1. Type 1 shift amount estimation FIG. 7 illustrates the concept of the first-type shift amount estimation by the memory system of the first embodiment. In FIG. 7, part (A) shows, as an example, threshold voltage lobes in the "S0" state and the "S1" state. The two threshold voltage lobes partially overlap and merge due to the change in threshold voltage immediately after data writing, forming a minimum point. In part (B), FIG. 7 illustrates the relationship between the read voltage and the number M of cell transistors MT that are turned on in response to the read voltage (the number of ON cells). In part (C), FIG. 7 illustrates the difference in the number of ON cells between two different read voltages.

[0076] As shown in part (B), as the read voltage V is lowered, the number of ON cells M decreases sharply at a voltage slightly lower than VS1mid, and |dM / dV| reaches a maximum. As the read voltage V is further lowered, the rate of decrease in the number of ON cells M decreases, and at a certain value of read voltage V, the rate of decrease in the number of ON cells M reaches a minimum. The minimum value of the rate of decrease in the number of ON cells M is zero when the threshold voltage lobes of the “S0” and “S1” states do not overlap. However, because the two threshold voltage lobes overlap, the minimum value of the rate of decrease in the number of ON cells M becomes a non-zero positive value. As the read voltage V is further lowered, the rate of decrease in the number of ON cells M increases again, and |dM / dV| reaches a maximum again at a voltage slightly higher than VS0mid.

[0077] By estimating the minimum point of the threshold voltage based on the change in the number of ON cells M, the read voltage at the minimum point can be used. Specifically, first, a single-state read is performed using voltage VT0 as the read voltage. The resulting number of ON cells is M0. Next, a single-state read is performed using voltage VT1, which is lower than voltage VT0 by ΔV, as the read voltage. The resulting number of ON cells is M1. Then, the number of cell transistors MT that are newly turned off while the read voltage decreases from voltage VT0 to voltage VT1 is C1 = M0 - M1, as shown in part (C). That is, the number of cells having a threshold voltage between voltage VT0 and voltage VT1 is C1.

[0078] Next, single-state read is performed using voltage VT2, which is ΔV lower than voltage VT1, as the read voltage. The resulting number of ON cells is M2. Therefore, the number of cell transistors MT that are newly turned off while the read voltage drops from voltage VT1 to voltage VT2 is C2 = M1 - M2. That is, the number of cells having a threshold voltage between voltage VT2 and voltage VT1 is C2. C1 is greater than C2. Therefore, it is considered that the voltage at which |dM / dV| is minimum is at least lower than voltage VT1.

[0079] Subsequently, a single-state read is performed using a voltage VT3, which is ΔV lower than voltage VT2, as the read voltage. As a result, the number of ON cells is M3. Therefore, the number of cell transistors MT that are newly turned off while the read voltage drops from voltage VT2 to voltage VT3 is C3 = M2 - M3. That is, the number of cells having a threshold voltage between voltage VT3 and voltage VT2 is C3. C3 is greater than C2.

[0080] As a result of the above, a threshold voltage distribution as shown by the dashed line in part (C) can be estimated using the interval cell number C. Therefore, the threshold voltage distribution is estimated to have a minimum point between voltage VT1 and voltage VT2, which is the interval where the interval cell number C is minimum. The estimated minimum point is the point where the overlap of the threshold voltage lobes of the "S0" and "S1" states is estimated to be smallest. Using the voltage at the minimum point as the read voltage V1 can result in a reduction in the number of failed bits in the read data. The difference between the voltage at the minimum point and the default read voltage is the estimated shift amount.

[0081] As described above with reference to Figure 4, values ​​in the page data may be distributed among non-adjacent states. That is, "1" data in the lower page data corresponds to a voltage range below read voltage V1 and a voltage range above read voltage V5. Therefore, it may be difficult to correctly calculate the number of ON cells using only the lower page data obtained by multiple lower page reads performed while shifting the read voltage.

[0082] Therefore, state separation is performed as shown in Fig. 8. Fig. 8 shows data obtained by the operation of the memory system of the first embodiment.

[0083] For state separation, the memory controller 10 performs at least one single-state read on the nonvolatile memory 20. In a single-state read for state separation, a read voltage between multiple discontinuous voltage ranges assigned the same value is used, which is determined based on the page to be read. In one example, a read voltage V3 is used in a single-state read for a lower page read. Data obtained by a single-state read may be referred to as separation data. The lower page data is then masked with the separation data. The masking can be performed by an appropriate logical operation between the lower page data and the separation data. By masking the lower page data, the masked bits have "0" data, regardless of their values ​​before masking. The unmasked bits contain information and may be referred to as valid data portions.

[0084] Specifically, data is obtained in which the bits of cell transistors MT with threshold voltages less than the read voltage V1 have data "1" and the bits of cell transistors MT with threshold voltages equal to or greater than the read voltage V1 have data "0." Masked bits are hatched. Similarly, by performing an appropriate logical operation on the lower page data and the separation data, data is obtained in which the bits of cell transistors MT with threshold voltages less than the read voltage V3 have data "0" and the bits of cell transistors MT with threshold voltages equal to or greater than the read voltage V5 have data "1."

[0085] Similarly, for the middle page data, state separation can be performed using data obtained by a single-state read using a read voltage V3 and data obtained by a single-state read using a read voltage V5. For the upper page data, state separation can be performed using data obtained by a single-state read using a read voltage V5.

[0086] State separation allows the number of on-cells to be calculated correctly.

[0087] Fig. 9 shows a flow of operation of the memory system of the first embodiment. Fig. 9 shows a subflow of step St7 (first type shift amount estimation) of the flow of Fig. 6, and shows the operation of the memory controller 10, in particular, the shift amount estimation unit 32.

[0088] 9, the memory controller 10 instructs the nonvolatile memory 20 to perform a single-state read using a read voltage Vk for the selected cell unit CUw (SSt1). k has a value based on the separation data obtained for state separation. If a shift amount is added to the read voltage Vk, the shift amount may be included in the instruction.

[0089] Upon receiving the instruction, the nonvolatile memory 20 performs a single-state read using the read voltage Vk on the selected cell unit CUw (SSt2). The nonvolatile memory 20 transmits the obtained single-state read data DkR to the memory controller 10. The memory controller 10 stores the received data DkR in the single-state read data storage unit 36.

[0090] The set of steps SSt1 and SSt2 is performed a number of times based on the selected page, that is, the same number of times as the number of separated data required for state separation, and the same number of data DkR as the number of separated data required for state separation is obtained.

[0091] The memory controller 10 sets the variable j to 0 (SSt3).

[0092] The memory controller 10 instructs the nonvolatile memory 20 to read data from the selected page using the shift amount group ΔVth_j (SSt4). The shift amount group ΔVth_j is different from the shift amount group ΔVtha and different from the shift amount group ΔVth_j used so far during the flow of FIG. 9. As a specific example, when the shift amount group ΔVtha includes a voltage corresponding to the voltage VT0 in FIG. 7, the shift amount group ΔVth_j includes the voltage VT1. Specifically, when the selected page is a lower page, the shift amount group ΔVth_j includes shift amounts ΔV1_j and ΔV5_j. When the selected page is a middle page, the shift amount group ΔVth_j includes shift amounts ΔV2_j, ΔV4_j, and ΔV6_j. When the selected page is an upper page, the shift amount group ΔVth_j includes shift amounts ΔV3_j and ΔV7_j.

[0093] Upon receiving the instruction, the nonvolatile memory 20 reads data from the selected page using the set of shift amounts ΔVth_j (SSt5). The nonvolatile memory 20 transmits the obtained page data D_j to the memory controller 10. The data D_j includes information about the number of ON cells as shown in FIG. 7, that is, the number of ON cells can be determined from the data D_j. The data D_j continues to be stored in the page data storage unit 35 at least until the state separation process is completed in step SS8 described below.

[0094] The memory controller 10 increments j by 1 (SSt6). When each value of j is distinct from the others, j may be referred to as j1, j2, j3, . . .

[0095] If j is not the predetermined maximum value (SSt7; Yes), the flow proceeds to step SSt4. The maximum value specifies the number of ON cells used in the first-type shift amount estimation and is based on the details of the first-type shift amount estimation method. The following description and figures are based on an example where the maximum value of j is 5.

[0096] If j is the maximum value (SSt7; Yes), the memory controller 10 performs state separation on the data D_j for each case where j is 0 to 4 (SSt8). As a result, for each case where j is 0 to 4 and for all values ​​of p based on the selected page, separated page data DSp_j is generated from the data D_j. p is 0 or a positive integer and depends on the selected page. That is, if the selected page is a lower page, p is 1 or 5. If the selected page is a middle page, p is 2, 4, or 6. If the selected page is an upper page, p is 3 or 7. When each value of p is distinct from others, p may be referred to as p1, p2, p3, .... The separated page data DSp_j is stored in the separated page data storage unit 37.

[0097] The memory controller 10 uses the data DSp_j to estimate the shift amount set ΔVthb (SSt9).

[0098] Fig. 10 shows an example of data obtained during the operation of the memory system of the first embodiment. Fig. 10 shows an example of data obtained during the loop of steps SSt4, SSt5, SSt6, and SSt7 of the flow of Fig. 9, and shows an example of the lower page as a representative example.

[0099] The shift amount set ΔVth_j used in step SSt4 varies depending on j. Therefore, as shown in FIG. 10, the cell transistors MT that turn on based on the threshold voltages of the cell transistors MT of the cell unit CU to be read differ depending on j, and thus the page data D_j also differs. Specifically, from the cell transistors MT having threshold voltages S1--, S1-, S1, S1+, S5--, S5-, S5, or S5+, “1”, “0”, “0”, “0”, “1”, “1”, “1”, and “1” are read as page data D_0, respectively. The threshold voltages Sk--, Sk-, Sk, and Sk+ are higher in this order in the threshold voltage lobe of the “Sk” state. Depending on j, the larger the shift amounts ΔV1 and ΔV5 used, the higher the cell transistors MT with higher threshold voltages will be turned on. As a result, the distribution of "0" data and "1" data in the data D_j differs depending on j. For example, from the cell transistors MT having threshold voltages S1--, S1-, S1, S1+, S5--, S5-, S5, or S5+, "1", "1", "0", "0", "0", "1", "1", and "1" are read out as the data D_1.

[0100] 11 shows another example of data obtained during operation of the memory system of the first embodiment. FIG. 11 shows an example of data obtained in step SSt8 of the flow of FIG. 9, and a representative example of the lower page is shown. As shown in FIG. 11, for each case where j is 0 to 4, post-separation page data DS1_j and DS5_j are generated from page data D_j. After the estimation of the shift amount set ΔVthb in step SSt9 is completed, data DS1_j and DS5_j may be discarded, i.e., may be treated as invalid data.

[0101] 1.2.2. Type 2 Shift Amount Estimation 12 shows the concept of second-type shift amount estimation by the memory system of Embodiment 1. As a representative example, FIG. 12 shows estimation of the shift amount ΔV1 of the read voltage V1.

[0102] 12, the number of cell transistors MT that have been moved to the "S1" state but are determined to be in the "S0" state, i.e., the number of memory cells E_01, corresponds to the area of ​​region (a) in FIG. 12. The number of cell transistors MT that have been moved to the "S0" state but are determined to be in the "S1" state, i.e., the number of memory cells E_10, corresponds to the area of ​​region (b). The numbers of memory cells E_01 and E_01 are obtained by comparing the data before error correction (i.e., input to the error correction unit 34) with the data after error correction of this data.

[0103] 12 shows a case in part (A) where the read voltage V1 used is equal to the threshold voltage V1opt at the intersection of the threshold voltage lobes in the "S0" and "S1" states. In the case of part (A), the area of ​​region (a) is equal to the area of ​​region (b). In this case, the number of fail bits E (=E_01+E_01) in the data read from the cell transistor MT in the "S0" or "S1" state is expected to be minimum.

[0104] 12 shows a case in part (B) where the read voltage V1 used is higher than the threshold voltage V1opt. In this case, the area of ​​region (a) is larger than the area of ​​region (b). Also, in this case, the number of fail bits E is larger than the number of fail bits E in the case of part (A). In the case of part (B), a read voltage V1 shifted to the lower voltage side is used when reading data from the selected page next, so the number of fail bits E is expected to be smaller.

[0105] 12 shows a case in which the read voltage V1 used is lower than the threshold voltage V1opt in part (C). In this case, the area of ​​region (a) is smaller than the area of ​​region (b). Also, in this case, the number of fail bits E is larger than the number of fail bits E in the case of part (A). In the case of part (C), a read voltage V1 shifted to the higher voltage side is used when reading data from the selected page next, so the number of fail bits E is expected to be smaller.

[0106] The absolute value of the difference between the area of ​​region (a) and the area of ​​region (b) increases as the read voltage V1 deviates from the threshold voltage V1opt. Therefore, in the cases of portions (B) and (C), the memory controller 10 determines a shift amount ΔV1 for the read voltage V1 based on the ratio between the area of ​​region (a) and the area of ​​region (b). The greater the ratio, the greater the shift amount used. Based on the absolute value of the difference between the area of ​​region (a) and the area of ​​region (b), the memory controller 10 determines the relationship between the shift amount ΔV1 for bringing the read voltage V1 closer to the threshold voltage V1opt by referring to a shift amount correspondence table. The shift amount correspondence table indicates various relationships between the absolute value of the difference between the area of ​​region (a) and the area of ​​region (b) and the shift amount ΔV1 for bringing the read voltage V1 closer to the threshold voltage V1opt. The shift amount correspondence table is prepared in advance and stored in the shift amount storage unit 38.

[0107] For the other read voltages V2 to V7, the shift amounts ΔV2 to ΔV7 are estimated in the same manner as for the read voltage V1.

[0108] A set of estimated shift amounts ΔV1 and ΔV5 is a shift amount group ΔVth0. A set of estimated shift amounts ΔV2, ΔV4, and ΔV6 is a shift amount group ΔVth1. A set of estimated shift amounts ΔV3 and ΔV7 is a shift amount group ΔVth2.

[0109] Fig. 13 shows a flow of the operation of the memory system of the first embodiment. Fig. 13 shows a subflow of step St17 (second-type shift amount estimation) of the flow of Fig. 6, and shows the operation of the memory controller 10, in particular, the shift amount estimation unit 33.

[0110] As shown in FIG. 13, the memory controller 10 acquires change bit specifying data DO (SSt21). The data DO is data in which the error-corrected bit in the error-corrected data Dc has a specific value (e.g., "1"). The data DO can be generated by any method. In one example, the data DO is generated by an exclusive OR (XOR operation) of the pre-error-correction data Db and the error-corrected data Dc.

[0111] The memory controller 10 acquires 10 change bit specific data D_10 (SSt22). The data D_10 has a specific value (e.g., "1") in the 10 change bits in the error-corrected data Dc. The 10 change bits are bits indicating cell transistors MT that were written to store "1" data but were determined to store "0" data. The data D_10 can be generated by any method. In one example, the data D_10 is generated by logically ANDing the data DO and the data Dc.

[0112] The change from "1" data to "0" data can occur at multiple discrete state boundaries. Specifically, in the case of a lower page read, the change occurs at the bit of the cell transistor MT that was moved to the "S0" state but determined to be in the "S1" state, and at the bit of the cell transistor MT that was moved to the "S5" state but determined to be in the "S4" state. Therefore, data D_10 has a specific value indicating the change both when the change occurs at the "S0" and "S1" state boundary and when the change occurs at the "S4" and "S5" state boundary. It is unclear at which state boundary the change occurs. The same applies to other pages.

[0113] The memory controller 10 acquires 01 change bit specifying data D_01 (SSt23). The data D_01 has a specific value (e.g., "1") in the 01 change bit in the error-corrected data Dc. The 01 change bit is a bit indicating a cell transistor MT that was written to store "0" data but was determined to store "1" data. The data D_01 can be generated by any method. In one example, the data D_01 is generated by the logical AND of the data DO and the negation of the data Dc.

[0114] The change from "0" data to "1" data can occur at multiple discrete state boundaries. Specifically, in the case of a lower page read, the change occurs at the bit of the cell transistor MT that has been moved to the "S1" state but is determined to be in the "S0" state, and at the bit of the cell transistor MT that has been moved to the "S4" state but is determined to be in the "S5" state. Therefore, data D_01 has a specific value indicating the change both when the change occurs at the boundary between the "S0" and "S1" states and when the change occurs at the boundary between the "S4" and "S5" states. It is unclear at which state boundary the change occurs. The same applies to other pages.

[0115] Step SSt23 may be performed before step SSt22.

[0116] The memory controller 10 performs state separation on the 10 change bit specifying data D_10 by using the single-state read data DkR obtained in step SSt1 of FIG. 9 (SSt24). Using the same principle as described above with reference to FIG. 8, state separation generates 10 change bit specifying data D_10_Sp after separation, the number of which is equal to the number of values ​​of p. The data D_10_Sp includes information specifying the 10 change bits that occurred only at the boundary between the "Sp" state and the "Sp-1" state. In the case of the lower page, data D_10_S1 and data D_10_S5 are generated.

[0117] The memory controller 10 performs state separation on the 01 change bit specifying data D_01 by using the single-state read data DkR obtained in step SSt1 of FIG. 9 (SSt25). Through state separation, separated 01 change bit specifying data D_01_Sp, the number of which is equal to the number of values ​​of p, is generated from the data D_01. The data D_01_Sp includes information that specifies the 01 change bit that occurs only at the boundary between the "Sp" state and the "Sp-1" state. In the case of the lower page, data D_01_S1 and data D_01_S5 are generated.

[0118] Step SSt25 may be performed before step SSt24.

[0119] The memory controller 10 estimates the shift amount set ΔVthc using the data D_10_Sp and the data D_01_Sp (SSt26). From the data D_10_Sp, the number of memory cells E_10_Sp at the boundary between the “Sp” state and the “Sp-1” state is obtained by counting. The number of memory cells E_10_Sp is the number of memory cells E_10 at the boundary between the “Sp” state and the “Sp-1” state. From the data D_01_Sp, the number of memory cells E_01_Sp at the boundary between the “Sp” state and the “Sp-1” state is obtained by counting. The number of memory cells E_01_Sp is the number of memory cells E_01 at the boundary between the “Sp” state and the “Sp-1” state. In the case of the lower page, the numbers of memory cells E_10_S1, E_10_S5, E_01_S1, and E_01_S5 are obtained. From the obtained numbers of memory cells E_10_S1, E_10_S5, E_01_S1, and E_01_S5, the shift amount group ΔVthc is estimated by the method described above with reference to FIG.

[0120] 1.3.Advantages (Effects) According to the first embodiment, as described below, a memory system that efficiently reads data can be provided.

[0121] The first-type shift amount estimation is difficult to achieve high accuracy due to factors such as noise that gets mixed into the data during processing and the difference in magnitude between the threshold voltage distribution immediately after writing data to the cell transistor and the threshold voltage distribution during the first-type shift amount estimation after some time has passed.

[0122] The second-type shift amount estimation is generally performed autonomously and periodically by the memory system while the memory system is not performing processing based on a request from the host device. The second-type shift amount estimation has high accuracy, but requires error-free page data for execution. Also, when a memory cell stores two or more bits of data as in the first embodiment, separate data is required.

[0123] According to the first embodiment, the second-type shift amount estimation is performed as part of reading page data. If the error correction of the page data read using the result of the first-type shift amount estimation is successful, the second-type shift amount estimation is subsequently performed. Since the error-corrected page data is obtained by the first-type shift amount estimation, the second-type shift amount estimation can be subsequently performed. Then, by using the shift amount obtained by the second-type shift amount estimation in the next page read, errors in the next page read are suppressed and the accuracy of data read is improved. Furthermore, by maintaining the separated data obtained by the first-type shift amount estimation until the second-type shift amount estimation and using it in the second-type shift amount estimation, the second-type shift amount estimation can be performed efficiently.

[0124] 2. Second embodiment The second embodiment is based on the first embodiment and differs from the first embodiment in the method of estimating the second type shift amount. The hardware configuration and the functional block configuration of the memory system 3 of the second embodiment are the same as those of the first embodiment.

[0125] 2.1. Operation 14 to 19 show the concept of second-type shift amount estimation by the memory system of the second embodiment. As a representative example, Fig. 14 to Fig. 19 show estimation of shift amounts ΔV1 and ΔV5 of the lower page.

[0126] The memory controller 10 continues to store the separated data obtained in steps SSt1 and SSt2 (that is, the single-state read data DkR (D3R)) in the page data storage unit 35 until it has been used in step St17 (second-type shift amount estimation).

[0127] The memory controller 10 continues to store the page data D_j obtained in the loop of steps SSt4, SSt5, SSt6, and SSt7 for each case where j is 0 to 4 in the page data storage unit 35 until it has been used in step St17. The error-corrected data Dc is stored in the error correction unit 34.

[0128] As shown in FIG. 14, for each case where j is 0 to 4, the reference data RD_j is generated by performing an exclusive OR (XOR) operation on the error-corrected data Dc and the page data D_j.

[0129] 15, for each case where j is 0 to 4, 10 change bit specifying data D_10_SS_j is generated by ANDing the error-corrected data Dc and the reference data RD_j. The data D_10_SS_j includes information specifying the 10 change bits in the data D_j.

[0130] For each case where j is 0 to 4, 01 change bit specifying data D_01_SS_j is generated by ANDing the negation of the error-corrected data Dc with the reference data RD_j. The data D_01_SS_j includes information specifying the 01 change bit in the data D_j.

[0131] 16, state separation is performed on data D_10_SS_j using data D3R for each case where j is from 0 to 4. As a result, for each case where j is from 0 to 4, post-separation 10 change bit specifying data D_10_S1_j and D_10_S5_j are generated from data D_10_SS_j.

[0132] The data D_10_S1_j includes information identifying the bits of the cell transistors MT that have been moved to the "S0" state but are determined to be in the "S1" state. The data D_10_S1_j masks the bits of the cell transistors MT that have been moved to the "S5" state but are determined to be in the "S4" state, and does not include information identifying the bits of the cell transistors MT that have been moved to the "S5" state but are determined to be in the "S4" state.

[0133] The data D_10_S5_j includes information identifying the bits of the cell transistors MT that have been moved to the "S5" state but are determined to be in the "S4" state. The data D_10_S5_j masks the bits of the cell transistors MT that have been moved to the "S0" state but are determined to be in the "S1" state, and does not include information identifying the bits of the cell transistors MT that have been moved to the "S0" state but are determined to be in the "S1" state.

[0134] 17, state separation is performed on data D_01_SS_j using data D3R for each case where j is from 0 to 4. As a result, for each case where j is from 0 to 4, post-separation 01 change bit specifying data D_01_S1_j and D_01_S5_j are generated from data D_01_SS_j.

[0135] The data D_01_S1_j includes information identifying the bits of the cell transistors MT that have been moved to the "S1" state but are determined to be in the "S0" state. The data D_01_S1_j masks the bits of the cell transistors MT that have been moved to the "S4" state but are determined to be in the "S5" state, and does not include information identifying the bits of the cell transistors MT that have been moved to the "S4" state but are determined to be in the "S5" state.

[0136] The data D_01_S5_j includes information identifying the bits of the cell transistors MT that have been moved to the "S4" state but are determined to be in the "S5" state. The data D_01_S5_j masks the bits of the cell transistors MT that have been moved to the "S1" state but are determined to be in the "S0" state, and does not include information identifying the bits of the cell transistors MT that have been moved to the "S1" state but are determined to be in the "S0" state.

[0137] As shown in Figure 18, for each case where j is 0 to 4, a number CC_10_S1_j is generated from data D_10_S1_j. The number CC_10_Sp_j is the number of "1" data in data D_10_Sp_j, i.e., the number of 10 change bits. The number CC_10_Sp_j indicates the case where a shift amount ΔVp_j is used.

[0138] Furthermore, for each case where j is 0 to 4, a number CC_01_S1_j is generated from the data D_01_S1_j. The number CC_01_Sp_j is the number of "1" data in the data D_01_Sp_j, i.e., the number of 01 change bits. The number CC_01_Sp_j indicates the case where the shift amount ΔVp_j is used.

[0139] For each case where j is 0 to 4, interpolation is performed on the number CC_10_S1_j. That is, for each case where j is 0 to 3, interpolation is performed on the number CC_10_S1_j and the number CC_10_S1_(j+1) in a two-dimensional space that includes the number CC_10_S1 as the vertical axis and the shift amount ΔV1_j as the horizontal axis. In one example, the interpolation is performed by calculating a mathematical formula that represents a line connecting the number CC_10_S1_j and the number CC_10_S1_(j+1) for each case where j is 0 to 3. The interpolation results in a polygonal line PL_10_Sp. The polygonal line PL_10_Sp is a polygonal line that includes the number CC_10_Sp_j as a vertex for all values ​​of j, and shows the relationship between the number CC_10_Sp_j and the magnitude of the shift amount ΔVp.

[0140] Similarly, for each case where j is 0 to 4, interpolation is performed on the number CC_01_S1_j. That is, for each case where j is 0 to 3, interpolation is performed on the number CC_01_S1_j and the number CC_01_S1_(j+1) in a two-dimensional space that includes the number CC_01_S1 as the vertical axis and the shift amount ΔV1_j as the horizontal axis. In one example, the interpolation is performed by calculating a mathematical formula that represents a line connecting the number CC_01_S1_j and the number CC_01_S1_(j+1) for each case where j is 0 to 3. The interpolation results in a polygonal line PL_01_S1. The polygonal line PL_01_Sp is a polygonal line that includes the number CC_01_Sp_j as a vertex for all cases of j, and shows the relationship between the number CC_01_Sp_j and the magnitude of the shift amount ΔVp.

[0141] Based on the broken lines PL_10_S1 and PL_01_S1, the sum of the numbers CC_10_S1_v and CC_01_S1_v is calculated for various shift amounts v. Next, the numbers CC_10_S1_Vm1 and CC_01_S1_Vm1 that form the smallest sum are searched for. Then, the shift amount Vm1 is adopted as the shift amount ΔV1 of the shift amount group ΔVthc.

[0142] 19, for each case where j is from 0 to 4, the number CC_10_S5_j is generated from the data D_10_S5_j. For each case where j is from 0 to 4, the number CC_01_S5_j is generated from the data D_01_S5_j.

[0143] For each case where j is 0 to 4, interpolation is performed on the number CC_10_S5_j in the same manner as described above with reference to Figure 18. By the interpolation, a polygonal line PL_10_S5 having vertices at numbers CC_10_S5_0 to CC_10_S5_j is obtained.

[0144] For each case where j is 0 to 4, interpolation is performed on the number CC_01_S5_j in the same manner as described above with reference to Figure 18. By the interpolation, a polygonal line PL_01_S5 having vertices at numbers CC_01_S5_0 to CC_01_S5_j is obtained.

[0145] Based on the broken lines PL_10_S5 and PL_01_S5, the sum of the numbers CC_10_S5_v and CC_01_S5_v is calculated for various shift amounts v. Next, the numbers CC_10_S5_Vm5 and CC_01_S5_Vm5 that form the smallest sum are searched for. Then, the shift amount Vm5 is adopted as the shift amount ΔV5 of the shift amount group ΔVthc.

[0146] Fig. 20 shows a flow of operation in the memory system of the second embodiment. Fig. 20 shows a subflow of step St17 (second-type shift amount estimation) of the flow in Fig. 6, and shows the operation of the memory controller 10, in particular, the shift amount estimation unit 33.

[0147] As shown in FIG. 20, the memory controller 10 generates reference data RD_j by performing a logical operation on the error-corrected data Dc and page data D_j for each case where j is 0 to 4 (SSt31).

[0148] The memory controller 10 generates 10 change bit specifying data D_10_SS_j by performing a logical operation on the error-corrected data Dc and the reference data RD_j for each case where j is 0 to 4 (SSt32).

[0149] The memory controller 10 generates 01 change bit specifying data D_01_SS_j by performing a logical operation on the error-corrected data Dc and the reference data RD_j for each case where j is 0 to 4 (SSt33). Step SSt33 may be performed before step SSt32.

[0150] The memory controller 10 generates post-separation 10-change-bit-specific data D_10_Sp_j by state separation for data D_10_SS_j for each case of j = 0 to 4 for all values ​​of p based on the selected page (step SSt34). When the selected page is a lower page, data D_10_S1_j and data D_10_S5_j are generated for each case of j = 0 to 4. When the selected page is a middle page, data D_10_S2_j, data D_10_S4_j, and data D_10_S6_j are generated for each case of j = 0 to 4. When the selected page is an upper page, data D_10_S3_j and data D_10_S7_j are generated for each case of j = 0 to 4.

[0151] The memory controller 10 generates post-separation 01 change bit specifying data D_01_Sp_j by state separation for data D_01_SS_j for each case of j = 0 to 4 for all cases of p based on the selected page (step SSt35). When the selected page is a lower page, data D_01_S1_j and data D_01_S5_j are generated for each case of j = 0 to 4. When the selected page is a middle page, data D_01_S2_j, data D_01_S4_j, and data D_01_S6_j are generated for each case of j = 0 to 4. When the selected page is an upper page, data D_01_S3_j and data D_01_S7_j are generated for each case of j = 0 to 4.

[0152] Step SSt35 may be performed before step SSt34.

[0153] The memory controller 10 acquires the number CC_10_Sp_j in the data D_10_Sp_j for each case of j=0 to 4 for all cases of p based on the selected page (SSt37). If the selected page is a lower page, the number CC_10_S1_j and the number CC_10_S5_j are acquired for each case of j=0 to 4. If the selected page is a middle page, the number CC_10_S2_j, the number CC_10_S4_j, and the number CC_10_S6_j are acquired for each case of j=0 to 4. If the selected page is an upper page, the number CC_10_S3_j and the number CC_10_S7_j are acquired for each case of j=0 to 4.

[0154] The memory controller 10 acquires the number CC_01_Sp_j in the data D_01_Sp_j for each case of j=0 to 4 for all cases of p based on the selected page (SSt38). If the selected page is a lower page, the number CC_01_S1_j and the number CC_01_S5_j are acquired for each case of j=0 to 4. If the selected page is a middle page, the number CC_01_S2_j, the number CC_01_S4_j, and the number CC_01_S6_j are acquired for each case of j=0 to 4. If the selected page is an upper page, the number CC_01_S3_j and the number CC_01_S7_j are acquired for each case of j=0 to 4.

[0155] Step SSt38 may be performed before step SSt37.

[0156] The memory controller 10 adopts the shift amount Vmp that minimizes the sum of the number CC_10_Sp_Vmp and the number CC_01_Sp_Vmp for each case of all values ​​of p based on the selected page as the shift amount ΔVp (SSt39).

[0157] If the selected page is a lower page, a shift amount Vm1 that minimizes the sum of the number CC_10_S1_Vm1 and the number CC_01_S1_Vm1 is searched for. The found shift amount Vm1 is adopted as the shift amount ΔV1. Also, a shift amount Vm5 that minimizes the sum of the number CC_10_S5_Vm5 and the number CC_01_S5_Vm5 is searched for. The found shift amount Vm5 is adopted as the shift amount ΔV5.

[0158] If the selected page is a middle page, a shift amount Vm2 that minimizes the sum of the number CC_10_S2_Vm2 and the number CC_01_S2_Vm2 is searched for. The found shift amount Vm2 is adopted as the shift amount ΔV2. Furthermore, a shift amount Vm4 that minimizes the sum of the number CC_10_S4_Vm4 and the number CC_01_S4_Vm4 is searched for. The found shift amount Vm4 is adopted as the shift amount ΔV4. Furthermore, a shift amount Vm6 that minimizes the sum of the number CC_10_S6_Vm6 and the number CC_01_S6_Vm6 is searched for. The found shift amount Vm6 is adopted as the shift amount ΔV6.

[0159] If the selected page is an upper page, a shift amount Vm3 that minimizes the sum of the number CC_10_S3_Vm3 and the number CC_01_S3_Vm3 is searched for. The found shift amount Vm3 is adopted as the shift amount ΔV3. Also, a shift amount Vm7 that minimizes the sum of the number CC_10_S7_Vm7 and the number CC_01_S7_Vm7 is searched for. The found shift amount Vm7 is adopted as the shift amount ΔV7.

[0160] In step SSt39, the shift amount group ΔVthc is obtained.

[0161] 2.2.Advantages According to the second embodiment, the number of 10 change bits and the number of 01 change bits for each j are obtained from a plurality of page data D_j obtained using a plurality of different shift amount groups ΔVth, and the shift amount group ΔVthc is estimated based on the shift amount that minimizes the sum of the number of 10 change bits and the number of 01 change bits. Therefore, the shift amount group ΔVthc can be obtained without referring to the shift amount correspondence table that is required when the shift amount is estimated from the ratio of the memory cell numbers E_01_Sp and E_10_Sp using the error-corrected data Dc.

[0162] According to the second embodiment, page data D_j for multiple j's are required in the second-type shift amount estimation. However, the data D_j are acquired during the first-type shift amount estimation. Therefore, by simply storing data acquired for another purpose until the end of generation of reference data RD_j in the second-type shift amount estimation, the shift amount group ΔVthc can be estimated without additional data reading.

[0163] 2.3. Variations The modified example differs from the basic form of the second embodiment in the second-type shift amount estimation. In the modified example, for the second-type shift amount estimation, the memory controller 10 continues to store the separated page data DSp_j obtained in step SSt8 for all cases of p based on the selected page and for each case of j from 0 to 4, instead of continuing to store the page data D_j. At the start of step SSt17 (second-type shift amount estimation), the memory controller 10 has stored the data DSp_j in the separated page data storage unit 37 for all cases of p based on the selected page and for each case of j from 0 to 4.

[0164] 21 to 26 show the concept of second-type shift amount estimation by the memory system of the modified example of Embodiment 2. As a representative example, Fig. 21 to Fig. 26 show estimation of shift amounts ΔV1 and ΔV5 of the lower page.

[0165] For each case where j is 0 to 4, the memory controller 10 continues to store the separated page data DS1_j and DS5_j stored in the separated page data storage unit 37 in step SSt8 until they are used in step SSt17 (second type shift amount estimation).

[0166] As shown in FIG. 21, for each case where j is 0 to 4, reference data RD1_j is generated by performing an XOR operation between the error-corrected data Dc and the separated page data DS1_j.

[0167] As shown in FIG. 22, for each case where j is 0 to 4, reference data RD5_j is generated by performing an XOR operation between the error-corrected data Dc and the separated page data DS5_j.

[0168] 23, data DS_10_S1_j is generated by ANDing the error-corrected data Dc and reference data RD1_j for each case where j is 0 to 4. Data DS_10_Sp_j includes information specifying 10 change bits that occurred only at the boundary between the “Sp” state and the “Sp-1” state in the separated page data DSp_j.

[0169] Furthermore, for each case where j is 0 to 4, data DS_01_S1_j is generated by ANDing the negation of the error-corrected data Dc with the reference data RD1_j. Data DS_01_Sp_j includes information specifying 01-change bits that occur only at the boundary between the “Sp” state and the “Sp-1” state in the separated page data DSp_j.

[0170] 24, for each case where j is from 0 to 4, data DS_10_S5_j is generated by an AND operation between the error-corrected data Dc and the reference data RD5_j. Also, for each case where j is from 0 to 4, data DS_01_S5_j is generated by an AND operation between the negation of the error-corrected data Dc and the reference data RD5_j.

[0171] As shown in Figure 25, for each case where j is 0 to 4, a number CCS_10_S1_j is generated from data DS_10_S1_j. The number CCS_10_Sp_j is the number of "1" data in data DS_10_Sp_j. Also, for each case where j is 0 to 4, a number CCS_01_S1_j is generated from data DS_01_S1_j. The number CCS_01_Sp_j is the number of "1" data in data DS_01_Sp_j.

[0172] Next, the differences between the four other than the smallest one of the numbers CCS_10_S1_0, CCS_10_S1_1, CCS_10_S1_2, CCS_10_S1_3, and CCS_10_S1_4 and the smallest one are calculated, resulting in the same numbers CC_10_S1_0, CC_10_S1_1, CC_10_S1_2, CC_10_S1_3, and CC_10_S1_4 as described above with reference to Figure 18.

[0173] Next, the differences between the four other than the smallest one of the numbers CCS_01_S1_0, CCS_01_S1_1, CCS_01_S1_2, CCS_01_S1_3, and CCS_01_S1_4 and the smallest one are calculated, resulting in the same numbers CC_01_S1_0, CC_01_S1_1, CC_01_S1_2, CC_01_S1_3, and CC_01_S1_4 as described above with reference to Figure 18.

[0174] 26, for each case where j is from 0 to 4, a number CCS_10_S5_j is generated from data DS_10_S5_j. Also, for each case where j is from 0 to 4, a number CCS_01_S5_j is generated from data DS_01_S5_j.

[0175] Next, the differences between the four other than the smallest one of the numbers CCS_10_S5_0, CCS_10_S5_1, CCS_10_S5_2, CCS_10_S5_3, and CCS_10_S5_4 and the smallest one are calculated, resulting in the same numbers CC_10_S5_0, CC_10_S5_1, CC_10_S5_2, CC_10_S5_3, and CC_10_S5_4 as described above with reference to Figure 19.

[0176] Fig. 27 shows a flow of operation in a memory system according to a modification of the second embodiment. Fig. 27 shows a subflow of step St17 (second-type shift amount estimation) in the flow of Fig. 6, and shows the operation of the memory controller 10, in particular, the shift amount estimation unit 33.

[0177] As shown in Figure 27, the memory controller 10 generates reference data RDp_j by performing an XOR operation between the error-corrected data Dc and the separated page data DSp_j for each case of j from 0 to 4 for all cases of p based on the selected page (SSt41).

[0178] The memory controller 10 generates data DS_10_Sp_j and data DS_01_Sp_j by performing a logical operation on the error-corrected data Dc and the reference data RDp_j for each case of j from 0 to 4 for all values ​​of p based on the selected page (SSt42).

[0179] The memory controller 10 obtains the number CCS_10_Sp_j from the data DS_10_Sp_j for each case where j is 0 to 4 for all cases of values ​​of p based on the selected page (SSt43).

[0180] The memory controller 10 obtains the number CCS_01_Sp_j from the data DS_01_Sp_j for each case where j is 0 to 4 for each case of all values ​​of p based on the selected page (SSt44).

[0181] Step SSt44 may be performed before step SSt43.

[0182] The memory controller 10 obtains the number CC_10_Sp_j from the number CCS_10_Sp_j for each case where j is 0 to 4 for each case of all values ​​of p based on the selected page (ST45).

[0183] The memory controller 10 obtains the number CC_01_Sp_j from the number CCS_01_Sp_j for each case where j is 0 to 4 for each case of all values ​​of p based on the selected page (SSt46).

[0184] Step SSt46 may be performed before step SSt45.

[0185] Step SSt46 continues to step SSt39.

[0186] According to the modified example, the single-state read data storage unit 36 ​​does not need to continue storing the single-state read data DkR until the second-type shift amount estimation.

[0187] 3. Third embodiment The third embodiment is additionally applied to the first or second embodiment. The hardware configuration of the memory system 3 of the third embodiment is the same as that of the first embodiment.

[0188] 3.1. Operation 28 shows an example of functional blocks during operation of the memory system of the third embodiment. As shown in Fig. 28, the memory system 3 includes a data synthesis unit 39 in addition to the functional blocks in the first embodiment during operation of the memory system 3.

[0189] The data synthesis unit 39 synthesizes a part of the page data and a part of the intermediate data based on the page data to generate another page data.

[0190] Fig. 29 shows a flow of an operation of the memory system of the third embodiment. The flow of Fig. 29 starts when the memory controller 10 receives a read request for certain data from the host device 2 and identifies a page from which the data is to be read in order to execute the data read request.

[0191] The memory controller 10 continues to store the post-separation page data DSp_j obtained in step SSt8 for all cases of p based on the selected page and for each case of j from 0 to 4. At the start of step St17 (second-type shift amount estimation), the memory controller 10 has stored the data DSp_j in the post-separation page data storage unit 37 for all cases of p based on the selected page and for each case of j from 0 to 4.

[0192] If the error correction fails (St14; No), the memory controller 10 attempts to correct the error in the combined page data using the data combining unit 39 and the error correction unit 34 (St21). The combined page data is composed of a combination of several parts of the separated page data DSp_j. The combined page data will be described further below. If the error correction fails (St21; No), the flow proceeds to step St15.

[0193] If the error correction is successful (St21; Yes), the error-corrected data Dc is obtained, and the flow proceeds to step St16. The memory controller 10 estimates a set of shift amounts ΔVthb from the error-corrected data Dc (St22). The set of shift amounts ΔVthb obtained in step St7 is updated by the set of shift amounts ΔVthb obtained in step St22. The estimation of the set of shift amounts ΔVthb will be further described later together with the combined page data. Step St22 continues to step St16.

[0194] 30 shows the concept of operation of the memory system of the third embodiment, and shows an example of combined page data, taking the case of reading the lower page as a representative example.

[0195] The post-isolation page data DS1_j includes valid data portions only for the cell transistors MT having threshold voltages that are turned on by receiving the read voltage V1.

[0196] On the other hand, the separated page data DS5_j includes valid data portions only for cell transistors MT that are turned off by receiving the read voltage V5. The valid data portions of data DS1_j and data DS5_j are combined to generate combined page data. The combined page data includes the same information as data DS1_j in bits of cell transistors MT having threshold voltages near the read voltage V1, and also includes the same information as data DS5_j in bits of cell transistors MT having threshold voltages near the read voltage V5. That is, data DSp1_j1 for a certain j(j1) and data Dsp2_j2 for another j(j2) are combined to generate combined page data DT_J. J is a set of j1 and j2. j1 and j2 may be the same or different. FIG. 30 shows an example of data DT_J consisting of the valid data portions of data DS1_1 and DS5_2.

[0197] The resultant page data can be generated by any logical operation. In one example, the logical operation is an OR operation or an XOR operation.

[0198] For the middle page, the valid data portions of data DS2_j1, DS4_j2, and DS6_j3 are combined. j3 may be the same as j1 and j2, or may be different. For the upper page, the valid data portions of data DS3_j1 and DS7_j2 are combined.

[0199] 31 shows a flow of operation in the memory system of the third embodiment. FIG. 31 shows a sub-flow of step St21 of the flow in FIG.

[0200] As shown in FIG. 31, the memory controller 10 generates a Cartesian product set from a set of specific valid data portions of the separated page data DSp_j (SSt50). That is, first, for all cases of p based on the selected page, a valid data portion DESp_j is generated for each case of j ranging from 0 to 4, thereby generating a set (array) of valid data portions DESp_j for each value of p. Next, one element of the Cartesian product set is generated from one valid data portion DESp_j for each value of p. That is, five elements DSp1_j1_0, DSp1_j1_1, DSp1_j1_2, DSp1_j1_3, and DSp1_j1_4 are generated from a valid data portion DESp1_j for one value of p and for one value of j, and valid data portions DESp2_j for the remaining values ​​of p and for all values ​​of j. A specific example of a lower page is as follows: That is, elements DS1_0_0, DS1_0_1, DS1_0_2, DS1_0_3, and DS1_0_4 are generated from valid data DSp1_0 and valid data portions DEsp2_0, Dsp2_1, Dsp2_2, Dsp2_3, and Dsp2_4, respectively. Similarly, elements DS1_1_j, DS1_2_j, DS1_3_j, and DS1_4_j are generated for each case where j is 1 to 4. The generated element is element DS_J of the Cartesian product set.

[0201] In other words, p valid data subgroups DEGSp are generated for all values ​​of p. Each valid data subgroup DEGSp consists of five valid data portions DESp_0, DESp_1, DESp_2, DESp_3, and DESp_4. One element DS_J is generated from one valid data portion DESp_0, DESp_1, DESp_2, DESp_3, or DESp_4 in each of the p valid data subgroups DEGSp. Thus, the Cartesian product consists of all combinations of values ​​for each parameter when the elements of the array of all values ​​of p (i.e., (p1, p2, p3, ...)) are used as parameters and each parameter has five valid data portions DESp_j.

[0202] To generate a Cartesian product, it is not necessary to actually generate the combined page data DT_J, but it is sufficient to generate information that identifies each element DT_J of the Cartesian product. For example, an index that uniquely identifies a combination of the value of p and the value of j is generated, and the index can be used to identify which valid data portion of data DSp_j is to be combined when combined page data is generated.

[0203] As shown in FIG. 31, the memory controller 10 assigns a value h to all elements DS_j of the Cartesian product to generate an element DS_J_h (SSt51). h is 0 or a positive integer and indicates the priority of the element DS_J to be assigned. The smaller h is, the higher the priority is. The priority may be determined by any rule. The element DS_J_h is assigned a higher priority if the combined page data DT_J_h generated from the element DS_J_h is expected to have a higher probability of successful error correction. An example is as follows:

[0204] The element DS_j has a higher priority as it is closer to j that uses a shift amount closer to the shift amounts ΔV1 to ΔV7 included in the shift amount group ΔVthb.

[0205] When the write data is randomized, the element DS_j has a higher priority when the number of ON cells based on the page data D_j obtained at j is closer to the expected value. As described above with reference to FIG. 4, when the write data is randomized, the number of cell transistors MT in each state is expected to be close to uniform, so that the expected value of the number of ON cells obtained by the first-type shift amount estimation can be estimated.

[0206] When two minimum points are found in the first-type shift amount estimation, the element DS_j has a higher priority the closer it is to the minimum point that was not used in calculating any of the shift amounts ΔV1 to ΔV7 included in the shift amount group ΔVthb.

[0207] The memory controller 10 sets h to 0 (SSt52).

[0208] The memory controller 10 generates the combined page data DT_J_h (SSt53).

[0209] The memory controller 10 attempts to correct the error in the data DT_J_h using the error correction unit 34 (SSt54).

[0210] If the error correction fails (SSt55; No), the memory controller 10 increments h by 1 (SSt56). If h is the maximum value (SSt57; Yes), the subflow ends, and the flow in FIG. 29 proceeds to step St15. The maximum value of h may have any size. In one example, the maximum value of h is equal to the number of elements DS_J in the Cartesian product set. In another example, the maximum value of h is smaller than the number of elements DS_J in the Cartesian product set.

[0211] If h is not the maximum value (SSt57; No), the flow continues to step SSt53.

[0212] If the error correction is successful (SSt55; Yes), the subflow ends and the flow in Fig. 29 proceeds to step St16. If the error correction is successful, data Dc is obtained.

[0213] If the error correction of the combined page data DT_J_h is successful, a shift amount group ΔVthb is estimated based on the data DT_J_h in step St22. That is, for example, if the selected page is a lower page and the data DT_J_h is composed of the valid data portion of the separated page data DS1_j1 and the valid data portion of the separated page data DS2_j2, the shift amount group ΔVthb includes the shift amount ΔV1 in the shift amount group ΔVth_j1 and the shift amount ΔV5 in the shift amount group ΔVth_j2.

[0214] Advantages According to the third embodiment, as described below, a memory system that efficiently reads data can be provided.

[0215] Even if error correction of page data obtained using the shift amount group ΔVthb obtained by the first type shift amount estimation fails, error correction may be successful by using a shift amount group ΔVthb that is slightly different from the shift amount group ΔVthb.

[0216] The memory system 3 of the third embodiment generates combined page data DT_J when error correction of page data obtained using the set of shift amounts ΔVthb obtained by the first-type shift amount estimation fails. The combined page data DT_J is composed of a combination of a portion of the set of shift amounts ΔVth of various magnitudes obtained during the first-type shift amount estimation process. Therefore, depending on the combination, error correction of the obtained combined page data may be successful. Advanced error correction such as that performed in step St15 can take a long time to perform. Therefore, if error correction is successful before the execution of advanced error correction, data can be read efficiently. Then, the separated page data DSp_j that provides part of the combined page data is obtained during the first-type shift amount estimation. Therefore, combined page data can be generated without additional data reading by simply storing data obtained for another purpose until the completion of the generation of the combined page data.

[0217] 3.3. Variations In a modified example, instead of continuing to store the separated page data DSp_j until step St21, the memory controller 10 continues to store the page data D_j and single-state read data DkR until step St21, and in step St21, performs state separation to generate the separated page data DSp_j.

[0218] Fig. 32 shows a flow of operation in a memory system according to a modified example of the third embodiment. Fig. 32 shows a subflow of step St21 of the flow shown in Fig. 29. At the start of step St21, page data D_j is stored for each case where j is 0 to 4, and single-state read data DkR is also stored.

[0219] 32, after step SSt52, the memory controller 10 generates all the separated page data DSp_j necessary for generating the combined page data DT_J_h (SSt59). When the data DT_J_h is composed of the valid data portion of the data DS1_1 and the valid data portion of the data DS5_2, the memory controller 10 Data DS1_1 is generated using the single-state read data D3R for the page data D_j, and data DS5_2 is generated using the data D3R for the page data D_j. Each time data DSp_j is generated, it is stored in the post-separation page data storage unit 37. If the data DSp_j required in step SSt59 is stored in the post-separation page data storage unit 37, the stored data DSp_j is used. Step SSt59 continues to step SSt53. If h is not the maximum value (SSt57; No), the flow continues to step SSt59.

[0220] 4. Fourth embodiment The fourth embodiment is applied to the third embodiment, and combined page data is generated from valid data portions generated based on the threshold voltages of the cell transistors MT of the cell units CU adjacent to the cell unit CU to be read. The hardware configuration of the memory system of the fourth embodiment is the same as that of the first embodiment (FIG. 4). The configuration of the functional blocks during operation of the memory system of the fourth embodiment is the same as that of the third embodiment (FIG. 28).

[0221] 4.1. Operation 33 to 36 show the concept of the first type shift amount estimation by the memory stem of the fourth embodiment, and represent the lower page.

[0222] 33 and 34, for each case where j is 0 to 4, each bit of page data D_j_w read from the selected cell unit CUw is masked based on whether it belongs to a first group or a second group of a certain characteristic. The group is based on the state of the adjacent cell transistor MTw+1 in the adjacent cell unit CUw+1. The adjacent cell unit CUw+1 is connected to the conductor CW (word line WL) connected to the selected cell unit CUw and the conductor CW adjacent to it on the positive side of the z-axis coordinate.

[0223] The first group includes bits of the selected cell transistor MTw adjacent to the adjacent cell transistor MTw+1 in a state below a certain "Su" state. u is 0 or a positive integer. The second group includes bits of the selected cell transistor MTw adjacent to the adjacent cell transistor MTw+1 in a state above the "Su" state. In one example, u is 4. In this example, the first group includes bits where the adjacent cell transistor MTw+1 belongs to any of the "S0", "S1", "S2", and "S3" states, and the second group includes bits where the adjacent cell transistor MTw+1 belongs to any of the "S4", "S5", "S6", and "S7" states. The following description is based on this example.

[0224] Whether the adjacent cell transistor MTw+1 is in a state below the "S4" state or in a state above the "S4" state can be determined from the single-state read data D4R_w+1. The data DkR_w+1 is data obtained by single-state read using a read voltage Vk for the adjacent cell transistor MTw+1.

[0225] To classify into the first or second group, the page data D_j_w is masked by data D4R_w+1 for each case where j is 0 to 4. By masking, data DM_G1_j and data DM_G2_j are generated for each case where j is 0 to 4. Data DM_Gt_j has masked bits belonging to groups other than the t-th group, has "0" data, and has valid data for bits belonging to the t-th group, where t is an integer equal to or greater than 0.

[0226] In one example, the data DM_G1_j is the logical product of the data D_j_w and the data D4R_w+1. In another example, the data DM_G2_j is the logical product of the data D_j_w and the negation of the data D4R_w+1.

[0227] As shown in FIG. 35 , for each case where j is 0 to 4, state separation is performed on data DM_G1_j using single-state read data D4R. That is, for each case where j is 0 to 4, data DM_G1_j is masked by data D4R. As a result, for each case where j is 0 to 4, data DM_G1_S1_j and data DM_G1_S5_j are generated from data DM_G1_j. Data DM_G1_S1_j includes information from data DM_G1_j that is based on reading using read voltage V1, but does not include information from data DM_G1_j that is based on reading using read voltage V5. Data DM_G1_S5_j includes information from data DM_G1_j that is based on reading using read voltage V5, but does not include information from data DM_G1_j that is based on reading using read voltage V1.

[0228] The shift amount ΔV1 is estimated using the data DM_G1_S1_j. The estimated shift amount ΔV1 is a shift amount using the cell transistor MT adjacent to the adjacent cell transistor MTw+1 in a state lower than the “S4” state.

[0229] The shift amount ΔV5 is estimated using the data DM_G1_S5_j. The estimated shift amount ΔV5 is a shift amount using the cell transistor MT adjacent to the adjacent cell transistor MTw+1 in a state lower than the “S4” state.

[0230] As shown in FIG. 36, for each case where j is 0 to 4, state separation is performed on data DM_G2_j using single-state read data D4R. That is, for each case where j is 0 to 4, data DM_G2_j is masked by data D4R. As a result, for each case where j is 0 to 4, data DM_G2_S1_j and data DM_G2_S5_j are generated from data DM_G2_j. Data DM_G2_S1_j includes information from data DM_G2_j that is based on reading using read voltage V1, but does not include information from data DM_G2_j that is based on reading using read voltage V5. Data DM_G2_S5_j includes information from data DM_G2_j that is based on reading using read voltage V5, but does not include information from data DM_G2_j that is based on reading using read voltage V1.

[0231] The shift amount ΔV1 is estimated using the data DM_G2_S1_j. The estimated shift amount ΔV1 is a shift amount using the cell transistor MT adjacent to the adjacent cell transistor MTw+1 in the “S4” state or higher.

[0232] The shift amount ΔV5 is estimated using the data DM_G2_S5_j. The estimated shift amount ΔV5 is a shift amount using the cell transistor MT adjacent to the adjacent cell transistor MTw+1 in the “S4” state or higher.

[0233] 37 illustrates the concept of operation of the memory cell of the fourth embodiment, showing an example of combined page data. The case of the lower page is shown as a representative example. The combined page data DT_GG consists of one valid data portion among the data DM_G1_S1_0 to DM_G1_S1_4, one valid data portion among the data DM_G1_S5_0 to DM_G1_S5_4, one valid data portion among the data DM_G2_S1_0 to DM_G2_S1_4, and one valid data portion among the data DM_G2_S5_0 to DM_G2_S5_4.

[0234] 38 to 40 show the flow of operation in the memory system of the fourth embodiment. The flow in Figures 38 to 40 is similar to the flow in Figure 6, and starts when a read request for certain data is received from the host device 2 and a selected page from which data is to be read is identified in the selected cell unit CUw.

[0235] 38 to 40, if the error correction fails (St4; No), the memory controller 10 instructs the nonvolatile memory 20 to perform a single-state read to acquire data for grouping (SSt61). Specifically, a single-state read using a read voltage Vu for the adjacent cell unit CUw+1 is instructed. If a shift amount is added to the read voltage Vu, the shift amount may be included in the instruction.

[0236] Upon receiving the instruction, the nonvolatile memory 20 performs a single-state read using the read voltage Vu on the adjacent cell unit CUw+1 (SSt62). The nonvolatile memory 20 transmits the obtained single-state read data DuR_w+1 to the memory controller 10. The memory controller 10 stores the received data DuR_w+1 in the single-state read data storage unit 36.

[0237] Step SSt62 follows step SSt1. The set of steps SSt1 and SSt2 may be performed before the set of steps SSt61 and SSt62.

[0238] If j is the maximum value (SSt7; Yes), the memory controller 10 sets t to 0 (SSt64).

[0239] The memory controller 10 masks the page data D_j using the single-state read data DuR_w+1 for each case where j is 0 to 4 (SSt65). The mask masks bits of the data D_j in groups other than the group Gt (non-Gt group). By the mask, data DM_Gt_j is generated from the data D_j for each case where j is 0 to 4.

[0240] The memory controller 10 performs state separation on the data DM_Gt_j for each case where j is 0 to 4 (SSt66). As a result, for each case of all values ​​of p based on the selected page, data DM_Gt_Sp_j is generated for each case where j is 0 to 4. For each case of a certain value of p based on the selected page, the data DM_Gt_Sp_j includes information based on reading using a read voltage Vp (e.g., read voltage Vp1) of the data DM_Gt_j, but does not include information based on reading using a read voltage Vp (e.g., read voltage Vp2, etc.) for another value of p.

[0241] Step SSt66 may be performed before step SSt65.

[0242] The memory controller 10 uses the data DM_Gt_Sp_j to estimate a set of shift amounts ΔVthb_Gt for all values ​​of p based on the selected page (SSt67). The set of shift amounts ΔVthb_Gt is the set of shift amounts ΔVthb for bits belonging to the group Gt. The estimation of the set of shift amounts ΔVthb_Gt is the same as the first-type shift amount estimation (step SSt9) except for the difference in the data used. That is, the data DM_Gt_Sp_j is used instead of the data DSp_j in step SSt9.

[0243] The memory controller 10 increments t by 1 (SSt68). The maximum value of t is equal to the number of groups plus 1. If t is not the maximum value (SSt69; No), the flow proceeds to step SSt65.

[0244] Steps SSt65, SSt66, and SSt67 may be performed while incrementing t from 0 to 1. That is, step SSt65 may be performed when t is 0 and 1, step SSt66 may be performed when t is 0 and 1, and step SSt67 may be performed when t is 0 and 1.

[0245] If t is the maximum value (SSt69; Yes), the shift amount groups ΔVthb_Gt for all group cases, that is, all values ​​of t, have been generated. The memory controller 10 again sets the variable t to 0 (SSt70).

[0246] The memory controller 10 instructs the nonvolatile memory 20 to read data from the selected page using the set of shift amounts ΔVthb_Gt (SSt71).

[0247] Upon receiving the instruction, the nonvolatile memory 20 reads data from the selected page using the set of shift amounts ΔVthb_Gt (SSt72). The nonvolatile memory 20 transmits the obtained page data D_Gt to the memory controller 10.

[0248] The memory controller 10 masks the page data D_Gt using the single-state read data DuR_w+1 for grouping (SSt73). The masking results in the acquisition of data DM_Gt. The data DM_Gt has a form in which bits belonging to the group Gt of the data D_Gt have valid data. In one example, the masking is performed by an AND operation of the data D_Gt and the data DuR_w+1.

[0249] The memory controller 10 increments t by 1 (SSt74). If t is not the maximum value (SSt75; No), the flow proceeds to step SSt71.

[0250] If t is the maximum value (SSt75; Yes), data DM_Gt for all group cases, i.e., all cases of all values ​​of t, have been generated. The memory controller 10 generates the logical sum of data DM_Gt for all group cases, i.e., all cases of all values ​​of t (SSt76). This generates data Db2 from which the influence of the state of the adjacent cell transistor MTw+1 on the state of the selected cell transistor MTw is eliminated.

[0251] The memory controller 10 attempts to correct the error in the data Db2 using the error correction unit 34 (SSt77). Step SSt77 is followed by step St14.

[0252] In generating the composite page data in step St21, p×t valid data subgroups DEGSp_Gt are generated for all values ​​of p and all values ​​of t. The valid data subgroups DEGSp_Gt are valid data subgroups DEGSp in the case of bits belonging to group Gt. Each valid data subgroup DEGSp_Gt consists of five valid data portions DESp_Gt_0, DESp_Gt_1, DESp_Gt_2, DESp_Gt_3, and DESp_Gt_4. Then, one element DS_J is generated from one valid data portion DESp_Gt_0, DESp_Gt_1, DESp_Gt_2, DESp_Gt_3, or DESp_Gt_4 in each of the p×t valid data subgroups DEGSp_Gt. Therefore, the Cartesian product consists of all combinations of p and t (i.e., (p1_G1, p1_G2, ..., p2_G1, p1_G2, ..., p3_G1, ...)) as parameters, and all combinations of values ​​for each parameter when assuming a case where each parameter has five valid data parts DESp_j. Then, a priority h is assigned to all elements of the Cartesian product.

[0253] Advantages According to the fourth embodiment, as described below, a memory system 3 is provided that reads data with high accuracy.

[0254] The threshold voltage of a cell transistor MT can be affected by the threshold voltage of an adjacent cell transistor MT to which data has been written after data has been written to that cell transistor MT. That is, after a first cell transistor MT has had its state changed by writing data, if the threshold voltage of an adjacent second cell transistor MT is raised by writing data, a state equivalent to the threshold voltage of the first cell transistor MT being raised by the threshold voltage of the second cell transistor MT can occur. This can lead to an erroneous determination of the state of the first cell transistor MT.

[0255] According to the fourth embodiment, a set of shift amounts ΔVthb_Gt is estimated for each group of selected cell transistors MT classified based on the state of the adjacent cell transistor MTw+1. Then, data is generated by ORing the page data obtained using the set of shift amounts ΔVthb_Gt. The data generated in this manner is based on the results of using a shift amount based on the influence of the adjacent cell transistor MTw+1 for each bit, so there is a high probability that error correction will be successful. Therefore, the error-corrected data Dc can be obtained with a high probability. Furthermore, as in the third embodiment, if error correction is successful, a set of shift amounts ΔVthc is estimated based on the combined page data. Therefore, the same advantages as in the third embodiment are obtained.

[0256] 4.4. Variations 4.4.1. First Variant The memory controller 10 may obtain the shift amount ΔVp_G2 when t is 2, i.e., when the bits of the second group are valid, based on the shift amount ΔVp_G1 when the bits of the first group are valid. That is, the relationship between the shift amount ΔVp_G1 and the shift amount ΔVp_G2 is known in advance by the memory controller 10 using a mathematical formula or a correspondence table generated through a previous evaluation. The memory controller 10 obtains the shift amount ΔVp_G2 using this relationship and the shift amount ΔVp_G1.

[0257] 4.4.2. Second Variant In the second modification, each bit of the page data D_j_w is classified into one of the first, second, and third groups. The first, second, and third groups are based on the state of the adjacent cell transistor MTw+1. The first group includes bits of the selected cell transistor MTw adjacent to the adjacent cell transistor MTw+1 in a state less than the "Su" state. The second group includes bits of the selected cell transistor MTw adjacent to the adjacent cell transistor MTw+1 in a state equal to or greater than the "Su" state but less than the "Sv" state. v is 0 or a positive integer. The third group includes bits of the selected cell transistor MTw adjacent to the adjacent cell transistor MTw+1 in a state equal to or greater than the "Sv" state.

[0258] Fig. 41 shows the concept of the first-type shift amount estimation by the memory system of the second modified example of the fourth embodiment. Fig. 41 shows the lower page as a representative example. As an example, u is 3 and v is 6. Whether the adjacent cell transistor MTw+1 belongs to the set of states less than the "S3" state, the set of states equal to or greater than the "S3" state but less than the "S6" state, or the set of states equal to or greater than the "S6" state but less than the "S6" state can be determined from the data D3R_w+1 and D6R_w+1.

[0259] For classification into the first, second, or third group, the page data D_j_w is masked by data D3R_w+1 and D6R_w+1 for each case where j is 0 to 4. The mask generates data DM_G1_j, DM_G2_j, and DM_G3_j for each case where j is 0 to 4.

[0260] In step SSt61, the memory controller 10 instructs a single-state read using a read voltage Vu for the adjacent cell unit CUw+1 and a single-state read using a read voltage Vv for the adjacent cell unit CUw+1. In the second variant, the maximum value of t is 3.

[0261] 4.4.3.Third Variant In the third modification, each bit of the page data D_j_w is classified into one of the first, second, third, and fourth groups. The first, second, third, and fourth groups are based on a combination of the state of the adjacent cell transistor MTw+1 and the state of the adjacent cell transistor MTw-1. The adjacent cell transistor MTw-1 is connected to the conductor CW (word line WL) connected to the selected cell unit CUw and the conductor CW adjacent to it on the negative side of the z-axis coordinate.

[0262] The first group includes bits of the selected cell transistor MTw adjacent to the adjacent cell transistor MTw+1 in a state less than the "Su" state and the adjacent cell transistor MTw-1 in a state less than the "Su" state.

[0263] The second group includes bits of the selected cell transistor MTw adjacent to the adjacent cell transistor MTw+1 in a state below the "Su" state and the adjacent cell transistor MTw-1 in a state above the "Su" state.

[0264] The third group includes bits of the selected cell transistor MTw adjacent to the adjacent cell transistor MTw+1 in a state equal to or higher than the "Su" state and the adjacent cell transistor MTw-1 in a state lower than the "Su" state.

[0265] The fourth group includes bits of the selected cell transistor MTw adjacent to the adjacent cell transistor MTw+1 in the "Su" state or higher and the adjacent cell transistor MTw-1 in the "Su" state or higher.

[0266] 42 shows the concept of the first-type shift amount estimation by the memory system of the third modified example of the fourth embodiment. FIG. 42 shows the lower page as a representative example. As an example, u is 4. Whether the adjacent cell transistor MTw-1 is in a state below the "S4" state or in a state above the "S4" state can be determined from the single-state read data D4R_w-1.

[0267] For classification into the first, second, third, or fourth group, the page data D_j_w is masked by data D4R_w+1 and D4R_w−1 for each case where j is 0 to 4. The mask generates data DM_G1_j, DM_G2_j, DM_G3_j, and DM_G4_j for each case where j is 0 to 4.

[0268] In step SSt61, the memory controller 10 instructs a single-state read using a read voltage Vu for the adjacent cell unit CUw+1 and a single-state read using a read voltage Vu for the adjacent cell unit CUw−1. In the third modification, the maximum value of t is 4.

[0269] 4.4.4. Fourth Variant 43 shows the flow of operation in a memory system according to a fourth modified example of the fourth embodiment. The flow of the fourth modified example includes additional steps after step St18 in the flow of the basic form of the fourth embodiment (FIGS. 38 to 40).

[0270] 43, step St18 continues to step St31. The memory controller 10 instructs the nonvolatile memory 20 to read from the selected page using the shift amount group ΔVthc (St31).

[0271] Upon receiving the instruction, the nonvolatile memory 20 reads data from the selected page using the shift amount set ΔVthc (St32). The nonvolatile memory 20 transmits the read data Dd to the memory controller 10.

[0272] Upon receiving the data Dd, the memory controller 10 attempts to correct the error in the data Dd using the error correction unit 34 (St33).

[0273] If the error correction is successful (St34; Yes), it means that it has been confirmed that the use of the set of shift amounts ΔVthc leads to the reading of data Dd that leads to successful error correction. Therefore, by using the set of shift amounts ΔVthc when reading from the next selected page, it is expected that data Dd that is more likely to be successfully corrected will be read. If the error correction is successful, the flow ends.

[0274] If the error correction fails (St34; No), this means that although the shift amount group ΔVthc was estimated based on the combined page data DT for which the error correction was successful, it has been confirmed that the error correction of the data Dd obtained using the shift amount group ΔVthc was not successful. Therefore, the memory controller 10 marks the selected page as a page to be refreshed (St35). Refreshing is a process that is autonomously performed by the memory system 3 while the memory system 3 is not performing processing based on a request from the host device 2. By refreshing, the memory system 3 reads data from the page to be refreshed, performs error correction on the read data using an advanced method, and writes the error-corrected data to the non-volatile memory 20 as data from the page to be refreshed.

[0275] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0276] 1...Information processing system, 2...host device, 3...Memory system, 10...Memory controller, 20...Non-volatile memory, 30...volatile memory, 11...CPU, 12...ROM, 13...RAM, 14...host interface, 15...Non-volatile memory interface, 16...volatile memory interface, 17...Error correction circuit, 31...Read control unit, 32...shift amount estimation unit, 33...shift amount estimation unit, 34...Error correction unit, 35...Page data storage unit, 36...single-state read data storage unit; 37... Post-separation page data storage unit, 38...shift amount storage unit, 39...Data synthesis unit, D_j...page data, DkR...single-state read data, Db: Data before error correction Dc: data after error correction, DSp_j: separated page data, DT_J...Merge page data

Claims

1. a non-volatile memory including a plurality of memory cells; reading first data from the plurality of memory cells using a first voltage and storing the first data in a storage circuit; reading second data from a bit group including each bit of the plurality of memory cells using a first read voltage group; performing an error correction process on the second data; when the error correction of the second data is successful and third data is obtained, a second read voltage group is determined based on the first data, the second data, and the third data stored in the memory circuit; A memory controller; A memory system comprising:

2. The memory controller determines the second set of read voltages based on a first number and a second number of the second data based on a comparison between the second data and the third data; the first number is the number of first bits in which a first type of error has been corrected in the third data; the second number is the number of second bits in which a second type of error has been corrected in the third data; 10. The memory system of claim 1.

3. the first bit is a bit having a first value in the second data and a second value in the third data; the second bit is a bit that has the second value in the second data and the first value in the third data; 3. The memory system of claim 2.

4. the memory controller determines the second set of read voltages based on a voltage that makes the ratio of the first number to the second number approach 1; 4. The memory system of claim 3.

5. the second read voltage group includes a first read voltage and a second read voltage; The memory controller acquiring a third number of the first bits of the third data, a fourth number of the first bits of the third data, a fifth number of the second bits of the third data, and a sixth number of the second bits of the third data based on the first data, the second data, and the third data stored in the memory circuit; determining the first read voltage based on the third number and the fifth number; determining the second read voltage based on the fourth number and the sixth number; 3. The memory system of claim 2.

6. the first read voltage group includes a third read voltage and a fourth read voltage; The memory controller reading the group of bits using a plurality of third read voltage groups to obtain a plurality of fourth data; generating a plurality of fifth data and a plurality of sixth data from the plurality of fourth data using the first data; determining the third read voltage based on the plurality of fifth data; determining the fourth read voltage based on the sixth data; 10. The memory system of claim 1.

7. a non-volatile memory including a plurality of memory cells; reading from a bit group including bits of each of the plurality of memory cells using a plurality of different first read voltage groups to obtain a plurality of first data; determining a second set of read voltages using the plurality of first data; reading second data from the set of bits using the second set of read voltages; when the error correction of the second data is successful and third data is obtained, a plurality of first numbers and a plurality of second numbers are obtained based on the plurality of first data and the third data; determining a third set of read voltages based on a comparison of the plurality of first numbers with the plurality of second numbers; A memory controller; A memory system comprising:

8. the plurality of first numbers have a first relationship distributed along the magnitude of read voltages used to read from the bits; the plurality of second numbers have a second relationship distributed along the magnitude of read voltages used to read from the bits; each of the plurality of first numbers is a number of first bits in which a first type of error has been corrected in one of the plurality of first data; each of the plurality of second numbers is a number of second bits in which a second type of error has been corrected in one of the plurality of first data; the memory controller determines the third set of read voltages based on the first relationship and the second relationship.

8. The memory system of claim 7.

9. the first bit is a bit having a first value in the second data and a second value in the third data; the second bit is a bit that has the second value in the second data and the first value in the third data; 9. The memory system of claim 8.

10. the second read voltage group includes a first read voltage and a second read voltage; the third read voltage group includes a third read voltage and a fourth read voltage; The memory controller reading fourth data from the plurality of memory cells using a first voltage; generating a plurality of fifth data and a plurality of sixth data from the plurality of first data using the fourth data; determining the first read voltage based on the plurality of fifth data; determining the second read voltage based on the sixth data; generating a plurality of seventh data and a plurality of eighth data from the plurality of first data, the third data, and the fourth data; each of the plurality of first numbers is the number of the first bits in one of the plurality of seventh data; each of the plurality of second numbers is the number of the second bits in one of the plurality of eighth data; 10. The memory system of claim 9.

11. a first storage circuit that stores the plurality of first data items until the generation of the plurality of seventh data items and the plurality of eighth data items is completed; a second storage circuit that stores the fourth data until the generation of the seventh data and the eighth data is completed; Further provided with The memory system of claim 10.

12. the second read voltage group includes a first read voltage and a second read voltage; the third read voltage group includes a third read voltage and a fourth read voltage; The memory controller The memory controller reading fourth data from the plurality of memory cells using a first voltage; generating a plurality of fifth data and a plurality of sixth data from the plurality of first data using the fourth data; determining the first read voltage based on the plurality of fifth data; determining the second read voltage based on the sixth data; generating a plurality of ninth data and a plurality of tenth data based on the third data and the plurality of fifth data; generating a plurality of eleventh data and a plurality of twelfth data based on the third data and the plurality of sixth data; each of the plurality of first numbers is a number of bits in which a first type error has been corrected in one of the plurality of ninth data and the plurality of eleventh data; each of the plurality of second numbers is the number of bits in which a second type of error has been corrected in one of the plurality of tenth data and the plurality of twelfth data; 8. The memory system of claim 7.

13. a non-volatile memory including a plurality of memory cells; reading from a bit group including bits of each of the plurality of memory cells using a plurality of first read voltage groups to obtain a plurality of first data; determining a second set of read voltages using the plurality of first data; reading second data from the set of bits using the second set of read voltages; if the error correction of the second data fails, an error correction process is performed on fifth data including a first portion of third data of one of the plurality of first data and a second portion of fourth data of one of the plurality of first data. A memory controller; Equipped with the third data and the fourth data are different, and the first portion and the second portion are different; Memory system.

14. the first portion of the third data includes a plurality of bits classified into a first group based on a first criterion in one of the plurality of first data; the second portion of the fourth data includes a plurality of bits in one of the plurality of first data that are classified into a second group based on the first criterion; The first group and the second group are different, 14. The memory system of claim 13.

15. the memory controller reads sixth data from the plurality of memory cells using a first voltage; the first portion of the third data includes a plurality of bits classified into the first group based on the sixth data of one of the plurality of first data; the fourth data includes a plurality of bits classified into the second group based on one of the plurality of first data and the sixth data; 15. The memory system of claim 14.

16. the plurality of bits classified into the first group have data based on memory cells among the plurality of memory cells that are determined to have a threshold voltage lower than the first voltage; the plurality of bits classified into the second group have data based on the first voltage and a memory cell determined to have a threshold voltage higher than the first voltage among the plurality of memory cells; 16. The memory system of claim 15.

17. the nonvolatile memory further includes a plurality of second memory cells; The memory controller reading seventh data from the plurality of second memory cells using a second voltage; the first portion of the third data includes a plurality of bits classified into a first group based on the seventh data of one of the plurality of first data; the second portion of the fourth data includes a plurality of bits classified into a second group based on the seventh data of one of the plurality of first data; 14. The memory system of claim 13.

18. the plurality of bits classified into the first group have data based on a memory cell among the plurality of memory cells that is adjacent to a second memory cell among the plurality of second memory cells that is determined to have a threshold voltage lower than the second voltage; the plurality of bits classified into the second group have data based on a memory cell of the plurality of memory cells adjacent to a second memory cell determined to have a threshold voltage at or higher than the second voltage, among the plurality of second memory cells; 18. The memory system of claim 17.

Images