Non-volatile memory device

Abstract

To provide a non-volatile memory device capable of realizing an effective configuration for guaranteeing a warranty period.SOLUTION: In a non-volatile memory device (1), when a second memory element (52) is in a programmed state and a second reference memory element (51) is in an unprogrammed state, a first memory element (42) is set to an unprogrammed state, and the gate voltage of the first memory element is set to a higher value than the gate voltage of the second memory element, and when the first memory element is in a programmed state and a first reference memory element is in an unprogrammed state, the second memory element is set to an unprogrammed state, and the gate voltage of the second memory element is set to a higher value than the gate voltage of the first memory element.SELECTED DRAWING: Figure 8A

Description

[Technical Field]

[0001] The present disclosure relates to non-volatile memory devices. [Background technology]

[0002] Conventionally, there are nonvolatile memory devices that use hot carrier injection into transistors. This type of nonvolatile memory device has first and second transistors as memory elements, whose characteristics are initially aligned. Hot carriers are injected into only one of the transistors to change its characteristics. In a subsequent read operation, whether data "0" or "1" is stored is determined based on the magnitude relationship of the drain currents when a common gate voltage is supplied to the first and second transistors. For example, a state in which the drain current of the first transistor is smaller (a state in which the characteristics of the first transistor have changed) corresponds to a state in which data "0" is stored, and a state in which the drain current of the second transistor is smaller (a state in which the characteristics of the second transistor have changed) corresponds to a state in which data "1" is stored.

[0003] The technology related to the above is disclosed in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-103158

[0005] [overview] In the nonvolatile memory device described above, data is read based on the magnitude relationship of the currents flowing through the memory elements, so it is necessary for there to be a sufficient difference between the currents flowing through the memory elements, but it is also necessary to guarantee that the magnitude relationship will not be reversed due to deterioration over time during the warranty period.

[0006] In view of the above circumstances, an object of the present disclosure is to provide a nonvolatile memory device that can realize an effective configuration for guaranteeing the warranty period.

[0007] A nonvolatile memory device according to one aspect of the present disclosure includes: a first current mirror configured to receive a first input current; a second current mirror configured to receive a second input current; Equipped with the first current mirror has a first reference memory element on an input side and a first memory element on an output side; the second current mirror includes a second reference memory element on the input side and a second memory element on the output side; data can be read based on the magnitude relationship between a first output current output from the first current mirror and a second output current output from the second current mirror; If the second memory element is in a programmed state and the second reference memory element is in an unprogrammed state, placing the first memory element in an unprogrammed state and setting a gate voltage of the first memory element higher than a gate voltage of the second memory element; When the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, the second memory element is in an unprogrammed state, and the gate voltage of the second memory element is configured to be higher than the gate voltage of the first memory element. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing voltage application to a memory element during a programming operation. [Figure 2] FIG. 2 is a cross-sectional view of the vertical structure of the memory element corresponding to FIG. [Figure 3] FIG. 3 is a diagram showing voltage application to a memory element during a read operation. [Figure 4] FIG. 4 is a cross-sectional view of the vertical structure of the memory element corresponding to FIG. [Figure 5]FIG. 5 is a diagram showing a configuration of a nonvolatile memory device according to a comparative example. [Figure 6] FIG. 6 is a schematic diagram showing the relationship between Vgs (gate-source voltage) and Ids (drain current) depending on the state of the memory element. [Figure 7] FIG. 7 is a diagram showing an example of variations in drain current due to a normal distribution. [Figure 8A] FIG. 8A is a diagram showing an example of a storage state of data in the nonvolatile memory device according to the first embodiment. [Figure 8B] FIG. 8B is a diagram showing another example of the storage state of data in the nonvolatile memory device according to the first embodiment. [Figure 9] FIG. 9 is a diagram showing a specific configuration of the nonvolatile memory device according to the first embodiment. [Figure 10A] FIG. 10A is a diagram showing the write mode in which data "0" is written. [Figure 10B] FIG. 10B is a diagram showing the write mode in which data "1" is written. [Figure 10C] FIG. 10C shows the case of the read mode. [Figure 11] FIG. 11 is a diagram showing the configuration of a nonvolatile memory device according to the second embodiment. [Figure 12A] FIG. 12A is a diagram showing the write mode in which data "0" is written. [Figure 12B] FIG. 12B is a diagram showing the case of the read mode. [Figure 13] FIG. 13 is a diagram showing the configuration of a nonvolatile memory device according to the third embodiment. [Figure 14] FIG. 14 is a diagram showing the configuration of a nonvolatile memory device according to the fourth embodiment.

[0009] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0010] <About memory elements> A memory element is an element that can perform a programmable operation and is composed of transistors. A memory element is also called an OTP (One Time Programmable) element.

[0011] 1 is a diagram showing voltage application to a memory element MT during a program operation. The memory element MT is composed of an NMOS transistor (N-channel MOSFET (metal-oxide-semiconductor field-effect transistor)). FIG. 2 is a cross-sectional view of the vertical structure of the memory element MT corresponding to FIG. 1.

[0012] 1 and 2, during a program operation, a high voltage Vpp is applied to the gate G of the memory element MT, a high voltage Vpp is applied to the source S, and a ground potential Vss (=0V) is applied to the drain D. The high voltage Vpp is, for example, +6.5V.

[0013] Such voltage application generates hot carriers (electrons) that flow from the drain D to the source S directly below the gate G, as indicated by the arrows in Figure 2. The hot carriers are attracted to the high voltage Vpp (positive voltage) applied to the gate G and trapped in the sidewall SSw on the source S side that is provided along the side of the gate G (trapped hot carriers E are shown in Figure 2).

[0014] 3 is a diagram showing voltage application to memory elements MT1 and MT2 (NMOS transistors) during a read operation, and FIG. 4 is a cross-sectional view of the vertical structure of memory elements MT1 and MT2 corresponding to FIG.

[0015] 3 and 4, during a read operation, gate voltages Vg1 and Vg2 are applied to the gates G of memory elements MT1 and MT2, drain voltages Vd1 and Vd2 are applied to the drains D, and a ground potential Vs (=0V) is applied to the sources. The gate voltages Vg1 and Vg2 are, for example, 2V. The drain voltages Vd1 and Vd2 are, for example, +0.5V.

[0016] 3 and 4 show, as an example, a case where the memory device MT1 is in a state before the execution of a program operation (unprogrammed state), and the memory device MT2 is in a state after the execution of a program operation (programmed state).

[0017] As shown in Figure 4, in memory element MT2 after the program operation has been performed, hot carriers E are trapped in the sidewall SSw. This prevents the electric field generated by the gate voltage Vg2 from reaching directly below the sidewall SSw, and the channel CN2 is interrupted on the source S side. This increases the gate threshold voltage, making it difficult for drain current to flow. On the other hand, as shown in Figure 4, memory element MT1, which has not yet been programmable, has a low gate threshold voltage, so it is in the on state and drain current flows. Data can be read out by utilizing the magnitude of the drain current depending on whether the memory element is in an unprogrammed or programmed state.

[0018] <Comparative Example> Before describing embodiments of the present disclosure, a comparative example will be described for comparison. Fig. 5 is a diagram showing the configuration of a nonvolatile memory device 100 according to the comparative example. The nonvolatile memory device 100 includes a constant current source 2, current mirrors 3, 4, and 5, and a readout unit 6.

[0019] The current mirror 3 has an input transistor 31, a first output transistor 32, and a second output transistor 33. The transistors 31 to 33 are all configured by PMOS transistors (P-channel MOSFETs). The drain of the input transistor 31 is connected to the constant current source 2. The gate and drain of the input transistor 31 are short-circuited. The gate of the input transistor 31 is connected to the gate of the first output transistor 32 and the gate of the second output transistor 33. The sources of the transistors 31 to 33 are connected to the application terminal of the power supply voltage VDD1.

[0020] The current mirror 4 has a first reference memory element 41 on the input side and a first memory element 42 on the output side. Both the first reference memory element 41 and the first memory element 42 are memory elements and are configured by NMOS transistors. The drain of the first reference memory element 41 is connected to the drain of the first output-side transistor 32. The gate and drain of the first reference memory element 41 are shorted. The gates of the first reference memory element 41 and the first memory element 42 are connected to each other. The sources of the first reference memory element 41 and the first memory element 42 are connected to a ground terminal (a terminal to which the ground potential is applied).

[0021] As previously mentioned, the memory elements are elements that can undergo a program operation. The first memory element 42 is the target of the program operation. That is, the first memory element 42 can be in an unprogrammed state or a programmed state. The first reference memory element 41 remains in an unprogrammed state.

[0022] The current mirror 5 has a second reference memory element 51 on the input side and a second memory element 52 on the output side. Both the second reference memory element 51 and the second memory element 52 are memory elements and are configured by NMOS transistors. The drain of the second reference memory element 51 is connected to the drain of the second output-side transistor 33. The gate and drain of the second reference memory element 51 are shorted. The gates of the second reference memory element 51 and the second memory element 52 are connected to each other. The sources of the second reference memory element 51 and the second memory element 52 are connected to the ground terminal.

[0023] The second memory element 52 is the target of the program operation, i.e., the second memory element 52 can be in an unprogrammed state or a programmed state, while the second reference memory element 51 remains in an unprogrammed state.

[0024] The reading unit 6 is a circuit that reads out the data states of the first memory element 42 and the second memory element 52, and includes PMOS transistors 61 and 62. The sources of the PMOS transistors 61 and 62 are connected to a terminal to which a power supply voltage VDD2 is applied. The drain of the PMOS transistor 61 and the gate of the PMOS transistor 62 are connected to the drain of the first memory element 42. The drain of the first memory element 42 is connected to the output terminal T1. The drain of the PMOS transistor 62 and the gate of the PMOS transistor 61 are connected to the drain of the second memory element 52. The drain of the second memory element 52 is connected to the output terminal T2.

[0025] The first reference memory device 41 and the second reference memory device 51 have the same structure and have the same electrical characteristics before a program operation is performed. The first memory device 51 and the second memory device 52 have the same structure and have the same electrical characteristics before a program operation is performed.

[0026] Note that, with respect to transistors, the concept of "structure" includes the size of the transistor. Therefore, for any plurality of transistors, the concept of "same structure" means that the sizes of the plurality of transistors are also the same. When certain transistors have the same structure, if hot carrier injection into the plurality of transistors by a program operation has not been performed on the plurality of transistors, the electrical characteristics (including gate threshold voltage, etc.) of the plurality of transistors will also be the same. However, the concept of "same structure" means that the structure and electrical characteristics of any plurality of transistors are the same in terms of design, and may actually include errors (i.e., "same" is understood to be a concept that includes errors).

[0027] The constant current generated by the constant current source 2 is mirrored by the current mirror 3, resulting in a current Ia flowing through the first reference memory element 41 and a current Ib flowing through the second reference memory element 51, where Ia=Ib. Since both the first reference memory element 41 and the second reference memory element 51 are in an unprogrammed state, the gate-source voltage Vgs1 of the first reference memory element 41 and the gate-source voltage Vgs2 of the second reference memory element 51 are Vgs1=Vgs2.

[0028] When the first memory element 42 and the second memory element 52 are both in an unprogrammed state, the drain current I1 flowing through the first memory element 42 and the drain current I2 flowing through the second memory element 52 are I1=I2, and the data state is indeterminate.

[0029] In order to store data, one of the first memory element 42 and the second memory element 52 is set to a programmed state, and the other is set to an unprogrammed state. Hereinafter, as an example, when the first memory element 42 is in a programmed state and the second memory element 52 is in an unprogrammed state, it is assumed that data "1" is stored, and when the first memory element 42 is in an unprogrammed state and the second memory element 52 is in a programmed state, it is assumed that data "0" is stored.

[0030] 6 is a schematic diagram showing the relationship between Vgs (gate-source voltage) and Ids (drain current) depending on the state of the memory element (unprogrammed state (initial state) INI, programmed state PRG). As shown in FIG. 6, the threshold voltage Vth2 in the programmed state is higher than the threshold voltage Vth1 in the unprogrammed state.

[0031] Here, when the first memory element 42 is in an unprogrammed state and the second memory element 52 is in a programmed state (data "0"), if Vgs1=Vgs2, the drain current I1>I2, as shown in FIG. 6. On the other hand, when the first memory element 42 is in a programmed state and the second memory element 52 is in an unprogrammed state (data "1"), I1 <I2となる。

[0032] The reading unit 6 (Fig. 5) reads data based on the magnitude relationship between I1 and I2 as described above. In the reading unit 6, the voltage of line L1 through which drain current I1 flows and the voltage of line L2 through which drain current I2 flows are set to VDD2 by initialization. Thereafter, I1 and I2 flow. Here, when I1 > I2, the voltage of line L1 drops rapidly, PMOS transistor 62 is turned on first, and the voltage of output terminal T2 becomes high level. At this time, PMOS transistor 61 is in the off state, and output terminal T1 becomes low level. On the other hand, when I1 < I2, the voltage of line L2 drops rapidly, PMOS transistor 61 is turned on first, and the voltage of output terminal T1 becomes high level. At this time, PMOS transistor 62 is in the off state, and output terminal T2 becomes low level. Thus, data is read according to the levels of output terminals T1 and T2.

[0033] Here, Fig. 7 is a diagram showing an example of the variation due to the normal distribution of the drain current Id_PRG flowing through the programmed memory element and the drain current Id_INI flowing through the unprogrammed memory element (initial state). The variation in current is the variation between products due to manufacturing variations. In Fig. 7, the current values on the horizontal axis are shown in logarithmic scale.

[0034] In Fig. 7, initially, there is a difference between drain current Id_PRG and drain current Id_INI, and the reversal of the magnitude relationship of the drain current does not occur. However, in the programmed memory element, due to aging degradation, charges leak from the sidewall, and drain current Id_PRG tries to return to drain current Id_INI in the unprogrammed state, increasing the current value (arrow in Fig. 7). As a result, the magnitude relationship of the drain current may be reversed. Explained with reference to Fig. 6, in the state where Vgs2 is applied to the second memory element 52 in the programmed state PRG, drain current I2 flows through the second memory element 52. However, when it changes to the programmed state PRG' due to aging degradation, the drain current changes to I2' accordingly and approaches drain current I1.

[0035] For nonvolatile memory devices, it is necessary to ensure that the drain current magnitude relationship does not reverse due to aging during the warranty period (maintaining the expected value). Therefore, during shipping testing, a test can be performed to simulate aging by increasing the gate voltage of a programmed memory element above normal, thereby increasing the drain current. However, this requires a test circuit, evaluation on an actual device to properly configure the test circuit, and long-term monitoring and correction, such as defect monitoring, after mass production begins, which increases development costs.

[0036] First Embodiment Next, a first embodiment of the present disclosure will be described. In this embodiment, in a nonvolatile memory device 1 having the same configuration as that shown in FIG. 5, a program operation is performed on reference memory elements 41 and 51, as shown in FIGS. 8A and 8B. Note that the specific configuration of the nonvolatile memory device 1 differs from that of the comparative example, as will be described later.

[0037] In Figure 8A, in the nonvolatile memory device 1, the second memory element 52 is in a programmed state, the second reference memory element 51 is in an unprogrammed state, the first memory element 42 is in an unprogrammed state, and the first reference memory element 41 is in a programmed state ("P" represents the programmed state). On the other hand, in Figure 8B, in the nonvolatile memory device 1, the first memory element 42 is in a programmed state, the first reference memory element 41 is in an unprogrammed state, the second memory element 52 is in an unprogrammed state, and the second reference memory element 51 is in a programmed state.

[0038] That is, in this embodiment, the reference memory element corresponding to one of the memory elements 42 and 52 that has been set to an unprogrammed state is set to a programmed state.

[0039] 8A, the first reference memory device 41 is in a programmed state, which increases Vgs1 compared to the unprogrammed state. Because Vgs1 is applied to the first memory device 42, the drain current I1 through the first memory device 42 increases. Therefore, the difference between I1 and I2 increases.

[0040] 7, the drain current Id_INI of the unprogrammed memory element increases, and the difference with the drain current Id_PRG of the programmed memory element is further ensured. As a result, the nonvolatile memory device 1 does not require the test circuit described above for guaranteeing the warranty period, which leads to a reduction in development costs.

[0041] Fig. 9 is a diagram showing a more specific configuration of the nonvolatile memory device 1 according to this embodiment. Regarding the configuration shown in Fig. 9, the nonvolatile memory device 1 includes switches NM1 to NM4, switches S1 to S4, a high-side switch HS1, a low-side switch LS1, and an inverter INV1, as will be described below.

[0042] The switches NM1 to NM4 are each composed of an NMOS transistor. The drain of the switch NM1 is connected to the drain of the first reference memory element 41. The source of the switch NM1 is connected to the ground terminal. The gate of the switch NM1 is connected to an application terminal of a "0" write signal W0. The "0" write signal W0 is a signal for writing data "0".

[0043] The drain of the switch NM2 is connected to the drain of the first memory element 42. The source of the switch NM2 is connected to the ground terminal. The gate of the switch NM2 is connected to the application terminal of the "1" write signal W1. The "1" write signal W1 is a signal for writing data "1".

[0044] The switches S1 to S4 are each composed of an NMOS transistor. The drain of the switch S1 is connected to the drain of the first output-side transistor 32. The source of the switch S1 is connected to the drain of the first reference memory element 41. The source of the switch S2 is connected to the drain of the first memory element 42. The gates of the switches S1 and S2 are connected to the output terminal of the inverter INV1. The input terminal of the inverter INV1 is connected to the application terminal of the write mode signal WM. The write mode signal WM is a signal for switching between write mode and read mode.

[0045] The drain of the switch NM3 is connected to the drain of the second reference memory element 51. The source of the switch NM3 is connected to the ground terminal. The gate of the switch NM3 is connected to the application terminal of the "1" write signal W1. The drain of the switch NM4 is connected to the drain of the second memory element 52. The source of the switch NM4 is connected to the ground terminal. The gate of the switch NM4 is connected to the application terminal of the "0" write signal W0.

[0046] The drain of the switch S3 is connected to the drain of the second output-side transistor 33. The source of the switch S3 is connected to the drain of the second reference memory element 51. The source of the switch S4 is connected to the drain of the second memory element 52. The gates of the switches S3 and S4 are connected to the output terminal of the inverter INV1.

[0047] The high-side switch HS1 is composed of a PMOS transistor. The low-side switch LS1 is composed of an NMOS transistor. The source of the high-side switch HS1 is connected to the application terminal of the power supply voltage VPP1. The drain of the high-side switch HS1 is connected to the drain of the low-side switch LS1. The source of the low-side switch LS1 is connected to the ground terminal. The sources of the reference memory elements 41 and 51 and the memory elements 42 and 52 are connected to the drain of the low-side switch LS1. The gates of the high-side switch HS1 and the low-side switch LS1 are connected to the output terminal of the inverter INV1.

[0048] The drains of the switches S2 and S4 are connected to a readout unit 6 (not shown).

[0049] The write / read operations in the nonvolatile memory device 1 configured as described above will now be described. FIG. 10A illustrates the write mode and the case where data "0" is written. In this case, the write mode signal WM is high, the "0" write signal W0 is high, and the "1" write signal is low. As a result, the switches NM1 are on, NM2 are off, NM3 are off, and NM4 are on, the switches S1 to S4 are off, the high-side switch HS1 is on, and the low-side switch LS1 is off. Therefore, a program operation is performed on the first reference memory element 41 and the second memory element 52, and the first reference memory element 41 and the second memory element 52 enter a programmed state.

[0050] 10B is a diagram showing the write mode and the case where data "1" is written. In this case, the write mode signal WM is high, the "0" write signal W0 is low, and the "1" write signal is high. As a result, the switches NM1 are off, NM2 are on, NM3 are on, and NM4 are off, the switches S1 to S4 are off, the high-side switch HS1 is on, and the low-side switch LS1 is off. Therefore, a program operation is performed on the first memory element 42 and the second reference memory element 51, and the first memory element 42 and the second reference memory element 51 are in a programmed state.

[0051] Figure 10C shows the read mode. In this case, the write mode signal WM is low, the "0" write signal W0 is low, and the "1" write signal is low. This causes switches NM1 to NM4 to be off, switches S1 to S4 to be on, the high-side switch HS1 to be off, and the low-side switch LS1 to be on. This results in the state shown in Figure 8A or 8B, making it possible to read data.

[0052] Second Embodiment FIG. 11 is a diagram showing the configuration of a nonvolatile memory device 1X according to a second embodiment of the present disclosure. Here, differences between the configuration of the nonvolatile memory device 1X and that of the first embodiment shown in FIG. 9 will be described. The nonvolatile memory device 1X includes changeover switches PS1 and PS2. Furthermore, a third output transistor 34 and a fourth output transistor 35 are added to the current mirror 3. Note that the nonvolatile memory device 1X does not include switches S1 and S3 and switches NM1 and NM3.

[0053] The changeover switches PS1 and PS2 are each composed of a PMOS transistor. The changeover switches PS1 and PS2 are switches for switching the conduction and cut-off of a current path. The changeover switch PS1 is connected between the drain of the first output side transistor 32 and the drain of the second output side transistor 33. The gate of the changeover switch PS1 is connected to the drain of the switch S2.

[0054] The sources of the third output transistor 34 and the fourth output transistor 35 are connected to the application terminal of the power supply voltage VDD1. The gates of the third output transistor 34 and the fourth output transistor 35 are connected to the gate of the input transistor 31.

[0055] The changeover switch PS2 is connected between the drain of the third output side transistor 34 and the drain of the fourth output side transistor 35. The gate of the changeover switch PS2 is connected to the drain of the switch S4.

[0056] When the selector switch PS1 is in the off state, the current flowing through the first output transistor 32 becomes the current Ia, and when the selector switch PS1 is in the on state, the current flowing through the first output transistor 32 and the current flowing through the second output transistor 33 are combined to become the current Ia. In other words, it is possible to switch between a small state and a large state of the current Ia.

[0057] Similarly, when the selector switch PS2 is in the off state, the current flowing through the third output transistor 34 becomes the current Ib, and when the selector switch PS2 is in the on state, the current flowing through the third output transistor 34 and the current flowing through the fourth output transistor 35 are combined to become the current Ib. In other words, it is possible to switch between a small state and a large state of the current Ib.

[0058] The write / read operations in the nonvolatile memory device 1X configured as described above will now be described. FIG. 12A shows the write mode and the case where data "0" is written. In this case, the write mode signal WM is at high level, the "0" write signal W0 is at high level, and the "1" write signal is at low level. This results in NM2 being in the off state, NM4 being in the on state, switches S2 and S4 being in the off state, the high-side switch HS1 being in the on state, and the low-side switch LS1 being in the off state. Therefore, a program operation is performed only on the second memory element 52, and only the second memory element 52 is in the programmed state.

[0059] After writing data as shown in FIG. 12A, the data is read in the read state (read mode) shown in FIG. 12B. Here, the write mode signal WM is low, the "0" write signal W0 is low, and the "1" write signal is low. This causes NM2 to be off, NM4 to be off, switches S2 and S4 to be on, the high-side switch HS1 to be off, and the low-side switch LS1 to be on. At this time, the drain of the first memory element 42, which is in an unprogrammed state, becomes a low-level voltage, and the selector switch PS1 is on. Also, PS2 is off. Therefore, the currents flowing through the output-side transistors 32 and 33 are combined to form a current Ia, increasing Vgs1 of the first reference memory element 41. This increases the drain current I1, ensuring the difference between I1 and I2.

[0060] In addition, when only the first memory element 42 is programmed (writing "1"), the changeover switch PS1 is set to the OFF state and PS2 is set to the ON state during reading, thereby increasing the current Ib and increasing the drain current I2.

[0061] <Third embodiment> 13 is a diagram showing the configuration of a nonvolatile memory device 1Y according to a third embodiment of the present disclosure. The nonvolatile memory device 1Y according to this embodiment differs from the configuration in FIG. 5 in that it includes switches SW1 and SW2.

[0062] One end of the switch SW1 is connected to the drain of the first output transistor 32 and the gate of the first reference memory element 41. A second end of the switch SW1 is connected to the drain of the first reference memory element 41. One end of the switch SW2 is connected to the drain of the second output transistor 33 and the gate of the second reference memory element 51. A second end of the switch SW2 is connected to the drain of the second reference memory element 51.

[0063] In the nonvolatile memory device 1Y, with a configuration similar to that of the second embodiment (FIG. 11), only the first memory element 42 or only the second memory element 52 can be set to a programmed state. During reading, the switch (SW1 or SW2) connected to the reference memory element corresponding to the memory element that has been set to an unprogrammed state is set to an off state.

[0064] Specifically, when only the second memory element 52 is programmed, the switch SW1 connected to the first reference memory element 41 is turned off and the switch SW2 is turned on during a read operation. This applies the power supply voltage VDD1 to the gate of the unprogrammed first memory element 42, increasing the drain current I1. This ensures the difference between I1 and I2.

[0065] Similarly, when only the first memory element 42 is programmed, the switch SW2 connected to the second reference memory element 51 is turned off and the switch SW1 is turned on during a read operation. This applies the power supply voltage VDD1 to the gate of the unprogrammed second memory element 52, increasing the drain current I2. This ensures the difference between I1 and I2.

[0066] <Fourth embodiment> 14 is a diagram showing the configuration of a nonvolatile memory device 1Z according to a fourth embodiment of the present disclosure. The nonvolatile memory device 1Z according to this embodiment differs from the configuration of FIG. 5 in that it includes bypass switches RS1 and RS2 and resistors R1 and R2.

[0067] A resistor R1 is connected between the source of the first reference memory element 41 and the ground terminal. A bypass switch RS1 is connected across the resistor R1. A resistor R2 is connected between the source of the second reference memory element 51 and the ground terminal. A bypass switch RS2 is connected across the resistor R2.

[0068] In the nonvolatile memory device 1Z, with a configuration similar to that of the second embodiment (FIG. 11), only the first memory element 42 or only the second memory element 52 can be set to a programmed state. During reading, the bypass switch (RS1 or RS2) connected to the reference memory element corresponding to the memory element that has been set to an unprogrammed state is set to an off state.

[0069] Specifically, when only the second memory element 52 is programmed, the bypass switch RS1 connected to the first reference memory element 41 is turned off and the bypass switch RS2 is turned on during a read operation. This enables the resistor R1 and bypasses the resistor R2, making it ineffective. The first reference memory element 41 and the second reference memory element 51 have the same structure and have the same electrical characteristics before a program operation is performed. Since Ia=Ib, Vgs1 of the first reference memory element 41 and Vgs2 of the second reference memory element 51 are Vgs1=Vgs2, but the voltage across resistor R1 is added to Vgs1 of the first reference memory element 41, so that Vgs of the first memory element 42 becomes higher than Vgs of the second memory element 52. Therefore, the drain current I1 is increased, and the difference between I1 and I2 is ensured.

[0070] Similarly, when only the first memory element 42 is in the programmed state, the bypass switch RS2 connected to the second reference memory element 51 is turned off during reading, and the bypass switch RS1 is turned on. This enables the resistor R2, and bypasses and disables the resistor R1. As a result, the voltage across the resistor R2 is added to the Vgs2 of the second reference memory element 51, so that the Vgs of the second memory element 52 becomes higher than the Vgs of the first memory element 42. Therefore, the drain current I2 is increased, and the difference between I1 and I2 is maintained.

[0071] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0072] <Additional Notes> As described above, the nonvolatile memory device (1) according to one aspect of the present disclosure has: a first current mirror (4) configured to receive a first input current (Ia); a second current mirror (5) configured to receive a second input current (Ib); Equipped with The first current mirror has a first reference memory element (41) on the input side and a first memory element (42) on the output side, the second current mirror comprises a second reference memory element (51) on the input side and a second memory element (52) on the output side; Data can be read based on the magnitude relationship between a first output current (I1) output from the first current mirror and a second output current (I2) output from the second current mirror, If the second memory element is in a programmed state and the second reference memory element is in an unprogrammed state, placing the first memory element in an unprogrammed state and setting a gate voltage of the first memory element higher than a gate voltage of the second memory element; When the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, the second memory element is in an unprogrammed state, and the gate voltage of the second memory element is higher than the gate voltage of the first memory element (first configuration, Figures 8A and 8B).

[0073] With this configuration, the difference between the first output current and the second output current is more secure, and it is guaranteed that the expected value is maintained during the warranty period.

[0074] In the first configuration, when the second memory element is in a programmed state and the second reference memory element is in an unprogrammed state, the first reference memory element is set to a programmed state, thereby making the gate voltage of the first memory element higher than the gate voltage of the second memory element; When the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, the second reference memory element may be configured to be in a programmed state, thereby making the gate voltage of the second memory element higher than the gate voltage of the first memory element (second configuration, Figures 8A and 8B).

[0075] In the first configuration, the first input current and the second input current are each switchable between a small state and a large state; When the second memory device is in a programmed state and the second reference memory device is in an unprogrammed state, the first input current is set to a large state and the second input current is set to a small state, thereby making the gate voltage of the first memory device higher than the gate voltage of the second memory device; When the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, the second input current may be set to a large state and the first input current may be set to a small state, thereby making the gate voltage of the second memory element higher than the gate voltage of the first memory element (third configuration, Figure 12B).

[0076] In addition, in the first configuration, when the second memory element is in a programmed state and the second reference memory element is in an unprogrammed state, a power supply voltage (VDD1) is applied to the gate of the first memory element, thereby making the gate voltage of the first memory element higher than the gate voltage of the second memory element; When the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, a power supply voltage may be applied to the gate of the second memory element, thereby making the gate voltage of the second memory element higher than the gate voltage of the first memory element (fourth configuration, Figure 13).

[0077] In the first configuration, a first resistor (R1) connected between the first reference memory element and a ground terminal; a second resistor (R2) connected between the second reference memory element and a ground terminal; When the second memory element is in a programmed state and the second reference memory element is in an unprogrammed state, enabling the first resistor and disabling the second resistor causes the gate voltage of the first memory element to be higher than the gate voltage of the second memory element; When the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, the first resistor may be disabled and the second resistor may be enabled, thereby making the gate voltage of the second memory element higher than the gate voltage of the first memory element (fifth configuration, Figure 14).

[0078] In addition, in any of the above first to fifth configurations, the first memory element and the second memory element may be configured to execute a program by trapping an electric charge (E) in a sidewall (SSw) (sixth configuration). [Industrial Applicability]

[0079] The present disclosure can be used, for example, in nonvolatile memory devices mounted on various semiconductor devices. [Explanation of symbols]

[0080] 1. Non-volatile memory device 1X~1Z non-volatile memory device 2 constant current source 3~5 current mirror 6 Readout section 31 Input transistor 32 First output transistor 33 Second output transistor 34 Third output transistor 35 Fourth output transistor 41 first reference memory element 42 second memory element 51 second reference memory element 52 second memory element 61,62 PMOS transistor 100 Non-volatile memory device E Hot Carrier HS1 High Side Switch INV1 inverter LS1 Low-Side Switch MT memory element MT1, MT2 memory elements NM1~NM4 switches PS1, PS2 switch R1,R2 resistance RS1, RS2 bypass switch S1~S4 switches SSw sidewall SW1, SW2 switches T1, T2 output terminals

Claims

1. a first current mirror configured to receive a first input current; a second current mirror configured to receive a second input current; Equipped with the first current mirror has a first reference memory element on an input side and a first memory element on an output side; the second current mirror includes a second reference memory element on the input side and a second memory element on the output side; data can be read based on the magnitude relationship between a first output current output from the first current mirror and a second output current output from the second current mirror; If the second memory element is in a programmed state and the second reference memory element is in an unprogrammed state, placing the first memory element in an unprogrammed state and setting a gate voltage of the first memory element higher than a gate voltage of the second memory element; When the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, the second memory element is in an unprogrammed state and a gate voltage of the second memory element is made higher than a gate voltage of the first memory element.

2. when the second memory element is in a programmed state and the second reference memory element is in an unprogrammed state, placing the first reference memory element in a programmed state, thereby causing a gate voltage of the first memory element to be higher than a gate voltage of the second memory element; 2. The nonvolatile memory device of claim 1, wherein when the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, the second reference memory element is set to a programmed state, causing a gate voltage of the second memory element to be higher than a gate voltage of the first memory element.

3. the first input current and the second input current are each switchable between a small state and a large state; When the second memory element is in a programmed state and the second reference memory element is in an unprogrammed state, the first input current is set to a large state and the second input current is set to a small state, thereby making the gate voltage of the first memory element higher than the gate voltage of the second memory element; 2. The nonvolatile memory device of claim 1, wherein when the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, the second input current is set to a large state and the first input current is set to a small state, thereby making the gate voltage of the second memory element higher than the gate voltage of the first memory element.

4. applying a power supply voltage to the gate of the first memory device when the second memory device is in a programmed state and the second reference memory device is in an unprogrammed state, thereby making the gate voltage of the first memory device higher than the gate voltage of the second memory device; 2. The nonvolatile memory device of claim 1, wherein when the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, a power supply voltage is applied to the gate of the second memory element, thereby making the gate voltage of the second memory element higher than the gate voltage of the first memory element.

5. a first resistor connected between the first reference memory element and a ground terminal; a second resistor connected between the second reference memory element and a ground terminal; When the second memory element is in a programmed state and the second reference memory element is in an unprogrammed state, enabling the first resistor and disabling the second resistor causes the gate voltage of the first memory element to be higher than the gate voltage of the second memory element; 2. The nonvolatile memory device of claim 1, wherein when the first memory element is in a programmed state and the first reference memory element is in an unprogrammed state, the first resistor is disabled and the second resistor is enabled, thereby causing the gate voltage of the second memory element to be higher than the gate voltage of the first memory element.

6. The nonvolatile memory device of claim 1 , wherein the first memory element and the second memory element are configured to execute programming by trapping charges in sidewalls.

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