Semiconductor memory device

Abstract

To provide a semiconductor memory device that allows high integration.SOLUTION: A semiconductor memory device includes: a substrate; a first via wiring line extending in a first direction; a plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via wiring line; a memory unit arranged in the first direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes arranged in the first direction and facing the plurality of first semiconductor layers; a plurality of first wiring lines arranged in the first direction and extending in a second direction, the plurality of first wiring lines being electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers arranged in the first direction and electrically connected to the plurality of first wiring lines; a plurality of second gate electrodes arranged in the first direction and facing the plurality of second semiconductor layers; a second via wiring line extending in the first direction and electrically connected to the plurality of second gate electrodes; and a plurality of second wiring lines extending in the first direction, electrically connected to the plurality of second semiconductor layers and arranged with the plurality of second semiconductor layers in a third direction.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] As semiconductor memory devices become more highly integrated, studies are underway to make semiconductor memory devices three-dimensional. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0399308 [Patent Document 2] US Patent Application Publication No. 2023 / 0387055 [Patent Document 3] US Patent Application Publication No. 2023 / 0397398 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that can be highly integrated is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate, a first via wiring extending in a first direction intersecting a surface of the substrate, a plurality of first semiconductor layers aligned in the first direction and electrically connected to the first via wiring, a memory unit aligned in the first direction and electrically connected to the plurality of first semiconductor layers, a plurality of first gate electrodes aligned in the first direction and facing the plurality of first semiconductor layers, a plurality of first wirings aligned in the first direction and extending in a second direction intersecting the first direction and electrically connected to the plurality of first gate electrodes, a plurality of second semiconductor layers aligned in the first direction and electrically connected to the plurality of first wirings, a plurality of second gate electrodes aligned in the first direction and facing the plurality of second semiconductor layers, a second via wiring extending in the first direction and electrically connected to the plurality of second gate electrodes, and a second wiring extending in the first direction and electrically connected to the plurality of second semiconductor layers, aligned with the plurality of second semiconductor layers in a third direction intersecting the first direction and the second direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a schematic circuit diagram for explaining a read operation of the semiconductor memory device. [Figure 3] FIG. 2 is a schematic perspective view showing a configuration of a part of the semiconductor memory device. [Figure 4] FIG. 2 is a schematic perspective view showing a configuration of a part of the semiconductor memory device. [Figure 5] FIG. 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 6] FIG. 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 7] FIG. 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 8] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 9] FIG. 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 10]FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 11] FIG. 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 12] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 13] FIG. 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 14] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 15] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 16] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 19] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 20] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 23] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 24] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 25] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 27] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 30] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 31] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 32] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 33] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 34] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 35] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 36] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 40] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 41] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 42] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 43] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 44] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 45] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 46] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 47]5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 48] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 49] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 50] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 51] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 52] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 53] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 54] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 55] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 56] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 57] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 58] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 59] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 60] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 61] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 62] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 63] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 64] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 65] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 66] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 67] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 68] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 69] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 70] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 71] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 72] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 73] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 74] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 75] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 76] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 77] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 78] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 79] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 80] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 81] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 82] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 83] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 84] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 85] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 86] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 87] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 88] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 89] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 90] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 91] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 92] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 93] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 94] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 95] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 96] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 97] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 98] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 99] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 100] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 101] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 102] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 103]5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 104] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 105] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 106] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 107] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 108] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 109] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 110] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 111] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 112] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 113] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 114] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 115] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 116] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 117] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 118] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 119] FIG. 10 is a schematic XY cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Next, semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. The following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Furthermore, parts common to multiple embodiments are given the same reference numerals, and explanations thereof may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0010] Furthermore, in this specification, when it is said that a first configuration is "electrically connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is electrically connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in the current path between the two wirings, and that the transistor or the like is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] In addition, in this specification, a direction along a predetermined plane may be referred to as the first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as the second direction, and a direction that intersects with this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as "up," and the direction approaching the substrate along the Z direction is referred to as "lower." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are referred to as side surfaces, etc.

[0015] Furthermore, in this specification, when we say the "center position" of a certain feature, it may mean, for example, the position of the center of the circumscribing circle of this feature, or it may mean the center of gravity of the image of this feature on a specified plane.

[0016] [First embodiment] [Circuit configuration] Fig. 1 is a schematic circuit diagram showing a partial configuration of a semiconductor memory device according to the first embodiment. As shown in Fig. 1, the semiconductor memory device according to this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers ML0 to ML3 (hereinafter sometimes referred to as "memory layers ML"), a plurality of bit lines BL connected to the plurality of memory layers ML0 to ML3, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL, and plate lines PL connected to the plurality of memory layers ML0 to ML3.

[0017] Each of the memory layers ML0 to ML3 includes a plurality of word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL") and a plurality of memory cells MC connected to the plurality of word lines WL0 to WL2. Each of the memory cells MC includes a transistor TrC and a capacitor CpC. One electrode of the transistor TrC is connected to a bit line BL. The other electrode of the transistor TrC is connected to the capacitor CpC. The one and the other electrodes of the transistor TrC function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrC. The gate electrode of the transistor TrC is connected to one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the other electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to a plate line PL.

[0018] Each bit line BL is connected to a plurality of memory cells MC corresponding to a plurality of memory layers ML0 to ML3, and each bit line BL is connected to a global bit line GBL.

[0019] Furthermore, the memory layers ML0 to ML3 each include a plurality of transistors TrR0a, TrR1a, TrR2a, and TrR3a (hereinafter sometimes referred to as "transistors TrRa") provided corresponding to a plurality of word lines WL0 to WL2, and a plurality of transistors TrR0b, TrR1b, TrR2b, and TrR3b (hereinafter sometimes referred to as "transistors TrRb"). One electrode of each of the transistors TrRa and TrRb is connected to one of the word lines WL0 to WL2. The other electrodes of each of the transistors TrRa, TrR1a, TrR2a, and TrR3a are connected to layer selection lines LL0a, LL1a, LL2a, and LL3a (hereinafter sometimes referred to as "layer selection line LL"). The other electrodes of each of the transistors TrR0b, TrR1b, TrR2b, and TrR3b are connected to a wiring NLL. The electrodes of the transistors TrRa and TrRb function as source or drain electrodes depending on the voltage supplied to the transistors TrRa and TrRb. The gate electrodes of the transistors TrRa and TrRb are connected to word line selection lines LW0a, LW1a, LW2a, LW0b, LW1b, and LW2b (hereinafter sometimes referred to as "word line selection lines LW"), respectively.

[0020] The word line selection line LW is connected to multiple transistors TrRa and TrRb corresponding to multiple memory layers ML0 to ML3. Furthermore, layer selection lines LL0a, LL1a, LL2a, and LL3a are connected in common to all transistors TrR0a, TrR1a, TrR2a, and TrR3a corresponding to memory layers ML0 to ML3, respectively. The wiring NLL is connected in common to all transistors TrR0b, TrR1b, TrR2b, and TrR3b corresponding to all word lines WL0, WL1, and WL2.

[0021] [Read operation] FIG. 2 is a schematic circuit diagram for explaining the read operation of the semiconductor memory device according to the first embodiment.

[0022] In a read operation, one of the plurality of memory layers ML0 to ML3 is selected. In the illustrated example, the memory layer ML0 is selected. When selecting the memory layer ML0 to ML3, for example, a voltage V is applied to the layer selection line LL0a corresponding to the memory layer ML0 that is the target of the read operation, among the plurality of layer selection lines LL0a, LL1a, LL2a, and LL3a. ON and supplies voltage V to the other layer selection lines LL1a, LL2a, and LL3a. OFF Also, for example, if the line NLL is supplied with a voltage V OFF supply.

[0023] Voltage V ON The voltage V has a magnitude sufficient to turn on the transistor TrC. OFF For example, when the transistor TrC is an NMOS transistor, the voltage V ON is the voltage V OFF For example, if the transistor TrC is a PMOS transistor, the voltage V ON is the voltage V OFF is smaller than.

[0024] In addition, in a read operation, one of the plurality of word lines WL0 to WL2 is selected. In the illustrated example, the word line WL0 is selected. When selecting the word line WL0 to WL2, for example, a voltage V is applied to the word line selection line LW0a corresponding to the word line WL0 that is the target of the read operation, among the plurality of word line selection lines LW0a, LW1a, and LW2a. ON ' is supplied to the other word line selection lines LW1a and LW2a, and the voltage V OFF Further, a voltage V is supplied to the word line selection line LW0b corresponding to the word line WL0 that is the target of the read operation among the plurality of word line selection lines LW0b, LW1b, and LW2b. OFF ' is supplied to the other word line selection lines LW1b and LW2b, and the voltage V ON ´ to supply.

[0025] Voltage V ONThe voltage V' has a magnitude sufficient to turn on the transistors TrRa and TrRb. OFF For example, when the transistors TrRa and TrRb are NMOS transistors, the voltage V ON ´ is the voltage V OFF For example, if the transistors TrRa and TrRb are PMOS transistors, the voltage V ON ´ is the voltage V OFF ´ is smaller than

[0026] Here, a voltage V ON is supplied. As a result, the transistor TrC in the selected memory cell MC is turned on. As a result, the voltage of the global bit line GBL fluctuates or a current flows through the global bit line GBL. By detecting this voltage fluctuation or current, it is possible to read the data stored in the selected memory cell MC.

[0027] In addition, the unselected word line WL0 corresponding to the memory layers ML1, ML2, and ML3 different from the selected memory cell MC is supplied with a voltage V OFF As a result, the transistor TrC in the memory cell MC is turned off.

[0028] Further, the unselected word lines WL1 and WL2 corresponding to the memory layers ML0, ML1, ML2, and ML3 are supplied with a voltage V OFF As a result, the transistor TrC in the memory cell MC is turned off.

[0029] In the following description, an example will be shown in which the transistors TrC, TrRa, and TrRb are all NMOS transistors.

[0030] [structure] FIG. 3 is a schematic perspective view showing a partial configuration of the semiconductor memory device according to the first embodiment. FIG. 4 is a schematic perspective view showing a partial configuration of the semiconductor memory device, enlarging a portion of FIG. 3. FIGS. 5 and 6 are schematic XY cross-sectional views showing a partial configuration of the semiconductor memory device. FIGS. 7, 9, and 11 are schematic XY cross-sectional views showing a partial configuration of the semiconductor memory device, each showing an enlarged portion of FIG. 5. FIG. 8 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, cutting the structure shown in FIG. 7 along line AA' and viewing in the direction of the arrows. FIG. 10 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, cutting the structure shown in FIG. 9 along line BB' and viewing in the direction of the arrows. FIG. 12 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, cutting the structure shown in FIG. 11 along line CC' and viewing in the direction of the arrows. FIG. 13 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device, enlarging a portion of FIG. 6. Fig. 14 is a schematic cross-sectional view showing a partial configuration of the same semiconductor memory device, showing the configuration obtained by cutting the structure shown in Fig. 13 along line DD' and looking in the direction of the arrows. Fig. 15 is a schematic cross-sectional view showing a partial configuration of the same semiconductor memory device, showing the configuration obtained by cutting the structure shown in Fig. 6 along line EE' and looking in the direction of the arrows.

[0031] FIG. 3 shows a part of a semiconductor substrate Sub and a memory cell array MCA provided above the semiconductor substrate Sub.

[0032] The semiconductor substrate Sub is a semiconductor substrate such as silicon (Si) containing a P-type impurity such as boron (B). An insulating layer and an electrode layer (not shown) are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub and the insulating layer and electrode layer (not shown) constitute a peripheral circuit for controlling the semiconductor memory device according to the first embodiment. For example, a sense amplifier circuit is provided in a region directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the global bit line GBL. In a read operation, the sense amplifier circuit can read data stored in a selected memory cell MC by detecting a voltage fluctuation or current on the bit line BL. The peripheral circuit also includes a sequencer that supplies predetermined voltages to each wiring in the memory cell array MCA and each component in the sense amplifier circuit at predetermined timing, thereby performing a read operation, etc.

[0033] The memory cell array MCA includes a plurality of memory layers ML arranged in the Z direction. Furthermore, insulating layers 103 such as silicon oxide (SiO2) are provided between the plurality of memory layers ML.

[0034] As shown in FIGS. 5 and 6, the memory cell array MCA includes a memory cell region R MC is provided.

[0035] As shown in FIG. 5, the memory cell array MCA includes a memory cell region R MC The transistor region R is provided on one side in the Y direction. TrRa and the transistor area R TrRa The wiring area R is located on one side of the Y direction. LL The memory cell array MCA is provided with a memory cell region R MC and transistor area R TrRa The connection wiring area R CL1 and the transistor area R TrRa and the wiring area R LL The connection wiring area R CL2 And, it is provided.

[0036] As shown in FIG. 6, the memory cell array MCA includes a memory cell region R MC The transistor region R is provided on the other side in the Y direction. TrRb The memory cell array MCA is provided with a memory cell region R MC and transistor area R TrRb The connection wiring area R CL1 is provided.

[0037] [Memory cell area R MC Structure of As shown in FIG. 5, the memory cell region R MC are provided with a plurality of insulating layers 101 aligned in the X direction and a conductive layer 102 provided between two insulating layers 101 adjacent in the X direction. The insulating layers 101 and the conductive layers 102 extend in the Y direction and the Z direction, and divide the plurality of memory layers ML in the X direction.

[0038] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0039] The conductive layer 102 includes, for example, a stacked structure of titanium nitride (TiN) and silicon germanium (SiGe), etc. The conductive layer 102 functions as, for example, a plate line PL (FIG. 1).

[0040] In addition, the memory cell region R MC A plurality of via wirings 104 are arranged in the Y direction in the region between the insulating layer 101 and the conductive layer 102. These via wirings 104 extend in the Z direction, penetrating through a plurality of memory layers ML, as shown in FIG.

[0041] 4, the via wiring 104 includes, for example, a conductive oxide film 104a containing a conductive oxide, a barrier conductive film 104b such as titanium nitride (TiN), and a conductive member 104c such as tungsten (W). Note that the via wiring 104 may contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 104a. The via wiring 104 may also contain only a conductive oxide, or may contain only ruthenium (Ru), iridium (Ir), or other metals.

[0042] In this specification, the term "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other conductive materials containing oxygen.

[0043] The conductive member 104c has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 104b has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive member 104c. The conductive oxide film 104a has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the barrier conductive film 104b. The via wiring 104 functions as, for example, a bit line BL (FIG. 1).

[0044] The memory layer ML includes a conductive layer 120 provided between the insulating layer 101 and the plurality of via wirings 104 and extending in the Y direction, a plurality of transistor structures 110 arranged in the Y direction corresponding to the plurality of via wirings 104, and a plurality of capacitor structures 130 provided between the conductive layer 102 and the plurality of transistor structures 110 and arranged in the Y direction corresponding to the plurality of via wirings 104.

[0045] As shown in FIG. 4, for example, the transistor structure 110 includes a semiconductor layer 111 connected to the outer peripheral surface of the via wiring 104 and extending in the X direction, an insulating layer 112 provided on the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111, and a conductive layer 113 provided on the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the insulating layer 112.

[0046] 7, both side surfaces in the X direction of the semiconductor layer 111 may be formed along a circle whose center is the center of the via wiring 104. Similarly, the side surfaces on one side in the X direction (the conductive layer 120 side) of the insulating layer 112 and the conductive layer 113 may be formed along a circle whose center is the center of the via wiring 104. Furthermore, both side surfaces in the Y direction of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 may be formed linearly along the side surfaces of the insulating layer 115.

[0047] Note that both side surfaces of the semiconductor layer 111 in the X direction do not have to be formed along a circle. Even in such a case, for example, both side surfaces of the semiconductor layer 111 in the X direction may be curved when viewed from the Z direction. For example, the length of the semiconductor layer 111 in the X direction may vary depending on the position in the Y direction. For example, the length of the semiconductor layer 111 in the X direction at a position close to the insulating layer 115 may be shorter than the length of the semiconductor layer 111 in the X direction at a position far from the insulating layer 115.

[0048] The semiconductor layer 111 functions as, for example, a channel region of the transistor TrC (FIG. 1). The semiconductor layer 111 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor. The multiple semiconductor layers 111 aligned in the Z direction are commonly connected to a via wiring 104 extending in the Z direction.

[0049] The insulating layer 112 functions as, for example, a gate insulating film of the transistor TrC (FIG. 1). The insulating layer 112 includes, for example, silicon oxide (SiO 2 ).

[0050] The conductive layer 113 functions as, for example, the gate electrode of the transistor TrC (FIG. 1). The conductive layer 113 includes, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). As shown in FIG. 5, the multiple conductive layers 113 aligned in the Y direction are commonly connected to a conductive layer 120 extending in the Y direction. As shown in FIGS. 7 and 8, the conductive layer 113 faces the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111 via the insulating layer 112.

[0051] 5, an insulating layer 115 made of silicon oxide (SiO2) or the like is provided between two semiconductor layers 111 adjacent to each other in the Y direction. The insulating layer 115 extends in the Z direction, penetrating the multiple memory layers ML.

[0052] The conductive layer 120 functions as, for example, a word line WL (FIG. 1). As described above, the conductive layer 120 extends in the Y direction. One side surface of the conductive layer 120 in the X direction is connected to a plurality of conductive layers 113 arranged in the Y direction. As shown in FIGS. 7 and 8, the conductive layer 120 includes, for example, a barrier conductive film 121 made of titanium nitride (TiN) or the like, and a conductive film 122 made of tungsten (W).

[0053] As shown in FIGS. 7 and 8, the capacitor structure 130 includes a conductive layer 131, an insulating layer 132 provided on the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the conductive layer 131, a conductive layer 133 provided on the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the insulating layer 132, and an insulating layer 134 provided on the upper surface, lower surface, and both side surfaces in the Y direction of the conductive layer 133.

[0054] The conductive layer 131 functions as one electrode of the capacitor CpC (FIG. 1). The conductive layer 131 includes, for example, a stacked structure of titanium nitride (TiN) and silicon germanium (SiGe). The conductive layer 131 is connected to the conductive layer 102.

[0055] The insulating layer 132 functions as an insulating layer for the capacitor CpC (FIG. 1). The insulating layer 132 may be, for example, zirconia (ZrO), alumina (AlO), or other insulating metal oxides. Alternatively, the insulating layer 132 may be, for example, a stacked film of multiple insulating metal oxides (for example, a stacked film of zirconia and alumina).

[0056] The conductive layer 133 functions as, for example, the other electrode of the capacitor CpC (FIG. 1). The conductive layer 133 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 is insulated from the conductive layer 131 via the insulating layer 132. The conductive layer 133 is connected to one side of the semiconductor layer 111 in the X direction (the conductive layer 102 side).

[0057] The insulating layer 134 includes, for example, silicon oxide (SiO 2 ), etc. In the illustrated example, the insulating layer 134 is continuous with the insulating layer 112.

[0058] [Transistor area R TrRa Structure of As shown in Figure 5, the transistor region R TrRa are provided with a plurality of insulating layers 201 aligned in the X direction corresponding to the plurality of insulating layers 101, and an insulating layer 202 provided between two insulating layers 201 adjacent to each other in the X direction. The insulating layers 201 and 202 extend in the Y and Z directions and separate the plurality of memory layers ML in the X direction. The insulating layers 201 and 202 include, for example, silicon oxide (SiO2) or the like.

[0059] Also, the transistor region R TrRa A plurality of via wirings 204 are provided in the region between the insulating layer 201 and the insulating layer 202. The plurality of via wirings 204 are aligned in the Y direction and extend in the Z direction, penetrating through a plurality of memory layers ML, as shown in FIG.

[0060] The via wiring 204 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W), etc. The via wiring 204 has a substantially cylindrical shape extending in the Z direction.

[0061] The via wirings 204 arranged in the Y direction function as, for example, one word line selection line LW (FIG. 1). As shown in FIG. 1, for example, a plurality of word line selection lines LW are provided corresponding to the plurality of word lines WL included in the memory layer ML.

[0062] The memory layer ML includes a portion of a plurality of transistor structures 210 corresponding to the plurality of conductive layers 120, a conductive layer 221 provided between the transistor structure 210 and the insulating layer 201, and a conductive layer 222 provided between the transistor structure 210 and the insulating layer 202.

[0063] 12, the transistor structure 210 includes a portion provided in the memory layer ML and a portion provided at a height position corresponding to the insulating layer 103. Of these, the portion provided in the memory layer ML includes, as shown in Fig. 11, a plurality of insulating layers 211 provided on the outer peripheral surfaces of a plurality of via wirings 204, and a semiconductor layer 213 provided on the outer peripheral surfaces of these plurality of insulating layers 211 and extending in the Y direction. Furthermore, as shown in Fig. 12, the portion provided at a height position corresponding to the insulating layer 103 includes insulating layers 214 provided on the upper and lower surfaces of the semiconductor layer 213, and conductive layers 215 provided on the upper and lower surfaces of the insulating layer 214.

[0064] In the XY cross section illustrated in FIG. 11, the side surfaces of the semiconductor layer 213 on both sides in the X direction may be formed along multiple overlapping circles centered on the central positions of the via wirings 204.

[0065] The insulating layer 211 includes, for example, silicon oxide (SiO2) or the like. The insulating layer 211 has a substantially cylindrical shape extending in the Z direction along part of the outer circumferential surface of the via wiring 204. The insulating layer 211 is continuous with the insulating layer 214 (FIG. 12).

[0066] The semiconductor layer 213 functions as, for example, a channel region of the transistor TrRa (FIG. 1). The semiconductor layer 213 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor.

[0067] The insulating layer 214 functions as, for example, a gate insulating film of the transistor TrRa (FIG. 1). The insulating layer 214 includes, for example, silicon oxide (SiO 2 ).

[0068] The conductive layer 215 functions as, for example, the gate electrode of the transistor TrRa (FIG. 1). The conductive layer 215 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 215 is connected to a plurality of via wirings 204 arranged in the Y direction. When focusing on two semiconductor layers 213 adjacent to each other in the Z direction, one conductive layer 215 provided between them faces the lower surface of the semiconductor layer 213 provided above and the upper surface of the semiconductor layer 213 provided below, with the insulating layer 214 interposed therebetween. The plurality of conductive layers 215 arranged in the Z direction are commonly connected to the via wirings 204 extending in the Z direction.

[0069] Note that when two conductive layers 215 adjacent to each other in the Z direction are considered, these conductive layers 215 are connected only through via wiring 204. That is, the ends of these two conductive layers 215 in the Y direction are spaced apart in the Z direction. Similarly, the ends of these two conductive layers 215 in the X direction are also spaced apart in the Z direction.

[0070] The conductive layer 221 is connected to a side surface of the semiconductor layer 213 on one side in the X direction (the insulating layer 201 side). As shown in FIG. 5, the conductive layer 221 is connected to a side surface of the transistor region R TrRa From the connection wiring area R CL2The conductive layer 221 extends in the Y direction from the first electrode of the transistor TrRa (FIG. 1) to the second electrode of the layer selection line LL (FIG. 1) and serves to electrically connect the other electrode of the transistor TrRa (FIG. 1) to the layer selection line LL (FIG. 1). The conductive layer 221 includes, for example, a conductive oxide. Note that the conductive layer 221 may include ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide. The conductive layer 221 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0071] 12, the conductive layer 221 may include a portion formed on the lower surface of the insulating layer 103, a portion formed on the upper surface of the insulating layer 103, and a portion formed on one side of the semiconductor layer 213 in the X direction (the insulating layer 201 side). In addition, insulating layers 223 and 224 such as silicon oxide (SiO2) may be provided in the region surrounded by the conductive layer 221.

[0072] The conductive layer 222 is connected to the semiconductor layer 213. As shown in FIG. TrRa From the connection wiring area R CL1 The conductive layer 222 extends in the Y direction from the first electrode of the transistor TrRa (FIG. 1) to the word line WL (FIG. 1) and serves to electrically connect the first electrode of the transistor TrRa (FIG. 1) to the word line WL (FIG. 1). The conductive layer 222 includes, for example, a conductive oxide. Note that the conductive layer 222 may include ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide. The conductive layer 222 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0073] 12, the conductive layer 222 may include a portion formed on the lower surfaces of the insulating layers 103 and 214, a portion formed on the upper surfaces of the insulating layers 103 and 214, and a portion formed on the side surface of the semiconductor layer 213 on the other side in the X direction (the insulating layer 202 side). In addition, insulating layers 223 and 224 made of silicon oxide (SiO2) or the like may be provided in the region surrounded by the conductive layer 222.

[0074] [Connection wiring area R CL1 Structure of As shown in Figure 5, the connection wiring area R CL1 Insulating layers 301 and 302 are provided in the memory cell region R, aligned in the Y direction. The insulating layer 301 is connected to the end of the insulating layer 101 in the Y direction. The insulating layer 302 is MC The insulating layer 301 is provided on the side of the insulating layer 202. The insulating layer 302 is connected to the Y-direction end of the insulating layer 202. The insulating layers 301 and 302 extend in the X and Z directions, and separate the multiple memory layers ML in the Y direction. The insulating layers 301 and 302 include, for example, silicon oxide (SiO2) or the like.

[0075] In addition, the connection wiring area R CL1 An insulating layer 304 made of silicon oxide (SiO2) or the like is provided in the region between the insulating layer 301 and the insulating layer 302. The insulating layer 304 extends in the Z direction, penetrating the multiple memory layers ML, as shown in FIG.

[0076] The memory layer ML includes a plurality of connection wiring parts 310 provided in correspondence with the plurality of conductive layers 120.

[0077] As shown in FIG. 9, the connection wiring portion 310 includes a semiconductor layer 311 such as silicon (Si) provided on the outer peripheral surface of the insulating layer 304, and a conductive layer 312 provided on the upper, lower and outer peripheral surfaces of the semiconductor layer 311.

[0078] 9, the side surfaces of the semiconductor layer 311 and the conductive layer 312 on both sides in the X direction may be formed along a circle centered on the central position of the insulating layer 304. Furthermore, the side surfaces of the semiconductor layer 311 and the conductive layer 312 on both sides in the Y direction may be formed linearly along the side surfaces of the insulating layers 301 and 302 in the Y direction.

[0079] One side surface of the conductive layer 312 in the X direction is connected to the conductive layer 120. The other side surface of the conductive layer 312 in the X direction is connected to the conductive layer 222. The conductive layer 312 has a function of electrically connecting the one electrode of the transistor TrRa (FIG. 1) to the word line WL (FIG. 1).

[0080] [Connection wiring area R CL2 Structure of As shown in Figure 5, the connection wiring area R CL2 Insulating layers 401 and 402 are provided in the memory cell region R. The insulating layer 402 is provided in the memory cell region R with respect to the insulating layer 401. MC The insulating layer 402 is connected to the Y-direction end of the insulating layer 202. The insulating layers 401 and 402 extend in the X and Z directions, and separate the multiple memory layers ML in the Y direction. The insulating layers 401 and 402 include, for example, silicon oxide (SiO2) or the like.

[0081] In addition, the connection wiring area R CL2 An insulating layer 404 made of silicon oxide (SiO2) or the like is provided in the region between the insulating layer 401 and the insulating layer 402. The insulating layer 404 extends in the Z direction, penetrating the multiple memory layers ML.

[0082] The memory layer ML includes a plurality of connection wiring parts 410 provided in correspondence with the plurality of conductive layers 120.

[0083] The connection wiring section 410 includes a semiconductor layer 411 made of silicon (Si) or the like provided on the outer peripheral surface of the insulating layer 404, and conductive layers 412 provided on the upper, lower and outer peripheral surfaces of the semiconductor layer 411.

[0084] 5, the side surfaces of the semiconductor layer 411 and the conductive layer 412 on both sides in the X direction may be formed along a circle centered on the central position of the insulating layer 404. Furthermore, the side surfaces of the semiconductor layer 411 and the conductive layer 412 on both sides in the Y direction may be formed linearly along the side surfaces of the insulating layers 401 and 402 in the Y direction.

[0085] One side surface of the conductive layer 412 in the X direction is connected to the conductive layer 221. The other side surface of the conductive layer 412 in the X direction is connected to the wiring region R LL The conductive layer 412 is connected to the conductive layer 501 in the middle. The conductive layer 412 has a function of electrically connecting the other electrode of the transistor TrRa (FIG. 1) to the layer selection line LL (FIG. 1).

[0086] [Wiring area R LL Structure of The memory layer ML includes a conductive layer 501 extending in the X direction. The conductive layer 501 functions as, for example, a layer selection line LL (FIG. 1). The conductive layers 501 are connected to a plurality of conductive layers 412 arranged in the X direction. The conductive layer 501 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0087] [Transistor area R TrRb Structure of As shown in Figure 6, the transistor region R TrRb are provided with a plurality of conductive layers 601 arranged in the X direction corresponding to the plurality of insulating layers 101, conductive layers 602 provided on the side surfaces of the conductive layers 601 in the X direction and the Y direction, and an insulating layer 202 provided between two conductive layers 601 adjacent to each other in the X direction (between two conductive layers 602 adjacent to each other in the X direction).

[0088] As shown in FIGS. 6 and 15 , the conductive layers 601 and 602 extend in the Y and Z directions and divide the memory layers ML in the X direction. The conductive layer 601 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 602 includes, for example, a conductive oxide. The conductive layer 602 may include ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide. The conductive layer 602 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals. The conductive layers 601 and 602 function, for example, as wiring NLL ( FIG. 1 ).

[0089] Also, the transistor region R TrRbIn the region between the conductive layers 601 and 602 and the insulating layer 202, a plurality of via wirings 204 are provided. TrRb In this figure, the conductive layers 601 and 602 and the insulating layer 202 are aligned with the via wirings 204 in the X direction.

[0090] The memory layer ML includes a portion of a plurality of transistor structures 610 corresponding to the plurality of conductive layers 120, a conductive layer 621 provided between the transistor structure 610 and the conductive layer 601, and a conductive layer 622 provided between the transistor structure 610 and the insulating layer 202.

[0091] 14, the transistor structure 610 includes a portion provided in the memory layer ML and a portion provided at a height position corresponding to the insulating layer 103. Of these, the portion provided in the memory layer ML includes, as shown in Fig. 13, a plurality of insulating layers 211 provided on the outer peripheral surfaces of a plurality of via wirings 204, and a semiconductor layer 613 provided on the outer peripheral surfaces of these plurality of insulating layers 211 and extending in the Y direction. Furthermore, as shown in Fig. 14, the portion provided at a height position corresponding to the insulating layer 103 includes insulating layers 614 provided on the upper and lower surfaces of the semiconductor layer 613, and conductive layers 615 provided on the upper and lower surfaces of the insulating layer 614.

[0092] The semiconductor layer 613, the insulating layer 614, and the conductive layer 615 are basically configured in the same manner as the semiconductor layer 213, the insulating layer 214, and the conductive layer 215 (FIGS. 11 and 12). However, the semiconductor layer 613, the insulating layer 614, and the conductive layer 615 function as the channel region, the gate insulating film, and the gate electrode of the transistor TrRb (FIG. 1), respectively. TrRb In the figure, the conductive layers 601 and 602 and the insulating layer 202 are aligned with the semiconductor layer 613, the insulating layer 614, and the conductive layer 615 in the X direction.

[0093] The conductive layer 621 is connected to one side surface of the semiconductor layer 613 in the X direction (the conductive layer 601 side). The conductive layer 621 is embedded in a region between two insulating layers 103 adjacent to each other in the Z direction. As shown in FIGS. 6 and 15, the conductive layer 621 is connected to the conductive layer 602 and functions to electrically connect the other electrode of the transistor TrRb (FIG. 1) to the wiring NLL (FIG. 1). The conductive layer 621 includes, for example, a conductive oxide. The conductive layer 621 may include ruthenium (Ru), iridium (Ir), or another metal instead of a conductive oxide. The conductive layer 621 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or another metal.

[0094] The conductive layer 622 is basically configured in the same manner as the conductive layer 222. However, the conductive layer 622 is connected to the semiconductor layer 613. In addition, as shown in FIG. 6, the conductive layer 622 is connected to the transistor region R TrRb From the connection wiring area R CL1 The electrode WL extends in the Y direction from the first electrode WL1 to the second electrode WL2, and serves to electrically connect the first electrode WL1 of the transistor TrRb (FIG. 1) to the word line WL (FIG. 1).

[0095] [Manufacturing method] 16 to 118 are schematic cross-sectional views for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Figures 16, 25, 27, 30, 32, 34, 37, 39, 42, 44, 46, 49, 51, 53, 55, 57, 59, 61, 103, 105, 107, 109, 111, 113, 115, and 117 show cross sections corresponding to Figure 7. Figures 17, 26, 28, 29, 31, 33, 35, 36, 38, 40, 43, 45, 47, 50, 52, 54, 56, 58, 60, 62, 104, 106, 108, 110, 112, 114, 116, and 118 show cross sections corresponding to Figure 8. Figures 18, 41, 48, and 69 show cross sections corresponding to Figure 6. Figures 19, 21, 23, 70, 74, 82, 86, 90, 94, 96, and 98 show cross sections corresponding to Figure 9. Figures 20, 22, 24, 71, 75, 83, 87, 91, 95, 97, 99, and 100 show cross sections corresponding to Figure 10. Figures 63, 67, 72, 76, 78, 80, 84, 88, 92, and 101 show cross sections corresponding to Figure 13. Figures 64, 65, 66, 68, 73, 77, 79, 81, 85, 89, 93, and 102 show cross sections corresponding to Figure 14.

[0096] In this manufacturing method, as shown in Fig. 17, for example, a plurality of insulating layers 103 and a plurality of sacrificial layers MLA are formed alternately. The sacrificial layers MLA include, for example, silicon nitride (Si3N4) or the like. This process is performed by, for example, CVD (Chemical Vapor Deposition) or the like.

[0097] Next, as shown in FIGS. 16 and 18, for example, insulating layers 115, 301, 302, and 402 are formed. Also, although not shown, insulating layer 401 (FIG. 5) is formed. In this step, for example, openings are formed at positions corresponding to insulating layers 115, 301, 302, 401, and 402. These openings extend in the X and Z directions and divide the multiple insulating layers 103 and multiple sacrificial layers MLA aligned in the Z direction in the Y direction. This step is performed by, for example, RIE. After the openings are formed, insulating layers 115, 301, 302, 401, and 402 are formed. This step is performed by, for example, CVD.

[0098] 19 and 20, an opening 304A is formed at a position corresponding to the insulating layer 304. The opening 304A extends in the Z direction as shown in Fig. 20, and penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction. This step is performed by, for example, RIE or the like.

[0099] Although not shown, the connection wiring portion 410 (FIG. 5) is formed in the same manner as the connection wiring portion 310. For example, in this step, an opening similar to the opening 304A is also formed in a position corresponding to the insulating layer 404 (FIG. 5). Similarly, in the following steps, the step performed at the position corresponding to the connection wiring portion 310 is also performed at the position corresponding to the connection wiring portion 410.

[0100] 21 and 22, an opening 310A is formed at a position corresponding to the connection wiring portion 310. Part of the upper surface and part of the lower surface of the insulating layer 103, part of the side surface of the sacrificial layer MLA in the X direction, and part of the side surfaces of the insulating layers 301 and 302 in the Y direction are exposed inside the opening 310A. In this step, for example, part of the sacrificial layer MLA is selectively removed through the opening 304A. This step is performed, for example, by wet etching or the like.

[0101] 23 and 24, a sacrificial layer 304B made of silicon (Si) or the like is formed inside the opening 310A and the opening 304A. This step is performed by, for example, CVD or the like.

[0102] 25 and 26, for example, an opening 104A is formed at a position corresponding to the via wiring 104. The opening 104A extends in the Z direction as shown in Fig. 26, and penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction. This step is performed by, for example, RIE or the like.

[0103] 27 and 28, an opening 111A is formed at a position corresponding to the semiconductor layer 111. Part of the upper surface and part of the lower surface of the insulating layer 103, part of the side surface of the sacrificial layer MLA in the X direction, and part of the side surface of the insulating layer 115 in the Y direction are exposed inside the opening 111A. In this step, for example, part of the sacrificial layer MLA is selectively removed through the opening 104A. This step is performed, for example, by wet etching or the like.

[0104] 29, a portion of the insulating layer 103 is removed. In this step, the width of the opening 111A in the Z direction is increased. This step is performed by, for example, wet etching or the like.

[0105] 30 and 31, an insulating layer 114A is formed on the inner circumferential surface of opening 104A, the inner circumferential surface of opening 111A, and the top and bottom surfaces of insulating layer 103. Insulating layer 114A includes silicon oxide (SiO2) containing boron (B), etc. This process is performed by, for example, CVD, etc.

[0106] 32 and 33, a conductive layer 113A and a sacrificial layer 111B made of silicon (Si) or the like are formed inside the openings 111A and 104A. The conductive layer 113A is formed on the upper and lower surfaces of the insulating layer 114A, the surface exposed to the opening 104A, the surface exposed to the opening 111A, and both side surfaces in the Y direction. The opening 111A is filled with the sacrificial layer 111B, but the opening 104A is not filled with the sacrificial layer 111B. This process is performed by, for example, CVD or the like.

[0107] 34 and 35, a portion of the sacrificial layer 111B is removed to expose a portion of the conductive layer 113A that is provided at a height position corresponding to the insulating layer 103. This step is performed by, for example, wet etching or the like.

[0108] 36, the conductive layer 113A is removed at a height corresponding to the insulating layer 103. This step is performed by, for example, wet etching.

[0109] Next, the sacrificial layer 111B is removed, for example, as shown in Figures 37 and 38. This step is performed by, for example, wet etching or the like.

[0110] 39 and 40, a sacrificial layer 104B made of silicon (Si) or the like is formed inside the opening 111A and the opening 104A. This step is performed by, for example, CVD or the like.

[0111] 41, an opening 101A is formed at a position corresponding to the insulating layer 101. The opening 101A extends in the Y and Z directions, penetrating the insulating layers 103 and the sacrificial layers MLA aligned in the Z direction, and dividing these structures in the X direction. This step is performed by, for example, RIE or the like.

[0112] Although not shown, the conductive layer 501 (FIG. 5) is formed in the same manner as the conductive layer 120. For example, in this step, an opening is also formed near the conductive layer 501 (FIG. 5). This opening extends in the X and Z directions, penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction, and divides these structures in the Y direction. Similarly, in the following steps, the step performed at the position corresponding to the conductive layer 120 is also performed at the position corresponding to the conductive layer 501.

[0113] Next, as shown in FIGS. 42 and 43, an opening 120A is formed at a position corresponding to the conductive layer 120. Part of the upper surface and part of the lower surface of the insulating layer 103, the X-direction side surface of the insulating layer 114A, and the X-direction side surface of the insulating layer 115 are exposed inside the opening 120A. In this step, for example, the sacrificial layer MLA is removed through the opening 101A. This step is performed by, for example, wet etching or the like.

[0114] 44 and 45, a portion of the insulating layer 114A provided on the surface of the conductive layer 113A exposed to the openings 120A and 101A in the X direction is removed through the openings 120A and 101A. This step is performed by, for example, wet etching or the like.

[0115] Next, as shown in FIGS. 46 and 47, for example, a conductive layer 120 is formed. In this step, a barrier conductive film 121 and a conductive film 122 are formed inside the openings 120A and 101A by a method such as CVD. In this step, the opening 120A is filled with the barrier conductive film 121 and the conductive film 122, but the opening 101A is not filled. Next, a portion of the barrier conductive film 121 and the conductive film 122 formed inside the opening 101A is removed by a method such as wet etching. Although not shown in the drawings, after this step is performed, an insulating layer 101 is formed inside the opening 101A.

[0116] 48 to 50, openings 102A are formed in positions corresponding to the conductive layers 102. The openings 102A extend in the Y and Z directions, penetrating the insulating layers 103 and sacrificial layers MLA arranged in the Z direction, and the insulating layer 115, to divide these structures in the X direction. This step is performed by, for example, RIE or the like.

[0117] 51 and 52, an opening 130A is formed in a position corresponding to the capacitor structure 130. In this step, the sacrificial layer MLA is removed through the opening 102A. This step is performed by, for example, wet etching.

[0118] 53 and 54, the insulating layer 114 is formed. In this step, for example, a portion of the insulating layer 114A provided on the side surface of the conductive layer 113A on the opening 102A side in the X direction is removed through the openings 102A and 130A. This step is performed by, for example, wet etching or the like.

[0119] 55 and 56, the conductive layer 113 is formed. In this step, for example, a portion of the conductive layer 113A provided on the side surface of the sacrificial layer 104B on the opening 102A side in the X direction is removed through the openings 102A and 130A. This step is performed by, for example, wet etching or the like.

[0120] Next, the sacrificial layer 104B is removed, for example, as shown in Figures 57 and 58. This step is performed by, for example, wet etching or the like.

[0121] Next, as shown in FIGS. 59 and 60, insulating layers 112 and 134 and a semiconductor layer 111C are formed inside openings 111A, 104A, 130A, and 102A. Insulating layers 112 and 134 are formed on the surface of conductive layer 113 exposed in opening 111A, part of the upper surface, part of the lower surface, and the surface exposed in opening 102A of insulating layer 103, the surface exposed in opening 104A of insulating layer 114, and part of the side surface of insulating layer 115 in the Y direction. Furthermore, opening 111A is filled with semiconductor layer 111C, while openings 104A, 130A, and 102A are not filled with semiconductor layer 111C. This process is performed by, for example, CVD or the like.

[0122] 61 and 62, a sacrificial layer 104C made of silicon (Si) or the like is formed inside the opening 104A. Also, a sacrificial layer 102B made of silicon (Si) or the like is formed inside the openings 102A and 130A. This process is performed by, for example, CVD or the like.

[0123] Next, as shown in Fig. 63 and Fig. 64, for example, an opening 204A is formed at a position corresponding to the via wiring 204. The opening 204A extends in the Z direction as shown in Fig. 64, and penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction. This step is performed by, for example, RIE or the like.

[0124] Next, as shown in FIG. 65, an opening 615A is formed at a position corresponding to the conductive layer 615. Part of the upper surface and part of the lower surface of the sacrificial layer MLA are exposed inside the opening 615A. In this step, for example, a part of the insulating layer 103 is selectively removed through the opening 204A. This step is performed by, for example, wet etching or the like.

[0125] Although not shown, the conductive layer 215, the insulating layer 214, and the semiconductor layer 213 (FIG. 12) are formed in the same manner as the conductive layer 615, the insulating layer 614, and the semiconductor layer 613, respectively. For example, in this step, an opening is also formed in a position corresponding to the conductive layer 215 (FIG. 12). In this step, for example, a portion of the insulating layer 103 is selectively removed through the opening 204A. Similarly, in the following steps, the steps performed in the positions corresponding to the conductive layer 615, the insulating layer 614, and the semiconductor layer 613 are also performed in the positions corresponding to the conductive layer 215, the insulating layer 214, and the semiconductor layer 213.

[0126] Next, a portion of the sacrificial layer MLA is removed, for example, as shown in Fig. 66. In this step, the width of the opening 615A in the Z direction is increased. This step is performed by, for example, wet etching or the like.

[0127] 67 and 68, the insulating layers 211 and 614, the conductive layer 615, and the via wiring 204 are formed inside the openings 615A and 204A. This process is performed by, for example, CVD or the like.

[0128] 69 to 73, openings 601A and 202A are formed at positions corresponding to the conductive layer 601 and the insulating layer 202. Although not shown, an opening similar to opening 601A is also formed at a position corresponding to the insulating layer 201 (FIG. 5). The openings 601A and 202A and the openings corresponding to the insulating layer 201 (FIG. 5) extend in the Y and Z directions, penetrating the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction, and dividing these structures in the X direction. This process is performed by, for example, RIE or the like.

[0129] Next, as shown in FIGS. 74 to 77, openings 222A, 621A, 622A, and 613A are formed at positions corresponding to the conductive layers 222, 621, and 622 and the semiconductor layer 613. Portions of the upper and lower surfaces of the insulating layer 103 and portions of the side surfaces of the insulating layers 302 and 402 on one side in the Y direction are exposed inside the openings 222A and 622A. Portions of the upper and lower surfaces of the insulating layer 103 and portions of the side surfaces of the insulating layer 301 on one side in the Y direction are exposed inside the opening 621A. Portions of the upper and lower surfaces of the insulating layer 614, the outer peripheral surface of the insulating layer 211, and portions of the side surfaces of the insulating layers 301 and 402 on one side in the Y direction are exposed inside the opening 613A. In this step, for example, portions of the sacrificial layer MLA are selectively removed through the openings 222A, 621A, and 622A. This step is performed by, for example, wet etching.

[0130] 78 and 79, a semiconductor layer 613B is formed inside the openings 613A, 622A, 202A, 621A, and 601A. The opening 613A is filled with the semiconductor layer 613B, and the openings 622A, 202A, 621A, and 601A are not filled with the semiconductor layer 613B. This step is performed by, for example, CVD or the like.

[0131] Next, as shown in Fig. 80 and Fig. 81, for example, the semiconductor layer 613 is formed. In this step, a part of the semiconductor layer 613B is removed by a method such as wet etching. Specifically, of the semiconductor layer 613B, the part formed inside the opening 613A is left, and the other part is removed.

[0132] Next, the upper part of the opening 601A is closed with an insulating layer or the like (not shown).

[0133] 82 and 83, a conductive layer 222B, an insulating layer 223A, and a sacrificial layer 224A are formed inside the openings 222A and 202A. Furthermore, as shown in FIGS. 84 and 85, a conductive layer 622B, an insulating layer 223A, and a sacrificial layer 224A are formed inside the openings 622A and 202A. The conductive layers 222B and 622B are formed on a part of the upper surface, a part of the lower surface, and the surface exposed to the opening 202A of the insulating layer 103, a part of the upper surface and a part of the lower surface of the insulating layers 214 and 614, the outer peripheral surfaces of the semiconductor layers 213 and 613, one side surface of the insulating layer 301 in the X direction, and one side surface of the insulating layers 302 and 402 in the Y direction. The openings 222A and 622A are filled with the insulating layer 223A and the sacrificial layer 224A, and the opening 202A is not filled with the insulating layer 223A and the sacrificial layer 224A. This step is performed by, for example, ALD, CVD, or the like.

[0134] In this step, a conductive layer corresponding to the conductive layer 221, an insulating layer 223A, and a sacrificial layer 224A are formed inside openings (not shown) corresponding to the conductive layer 221 (FIGS. 11 and 12) and the insulating layer 201 (FIG. 5). The conductive layer (not shown) corresponding to the conductive layer 221 is formed on a part of the upper surface, a part of the lower surface, and a surface exposed in an opening (not shown) corresponding to the insulating layer 201 of the insulating layer 103, a part of the upper surface and a part of the lower surface of the insulating layer 214, the outer peripheral surface of the semiconductor layer 213, one side surface of the insulating layer 402 in the X direction, and one side surface of the insulating layers 301 and 401 in the Y direction. The opening (not shown) corresponding to the conductive layer 221 is filled with the insulating layer 223A and the sacrificial layer 224A, and the opening (not shown) corresponding to the insulating layer 201 is not filled with the insulating layer 223A and the sacrificial layer 224A.

[0135] Next, as shown in FIGS. 86 to 89, conductive layers 222 and 622 and an insulating layer 223 are formed. Furthermore, a conductive layer 221 (FIGS. 11 and 12) is formed. In this step, of the conductive layers 222B and 622B, the conductive layer (not shown) corresponding to the conductive layer 221, the insulating layer 223A, and the sacrificial layer 224A, portions of the insulating layer 103 that are formed on the exposed surface of the opening (not shown) corresponding to the opening 202A and the insulating layer 201 (FIG. 5) are removed, exposing the insulating layer 103 to the opening 202A. As a result, the conductive layers 222B and 622B, the conductive layer (not shown) corresponding to the conductive layer 221, and the insulating layer 223A are divided in the Z direction, and the conductive layers 222, 622, and 221 and the insulating layer 223 are formed. This step is performed by, for example, wet etching or the like.

[0136] Next, as shown in Figures 90 to 93, the sacrificial layer 224A is removed. This step is performed by, for example, wet etching or the like.

[0137] Next, the sacrificial layer 304B is removed as shown in Figures 94 and 95. This step is performed by, for example, wet etching.

[0138] 96 and 97, for example, a conductive layer 312B and a semiconductor layer 311B are formed inside the openings 311A ​​and 304A. The conductive layer 312B is formed on a part of the upper surface, a part of the lower surface, and the surface exposed in the opening 304A of the insulating layer 103, one side surface in the X direction of the conductive layer 222, and one side surface in the X direction of the conductive layer 120. The opening 311A ​​is filled with the semiconductor layer 311B, and the opening 304A is not filled with the semiconductor layer 311B. This step is performed by, for example, CVD or the like.

[0139] Next, as shown in FIGS. 98 and 99, the semiconductor layer 311 is formed. In this step, a portion of the semiconductor layer 311B formed on the inner circumferential surface of the insulating layer 103 toward the opening 304A is removed to expose a portion of the conductive layer 312B in the opening 304A. This causes the semiconductor layer 311B to be divided in the Z direction, forming a plurality of semiconductor layers 311 aligned in the Z direction. This step is performed by, for example, wet etching or the like.

[0140] Next, as shown in FIG. 100, a conductive layer 312 is formed. In this step, a portion of the conductive layer 312B formed on the inner circumferential surface of the insulating layer 103 toward the opening 304A is removed to expose the insulating layer 103 in the opening 304A. This causes the conductive layer 312B to be divided in the Z direction, forming a plurality of conductive layers 312 aligned in the Z direction. This step is performed by, for example, wet etching or the like.

[0141] 9 to 12, 101 and 102, an insulating layer 224 is formed inside openings 222A, 622A and openings (not shown) corresponding to conductive layer 221, and an insulating layer 202 is formed inside opening 202A. Also, an insulating layer 304 is formed inside opening 304A. This process is performed by, for example, CVD or the like.

[0142] 15, conductive layers 621, 602, and 601 are formed inside the openings 621A and 601A. This process is performed by, for example, ALD and CVD.

[0143] Next, the sacrificial layer 102B is removed, for example, as shown in Figures 103 and 104. This step is performed by, for example, wet etching or the like.

[0144] 105 and 106, the semiconductor layer 111 is formed. In this step, a portion of the semiconductor layer 111C formed on the surface of the insulating layer 134 exposed to the openings 130A and 102A is removed to divide the semiconductor layer 111C in the Y and Z directions. This step is performed by, for example, wet etching or the like.

[0145] 107 and 108, a conductive layer 133A, an insulating layer 130B, and a sacrificial layer 130C are formed on one side surface in the X direction of the semiconductor layer 111 (the side surface on the opening 102A side) and on the exposed surfaces of the insulating layer 134 in the openings 130A and 102A. This process is performed by, for example, ALD, CVD, or the like.

[0146] 109 and 110, a portion of the sacrificial layer 130C is removed through the opening 102A. In this step, for example, portions of the insulating layer 130B corresponding to the side surfaces of the insulating layer 115 and the insulating layer 103 in the X direction are exposed. This step is performed by, for example, wet etching or the like.

[0147] 111 and 112, a portion of the insulating layer 130B is removed through the opening 102A. In this step, for example, a portion of the conductive layer 133A corresponding to the side surfaces of the insulating layer 115 and the insulating layer 103 in the X direction is exposed. This step is performed by, for example, wet etching or the like.

[0148] Next, as shown in Fig. 113 and Fig. 114, a conductive layer 133 is formed. In this step, for example, portions of the conductive layer 133A provided on the side surfaces of the insulating layer 115 and the insulating layer 103 in the X direction are removed, and the conductive layer 133A is divided in the Y direction and the Z direction. This step is performed by, for example, wet etching or the like.

[0149] Next, the sacrificial layer 130C and the insulating layer 130B are removed through the opening 102A as shown in Figures 115 and 116. This step is performed by, for example, wet etching or the like.

[0150] 117 and 118, the capacitor structure 130 and the conductive layer 102 are formed. In this step, the insulating layer 132 and the conductive layers 131 and 102 are formed on, for example, the upper surface, the lower surface, one side surface in the X direction (the side surface on the opening 102A side), and both side surfaces in the Y direction of the conductive layer 133, and the X direction side surface of the insulating layer 134. This step is performed by, for example, CVD or the like.

[0151] Thereafter, the sacrificial layer 104C is removed and via wirings 104 (FIGS. 7 and 8) and the like are formed, thereby completing the manufacture of the semiconductor memory device according to the first embodiment.

[0152] [effect] As explained with reference to FIG. 1, in the semiconductor memory device according to the first embodiment, the gate voltage of the transistors TrRa and TrRb is common among the multiple memory layers ML. With this configuration, as explained with reference to FIG. 12, the conductive layer 215 functioning as the gate electrodes of the transistors TrRa and TrRb can be provided at a height position corresponding to the insulating layer 103, making it possible to use it as a common gate electrode for two transistors TrRa and TrRb adjacent in the Z direction. This makes it possible to thicken the gate insulating films of the transistors TrRa and TrRb without hindering the high integration of the semiconductor memory device. Therefore, the voltage V as explained with reference to FIG. ON ´, voltage V ON , and the voltage V applied to the selected word line WL in the read operation is set to a voltage sufficiently larger than ON This makes it possible to speed up the transfer of data.

[0153] Here, in order to connect the plurality of layer select lines LL to the peripheral circuit, it is conceivable to provide terrace portions on the plurality of conductive layers 501 (FIG. 5) and connect via contact electrodes to these terrace portions. The terrace portions are, for example, portions of the upper surface of the conductive layer 501 that do not overlap with other conductive layers when viewed from above. The memory cell array MCA requires the same number of terrace portions as the number of memory layers ML aligned in the Z direction.

[0154] 2, two transistors TrRa and TrRb are connected to the word line WL. MC 5 and 6, the transistor regions R TrRa and wiring area R LL However, when such a configuration is adopted, the memory cell region R MC In contrast to (FIGS. 5 and 6), it becomes necessary to provide terrace portions on one side and the other side in the Y direction, the number of which is equal to the number of memory layers ML arranged in the Z direction, which may hinder reduction in the circuit area.

[0155] Therefore, in this embodiment, the memory cell region R MC In the region on the other side in the Y direction, a plurality of conductive layers 621 arranged in the Z direction are commonly connected to the conductive layers 601 and 602 extending in the Z direction, and a wiring region R LL In this configuration, the memory cell region R MC On the other hand, the terrace portion can be omitted in the region on the other side in the Y direction, thereby reducing the circuit area of ​​the memory cell array MCA.

[0156] Furthermore, when a plurality of conductive layers 621 arranged in the Z direction are commonly connected to a conductive layer extending in the Z direction, for example, in the memory cell region R MC The wiring area R on the other side of the Y direction LL It is also conceivable to provide a conductive layer extending in the Z direction at a position corresponding to the semiconductor layer 613, the insulating layer 614, and the conductive layer 615. However, in this embodiment, the conductive layers 601 and 602 are provided at positions aligned with the semiconductor layer 613, the insulating layer 614, and the conductive layer 615 in the X direction. With this configuration, there is no need to provide a separate region for the conductive layers 601 and 602, and therefore it is possible to further reduce the circuit area of ​​the memory cell array MCA.

[0157] In the transistor structure 110 according to this embodiment, the conductive layer 113 faces the upper surface, the lower surface, and both side surfaces in the Y direction of the semiconductor layer 111.

[0158] In such a configuration, it is possible to suppress interference of electric fields between the plurality of semiconductor layers 111 arranged in the Z direction. Therefore, even when the memory cell array MCA is highly integrated in the Z direction, it is possible to provide a semiconductor memory device that can control the semiconductor layers 111 to be in an ON state or an OFF state and that operates appropriately.

[0159] Furthermore, when the transistor TrC is turned on, channels are formed on the top surface, bottom surface, and both side surfaces in the Y direction of the semiconductor layer 111. This allows the ON current of the transistor TrC to be relatively large, thereby enabling faster and more stable operation.

[0160] Furthermore, in this embodiment, the conductive layer 120 functioning as the word line WL is provided on the opposite side of the plate line PL with respect to the transistor structure 110, and is provided at a position that does not overlap with the transistor structure 110 when viewed from the Z direction. Therefore, the conductive layer 120 and the transistor structure 110 can be formed independently, and can be manufactured relatively easily. Furthermore, it is possible to reduce the width of the memory layer ML in the Z direction while setting the wiring resistance of the conductive layer 120 to a relatively small value.

[0161] [Second embodiment] [structure] Next, a semiconductor memory device according to the second embodiment will be described with reference to Fig. 119. Fig. 119 is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the second embodiment.

[0162] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0163] However, as described with reference to FIGS. 5 and 6, in the first embodiment, the transistor region R corresponding to the transistor TrRa TrRa is the memory cell area R MC , which is provided on one side in the Y direction with respect to the transistor region R corresponding to the transistor TrRb. TrRb is the memory cell area R MC The second electrode 11 is provided on the other side in the Y direction.

[0164] On the other hand, as shown in FIG. 119, in the second embodiment, the transistor region R corresponding to the transistor TrRa TrRa ´ is the memory cell area R MC , which is provided on one side in the Y direction with respect to the transistor region R corresponding to the transistor TrRb. TrRb ´ is the memory cell region R MC and transistor area R TrRa It is placed between

[0165] Transistor region RTrRa ´,R TrRb Between the insulating layers 701, a plurality of insulating layers 701 are provided lined up in the X direction corresponding to the insulating layers 101. The insulating layers 701 extend in the X and Z directions and separate the plurality of memory layers ML in the Y direction. The insulating layers 701 include, for example, silicon oxide (SiO2) or the like.

[0166] Transistor region R TrRa ´,R TrRb ´ is basically the transistor region R TrRa ,R TrRb However, the transistor region R TrRa ´,R TrRb ', a conductive layer 722 is provided instead of the conductive layers 222 and 622. The conductive layer 722 is basically configured in the same manner as the conductive layers 222 and 622. However, the conductive layer 722 is provided in the transistor region R TrRa ´ to transistor region R TrRb ´ through the connection wiring area R CL1 and has the function of electrically connecting the one electrode of the transistor TrRa (FIG. 1), the one electrode of the transistor TrRb (FIG. 1), and the word line WL (FIG. 1).

[0167] According to this configuration, a connection wiring region R for connecting the configurations between the respective regions is provided. CL1 It is possible to further reduce the circuit area of ​​the memory cell array MCA by reducing the number of memory cells.

[0168] [Other embodiments] The semiconductor memory devices according to the first and second embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific configurations and the like can be adjusted as appropriate.

[0169] For example, in the semiconductor memory devices according to the first and second embodiments, the via interconnects 104 functioning as bit lines contain a conductive oxide such as indium tin oxide (ITO). However, such conductive oxide may be included in the transistor structure 110, rather than in the via interconnects 104 extending in the Z direction. Furthermore, the via interconnects 104 and the transistor structure 110 may contain other materials.

[0170] Furthermore, in the semiconductor memory devices according to the first and second embodiments, the conductive layers 113, 215, 615 functioning as the gate electrodes of the transistors TrC, TrRa, TrRb may face only one of the upper and lower surfaces of the semiconductor layers 111, 213, 613 functioning as the channel regions of the transistors TrC, TrRa, TrRb.

[0171] Furthermore, in the semiconductor memory devices according to the first and second embodiments, the semiconductor layers 111, 213, 613 functioning as channel regions of the transistors TrC, TrRa, TrRb may face the upper and lower surfaces of the conductive layers 113, 215, 615 functioning as gate electrodes of the transistors TrC, TrRa, TrRb.

[0172] In the above description, an example has been described in which a capacitor CpC is used as the memory unit connected to the transistor structure 110. However, the memory unit does not have to be a capacitor CpC. For example, the memory unit may include a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other material, and may record data using the properties of these materials. For example, in any of the structures described above, the insulating layer between the electrodes that forms the capacitor CpC may include one of these materials.

[0173] The manufacturing methods of the semiconductor memory devices according to the first and second embodiments can also be adjusted as appropriate. For example, the order of any two of the above-described steps can be reversed, or any two of the above-described steps can be performed simultaneously.

[0174] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0175] Sub...semiconductor substrate, ML...memory layer, BL...bit line, WL...word line, PL...plate line, TrC, TrRa, TrRb...transistor, CpC...capacitor, 101...insulating layer, 102...conductive layer, 104,204...via wiring, 110,210,610...transistor structure, 111,213,613...semiconductor layer, 112,214,614...insulating layer, 113,215,615...conductive layer, 120,501...conductive layer, 130...capacitor structure.

Claims

1. A substrate; a first via wiring extending in a first direction intersecting the surface of the substrate; a plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via wiring; a memory section arranged in the first direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes aligned in the first direction and facing the plurality of first semiconductor layers; a plurality of first wirings arranged in the first direction, extending in a second direction intersecting the first direction, and electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings; a plurality of second gate electrodes aligned in the first direction and facing the plurality of second semiconductor layers; second via wirings extending in the first direction and electrically connected to the plurality of second gate electrodes; second wirings extending in the first direction, electrically connected to the second semiconductor layers, and aligned with the second semiconductor layers in a third direction intersecting the first direction and the second direction; A semiconductor memory device comprising:

2. Among the plurality of second gate electrodes, two adjacent ones in the first direction have ends in the second direction and the third direction spaced apart from each other in the first direction.

2. The semiconductor memory device according to claim 1.

3. a plurality of insulating layers arranged alternately with the plurality of first semiconductor layers in the first direction; The second gate electrodes are provided at positions in the first direction corresponding to the insulating layers, respectively.

2. The semiconductor memory device according to claim 1.

4. One of the plurality of second gate electrodes is provided between two second semiconductor layers adjacent to each other in the first direction among the plurality of second semiconductor layers, and faces these two second semiconductor layers.

2. The semiconductor memory device according to claim 1.

5. The second semiconductor layer contains at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

2. The semiconductor memory device according to claim 1.

6. The first gate electrode faces one and the other surfaces of the first semiconductor layer in the first direction and one and the other surfaces of the first semiconductor layer in the second direction.

2. The semiconductor memory device according to claim 1.

7. The memory unit a first electrode electrically connected to the first semiconductor layer; a second electrode facing the first electrode; an insulating layer provided between the first electrode and the second electrode; 2. The semiconductor memory device according to claim 1, comprising:

8. The first semiconductor layer contains at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

2. The semiconductor memory device according to claim 1.

9. a plurality of third semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings; a plurality of third gate electrodes aligned in the first direction and facing the plurality of third semiconductor layers; third via wirings extending in the first direction and electrically connected to the plurality of third gate electrodes; a plurality of third wirings aligned in the first direction, extending in the third direction, and electrically connected to the plurality of third semiconductor layers; 2. The semiconductor memory device according to claim 1, comprising:

10. The position of the first via wiring in the second direction is between the position of the second via wiring in the second direction and the position of the third via wiring in the second direction.

10. The semiconductor memory device according to claim 9.

11. The position of the second via wiring in the second direction is between the position of the first via wiring in the second direction and the position of the third via wiring in the second direction.

10. The semiconductor memory device according to claim 9.

12. Among the plurality of third gate electrodes, two adjacent ones in the first direction have ends in the second direction and the third direction spaced apart from each other in the first direction.

10. The semiconductor memory device according to claim 9.

13. a plurality of insulating layers arranged alternately with the plurality of first semiconductor layers in the first direction; The third gate electrodes are provided at positions in the first direction corresponding to the insulating layers, respectively.

10. The semiconductor memory device according to claim 9.

14. One of the plurality of third gate electrodes is provided between two third semiconductor layers adjacent to each other in the first direction among the plurality of third semiconductor layers, and faces these two third semiconductor layers.

10. The semiconductor memory device according to claim 9.

15. The third semiconductor layer contains at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

10. The semiconductor memory device according to claim 9.

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