Semiconductor memory device

Abstract

To provide a semiconductor memory device capable of reducing man-hours in manufacturing and reducing a chip area.SOLUTION: A semiconductor memory device 3 according to an embodiment includes: a wiring layer 21 having a lead-out region HA and a memory region MA arranged in a X direction when viewed in a Z direction; a plurality of wiring layers 23 provided above the wiring layer 21 so as to be separated from each other in the Z direction and including a plurality of first terrace parts in the lead-out region HA; a plurality of wiring layers 24 which are provided above the plurality of wiring layers 23 so as to be separated from each other in the Z direction, and which include the plurality of first terrace parts and a plurality of second terrace parts aligned in the Z direction and having a portion overlapping with the plurality of first terrace parts in the extraction region HA; and a contact CC that extends in the Z direction at a position where the plurality of first terrace parts and the plurality of second terrace parts of the lead-out region HA overlap each other, has one end positioned between the wiring layer 21 and the plurality of wiring layers 23, passes through one of the plurality of second terrace parts, and is electrically connected to one of the plurality of first terrace parts.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is a well-known semiconductor memory device capable of storing data nonvolatilely. NAND flash memory often employs a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 415794 [Patent Document 2] Japanese Patent Publication No. 2022-126320 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device is provided that can reduce the number of manufacturing steps and the chip area. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a first wiring layer having a first region and a second region aligned in a second direction intersecting the first direction when viewed in a first direction; a plurality of second wiring layers provided above the first wiring layer and spaced apart from one another in the first direction, each of the second wiring layers having a first staircase region in the first region, the first staircase region being such that the second wiring layers do not overlap with the second wiring layer above them in the first direction; and the second staircase regions provided above the plurality of second wiring layers and spaced apart from one another in the first direction, aligned with the first staircase region in the first direction, and having a portion overlapping the first staircase region. a plurality of third wiring layers, each of the plurality of third wiring layers having a plurality of second terrace portions arranged in a second staircase region so as not to overlap with an upper third wiring layer in a first direction, a first memory pillar extending in the first direction in the second region, one end of which contacts the first wiring layer and passes through the plurality of second wiring layers and the plurality of third wiring layers; and a first contact extending in the first direction at a position in the first region where the first staircase region and the second staircase region overlap, one end of which is located between the first wiring layer and the plurality of second wiring layers, passing through one of the plurality of second terrace portions and electrically connected to one of the plurality of first terrace portions. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a memory region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 5] 5 is a cross-sectional view taken along line VV in FIG. 4, showing an example of a cross-sectional structure in a memory region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 6]6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of a cross-sectional structure of a memory pillar included in the semiconductor memory device according to the first embodiment. [Figure 7] FIG. 2 is a schematic diagram showing an example of a cross-sectional structure of stacked wiring in a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 8] 3 is a cross-sectional view showing an example of a cross-sectional structure of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 9] 9 is an enlarged view of region IX in FIG. 8, showing an example of a cross-sectional structure in a lead-out region of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 10] FIG. 2 is a plan view showing an example of a planar layout of upper stacked wirings in a lead-out region of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 11] 10 is a plan view showing an example of a plane taken along line XI-XI in FIG. 8 in the lead-out region of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 12] 6 is a flowchart showing an example of a method for manufacturing a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 13] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 14] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 15] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 16] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 17] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 18]3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 19] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 20] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 21] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 22] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 23] FIG. 2 is a plan view showing an example of a planar layout during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 24] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 25] FIG. 2 is a plan view showing an example of a planar layout during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 26] 3 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. [Figure 27] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a lead-out region of a memory cell array included in a semiconductor memory device according to a first modification of the first embodiment. [Figure 28] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a lead-out region of a memory cell array included in a semiconductor memory device according to a second modification of the first embodiment. [Figure 29] FIG. 11 is a schematic view showing an example of a cross-sectional structure of stacked wiring in a lead-out region of a memory cell array included in a semiconductor memory device according to a third modification of the first embodiment. [Figure 30]FIG. 10 is a plan view showing an example of a planar layout of upper multilayer wirings in a lead-out region of a memory cell array included in a semiconductor memory device according to a fourth modification of the first embodiment. [Figure 31] FIG. 10 is a plan view showing an example of a planar layout of a memory region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 32] FIG. 10 is a schematic diagram showing an example of a cross-sectional structure of stacked wiring in a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 33] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 34] 34 is an enlarged view of a region XXXIV in FIG. 33, showing an example of a cross-sectional structure in a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 35] FIG. 10 is a plan view showing an example of a planar layout of upper stacked wirings in a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 36] FIG. 10 is a plan view showing an example of a planar layout of lower multilayer wiring in a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 37] 37 is a plan view showing an example of a plane taken along line XXXVII-XXXVII in FIG. 33 in a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 38] 10 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 39] 10 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 40] 10 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 41] 10 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 42] 10 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 43] 10 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 44] 10 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 45] 10 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 46] FIG. 11 is a plan view showing an example of a planar layout of upper multilayer wirings in a lead-out region of a memory cell array included in a semiconductor memory device according to a first modification of the second embodiment. [Figure 47] FIG. 10 is a plan view showing an example of a planar layout of upper multilayer wirings in a lead-out region of a memory cell array included in a semiconductor memory device according to a second modification of the second embodiment. [Figure 48] FIG. 11 is a schematic view showing an example of a cross-sectional structure of stacked wiring in a lead-out region of a memory cell array included in a semiconductor memory device according to a third modification of the second embodiment. [Figure 49] FIG. 11 is a plan view showing an example of a planar layout of upper multilayer wirings in a lead-out region of a memory cell array included in a semiconductor memory device according to a fourth modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic, and the dimensions and proportions of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0008] In the following description, when a first element is "connected" to another second element, it includes the first element being indirectly connected to the second element via an intermediate element that is always or selectively conductive, or directly connected to the second element without an intermediate element.

[0009] 1. First embodiment 1.1 Configuration 1.1.1 Memory System A semiconductor memory device according to the first embodiment will be described. FIG. 1 is a block diagram showing an example of the configuration of a memory system 1 according to the first embodiment. The memory system 1 is a memory device configured to be connected to an external host device (not shown). The memory system 1 is, for example, a storage device such as an SD TM The memory system 1 includes a memory controller 2 and a semiconductor memory device 3. The memory system 1 may be a memory card such as a card, a Universal Flash Storage (UFS), or a Solid State Drive (SSD).

[0010] The memory controller 2 is configured by an integrated circuit such as an SoC (System on a Chip). The memory controller 2 controls the semiconductor memory device 3 based on a request from an external host device. Specifically, the memory controller 2 writes data requested to be written by the external host device to the semiconductor memory device 3. In addition, the memory controller 2 reads data requested to be read by the external host device from the semiconductor memory device 3 and outputs the data to the external host device.

[0011] The semiconductor memory device 3 is, for example, a NAND flash memory that can store data in a nonvolatile manner.

[0012] The communication between the memory controller 2 and the semiconductor memory device 3 complies with, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0013] 1.1.2 Semiconductor memory devices Continuing with the description of the internal configuration of the semiconductor memory device 3 according to the first embodiment, with reference to the block diagram shown in Fig. 1, the semiconductor memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0014] The memory cell array 10 is a set of memory cell transistors and a collection of components connected to the memory cell transistors. The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). A block BLK is a collection of a plurality of memory cell transistors capable of storing data in a non-volatile manner. The block BLK is used, for example, as an erase unit when erasing data stored in the memory cell transistors. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with, for example, a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The command register 11 stores the command CMD that the semiconductor memory device 3 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute a read operation, a write operation, an erase operation, or the like.

[0016] The address register 12 stores address information ADD that the semiconductor memory device 3 receives from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select a block BLK, a word line, and a bit line, respectively.

[0017] The sequencer 13 controls the overall operation of the semiconductor memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD stored in the command register 11, and executes a read operation, a write operation, an erase operation, etc.

[0018] The driver module 14 generates a plurality of voltages of different magnitudes to be used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a word line selected based on, for example, a page address PA stored in the address register 12.

[0019] The row decoder module 15 selects a corresponding block BLK in the memory cell array 10 based on the block address BA stored in the address register 12. Then, the row decoder module 15 transfers, for example, the voltage of the signal line applied by the driver module 14 to a selected word line in the selected block BLK.

[0020] In a write operation, the sense amplifier module 16 applies a desired voltage to each bit line in accordance with the write data DAT received from the memory controller 2. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell transistor based on the magnitude of the voltage on the bit line, and transfers the determination result to the memory controller 2 as read data DAT.

[0021] 1.1.3 Memory cell array circuit configuration 2 is a circuit diagram showing an example of a circuit configuration of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. Fig. 2 shows a block BLK0. The block BLK0 includes, for example, four string units SU0 to SU3.

[0022] Each string unit SU includes a plurality of NAND strings NS associated with respective bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes, for example, 16 memory cell transistors MT0 to MT15 and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data in a nonvolatile manner based on the amount of charge in the charge storage film. Each of the select transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0023] In each NAND string NS, the memory cell transistors MT0 to MT15 are connected in series in this order. The drain of the select transistor ST1 is connected to the associated bit line BL, and the source of the select transistor ST1 is connected to the drain of the memory cell transistor MT15. The drain of the select transistor ST2 is connected to the source of the memory cell transistor MT0, and the source of the select transistor ST2 is connected to the source line SL.

[0024] The control gates of memory cell transistors MT0 to MT15 in the same block BLK are connected to word lines WL0 to WL15, respectively. The gates of select transistors ST1 in string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The gate of select transistor ST2 in the same block BLK is connected to select gate line SGS.

[0025] A different column address CA is assigned to each of the bit lines BL0 to BLm. Each bit line BL is shared by NAND strings NS that are assigned the same column address CA among multiple blocks BLK. Each of the word lines WL0 to WL15 is provided for each block BLK. The source line SL is shared, for example, among multiple blocks BLK.

[0026] A collection of memory cell transistors MT connected to a common word line WL within one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0027] The circuit configuration of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment is not limited to the above description. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0028] 1.1.4 Memory Cell Array Structure An example of the structure of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment will be described below. A three-dimensional Cartesian coordinate system is used in the drawings referred to below. The X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate 20 used to form the semiconductor memory device 3. The Z direction on the side of the semiconductor substrate 20 where the semiconductor circuit is formed is defined as the upward direction, and the opposite direction to the upward direction is defined as the downward direction. Hatching is added appropriately in plan views to improve the visibility of the drawings. Hatching added in plan views does not necessarily relate to the materials or properties of the components to which hatching is added. In cross-sectional views, illustrations of components are omitted appropriately to improve the visibility of the drawings.

[0029] 1.1.4.1 Planar Layout Overview FIG. 3 is a plan view showing an example of a planar layout of a memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. FIG. 3 shows areas corresponding to four blocks BLK0 to BLK3. Serial numbers at the end for distinguishing the blocks BLK are assigned in ascending order from the top of the page. In the memory cell array 10, for example, the layout shown in FIG. 3 is repeatedly arranged in the Y direction. As shown in FIG. 3, the memory cell array 10 includes a plurality of members SLT and a plurality of members SHE. The planar layout of the memory cell array 10 is divided, for example, in the X direction, into a memory region MA and a lead-out region HA.

[0030] The memory area MA is an area including a plurality of NAND strings NS. The lead-out area HA is an area used for connection between the row decoder module 15 and stacked wiring formed by stacking a plurality of wiring layers (e.g., word lines WL0 to WL15 and select gate lines SGS and SGD) spaced apart from each other in the Z direction.

[0031] The multiple members SLT each extend along the X direction and are aligned in the Y direction. Each member SLT crosses the memory area MA and the lead-out area HA in the X direction in the boundary area between adjacent blocks BLK. In other words, each area partitioned by the member SLT corresponds to one block BLK in the memory cell array 10. Each member SLT has a structure in which, for example, an insulator or a plate-shaped contact is embedded. Each member SLT separates adjacent stacked wirings via the member SLT.

[0032] The plurality of members SHE are arranged in the memory region MA and part of the lead-out region HA. The plurality of members SHE are each arranged across the memory region MA in the X direction and aligned in the Y direction. The right end of each member SHE is included in the lead-out region HA. For example, three members SHE are arranged between adjacent members SLT in the Y direction. Each of the regions separated by the members SLT and SHE in the memory region MA corresponds to one string unit SU in the memory cell array 10. Each member SHE has a structure in which an insulator is embedded, for example. Each member SHE separates adjacent select gate lines SGD via the member SHE.

[0033] The planar layout of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment is not limited to the layout described above. For example, the number of components SHE arranged between adjacent components SLT can be designed to be any number. The number of string units SU formed between adjacent components SLT can be changed based on the number of components SHE arranged between adjacent components SLT.

[0034] 1.1.4.2 Memory Area (flat layout) 4 is a plan view showing an example of a planar layout of a memory region MA of a memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. As shown in FIG. 4, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in the memory region MA. Furthermore, each member SLT includes a contact LI and a spacer SP.

[0035] Each memory pillar MP functions as, for example, one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the Y direction in the region between two adjacent members SLT. In the example shown in FIG. 4, one member SHE overlaps each of the memory pillars MP in the fifth, tenth, and fifteenth rows counting from the top of the page.

[0036] The multiple bit lines BL each extend in the Y direction and are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In the example shown in FIG. 4, two bit lines BL are arranged so as to overlap one memory pillar MP. When multiple bit lines BL overlap a memory pillar MP, one of the multiple bit lines BL is electrically connected to the corresponding memory pillar MP via a contact CV. Note that when only one bit line BL overlaps a memory pillar MP, the bit line BL is electrically connected to the corresponding memory pillar MP via a contact CV.

[0037] For example, the contact CV between the memory pillar MP in contact with the member SHE and the corresponding bit line BL is omitted. In other words, the contact CV between the memory pillar MP in contact with two different select gate lines SGD and the bit line BL is omitted. The number and arrangement of the memory pillar MP, member SHE, etc. between adjacent members SLT are not limited to the configuration shown in FIG. 4 and can be changed as appropriate. For example, the number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0038] The contact LI is a conductor extending in the XZ plane. The lower surface of the contact LI is in contact with a source line SL (not shown). The spacer SP is an insulator provided on the side surface of the contact LI. In other words, the spacer SP is provided in contact with the contact LI so as to sandwich the contact LI in the Y direction.

[0039] (Cross-sectional structure) 5 is a cross-sectional view taken along line VV in FIG. 4, showing an example of a cross-sectional structure of a memory region MA of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. As shown in FIG. 5, the memory cell array 10 further includes wiring layers 21-26.

[0040] The stacked wiring included in the memory cell array 10 includes an upper stacked wiring U and a lower stacked wiring L. The lower stacked wiring L includes a wiring layer 22 corresponding to the select gate line SGS and a plurality of wiring layers 23 corresponding to the word lines WL0 to WL7. The upper stacked wiring U includes a wiring layer 24 corresponding to the word lines WL8 to WL15 and a wiring layer 25 corresponding to the select gate line SGD.

[0041] A wiring layer 21 is provided above the semiconductor substrate 20 via an insulator layer INS. The wiring layer 21 is formed, for example, in a plate shape extending along the X direction on the XY plane. The wiring layer 21 is used as a source line SL. The wiring layer 21 includes, for example, silicon doped with phosphorus.

[0042] A wiring layer 22 is provided above the wiring layer 21 via an insulating layer (not shown). The wiring layer 22 is formed, for example, in a plate shape extending along the X direction on the XY plane. The wiring layer 22 is used as a select gate line SGS. The wiring layer 22 includes, for example, tungsten.

[0043] A plurality of insulating layers (not shown) and a plurality of wiring layers 23 are alternately stacked one by one above the wiring layer 22. The wiring layer 23 is formed, for example, in a plate shape extending along the X direction on the XY plane. The stacked wiring layers 23 are used as word lines WL0 to WL7, respectively, in order from the semiconductor substrate 20 side. The wiring layer 23 includes, for example, tungsten.

[0044] A plurality of insulating layers (not shown) and a plurality of wiring layers 24 are alternately stacked one by one above the uppermost wiring layer 23. The wiring layer 24 is formed, for example, in a plate shape extending along the X direction on the XY plane. The stacked wiring layers 24 are used as word lines WL8 to WL15, respectively, in order from the semiconductor substrate 20 side. The wiring layer 24 includes, for example, tungsten.

[0045] A wiring layer 25 is provided above the uppermost wiring layer 24 via an insulating layer (not shown). The wiring layer 25 is formed, for example, in a plate shape extending along the X direction on the XY plane. The wiring layer 25 is used as a select gate line SGD. The wiring layer 25 includes, for example, tungsten.

[0046] A wiring layer 26 is provided above the wiring layer 25 via an insulating layer. The wiring layer 26 is formed, for example, in a line shape extending along the Y direction. The wiring layer 26 is used as a bit line BL. In a region not shown, multiple wiring layers 26 are lined up along the X direction. The wiring layer 26 includes, for example, copper.

[0047] Each of the memory pillars MP extends along the Z direction. Each of the memory pillars MP includes an upper pillar UMP and a lower pillar LMP. The lower pillar LMP penetrates the lower stacked wiring L, i.e., the wiring layers 22 and 23, and the insulator layer provided between the wiring layer 21 and the wiring layer 23. The upper pillar UMP penetrates the upper stacked wiring U, i.e., the wiring layers 24 and 25, and the insulator layer provided between the wiring layer 24 and the wiring layer 25. The upper end of the lower pillar LMP and the lower end of the upper pillar UMP are in contact with each other between the uppermost wiring layer 23 and the lowermost wiring layer 24. For example, the cross-sectional area (XY cross-sectional area) of each of the lower pillar LMP and the upper pillar UMP along the XY plane increases from bottom to top.

[0048] Each of the memory pillars MP includes, for example, a core film 30, a semiconductor film 31, and a stacked film 32. The core film 30 is provided so as to extend along the Z direction. For example, the upper end of the core film 30 is located above the wiring layer 25, and the lower end of the core film is located within the wiring layer 21. The core film 30 includes, for example, an insulator such as silicon oxide. The semiconductor film 31 covers, for example, the periphery of the core film 30. At the lower end of the memory pillar MP, a portion of the semiconductor film 31 contacts the wiring layer 21. The semiconductor film 31 includes, for example, silicon. The stacked film 32 covers the side and bottom surfaces of the semiconductor film 31 except for the portion where the semiconductor film 31 and the wiring layer 21 contact each other.

[0049] 5, the portion where the memory pillar MP intersects with the wiring layer 22 functions as the select transistor ST2. The portions where the memory pillar MP intersects with the wiring layers 23 and 24 function as the memory cell transistors MT0 to MT15, respectively. The portion where the memory pillar MP intersects with the wiring layer 25 functions as the select transistor ST1.

[0050] Pillar-shaped contacts CV are provided on the top surface of the semiconductor film 31 in the memory pillars MP. In the region shown in Figure 5, two contacts CV are shown corresponding to two of the six memory pillars MP. In this region, memory pillars MP that do not overlap with the member SHE and are not connected to a contact CV are connected to other contacts CVs in a region not shown. One wiring layer 26, i.e., one bit line BL, is in contact with the upper surface of each contact CV. One contact CV is connected to one wiring layer 26 in each space partitioned by the members SLT and SHE. That is, each wiring layer 26 is electrically connected to, for example, one memory pillar MP in each region between adjacent members SLT and SHE, and one memory pillar MP in each region between two adjacent members SHE.

[0051] The member SLT is formed so as to extend along the XZ plane, for example, and divides the wiring layers 22 to 25 and the insulating layer (not shown) provided between the wiring layer 21 and the wiring layer 25.

[0052] In the member SLT, the contacts LI are provided so as to extend along the XZ plane, and spacers SP are provided between the contacts LI and the wiring layers 22 to 25. The upper ends of the contacts LI are located, for example, in an insulating layer (not shown) between the wiring layers 25 and 26. The lower ends of the contacts LI are in contact with, for example, the wiring layer 21. The contacts LI may be omitted depending on the structure of the memory cell array 10.

[0053] The member SHE is formed, for example, in the shape of a plate extending along the XZ plane, and divides the wiring layer 25. The upper end of the member SHE is located in an insulator layer (not shown) between the wiring layer 25 and the wiring layer 26. The lower end of the member SHE is located, for example, in an insulator layer (not shown) between the uppermost wiring layer 24 and the wiring layer 25. The member SHE includes an insulator such as silicon oxide. The upper end of the member SHE and the upper end of the member SLT may or may not be aligned. Furthermore, the upper end of the member SHE and the upper end of the memory pillar MP may or may not be aligned.

[0054] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of the cross-sectional structure of a memory pillar MP included in the semiconductor memory device 3 according to the first embodiment. More specifically, FIG. 6 shows the cross-sectional structure of the memory pillar MP in a layer that is parallel to the surface of the semiconductor substrate 20 and includes the wiring layer 23. As shown in FIG. 6, the stacked film 32 includes, for example, a tunnel insulating film 33, a charge storage film 34, and a block insulating film 35.

[0055] In a cross section including the wiring layer 23, the core film 30 is provided, for example, in the center of the memory pillar MP. The semiconductor film 31 surrounds the side surfaces of the core film 30. The tunnel insulating film 33 surrounds the side surfaces of the semiconductor film 31. The charge storage film 34 surrounds the side surfaces of the tunnel insulating film 33. The block insulating film 35 surrounds the side surfaces of the charge storage film 34. The wiring layer 23 surrounds the side surfaces of the block insulating film 35.

[0056] The semiconductor film 31 is used as the channels (current paths) of the memory cell transistors MT0 to MT15 and the select transistors ST1 and ST2. The tunnel insulating film 33 and the block insulating film 35 each contain, for example, silicon oxide. The charge storage film 34 has the function of storing charges and contains, for example, silicon nitride. With this configuration, each memory pillar MP can function as one NAND string NS.

[0057] 1.1.4.3 Drawer area (Cross-sectional structure) FIG. 7 is a schematic diagram showing an example of the cross-sectional structure of the stacked wiring in the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. FIG. 8 is a cross-sectional view showing an example of the cross-sectional structure in the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. In addition to the lead-out region HA corresponding to one block BLK, FIGS. 7 and 8 also show a portion of the nearby memory region MA. FIG. 7 shows multiple regions of the stacked wiring. For simplicity of explanation, FIG. 7 omits memory pillars MP, contacts CV and wiring layers provided above the stacked wiring, and contacts CC, which will be described later. FIG. 8 shows details of the cross-sectional structure in the lead-out region HA of the memory cell array.

[0058] First, with reference to FIG. 7, the cross-sectional structure of the laminated wiring in the lead-out region HA will be described.

[0059] As shown in FIG. 7, the lead-out area HA includes, for example, four staircase areas USTP1, USTP2, LSTP1, and LSTP2.

[0060] The staircase regions USTP1 and USTP2 are provided in the upper stacked wiring U. The staircase regions USTP1 and USTP2 are regions in which the ends of the wiring layers 24 and 25 are drawn out in a staircase shape.

[0061] The staircase regions LSTP1 and LSTP2 are provided in the lower laminated wiring L. The staircase regions LSTP1 and LSTP2 are regions in which the ends of the wiring layers 22 and 23 are drawn out in a staircase shape.

[0062] It should be noted that there is no particular limitation on the number of staircase regions provided in the upper stacked wiring U and the lower stacked wiring L. Hereinafter, when any of the staircase regions USTP1, USTP2, LSTP1, and LSTP2 is not limited, it will be referred to as a "staircase region STP."

[0063] The staircase region STP includes a double-sided staircase structure. The double-sided staircase structure is a staircase structure in which a front staircase F_SP and a back staircase B_SP are arranged side by side in the X direction. The front staircase F_SP is a staircase structure in which a portion of a plurality of wiring layers is drawn down in a staircase-like manner in the X direction away from the memory area MA. The back staircase B_SP is a staircase structure in which a portion of a plurality of wiring layers is drawn up in a staircase-like manner in the X direction away from the memory area MA. The front staircase F_SP and the back staircase B_SP are similar to steps, terraces, rimstones, etc. The front staircase F_SP and the back staircase B_SP are arranged opposite each other in the X direction so that the lowest staircase portion is located at the center of the double-sided staircase structure. Note that the lowest staircase portion of the double-sided staircase structure is included in the front staircase F_SP. Hereinafter, the area of ​​the staircase region STP including the front staircase F_SP will be referred to as the front staircase region, and the area including the back staircase B_SP will be referred to as the back staircase region. The front staircase area and the back staircase area are aligned in the X direction. The front staircase area is provided on the side of the staircase area STP that is closer to the memory area MA. The back staircase area is provided on the side of the staircase area STP that is farther from the memory area MA.

[0064] Specifically, the staircase region USTP1 includes a front staircase region USTP1a and a back staircase region USTP1b. The front staircase region USTP1a and the back staircase region USTP1b are aligned with each other in the X direction. The front staircase region USTP1a is provided closer to the memory region MA than the back staircase region USTP1b. The staircase region USTP1 has, for example, a double-sided staircase structure provided in four wiring layers 24 corresponding to the word lines WL12 to WL15 and a wiring layer 25 corresponding to the select gate line SGD. The front staircase F_SP of the front staircase region USTP1a is provided in the four wiring layers 24 corresponding to the word lines WL12 to WL15 and the wiring layer 25 corresponding to the select gate line SGD. The back staircase B_SP of the back staircase region USTP1b is provided in the three wiring layers 24 corresponding to the word lines WL13 to WL15 and the wiring layer 25 corresponding to the select gate line SGD.

[0065] The staircase region USTP2 includes a front staircase region USTP2a and a back staircase region USTP2b. The front staircase region USTP2a and the back staircase region USTP2b are aligned with each other in the X direction. The front staircase region USTP2a is provided closer to the memory area MA than the back staircase region USTP2b. The staircase region USTP2 has, for example, a double-sided staircase structure provided in four wiring layers 24 corresponding to the word lines WL8 to WL11. The front staircase F_SP of the front staircase region USTP2a is provided in the four wiring layers 24 corresponding to the word lines WL8 to WL11. The back staircase B_SP of the back staircase region USTP2b is provided in the three wiring layers 24 corresponding to the word lines WL9 to WL11.

[0066] The staircase region LSTP1 includes a front staircase region LSTP1a and a back staircase region LSTP1b. The front staircase region LSTP1a and the back staircase region LSTP1b are aligned with each other in the X direction. The front staircase region LSTP1a is provided closer to the memory region MA than the back staircase region LSTP1b. The staircase region LSTP1 has, for example, a double-sided staircase structure provided at the ends of five wiring layers 23 corresponding to the word lines WL3 to WL7. The front staircase F_SP of the front staircase region LSTP1a is provided in the five wiring layers 23 corresponding to the word lines WL3 to WL7. The back staircase B_SP of the back staircase region LSTP1b is provided in the four wiring layers 24 corresponding to the word lines WL4 to WL7.

[0067] The staircase region LSTP2 includes a front staircase region LSTP2a and a back staircase region LSTP2b. The front staircase region LSTP2a and the back staircase region LSTP2b are aligned with each other in the X direction. The front staircase region LSTP2a is provided closer to the memory region MA than the back staircase region LSTP2b. The staircase region LSTP2 has, for example, a double-sided staircase structure provided at the ends of the wiring layer 22 corresponding to the select gate line SGS and the three wiring layers 23 corresponding to the word lines WL0 to WL2. The front staircase F_SP of the front staircase region LSTP2a is provided in the wiring layer 22 corresponding to the select gate line SGS and the three wiring layers 23 corresponding to the word lines WL0 to WL2. The back staircase B_SP of the back staircase region LSTP2b is provided in the three wiring layers 23 corresponding to the word lines WL0 to WL2.

[0068] The front staircase region and back staircase region of each staircase region STP are arranged so that the upper stacked wiring U and the lower stacked wiring L alternate when viewed in the Z direction. The front staircase regions USTP1a and USTP2a corresponding to the upper stacked wiring U are not provided above the front staircase regions LSTP1a and LSTP2a corresponding to the lower stacked wiring L. For example, the front staircase region USTP1a is provided above the region of the lower stacked wiring L where the staircase structure on both sides is not formed. The front staircase region USTP2a is provided above the back staircase region LSTP1b. The front staircase region LSTP1a is provided below the back staircase region USTP1b. The front staircase region LSTP2a is provided below the back staircase region USTP2b. The staircase structure on both sides of the upper stacked wiring U is not formed above the back staircase region LSTP2b.

[0069] As shown in FIG. 8, the memory cell array 10 further includes a plurality of contacts CC, a wiring layer 28, and a stop member SPF in the lead-out region HA.

[0070] The contacts CC are provided corresponding to the select gate lines SGS and SGD and the word lines WL0 to WL15, respectively. In the example shown in FIG. 8, the contacts CC correspond, in order from the memory area MA side, to the select gate line SGD, the word lines WL15, WL14, WL13, WL12, WL7, WL6, WL5, WL4, WL3, WL11, WL10, WL9, WL8, WL2, WL1, WL0, and the select gate line SGS. Each contact CC extends in the Z direction. Each contact CC penetrates (passes through) in the Z direction through the wiring layer (22, 23, 24, and 25) that is provided at the position where the contact CC is provided in a plan view, and through an insulating layer (not shown). The lower surface of each contact CC is in contact with the stop member SPF. A contact provided to penetrate the stacked wiring in the Z direction is called a "through contact."

[0071] Each contact CC penetrates at least one or more staircase regions STP in the Z direction. Each contact CC is connected to one or more of the wiring layers 22, 23, 24, and 25 in each of the one or more staircase regions STP that it passes through in the Z direction. That is, each of the wiring layers 22, 23, 24, and 25 has a connection portion that is electrically connected to the contact CC in the corresponding staircase region STP. Hereinafter, the connection portion of each of the wiring layers 22, 23, 24, and 25 with the contact CC will be referred to as a CC connection portion CCT.

[0072] Each contact CC is arranged to penetrate one of the CC connection parts CCT formed in the front staircase region in the Z direction and is connected to the wiring layer at its side. Some contacts CC are also arranged to penetrate one of the CC connection parts CCT formed in the back staircase region in the Z direction and are connected to the wiring layer corresponding to each CC connection part CCT at their side. Each contact CC corresponds to a wiring layer 22, 23, 24, or 25 connected by a CC connection part CCT formed in the front staircase region.

[0073] Specifically, in the front staircase region USTP1a of the staircase region USTP1, CC connection portions CCT are provided for four wiring layers 24 corresponding to the word lines WL12 to WL15, respectively, and for a wiring layer 25 corresponding to the select gate line SGD. A different contact CC is connected to each CC connection portion CCT. In the front staircase region USTP1a, five contacts CC connected to the CC connection portions CCT correspond to the word lines WL12 to WL15 and the select gate line SGD, respectively. In the back staircase region USTP1b of the staircase region USTP1, CC connection portions CCT are provided for wiring layers 24 corresponding to the word lines WL13 to WL15, respectively, and for a wiring layer 25 corresponding to the select gate line SGD, respectively. A different contact CC is connected to each CC connection portion CCT. In the back staircase region USTP1b, the four contacts CC connected to the CC connection portions CCT are also connected below to CC connection portions CCT formed in the front staircase region LSTP1a.

[0074] In the front staircase region USTP2a of the staircase region USTP2, CC connection portions CCT of the wiring layer 24 corresponding to the word lines WL8 to WL11 are provided. A different contact CC is connected to each CC connection portion CCT. In the front staircase region USTP2a, the four contacts CC connected to the CC connection portions CCT correspond to the word lines WL8 to WL11, respectively. In the front staircase region USTP2a, the four contacts CC connected to the CC connection portions CCT are also connected below to CC connection portions CCT formed in the back staircase region LSTP1b. In the back staircase region USTP2b of the staircase region USTP2, CC connection portions CCT of the wiring layer 24 corresponding to the word lines WL9 to WL11 are provided. A different contact CC is connected to each CC connection portion CCT. In the back staircase region USTP2b, the three contacts CC connected to each CC connection portion CCT are also connected below to CC connection portions CCT formed in the front staircase region LSTP2a.

[0075] In the front staircase region LSTP1a of the staircase region LSTP1, CC connection portions CCT of the wiring layer 23 corresponding to the word lines WL3 to WL7 are provided. A different contact CC is connected to each CC connection portion CCT. In the front staircase region LSTP1a, the five contacts CC connected to the CC connection portions CCT correspond to the word lines WL3 to WL7, respectively. In the back staircase region LSTP1b of the staircase region LSTP1, CC connection portions CCT of the wiring layer 23 corresponding to the word lines WL4 to WL7 are provided. A different contact CC is connected to each CC connection portion CCT.

[0076] In the front staircase region LSTP2a of the staircase region LSTP2, there are provided CC connection parts CCT of the wiring layer 22 corresponding to the select gate line SGS and the wiring layer 23 corresponding to the word lines WL0 to WL2. In the front staircase region LSTP2a, four contacts CC connected to the CC connection parts CCT correspond to the select gate line SGS and the word lines WL0 to WL2, respectively. A different contact CC is connected to each CC connection part CCT.

[0077] Fig. 9 is an enlarged view of region IX in Fig. 8. Fig. 9 corresponds to a cross-sectional view of the staircase region USTP1. The connection between the contact CC and the CC connection part CCT will be described in detail with reference to Fig. 9.

[0078] 9, each wiring layer of the laminated wiring includes a laminated portion LYR and a terrace portion TER. The laminated portion LYR extends in the X direction and has, for example, a first thickness D1 in the Z direction. The terrace portion TER has, for example, a second thickness D2 in the Z direction that is thicker than the first thickness D1. Note that, depending on the configuration of the contacts CC described below, the terrace portion TER may have a thickness in the Z direction that is equal to or thinner than the first thickness D1.

[0079] The terrace portions TER of each wiring layer are provided on the tread surfaces of the front staircase F_SP and the back staircase B_SP formed in the staircase region STP. The terrace portions TER of each wiring layer 24 and 25 included in the upper stacked wiring U do not overlap in the Z direction with the upper wiring layers 24 and 25. Similarly, as shown in FIG. 8, the terrace portions TER of each wiring layer 22 and 23 included in the lower stacked wiring L do not overlap in the Z direction with the wiring layer 23 of the lower stacked wiring L provided above the terrace portions TER. Note that the terrace portions TER of each wiring layer 22 and 23 included in the lower stacked wiring L may overlap in the Z direction with the wiring layers 24 and 25 included in the upper stacked wiring U.

[0080] 9, in each staircase region STP, the multiple terrace portions TER provided in each wiring layer are arranged side by side in the X direction. Each terrace portion TER is spaced apart in the X direction from the side surface of the terrace portion TER provided in the layer immediately above. That is, the multiple terrace portions TER provided in one staircase region STP are arranged spaced apart in the X direction.

[0081] As shown in FIG. 8, in each staircase region STP, the terrace portions TER of the wiring layers 22, 23, 24, and 25, except for the terrace portions TER of the wiring layers 22 and 23 formed in the back staircase B_SP of the back staircase region LSTP2b, function as CC connection portions CCT.

[0082] 9, the wiring layer 24 corresponding to the word line WL14 includes two stacked portions LYR and two terrace portions TER in the illustrated staircase region USTP1. Two terrace portions TER are provided, one for the front staircase F_SP and one for the back staircase B_SP. Each of the two stacked portions LYR is connected to a respective terrace portion TER. Of these, the stacked portion LYR connected to the terrace portion TER provided in the front staircase F_SP extends to the memory region MA. On the other hand, the stacked portion LYR connected to the terrace portion TER provided in the back staircase B_SP is not connected to the memory region MA.

[0083] Each contact CC includes a conductor 27 and multiple insulators 51. The conductor 27 extends in the Z direction and is connected to one of the wiring layers 22, 23, 24, and 25 on which the terrace portion TER is formed, at a portion where the conductor 27 penetrates the terrace portion TER. The conductor 27 may be connected to the terrace portion TER formed on the front staircase F_SP or to both the terrace portion TER formed on the front staircase F_SP and the terrace portion TER formed on the back staircase B_SP. The conductor 27 includes, for example, tungsten. The multiple insulators 51 are provided to surround the side surfaces of the conductor 27 at a portion where the conductor 27 penetrates the stacked portion LYR of the wiring layers 22, 23, 24, and 25. The multiple insulators 51 insulate the conductor 27 from the stacked portion LYR of the wiring layers 22, 23, 24, and 25 through which the corresponding contact CC penetrates. That is, each contact CC is connected to the wiring layer that penetrates the terrace portion TER among the wiring layers 22, 23, 24, and 25, and is insulated from the wiring layer that penetrates the laminate portion LYR. Note that the configuration of the contact CC is not limited to the above configuration, as long as it is a through contact that is connected to the corresponding CC connection portion CCT of each wiring layer and is insulated from other wiring layers.

[0084] The plurality of wiring layers 28 are provided on the plurality of contacts CC, respectively. The plurality of wiring layers 28 are located, for example, in the same layer as the plurality of wiring layers 26. Each contact CC is electrically connected to the row decoder module 15 via the wiring layer 28.

[0085] 8, in the lead-out region HA, a stopping member SPF is provided on the wiring layer 21. The stopping member SPF functions as an etching stopper layer to prevent the bottom surfaces of the holes from reaching the wiring layer 21 when holes corresponding to the plurality of contacts CC are formed in the manufacturing process of the lead-out region HA.

[0086] (flat layout) FIG. 10 is a plan view showing an example of a planar layout of the upper stacked wiring U in the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. FIG. 11 is a plan view showing an example of a plane along line XI-XI in FIG. 8 in the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. FIGS. 10 and 11 show the lead-out region HA and a portion of the nearby memory region MA. FIG. 11 corresponds to the planar structure of the wiring layer 24 corresponding to the word line WL14. Note that, for simplicity of explanation, the stacked portion LYR and terrace portion TER of each wiring layer are omitted in FIG. 10. Furthermore, in FIG. 11, the wiring layer 24 corresponding to the word line WL14 is hatched, and the boundary between the stacked portion LYR and the terrace portion TER is indicated by a dashed line.

[0087] As shown in FIG. 10, the select gate line SGD and the word lines WL9 to WL15 include multiple portions separated in the X direction by a staircase formation. Of these multiple portions, the portion connected to the memory area MA is called the first portion and is distinguished by adding an m to the end. The portion not connected to the memory area MA is called the second portion and is distinguished by adding an f to the end. Note that there may be multiple second portions. In that case, they are distinguished by adding f_1, f_2, ... to the end in order from the memory area MA side. The word line WL8 includes the first portion connected to the memory area MA, but does not include the second portion not connected to the memory area MA.

[0088] The select gate line SGD includes a first portion SGDm connected to the memory area MA and second portions SGDf_1 and SGDf_2 not connected to the memory area MA. The wiring layer 25 corresponding to the first portion SGDm of the select gate line SGD is divided in the Y direction by multiple members SHE. For example, in one block BLK, the wiring layer 25 divided by three members SHE are designated, from the top of the page, as select gate lines SGD0 to SGD3. The select gate lines SGD0 to SGD3 are insulated from one another by the multiple members SHE. A plurality of contacts CC are provided corresponding to each of the four select gate lines SGD0 to SGD3.

[0089] The word line WL15 includes a first portion WL15m connected to the memory area MA, a second portion WL15f_1 not connected to the memory area MA, and a second portion WL15f_2 in an area not shown.

[0090] The word line WL14 includes a first portion WL14m connected to the memory area MA, a second portion WL14f_1 not connected to the memory area MA, and a second portion WL14f_2 in an area not shown.

[0091] The word line WL13 includes a first portion WL13m connected to the memory area MA, a second portion WL13f_1 not connected to the memory area MA, and a second portion WL13f_2 in an area not shown.

[0092] The word line WL12 includes a first portion WL12m connected to the memory area MA and a second portion WL12f in an area not shown that is not connected to the memory area MA.

[0093] The word line WL11 includes a first portion WL11m connected to the memory area MA and a second portion WL11f not connected to the memory area MA.

[0094] The word line WL10 includes a first portion WL10m connected to the memory area MA and a second portion WL10f not connected to the memory area MA.

[0095] The word line WL9 includes a first portion WL9m connected to the memory area MA and a second portion WL9f not connected to the memory area MA.

[0096] The word line WL8 includes a first portion WL8m connected to the memory area MA.

[0097] Although not shown, the word lines WL0 to WL7 are also similarly divided in the X direction by the staircase formation and include a first portion connected to the memory area MA and a second portion not connected to the memory area MA. The select gate line SGS includes the first portion connected to the memory area MA, but does not include the second portion not connected to the memory area MA.

[0098] 11, the word line WL14 includes one stack portion LYR and one terrace portion TER in each of the first portion WL14m and the second portion WL14f_1, and includes the stack portion LYR in the second portion WL14f_2.

[0099] A terrace portion TER corresponding to the front staircase F_SP of the staircase region USTP1 is formed in a first portion WL14m of the word line WL14. The terrace portion TER of the first portion WL14m is connected to the conductor 27 of the contact CC corresponding to the word line WL14. That is, a voltage corresponding to the word line WL14 is applied to the first portion WL14m from the row decoder module 15 via the contact CC.

[0100] A terrace portion TER corresponding to the back staircase B_SP of the staircase region USTP1 is formed in the second portion WL14f_1. The terrace portion TER of the second portion WL14f_1 is connected to the conductor 27 of the contact CC corresponding to a wiring layer different from that of the word line WL14. The first portion WL14m and the second portion WL14f_1 of the word line WL14 are not in contact with each other but are spaced apart in the X direction with an insulating layer (not shown) interposed therebetween. Therefore, the contact CC connected to the terrace portion TER of the second portion WL14f_1 is not electrically connected to the first portion WL14m of the word line WL14.

[0101] Moreover, the second portion WL14f_2 of the word line WL14 is not connected to the contact CC and is in a floating state.

[0102] Therefore, for example, the contact CC supplies a voltage (current) to the memory area MA via the terrace portion TER of the first portion WL14m (front staircase F_SP). The second portions WL14f_1 (back staircase B_SP) and WL14f_2 do not contribute to the supply of a voltage (current) from the contact CC to the memory area MA. In other words, the back staircase B_SP does not function as a current path for the contact CC. Therefore, even if the contact CC and the back staircase B_SP are connected, it does not affect the characteristics of the memory cell array 10.

[0103] Although not shown, for example, a terrace portion TER corresponding to the front staircase F_SP is formed in the first portion of each of the select gate lines SGS and SGD and the other word lines WL0 to WL13 and WL15. Each of the multiple contacts CC supplies a voltage (current) to the memory area MA via the terrace portion TER of the first portion (front staircase F_SP) of the corresponding select gate line SGS or SGD or word line WL0 to WL13 or WL15. A terrace portion TER corresponding to the back staircase B_SP is formed in one of the second portions of each of the select gate line SGD and word lines WL0 to WL2, WL4 to WL7, WL9 to WL11, WL13, and WL15. Each of the second portions (back staircase B_SP) does not contribute to the supply of a voltage (current) from the contact CC to the memory area MA. That is, the terrace portions TER corresponding to the back stairs B_SP formed on the select gate lines SGD and the word lines WL0 to WL2, WL4 to WL7, WL9 to WL11, WL13, and WL15 do not function as current paths for the contacts CC. Therefore, even if the contacts CC and the terrace portions TER corresponding to the back stairs B_SP are connected, this does not affect the characteristics of the memory cell array 10.

[0104] 1.2 Manufacturing method of the pull-out area FIG. 12 is a flowchart showing an example of a method for manufacturing the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. FIGS. 13 to 22, 24, and 26 are cross-sectional views showing an example of the cross-sectional structure of the lead-out region HA during the manufacturing process of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. The cross-sectional structures shown in FIGS. 13 to 17, 22, 24, and 26 show the region corresponding to FIG. 8. The cross-sectional structures shown in FIGS. 18 to 21 show the region corresponding to region XVIII in FIG. 17. FIGS. 23 and 25 are plan views showing an example of the planar layout of the lead-out region HA during the manufacturing process of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment. The planar layouts shown in FIGS. 23 and 25 show the region corresponding to FIG. 10. Note that the stack portion LYR, terrace portion TER, and insulating layer are omitted in FIGS. 23 and 25.

[0105] 12, in the manufacturing process of the lead-out area HA, the processes of S101 to S117 are executed in order. An example of the manufacturing process of the lead-out area HA will be described below with reference to FIGS.

[0106] In this embodiment, a method of forming the multiple wiring layers 22, 23, 24, and 25 corresponding to the select gate lines SGS and SGD and the word lines WL0 to WL15, respectively, will be described in which, for example, structures corresponding to the wiring layers 22, 23, 24, and 25 are formed using sacrificial materials 42, 44, 46, and 48, respectively, and then the sacrificial materials are replaced with conductive materials to form the wiring layers 22, 23, 24, and 25 (hereinafter referred to as "replace").

[0107] First, the processes of S101 and S103 are performed in order to form a double-sided staircase structure of the lower laminated wiring L including the sacrificial members 42 and 44.

[0108] Specifically, as shown in FIG. 13, first, an insulator layer INS and a wiring layer 21 are stacked in this order on a semiconductor substrate 20. Next, in the lead-out region HA, a stopping member SPF is provided on the wiring layer 21. An insulator layer 41 and a sacrificial member 42 are stacked in this order on the wiring layer 21 and the stopping member SPF. For example, nine insulator layers 43 and eight sacrificial members 44 are stacked alternately one by one on the sacrificial member 42 (S101). The uppermost layer is the insulator layer 43. The Z-direction thickness of each of the sacrificial members 42 and 44 is equal to the first thickness D1. The insulator layers 41 and 43 include, for example, silicon oxide (SiO). The sacrificial members 42 and 44 include, for example, silicon nitride (SiN).

[0109] Thereafter, for example, in the regions corresponding to the staircase regions LSTP1 and LSTP2, four insulating layers 43 and four sacrificial members 44 are processed from the top into a staircase shape, with one pair of insulating layer 43 and one sacrificial member 44 forming one step (S102). At this time, a front staircase F_SP is formed in the front staircase regions LSTP1a and LSTP2a, and a back staircase B_SP is formed in the back staircase regions LSTP1b and LSTP2b. Specifically, first, a mask having an opening corresponding to the lowest step portion is formed by photolithography or the like. Then, one step of the insulating layers 43 and the sacrificial members 44 is removed by anisotropic etching using the mask. Next, a portion of the mask corresponding to the next lowest step is removed. Then, one step of the insulating layers 43 and the sacrificial members 44 is removed by anisotropic etching using the mask. In this way, by repeating the reduction of the mask region and the anisotropic etching, the insulating layers 43 and the sacrificial members 44 are processed into a staircase shape. This type of processing is called "slimming." This results in the formation of a double-sided staircase structure.

[0110] 14, multi-step processing is performed on the double-sided staircase structure formed in the staircase region LSTP2 so that the double-sided staircase structure corresponds to a wiring layer lower than the double-sided staircase structure formed in the staircase region LSTP1 (S103). The multi-step processing is a process for collectively removing multiple insulator layers and multiple sacrificial members in the processing region.

[0111] Specifically, first, a mask having an opening in a region corresponding to the staircase region LSTP2 is formed by photolithography or the like. Then, by anisotropic etching using the mask, for example, five steps of the insulator layers 43 and the sacrificial members 44 are removed. As a result, in the staircase region LSTP2, a double-sided staircase structure is formed in which the bottom four insulator layers 43, the sacrificial members 42, and the bottom three sacrificial members 44 are processed into a staircase shape, with one pair of one insulator layer 43 and one sacrificial member 42 or 44 forming one step.

[0112] Next, the process of S104 is executed, and as shown in FIG. 15, in each staircase region, portions corresponding to the terrace portions TER of each wiring layer included in the lower multilayer wiring L are formed in the sacrificial members 42 and 44.

[0113] Specifically, in the staircase regions LSTP1 and LSTP2, the insulator layer 43 exposed on the upper surfaces of the staircase structure on both sides is removed. Then, sacrificial members corresponding to the sacrificial members 42 and 44 are formed, and the sacrificial members in the staircase portions are thickened. Then, the sacrificial members formed on the uppermost insulator layer 43 and the portions of the sacrificial members in the thickened staircase portions of the sacrificial members 42 and 44 that are in contact with the side surfaces of the sacrificial member 44 provided in the layer immediately above the sacrificial member 42 or 44 via the insulator layer 43 are removed. This forms thickened portions of the sacrificial member 42 or 44 corresponding to the terrace portions TER. The thickness in the Z direction of the thickened portions of the sacrificial member 42 or 44 corresponding to the terrace portions TER is equal to the second thickness D2.

[0114] Thereafter, the staircase regions LSTP1 and LSTP2 of the lower multilayer wiring L are buried with an insulating layer 45. The insulating layer 45 includes, for example, SiO. For example, the surface of the insulating layer 45 is planarized by CMP (Chemical Mechanical Polishing).

[0115] Next, the processes of S105 to S108 are executed, and as shown in FIG. 16, an upper stacked structure including sacrificial members 46 and 48 is formed, a staircase structure on both sides of the upper stacked wiring U is formed, and portions corresponding to the terrace portions TER of each wiring layer included in the upper stacked wiring U are formed.

[0116] Specifically, first, for example, eight layers of sacrificial members 46 and insulator layers 47 are alternately stacked one by one on the stacked structure. A sacrificial member 48 and an insulator layer 49 are stacked in this order on the topmost insulator layer 47 (S105). The Z-direction thickness of each of the sacrificial members 46 and 48 is equal to the first thickness D1. The insulator layers 47 and 49 contain, for example, SiO. The sacrificial members 46 and 48 contain, for example, SiN.

[0117] Next, for example by slimming, in the regions corresponding to the staircase regions USTP1 and USTP2, the insulator layer 49 and the top three insulator layers 47, and the sacrificial member 48 and the top three sacrificial members 46 are processed into a staircase shape, with one step consisting of one insulator layer 47 or 49 and one sacrificial member 46 or 48 (S106). At this time, a front staircase F_SP is formed in the front staircase regions USTP1a and USTP2a, and a back staircase B_SP is formed in the back staircase regions USTP1b and USTP2b.

[0118] Thereafter, multi-step processing is performed on the double-sided staircase structure formed in the staircase region USTP2, and the double-sided staircase structure is processed so as to correspond to a wiring layer lower than the double-sided staircase structure formed in the staircase region USTP1 (S107). As a result, in the staircase region USTP2, a staircase-like structure is formed in which the four lowest layers of insulator layers 47 and sacrificial members 46 form one step, with one pair of one insulator layer 47 and one sacrificial member 46.

[0119] Next, in the staircase regions USTP1 and USTP2, the insulator layers 47 and 49 exposed on the upper surfaces of the staircase structures on both sides are removed. Thereafter, sacrificial members corresponding to the sacrificial members 46 and 48 are formed, and the sacrificial members in the staircase portions are thickened. Thereafter, the sacrificial member formed on the uppermost insulator layer 49 and the portion of the sacrificial member in the thickened staircase portion of the sacrificial member 46 that contacts the side surface of the sacrificial member 46 or 48 provided in the layer immediately above the sacrificial member 46 via the insulator layer 47 are removed (S108). As a result, a thickened portion of the sacrificial member 46 or 48 corresponding to the terrace portion TER is formed. The thickness in the Z direction of the thickened portion of the sacrificial member 46 or 48 corresponding to the terrace portion TER becomes equal to the second thickness D2. Thereafter, the staircase regions USTP1 and USTP2 of the upper stack wiring U are filled with an insulator layer 50. The insulator layer 50 includes, for example, SiO. For example, the surface of the insulator layer 50 is planarized by CMP.

[0120] Next, the process of S109 is performed, and a plurality of holes CH corresponding to a plurality of contacts CC are formed as shown in FIGS.

[0121] Specifically, a mask having openings corresponding to the contacts CC is first formed by photolithography or the like. Then, a plurality of holes CH corresponding to the contacts CC are formed by anisotropic etching using the mask. Each hole CH penetrates the insulator layers 41, 43, 45, 47, 49, and 50 and the sacrificial members 42, 44, 46, and 48, respectively, and penetrates at least one of the thickened portions of the sacrificial members 42, 44, 46, and 48. A portion of the stopping member SPF is exposed at the bottom of each hole CH.

[0122] Next, the processes of S110 to S113 are performed to form a structure corresponding to a plurality of contacts CC.

[0123] 19, first, peripheral portions of the sacrificial members 42, 44, 46, and 48 exposed on the side surfaces of each hole CH are removed by wet etching through each hole CH (S110). As a result, multiple grooves are formed on the side surfaces of each hole CH, where the sacrificial members 42, 44, 46, and 48 are recessed in the XY plane direction relative to the insulator layers 41, 43, 45, and 47.

[0124] 20, an insulator 51 is deposited on the inner wall of each hole CH (S111). In the non-thickened portions of the sacrificial members 42, 44, 46, and 48, the insulator 51 is deposited so as to fill the grooves formed in S108. On the other hand, in the thickened portions of the sacrificial members 42, 44, 46, and 48, the insulator 51 is deposited so as to cover the side surfaces of the grooves, leaving a recessed portion in the center. The insulator 51 includes, for example, SiO.

[0125] 21, a portion of the insulator 51 in the hole CH is removed by wet etching (S112). At this time, in the non-thickened portions of the sacrificial members 42, 44, 46, and 48, the insulator 51 embedded in the grooves is not completely removed, and none of the sacrificial members 42, 44, 46, and 48 is exposed on the side surface of each hole CH. On the other hand, in the thickened portions of the sacrificial members 42, 44, 46, and 48, the insulator 51 provided to cover the side surface of the groove is removed, and the sacrificial members 42, 44, 46, and 48 are exposed on the side surface of each hole CH.

[0126] 22, sacrificial members 52 are then buried in each hole CH (S113). Each of the buried sacrificial members 52 contacts the sacrificial members 42, 44, 46, and 48 laterally in grooves formed in the thickened portions of the sacrificial members 42, 44, 46, and 48. Each sacrificial member 52 also contacts the stopping member SPF on its underside. The sacrificial members 52 include, for example, amorphous silicon.

[0127] Next, the process of S114 is carried out, and a plurality of slits SH are formed as shown in FIG.

[0128] Specifically, first, a mask having openings in regions corresponding to the members SLT is formed by photolithography, etc. Then, by anisotropic etching using the mask, slits SH are formed that penetrate, for example, the insulator layers 41, 43, 45, 47, 49, and 50 and the sacrificial members 42, 44, 46, and 48, respectively.

[0129] Next, the process of S115 is performed, and a stacked wiring structure is formed by replacement, as shown in FIG.

[0130] Specifically, first, the sacrificial members 42, 44, 46, and 48 are removed through the slits SH by wet etching. At this time, the three-dimensional structure of the structure after the sacrificial members 42, 44, 46, and 48 have been removed is maintained by a plurality of memory pillars MP and a plurality of support pillars (not shown). Then, conductors are filled through the slits SH into the spaces left by the removal of the sacrificial members 42, 44, 46, and 48. The conductors in this process are formed, for example, by chemical vapor deposition (CVD). Thereafter, the conductors formed inside the slits SH are removed by an etch-back process, and the conductors are separated from the wiring layers adjacent in the Z direction. This results in the formation of a wiring layer 22 that functions as the select gate line SGS, a plurality of wiring layers 23 that function as the word lines WL0 to WL7, a plurality of wiring layers 24 that function as the word lines WL8 to WL15, and a wiring layer 25 that functions as the select gate line SGD. The wiring layers 22, 23, 24, and 25 formed in this step may contain a barrier metal. In this case, when forming the conductor after removing the sacrificial members 42, 44, 46, and 48, for example, titanium nitride is formed as a barrier metal, and then tungsten is formed.

[0131] Next, the process of S116 is performed, and members SLT are formed in each slit SH as shown in Fig. 25. Furthermore, members SHE are formed in the terrace portion TER of the first portion SGDm of the select gate line SGD.

[0132] Specifically, first, insulating portions (spacers SP) are formed so as to cover the side and bottom surfaces of the slits SH. Then, a portion of the spacer SP provided at the bottom of the slits SH is removed, exposing a portion of the wiring layer 21 at the bottom of the slits SH. Then, a conductor (contact LI) is formed in the slits SH, and the conductor formed outside the slits SH is removed by, for example, CMP. After that, multiple grooves are formed parallel to the members SLT in regions corresponding to the members SHE between the members SLT adjacent in the Y direction. Then, an insulating film is buried in each groove, thereby forming members SHE that divide the wiring layer 25 in the Y direction.

[0133] Finally, the process of S117 is performed, and as shown in FIG. 26, a replacement process is performed for the sacrificial member 52 embedded in the hole CH, thereby forming a contact CC.

[0134] Specifically, first, the sacrificial member 52 embedded in each hole CH is removed by wet etching. Then, a plurality of conductors 27 are embedded in the holes CH. Each conductor 27 contacts the side of the wiring layers 22, 23, 24, and 25 in a groove formed in each terrace portion TER of the wiring layers 22, 23, 24, and 25. Each conductor 27 also contacts the stopping member SPF on its bottom surface. Finally, the conductors formed on the top surface of the stacked structure are removed by, for example, CMP, thereby exposing surfaces corresponding to the top ends of the plurality of contacts CC.

[0135] The structure of the lead-out region HA in the memory cell array 10 is formed by the manufacturing process described above. Note that the manufacturing process described above is merely an example and is not limited to this. For example, other processes may be inserted between each manufacturing process, or some processes may be omitted or integrated. Furthermore, each manufacturing process may be interchanged to the extent possible.

[0136] 1.3 Effects of the First Embodiment According to the first embodiment, it is possible to provide a semiconductor memory device that can reduce the number of manufacturing steps and the chip area. The effects of this will be described in detail below.

[0137] In the semiconductor memory device 3 according to the first embodiment, a portion of the staircase region of the upper stacked wiring U and a portion of the staircase region of the lower stacked wiring L can overlap in the Z direction of the memory cell array 10. Specifically, the front staircase F_SP and the back staircase B_SP of the upper stacked wiring U and the lower stacked wiring L can be arranged so as to alternate when viewed in the Z direction. The front staircase F_SP of the upper stacked wiring U and the front staircase F_SP of the lower stacked wiring L do not overlap in the Z direction. In other words, the back staircase B_SP of the upper stacked wiring U may overlap the front staircase F_SP of the lower stacked wiring L in the Z direction. The back staircase B_SP of the lower stacked wiring L may overlap the front staircase F_SP of the upper stacked wiring U in the Z direction. This structure allows the CC connection portions CCT of each wiring layer to be overlapped in the Z direction. This prevents the terrace portions TER of each wiring layer from lining up in one direction (e.g., the X direction) and thus reduces (suppresses expansion of) the chip area of ​​the semiconductor memory device 3.

[0138] Furthermore, the double-sided staircase structure of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment can be formed simultaneously with multiple double-sided staircase structures by performing slimming and multi-stage processing. For example, double-sided staircase structures included in the staircase regions LSTP1 and LSTP2 can be formed simultaneously. Double-sided staircase structures included in the staircase regions USTP1 and USTP2 can be formed simultaneously. This reduces the number of steps required to manufacture the semiconductor memory device 3, thereby reducing the manufacturing cost of the semiconductor memory device 3.

[0139] 1.4 Modification of the first embodiment The semiconductor memory device 3 according to the first embodiment described above can be modified in various ways. Differences between the first embodiment and the first, second, third, and fourth modifications of the first embodiment will be described below.

[0140] 1.4.1 First Modification of the First Embodiment 1.4.1.1 Drawer Area Structure 27 is a cross-sectional view showing an example of the cross-sectional structure of a lead-out region HA of a memory cell array 10 included in a semiconductor memory device 3 according to a first modification of the first embodiment. In addition to the lead-out region HA corresponding to one block BLK, a part of the nearby memory region MA is also shown in FIG.

[0141] As shown in FIG. 27, the plurality of contacts CC in this modification includes a plurality of contacts CC1 and CC2.

[0142] The contacts CC1 are through contacts that penetrate the upper laminated wiring U and the lower laminated wiring L. The contacts CC1 correspond to the wiring layers 22 and 23 included in the lower laminated wiring L. Each contact CC1 connects one of the wiring layers 22 and 23 to the corresponding wiring layer 28. In this modification, the upper laminated wiring U does not have a terrace portion TER. Therefore, the contacts CC1 are not connected to the upper laminated wiring U.

[0143] By using the contact CC1, even if other wiring layers (for example, wiring layers 24 and 25) are provided above, the contact CC1 can be connected to the desired wiring layer.

[0144] The contacts CC2 are contacts provided on the tread surfaces of the front staircase F_SP provided in the upper laminated wiring U. Each contact CC2 corresponds to one of the wiring layers 24 and 25 included in the upper laminated wiring U. The tread surfaces of the front staircase F_SP formed by each of the wiring layers 24 and 25 function as the respective CC connection portions CCT. Each contact CC2 extends in the Z direction between the tread surfaces of the front staircase F_SP of the wiring layers 24 and 25 and the corresponding wiring layer 28, connecting them together. Each contact CC2 does not penetrate any of the wiring layers 22, 23, 24, and 25 in the Z direction.

[0145] Since no laminated wiring is provided between the CC connection portion CCT of the wiring layers 24 and 25 included in the upper laminated wiring U and the corresponding wiring layer 28, the contact CC2 can be connected to the desired wiring layer without using a through contact.

[0146] In the example shown in FIG. 27, the plurality of wiring layers 24 and 25 included in the upper laminated wiring U are not provided with terrace portions TER, but may be provided with terrace portions TER.

[0147] 1.4.2 Second Modification of the First Embodiment 28 is a cross-sectional view showing an example of the cross-sectional structure of a lead-out region HA of a memory cell array 10 included in a semiconductor memory device 3 according to a second modification of the first embodiment. In addition to the lead-out region HA corresponding to one block BLK, a part of the nearby memory region MA is also shown in FIG.

[0148] As shown in FIG. 28, the plurality of contacts CC in this modification includes a plurality of contacts CC2 and CC3.

[0149] The plurality of contacts CC2 are contacts having the same structure as the plurality of contacts CC2 in the first modification of the first embodiment.

[0150] The contacts CC3 are contacts provided on the treads of the front staircase F_SP provided in the lower laminated wiring L. Each contact CC3 corresponds to one of the wiring layers 22 and 23 included in the lower laminated wiring L. The treads of the front staircase F_SP formed by each of the wiring layers 22 and 23 function as the respective CC connection parts CCT.

[0151] Each contact CC3 includes a first portion CC3a and a second portion CC3b. The first portion CC3a includes a conductor 27a. The conductor 27a extends in the Z direction, contacts the tread of the surface staircase F_SP of the corresponding wiring layer 22 or 23 at its lower surface, and contacts the lower surface of the second portion CC3b at its upper surface. The conductor 27a includes, for example, tungsten. The first portion CC3a does not penetrate any of the wiring layers 22, 23, 24, and 25 in the Z direction. The second portion CC3b is a via contact that penetrates the upper laminated wiring U in the Z direction. The second portion CC3b includes a conductor 27b and an insulator 53. The conductor 27b contacts the conductor 27a of the first portion CC3a at its lower surface and contacts the lower surface of the wiring layer 28 at its upper surface. The insulator 53 is provided in the upper laminated wiring U so as to cover the conductor 27b from the side. The insulator 53 insulates the conductor 27b from the upper multilayer wiring U.

[0152] By using contact CC3, contact CC3 can be connected to the desired wiring layer even when other wiring layers (e.g., wiring layers 24 and 25) are provided above the corresponding wiring layer (e.g., wiring layer 22 or 23).

[0153] 1.4.3 Third Modification of the First Embodiment 29 is a schematic diagram showing an example of a cross-sectional structure of stacked wiring in a lead-out region HA of a memory cell array 10 included in a semiconductor memory device 3 according to a third modification of the first embodiment. For simplicity of explanation, memory pillars MP, contacts CV and wiring layers provided above the stacked wiring, contacts CC, and the like are omitted from FIG.

[0154] 29, the memory cell array 10 included in the semiconductor memory device 3 according to the third modification of the first embodiment includes upper stacked wiring U, middle stacked wiring M, and lower stacked wiring L. The wiring layer 22 corresponding to the select gate line SGS and the wiring layer 23 corresponding to the word lines WL0 to WL4 correspond to the lower stacked wiring L. The wiring layer 29 corresponding to the word lines WL5 to WL10 corresponds to the middle stacked wiring M. The wiring layer 24 corresponding to the word lines WL11 to WL15 and the wiring layer 25 corresponding to the select gate line SGD correspond to the upper stacked wiring U.

[0155] The lead-out region HA includes staircase regions MSTP1 and MSTP2 in addition to staircase regions USTP1, USTP2, LSTP1, and LSTP2. The staircase regions MSTP1 and MSTP2 are regions where the ends of the wiring layer 29 are led out in a staircase shape. The number of staircase regions provided in the middle stacked wiring M is arbitrary. The staircase regions MSTP1 and MSTP2 are included in the staircase region STP and include a double-sided staircase structure.

[0156] The staircase area MSTP1 includes a front staircase area MSTP1a and a back staircase area MSTP1b. The front staircase area MSTP1a and the back staircase area MSTP1b are aligned with each other in the X direction. The front staircase area MSTP1a is provided closer to the memory area MA than the back staircase area MSTP1b.

[0157] The staircase area MSTP2 includes a front staircase area MSTP2a and a back staircase area MSTP2b. The front staircase area MSTP2a and the back staircase area MSTP2b are aligned with each other in the X direction. The front staircase area MSTP2a is provided closer to the memory area MA than the back staircase area MSTP2b.

[0158] The front staircase region and back staircase region of each staircase region are arranged so that two or more front staircase regions do not overlap when viewed in the Z direction. A front staircase region may overlap multiple back staircase regions when viewed in the Z direction. For example, the front staircase region USTP1a is provided above an area where a stair structure is not formed in the middle stacked wiring M and the lower stacked wiring L. The front staircase region MSTP1a is provided below the back staircase region USTP1b. The front staircase region LSTP1a is provided below the back staircase region MSTP1b. The front staircase region USTP2a is provided above the back staircase region LSTP1b. The front staircase region LSTP2a is provided below the back staircase region USTP2b. The front staircase region MSTP2a is provided above the back staircase region LSTP2b. Above and below the back staircase region MSTP2b, a stair structure is not formed in the upper stacked wiring U and the lower stacked wiring L. Note that the above arrangement is an example, and the arrangement of the staircase regions is not limited to this.

[0159] In the third modification of the first embodiment, the stacked wiring is divided into three parts: the upper stacked wiring U, the middle stacked wiring M, and the lower stacked wiring L, and a staircase region STP is provided for each of them, but the number of divisions of the stacked wiring may be four or more.

[0160] Furthermore, the third modified example of the first embodiment may have the same configuration as the first and second modified examples of the first embodiment. For example, in the third modified example, contacts CC1 and CC2, or contacts CC2 and CC3, may be used instead of contact CC.

[0161] 1.4.4 Fourth Modification of the First Embodiment 30 is a plan view showing an example of a planar layout of the upper stacked wiring U in the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the fourth modification of the first embodiment. In FIG. 30, the boundary between the stacked portion LYR and the terrace portion TER of the wiring layer corresponding to each of the word lines WL8 to WL15 is indicated by a dashed line.

[0162] 30, the select gate lines SGD and word lines WL8 to WL15 included in the upper multilayer wiring U are arranged in two rows in the Y direction, with one step in the Y direction and a double-sided staircase structure in the X direction. Although not shown, the word lines WL0 to WL7 included in the lower multilayer wiring L are also arranged in two rows in the Y direction, with one step in the Y direction and a double-sided staircase structure in the X direction.

[0163] Each terrace portion TER of the word lines WL8 to WL14 is spaced apart in the X direction from the side surface of the terrace portion TER of the word line WL or select gate line SGD provided in the second wiring layer above the word line WL. Also, each terrace portion TER of the word line WL(2×i) (i is an integer between 4 and 7) is spaced apart in the Y direction from the side surface of the terrace portion TER of the word line WL provided in the next wiring layer above the word line WL. The terrace portion TER of the second portion WL15f of the word line WL15, which is arranged in parallel in the Y direction with the terrace portion of the second portion SGDf of the select gate line SGD, is spaced apart in the Y direction from the side surface of the terrace portion TER of the second portion SGDf of the select gate line SGD. The terrace portions TER of the select gate line SGD and the word lines WL8 to WL15 function as CC connection portions CCT.

[0164] Although not shown, each terrace portion TER of word lines WL0 to WL5 is similarly spaced in the X direction from the side surface of the terrace portion TER of the word line WL provided in the wiring layer two layers above the word line WL. Also, each terrace portion TER of word line WL(2×j) (j is an integer between 0 and 3) is spaced in the Y direction from the side surface of the terrace portion TER of the word line WL provided in the wiring layer one layer above the word line WL. Each terrace portion TER of word lines WL0 to WL7 functions as a CC connection portion CCT.

[0165] The terrace portions TER of the wiring layer 22 corresponding to the select gate lines SGS are provided, for example, at positions aligned in the X direction with two rows of staircase structures. The terrace portions TER of the wiring layer 22 are spaced apart in the X direction from the side surfaces of the terrace portions TER of the wiring layer 23 provided in the layer immediately above the wiring layer 22 and the wiring layer 23 provided in the layer two above the wiring layer 22.

[0166] In the fourth modification of the first embodiment, the terrace portions TER of each wiring layer are arranged in two rows in the Y direction, but the number of rows in the Y direction may be three or more.

[0167] Furthermore, the fourth modification of the first embodiment may have the same configuration as the first, second, and third modifications of the first embodiment. For example, in the fourth modification, contacts CC1 and CC2, or contacts CC2 and CC3, may be used instead of contact CC. In the fourth modification, the stacked wiring may be divided into three or more parts, and a staircase region STP may be provided in each part.

[0168] 2. Second embodiment Next, a semiconductor memory device 3 according to a second embodiment will be described. The semiconductor memory device 3 according to the second embodiment differs from the semiconductor memory device 3 according to the first embodiment in that the lead-out area HA is provided in the center between two memory areas MA1 and MA2. In the following explanation, explanations of the configuration and manufacturing method equivalent to those of the first embodiment will be omitted, and the configuration and manufacturing method different from those of the first embodiment will be mainly explained.

[0169] 2.1 Configuration 2.1.1 Overview of memory cell array planar layout 31 is a plan view showing an example of a planar layout of the memory cell array 10 included in the semiconductor memory device 3 according to the second embodiment. In FIG. 31, areas corresponding to four blocks BLK0 to BLK3 are shown.

[0170] 31, the planar layout of the memory cell array 10 is divided, for example, in the X direction into memory areas MA1 and MA2 and a lead-out area HA. ​​The memory areas MA1 and MA2 are provided side by side on either side of the lead-out area HA in the X direction.

[0171] The memory cell array 10 includes stacked wiring, a plurality of members SLT, and a plurality of members SHE.

[0172] The plurality of members SLT cross the memory regions MA1 and MA2 and the lead-out region HA in the X direction in the boundary region between adjacent blocks BLK. Each region separated by the members SLT corresponds to one block BLK in the memory cell array 10. Each member SLT has a structure in which, for example, an insulator or a plate-shaped contact is embedded. Each member SLT separates adjacent stacked wirings via the member SLT.

[0173] In this embodiment, among the multiple components SLT lined up in the Y direction, the odd-numbered components SLT are referred to as “SLTo,” and the even-numbered components SLT are referred to as “SLTe.” In the memory cell array 10, multiple pairs of components SLTo and SLTe are lined up in the Y direction.

[0174] A plurality of members SHE are arranged in each of the memory areas MA1 and MA2. The plurality of members SHE corresponding to the memory area MA1 are arranged across the memory area MA1 and aligned in the Y direction. The plurality of members SHE corresponding to the memory area MA2 are arranged across the memory area MA2 and aligned in the Y direction.

[0175] The lead-out region HA includes a plurality of lead-out portions HP and a plurality of bridge portions BRG aligned in the Y direction. Each lead-out portion HP is arranged for every two blocks BLK adjacent in the Y direction with a member SLTe sandwiched between them. In other words, each lead-out portion HP is arranged in the lead-out region HA in an area sandwiched between two members SLTo that sandwich two adjacent blocks BLK between them. Each bridge portion BRG is arranged for every block BLK in an area sandwiched between the member SLTo and the lead-out portion HP in the Y direction.

[0176] 2.1.2 Drawer area (Cross-sectional structure) FIG. 32 is a schematic diagram showing an example of a cross-sectional structure in a lead-out region HA of a memory cell array 10 included in a semiconductor memory device 3 according to the second embodiment. FIG. 33 is a cross-sectional view showing an example of a cross-sectional structure in a lead-out region HA of a memory cell array 10 included in a semiconductor memory device 3 according to the second embodiment. In addition to the lead-out region HA corresponding to one block BLK, parts of the nearby memory regions MA1 and MA2 are also shown in FIGS. 32 and 33. FIG. 32 shows each region of the lead-out region HA of the memory cell array 10. For simplicity of explanation, FIG. 32 omits memory pillars MP, contacts CV and wiring layers provided above stacked wiring, contacts CC, and the like. FIG. 33 shows details of the cross-sectional structure in the lead-out region HA of the memory cell array 10.

[0177] In the second embodiment, the stacked wiring included in the memory cell array 10 includes an upper stacked wiring U and a lower stacked wiring L. The lower stacked wiring L includes a wiring layer 22 corresponding to the select gate line SGS and multiple wiring layers 23 corresponding to the word lines WL0 to WL6. The upper stacked wiring U includes a wiring layer 24 corresponding to the word lines WL7 to WL15. In addition, in the second embodiment, a front staircase F_SP indicates a staircase structure in which some of the multiple wiring layers are drawn down in the X direction from the memory region MA1 side toward the memory region MA2 side. A back staircase B_SP indicates a staircase structure in which some of the multiple wiring layers are drawn up in the X direction from the memory region MA1 side toward the memory region MA2 side.

[0178] 32, the drawer area HA includes, for example, four staircase areas USTP1, USTP2, LSTP1, and LSTP2, and a boundary area MBDY. Each staircase area includes a front staircase area, a back staircase area, and a boundary area BDY provided between the front staircase area and the back staircase area.

[0179] The staircase regions USTP1 and USTP2 are provided in the upper stacked wiring U. The staircase regions USTP1 and USTP2 are regions where the ends of the wiring layers 24 and 25 are drawn out in a staircase shape. The staircase regions LSTP1 and LSTP2 are provided in the lower stacked wiring L. The staircase regions LSTP1 and LSTP2 are regions where the ends of the wiring layers 22 and 23 are drawn out in a staircase shape. The number of staircase regions provided in the upper stacked wiring U and the lower stacked wiring L is arbitrary. Hereinafter, when any of the staircase regions USTP1, USTP2, LSTP1, and LSTP2 is not specified, it will be referred to as the "staircase region STP".

[0180] The stair region STP includes a different height double stair structure. A different height double stair structure is a double stair structure in which the front stair F_SP and the back stair B_SP correspond to different wiring layers. For example, the lowest stair portion (tread) of the front stair F_SP is located in a higher layer than the highest stair portion (tread) of the back stair B_SP. A different height double stair structure is formed, for example, by multi-step processing the portion of the double stair structure corresponding to the back stair B_SP. In this case, the boundaries of the multi-step processing included in the different height double stair structure are collectively referred to as the multi-step processed portion MS. A portion of the multi-step processed portion MS includes a boundary formed by multiple multi-step processing.

[0181] Specifically, the staircase region USTP1 includes a front staircase region USTP1a, a back staircase region USTP1b, and a boundary region BDY. The front staircase region USTP1a, boundary region BDY, and back staircase region USTP1b are aligned in the X direction. In the X direction, the boundary region BDY is provided between the front staircase region USTP1a and the back staircase region USTP1b. The front staircase region USTP1a is provided on the memory region MA1 side, and the back staircase region USTP1b is provided on the memory region MA2 side. The staircase region USTP1 has, for example, a different height double staircase structure provided in five wiring layers 24 corresponding to the word lines WL11 to WL15, respectively. The front staircase F_SP of the front staircase region USTP1a is provided in three wiring layers 24 corresponding to the word lines WL13 to WL15, respectively. The back staircase B_SP of the back staircase region USTP1b is provided in two wiring layers 24 corresponding to the word lines WL11 and WL12, respectively. A multi-stage machining portion MS is provided in the boundary region BDY.

[0182] The staircase region USTP2 includes a front staircase region USTP2a, a back staircase region USTP2b, and a boundary region BDY. The front staircase region USTP2a, boundary region BDY, and back staircase region USTP2b are aligned in the X direction. In the X direction, a boundary region BDY is provided between the front staircase region USTP2a and the back staircase region USTP2b. The front staircase region USTP2a is provided on the memory region MA1 side, and the back staircase region USTP2b is provided on the memory region MA2 side. The staircase region USTP2 has, for example, a different height double staircase structure provided in four wiring layers 24 corresponding to the word lines WL7 to WL10, respectively. The front staircase F_SP of the front staircase region USTP2a is provided in two wiring layers 24 corresponding to the word lines WL9 and WL10, respectively. The back staircase B_SP of the back staircase region USTP2b is provided in two wiring layers 24 corresponding to the word lines WL7 and WL8, respectively. A multi-stage machining portion MS is provided in the boundary region BDY.

[0183] The staircase region LSTP1 includes a front staircase region LSTP1a, a back staircase region LSTP1b, and a boundary region BDY. The front staircase region LSTP1a, boundary region BDY, and back staircase region LSTP1b are aligned in the X direction. In the X direction, a boundary region BDY is provided between the front staircase region LSTP1a and the back staircase region LSTP1b. The front staircase region LSTP1a is provided on the memory region MA1 side, and the back staircase region LSTP1b is provided on the memory region MA2 side. The staircase region LSTP1 has, for example, a different height double staircase structure provided in four wiring layers 23 corresponding to the word lines WL3 to WL6, respectively. The front staircase F_SP of the front staircase region LSTP1a is provided in two wiring layers 23 corresponding to the word lines WL5 and WL6, respectively. The back staircase B_SP of the back staircase region LSTP1b is provided in two wiring layers 23 corresponding to the word lines WL3 to WL4, respectively. A multi-step processed portion MS is provided in the boundary region BDY.

[0184] The staircase region LSTP2 includes a front staircase region LSTP2a, a back staircase region LSTP2b, and a boundary region BDY. The front staircase region LSTP2a, boundary region BDY, and back staircase region LSTP2b are aligned in the X direction. In the X direction, a boundary region BDY is provided between the front staircase region LSTP2a and the back staircase region LSTP2b. The front staircase region LSTP2a is provided on the memory region MA1 side, and the back staircase region LSTP2b is provided on the memory region MA2 side. The staircase region LSTP2 has, for example, a different-height double-sided staircase structure provided in a wiring layer 22 corresponding to the select gate line SGS and three wiring layers 23 corresponding to the word lines WL0 to WL2. The front staircase F_SP of the front staircase region LSTP2a is provided in two wiring layers 23 corresponding to the word lines WL1 and WL2, respectively. The back staircase B_SP of the back staircase region LSTP2b is provided in the wiring layer 22 corresponding to the select gate line SGS and the wiring layer 23 corresponding to the word line WL0. A multi-stage machining portion MS is provided in the boundary region BDY.

[0185] The boundary region MBDY is the region sandwiched in the X direction between the memory region MA and the staircase region STP, and the region sandwiched in the X direction between two staircase regions STP. Specifically, boundary regions MBDY are provided between the memory region MA1 and the staircase region USTP1, between the staircase regions USTP1 and USTP2, and between the staircase region USTP2 and the memory region MA2. Boundary regions MBDY are provided between the memory region MA1 and the staircase region LSTP1, between the staircase regions LSTP1 and LSTP2, and between the staircase region LSTP2 and the memory region MA2. A multi-stage processed portion MS is provided in each boundary region MBDY.

[0186] The front staircase region and back staircase region of each staircase region STP are arranged in positions where they do not overlap each other in the upper stacked wiring U and the lower stacked wiring L when viewed in the Z direction. The front staircase regions USTP1a and USTP2a and back staircase regions USTP1b and USTP2b corresponding to the upper stacked wiring U are not provided above the front staircase regions LSTP1a and LSTP2a and back staircase regions LSTP1b and LSTP2b corresponding to the lower stacked wiring L. In other words, the front staircase regions USTP1a and USTP2a and back staircase regions USTP1b and USTP2b corresponding to the upper stacked wiring U are provided above the boundary region MBDY or BDY in the lower stacked wiring L. The front staircase regions LSTP1a and LSTP2a and back staircase regions LSTP1b and LSTP2b corresponding to the lower stacked wiring L are not provided below the front staircase regions USTP1a and USTP2a and back staircase regions USTP1b and USTP2b corresponding to the upper stacked wiring U. In other words, the front staircase regions LSTP1a and LSTP2a and the back staircase regions LSTP1b and LSTP2b corresponding to the lower multilayer wiring L are provided below the boundary region MBDY or BDY in the upper multilayer wiring U.

[0187] For example, the front staircase region USTP1a is provided above the boundary region MBDY of the lower stacked wiring L. The front staircase region LSTP1a is provided below the boundary region BDY of the staircase region USTP1. The back staircase region USTP1b is provided above the boundary region BDY of the staircase region LSTP1. The back staircase region LSTP1b is provided below the boundary region MBDY of the upper stacked wiring U. The front staircase region USTP2a is provided above the boundary region MBDY of the lower stacked wiring L. The front staircase region LSTP2a is provided below the boundary region BDY of the staircase region USTP2. The back staircase region USTP2b is provided above the boundary region BDY of the staircase region LSTP2. The back staircase region LSTP2b is provided below the boundary region MBDY of the upper stacked wiring U.

[0188] As shown in FIG. 33, the memory cell array 10 further includes a plurality of contacts CC, a wiring layer 28, and a stop member SPF in the lead-out region HA.

[0189] The contacts CC are, for example, through contacts. The contacts CC are provided corresponding to the select gate lines SGS and SGD and the word lines WL0 to WL15, respectively. In the example shown in FIG. 33, the contacts CC correspond, in order from the memory region MA1 side, to the select gate line SGD, the word lines WL15, WL14, WL13, WL6, WL5, WL11, WL12, WL3, WL4, WL10, WL9, WL2, WL1, WL7, WL8, the select gate line SGS, the word line WL0, and the select gate line SGD. Each contact CC extends in the Z direction. Each contact CC penetrates (passes through) in the Z direction through a wiring layer among the wiring layers 22, 23, 24, and 25 that is provided at the position where the contact CC is provided in a plan view, and an insulating layer (not shown). The lower surface of each contact CC is in contact with the stopping member SPF.

[0190] Each contact CC, except for the contact CC corresponding to the select gate line SGD, penetrates one staircase region STP in the Z direction. Each contact CC is connected to one of the CC connection portions CCT of the wiring layers 22, 23, and 24 in the staircase region STP that it passes through in the Z direction.

[0191] Each contact CC is provided to penetrate a CC connection portion CCT of any one of the wiring layers 22, 23, 24, or 25 in the Z direction, and is connected to the wiring layer at its side surface. Each contact CC corresponds to the wiring layer 22, 23, 24, or 25 to which it is connected at the CC connection portion CCT.

[0192] Specifically, in the back staircase region LSTP2b of the staircase region LSTP2, CC connection portions CCT are provided for the wiring layer 22 corresponding to the select gate line SGS and the wiring layer 23 corresponding to the word line WL0. In the front staircase region LSTP2a of the staircase region LSTP2, CC connection portions CCT are provided for each of the two wiring layers 23 corresponding to the word lines WL1 and WL2, respectively. In the back staircase region LSTP1b of the staircase region LSTP1, CC connection portions CCT are provided for each of the two wiring layers 23 corresponding to the word lines WL3 and WL4, respectively. In the front staircase region LSTP1a of the staircase region LSTP1, CC connection portions CCT are provided for each of the two wiring layers 23 corresponding to the word lines WL5 and WL6, respectively. In the back staircase region USTP2b of the staircase region USTP2, CC connection portions CCT are provided for each of the two wiring layers 24 corresponding to the word lines WL7 and WL8, respectively. In the front staircase region USTP2a of the staircase region USTP2, CC connection portions CCT of two wiring layers 24 corresponding to word lines WL9 and WL10, respectively, are provided. In the back staircase region USTP1b of the staircase region USTP1, CC connection portions CCT of two wiring layers 24 corresponding to word lines WL11 and WL12, respectively, are provided. In the front staircase region USTP1a of the staircase region USTP1, CC connection portions CCT of three wiring layers 24 corresponding to word lines WL13 to WL15, respectively, are provided. Different contacts CC are connected to each CC connection portion CCT. Note that the configuration of the contacts CC is not limited to the above configuration, as long as they are through contacts connected to the corresponding CC connection portions CCT of each wiring layer and insulated from other wiring layers.

[0193] Fig. 34 is an enlarged view of region XXXIV in Fig. 33. Fig. 34 corresponds to a cross-sectional view of the staircase region USTP1. Details of the connection between the contacts CC and the CC connection portions CCT, and the multi-step processed portion MS will be described using Fig. 34.

[0194] 34, the wiring layer 24 includes a stacked portion LYR and a terrace portion TER, as do the wiring layers 22, 23, and 25 (not shown).

[0195] For example, the terrace portion TER is provided on the tread surface of either the front staircase F_SP or the back staircase B_SP. The terrace portion TER is not provided in the boundary region BDY. One terrace portion TER is provided in each of the wiring layers 22, 23, and 24. The structures of the stack portion LYR and the terrace portion TER are the same as those in the first embodiment. The terrace portion TER functions as the CC connection portion CCT.

[0196] The multi-step processed portion MS is provided in the boundary region MBDY or the boundary region BDY of each staircase region STP. The multi-step processed portion MS may be located anywhere in the boundary region MBDY or BDY as long as it does not interfere with the formation of the contacts CC and other components. The multi-step processed portion MS may include, for example, a sloped surface with a downward inclination.

[0197] (flat layout) 35 is a plan view showing a planar layout of upper stacked wiring U in a lead-out region HA of a memory cell array 10 included in a semiconductor memory device 3 according to the second embodiment. FIG. 36 is a plan view showing a planar layout of lower stacked wiring L in a lead-out region HA of a memory cell array 10 included in a semiconductor memory device 3 according to the second embodiment. The lead-out region HA and parts of nearby memory regions MA1 and MA2 are shown in FIGS. 35 and 36. For ease of explanation, stacked portions LYR and terrace portions TER of each wiring layer are omitted in FIGS. 35 and 36.

[0198] As shown in FIG. 35, the select gate line SGD includes a first portion SGDa connected to memory area MA1 and a second portion SGDb connected to memory area MA2. The first portion SGDa and the second portion SGDb of the select gate line SGD are insulated from each other. The select gate line SGD also has portions in the first portion SGDa and the second portion SGDb that are divided in the Y direction by multiple members SHE. In each block BLK, the first portion SGDa of the select gate line SGD divided by three members SHE is referred to as select gate lines SGD0a to SGD3a from the top of the page. The select gate lines SGD0a to SGD3a are insulated from each other by multiple members SHE. The second portion SGDb of the select gate line SGD divided by three members SHE is referred to as select gate lines SGD0b to SGD3b from the top of the page. That is, in one block BLK, the select gate line SGD is divided into eight portions. One contact CC is provided for each of the eight divided select gate lines SGD.

[0199] As shown in FIGS. 35 and 36, in each staircase region STP, the differential height double staircase structure is provided so as to straddle the member SLTe, and has a structure symmetrical with respect to the member SLTe.

[0200] As shown in FIG. 35, each lead-out portion HP includes multi-stage processing boundaries MSBD1, MSBD2, and MSBD3 in the upper stacked wiring U. The multi-stage processing boundaries MSBD1, MSBD2, and MSBD3 are steps that are rectangular in plan view and include ends of multiple consecutive wiring layers. Note that in FIG. 35, to clarify the steps, the ends of each wiring layer having a step are shown side by side. The multi-stage processing boundaries MSBD1, MSBD2, and MSBD3 are formed by multi-stage processing. The multi-stage processing boundaries MSBD1, MSBD2, and MSBD3 are provided for each lead-out portion HP.

[0201] The multi-step processing boundary MSBD1 is a step formed by the side surfaces of two wiring layers. The multi-step processing boundary MSBD1 is provided across the member SLTe so as to surround the terrace portions TER of the word lines WL11 and WL12. The multi-step processing boundary MSBD1 includes the multi-step processed portion MS.

[0202] The multi-step processing boundary MSBD2 is a step consisting of a side surface equivalent to two wiring layers. The multi-step processing boundary MSBD2 is provided across the member SLTe so as to surround the terrace portions TER of the word lines WL7 and WL8. The multi-step processing boundary MSBD2 includes the multi-step processed portion MS.

[0203] The multi-step processing boundary MSBD3 is a step consisting of side surfaces equivalent to four wiring layers, and is provided across the member SLTe so as to surround the terrace portions TER of the word lines WL7 to WL10 and the multi-step processing boundary MSBD2. The multi-step processing boundary MSBD3 includes the multi-step processed portion MS.

[0204] As shown in FIG. 36, each lead-out portion HP includes multi-stage processing boundaries MSBD4, MSBD5, and MSBD6 in the lower laminated wiring L. The multi-stage processing boundaries MSBD4, MSBD5, and MSBD6 are steps that are rectangular in plan view and include ends of multiple consecutive wiring layers. Note that in FIG. 36, to clarify the steps, the ends of each wiring layer having a step are shown side by side. The multi-stage processing boundaries MSBD4, MSBD5, and MSBD6 are formed by multi-stage processing. The multi-stage processing boundaries MSBD4, MSBD5, and MSBD6 are provided for each lead-out portion HP.

[0205] The multi-step processing boundary MSBD4 is a step consisting of a side surface equivalent to two wiring layers. The multi-step processing boundary MSBD4 is provided across the member SLTe so as to surround the terrace portions TER of the word lines WL3 and WL4. The multi-step processing boundary MSBD4 includes the multi-step processed portion MS.

[0206] The multi-level processing boundary MSBD5 is a step formed by the side surfaces of two wiring layers. The multi-level processing boundary MSBD5 is provided across the member SLTe so as to surround the terrace portions TER of the select gate line SGS and the word line WL0. The multi-level processing boundary MSBD5 includes the multi-level processing portion MS.

[0207] The multi-stage processing boundary MSBD6 is a step having a side surface equivalent to four wiring layers, and is provided across the member SLTe so as to surround the terrace portions TER of the select gate lines SGS and the word lines WL0 to WL2, and the multi-stage processing boundary MSBD5. The multi-stage processing boundary MSBD6 includes the multi-stage processing portion MS.

[0208] Next, as an example of a wiring layer in which a terrace portion TER is provided in the back staircase B_SP, a planar layout of the wiring layer 24 corresponding to the word line WL12 will be described. FIG. 37 is a plan view showing an example of a plane taken along line XXXVII-XXXVII in FIG. 33 in the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the second embodiment. FIG. 37 corresponds to the planar structure of the wiring layer 24 corresponding to the word line WL12. FIG. 37 shows the lead-out region HA and parts of the nearby memory regions MA1 and MA2. In FIG. 37, the wiring layer 24 corresponding to the word line WL12 is hatched, and the boundary between the stack portion LYR and the terrace portion TER is indicated by a dashed line. In the second embodiment, the part of the wiring layer in which the back staircase B_SP is provided is connected to other parts of the wiring layer.

[0209] As shown in FIG. 37, the word line WL12 includes a first portion WL12_1, a second portion WL12_2, a third portion WL12_3, and a connection portion WL12_c. The first portion WL12_1 includes a memory area MA1. The second portion WL12_2 includes a memory area MA2. The third portion WL12_3 includes a terrace portion TER. The third portion WL12_3 is provided between the first portion WL12_1 and the second portion WL12_2 in the X direction. An insulating layer (not shown) is interposed between the first portion WL12_1 and the third portion WL12_3 and between the second portion WL12_2 and the third portion WL12_3. The connection portion WL12_c is provided in the bridge portion BRG. The first portion WL12_1, the second portion WL12_2, and the third portion WL12_3 are connected to each other via the connection portion WL12_c provided in the bridge portion BRG. That is, the word line WL12 is not divided in the X direction between the memory areas MA1 and MA2.

[0210] The word line WL12 is connected to the conductor 27 of the contact CC corresponding to the word line WL12 in the terrace portion TER provided in the third portion WL12_3. That is, a voltage corresponding to the word line WL12 is applied to the word line WL12 from the row decoder module 15 via the contact CC. The contact CC supplies a voltage (current) to the memory areas MA1 and MA2 via the terrace portion TER provided in the back staircase B_SP. That is, the terrace portion TER provided in the back staircase B_SP functions as a path for supplying a voltage (current) to the memory areas MA1 and MA2.

[0211] Similarly, the select gate line SGS and other word lines WL0 to WL11, WL13 to WL15 are each connected to both the memory areas MA1 and MA2 via connection portions provided in the bridge portion BRG. Each of the plurality of contacts CC supplies a voltage (current) to the memory areas MA1 and MA2 via the terrace portion TER of the corresponding select gate line SGS or word line WL0 to WL13 or WL15.

[0212] 2.2 Manufacturing method of the pull-out area 38 to 45 each show an example of a cross-sectional structure during the manufacturing process of the memory cell array 10 included in the semiconductor memory device 3 according to the second embodiment. The cross-sectional structures shown in FIGS. 38 to 45 show the region corresponding to FIG. 33. A method for manufacturing the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the second embodiment is similar to the method for manufacturing the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment shown in FIG. 12. Below, differences from the first embodiment will be described with appropriate reference to the flowchart shown in FIG. 12 and FIGS. 38 to 45.

[0213] First, through the processes of S101 and S102, the staircase structure of the lower stack structure shown in FIG. 38 is formed.

[0214] Thereafter, in S103, in this embodiment, multi-stage machining is performed twice.

[0215] First, as shown in Figure 39, a first multi-step processing is performed on one stair structure (back stair) of the double-sided stair structure. Specifically, multi-step processing is performed on the portions corresponding to the multi-step processing boundaries MSBD4 and MSBD5. By the first multi-step processing, the back stair B_SP is processed to correspond to a wiring layer lower than the front stair F_SP, and a different height double-sided stair structure is formed. By the first multi-step processing, multi-step processed portions MS are formed in the corresponding boundary regions MBDY and BDY, respectively.

[0216] Next, as shown in FIG. 40, a second multi-step processing is performed on the different height type double staircase structure formed in the staircase region LSTP2. Specifically, multi-step processing is performed on the portion corresponding to the multi-step processing boundary MSBD6. By the second multi-step processing, the different height type double staircase structure formed in the staircase region LSTP2 is processed so that it corresponds to a wiring layer lower than the different height type double staircase structure formed in the staircase region LSTP1. By the second multi-step processing, multi-step processed portions MS are formed in the corresponding boundary regions MBDY.

[0217] Next, in S104, as shown in FIG. 41, a portion corresponding to the terrace portion TER of the lower stacked structure is formed.

[0218] Specifically, in the staircase regions LSTP1 and LSTP2, the insulator layer 43 exposed on the upper surface of the differential height double staircase structure is removed. Then, in the portion from which the insulator layer 43 was removed, sacrificial members corresponding to the sacrificial members 42 and 44 are formed and thickened. In the thickened portions, the thicknesses of the sacrificial members 42 and 44 in the Z direction become equal to the second thickness D2. Then, the sacrificial member formed on the uppermost insulator layer 43 is removed. Furthermore, in this embodiment, of the thickened portions of the sacrificial members 42 and 44, in addition to the portions that contact the side surfaces of the sacrificial member 44 provided in the layer one layer above the sacrificial member 42 or 44 via the insulator layer 43, the portions provided in the boundary region BDY are removed.

[0219] The staircase regions LSTP1 and LSTP2 of the lower stack are then filled with an insulating layer 45.

[0220] Next, through steps S105 to S108, an upper stacked structure is formed, and in the staircase regions USTP1 and USTP2, a different height type double staircase structure is formed, and a terrace portion TER is formed. Below, the parts that differ from the processing in the lower stacked structure will be described.

[0221] In S106, in this embodiment, when the staircase structure of the upper stack structure is formed, after a double-sided staircase structure is formed in the staircase regions USTP1 and USTP2 of the lead-out portion HP, as shown in FIG. 42, a single-step staircase structure is formed in the sacrificial material 46 corresponding to the word line WL15. Specifically, a mask is formed by photolithography or the like, which opens the processing region HPA excluding the portion of the lead-out region HA corresponding to the select gate line SGD. Then, the sacrificial material 48 and the insulator layer 49 are removed by anisotropic etching using the mask. This separates the sacrificial material 48 on the memory region MA1 side from the sacrificial material 48 on the memory region MA2 side in the X direction. Note that after processing the staircase structure of the sacrificial material 46 corresponding to the word line WL15, a double-sided staircase structure may be formed in the staircase regions USTP1 and USTP2.

[0222] Next, in S107, in this embodiment, multi-stage machining is performed twice.

[0223] First, as shown in Figure 43, a first multi-step processing is performed on one stair structure (back stair) of the double-sided stair structure. Specifically, multi-step processing is performed on the portions corresponding to the multi-step processing boundaries MSBD1 and MSBD2. By the first multi-step processing, the back stair B_SP is processed to correspond to a wiring layer lower than the front stair F_SP, and a different height double-sided stair structure is formed. By the first multi-step processing, multi-step processed portions MS are formed in the corresponding boundary regions MBDY and BDY, respectively.

[0224] Next, as shown in FIG. 44, a second multi-step processing is performed on the different height type double staircase structure formed in the staircase region USTP2. Specifically, multi-step processing is performed on the portion corresponding to the multi-step processing boundary MSBD3. By the second multi-step processing, the different height type double staircase structure formed in the staircase region USTP2 is processed so that it corresponds to a wiring layer lower than the different height type double staircase structure formed in the staircase region USTP1. By the second multi-step processing, multi-step processed portions MS are formed in the corresponding boundary regions MBDY.

[0225] Next, in S108, as shown in FIG. 45, a portion corresponding to the terrace portion TER of the upper stacked structure is formed.

[0226] Specifically, in the staircase regions USTP1 and USTP2, the insulator layers 47 and 49 exposed on the upper surface of the differential height double staircase structure are removed. Then, in the portions from which the insulator layers 47 and 49 have been removed, sacrificial members corresponding to the sacrificial members 46 and 48 are formed and thickened. In the thickened portions, the thicknesses of the sacrificial members 46 and 48 in the Z direction become equal to the second thickness D2. Then, the sacrificial member formed on the uppermost insulator layer 49 is removed. Furthermore, in this embodiment, of the thickened portions of the sacrificial members 46 and 48, in addition to the portions that contact the side surfaces of the sacrificial member 46 or 48 provided in the layer immediately above the sacrificial member 46 or 48 via the insulator layer 47, the portions provided in the boundary regions MBDY and BDY are also removed.

[0227] Thereafter, the processes of S109 to S117 are carried out, which are the same as those in the first embodiment.

[0228] The structure of the lead-out region HA in the memory cell array 10 is formed by the manufacturing process described above. Note that the manufacturing process described above is merely an example and is not limited to this. For example, other processes may be inserted between each manufacturing process, or some processes may be omitted or integrated. Furthermore, each manufacturing process may be interchanged to the extent possible.

[0229] 2.3 Effects of the Second Embodiment According to the second embodiment, similarly to the first embodiment, it is possible to provide a semiconductor memory device that requires fewer manufacturing steps and has a reduced chip area.

[0230] Specifically, the memory cell array 10 according to the second embodiment can have CC connection parts CCT above or below the boundary regions MBDY and BDY of the stacked wiring, which can prevent the memory cell array 10 from increasing in length in the X direction by the boundary regions MBDY and BDY of the stacked wiring, thereby reducing (suppressing expansion of) the chip area of ​​the semiconductor memory device 3.

[0231] Furthermore, in the memory cell array 10 according to the second embodiment, memory regions MA1 and MA2 are provided on both sides of the lead-out region in the X direction. Therefore, the memory pillars MP can be efficiently distributed and arranged in the memory regions MA1 and MA2, allowing for an increase in the number of memory pillars MP per chip area. Therefore, it is possible to provide a large-capacity semiconductor memory device 3 while preventing an increase in chip area.

[0232] Furthermore, in the memory cell array 10 according to the second embodiment, it is possible to suppress the extension of the bridge portion BRG in the X direction. Therefore, it is possible to suppress the extension of the wiring length of the circuit, which depends on the length of the bridge portion BRG, and it is possible to suppress an increase in electrical resistance in the memory cell array 10.

[0233] 2.4 Modification of the second embodiment The semiconductor memory device 3 according to the second embodiment described above can be modified in various ways. Differences between the first, second, third, and fourth modifications of the second embodiment and the second embodiment will be described below.

[0234] 2.4.1 First variant 46 is a plan view showing an example of a planar layout of the upper stacked wiring U in the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the first modification of the second embodiment. In addition to the lead-out region HA corresponding to one block BLK, parts of the nearby memory regions MA1 and MA2 are also shown in FIG. 46. For the sake of simplicity, the stacked portion LYR and terrace portion TER of each wiring layer are omitted in FIG.

[0235] 46, in this modification, a lead-out portion HP is provided for each block BLK. A different height staircase structure corresponding to the CC connection portions CCT of the word lines WL7 to WL14 in the upper stacked wiring U is formed for each lead-out portion HP. Meanwhile, as in the second embodiment, multi-stage processing is performed for each two blocks BLK adjacent in the Y direction with the member SLTe sandwiched between them. Multi-stage processing boundaries MSBD1, MSBD2, and MSBD3 are provided across the two lead-out portions HP adjacent in the Y direction so as to straddle the member SLTe.

[0236] Although not shown, a different height staircase structure corresponding to the CC connection portions CCT of the select gate lines SGS and the word lines WL0 to WL6 is also formed for each lead-out portion HP in the lower stacked wiring L. Meanwhile, the multi-step processing boundaries MSBD4, MSBD5, and MSBD6 are provided across two lead-out portions HP adjacent to each other in the Y direction so as to straddle the member SLTe.

[0237] 2.4.2 Second variant 47 is a plan view showing an example of a planar layout of the upper stacked wiring U in the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the second modification of the second embodiment. In addition to the lead-out region HA corresponding to one block BLK, parts of the nearby memory regions MA1 and MA2 are also shown in FIG. 47. For the sake of simplicity, the stacked portion LYR and terrace portion TER of each wiring layer are omitted in FIG.

[0238] 47, in this modification, the different height staircase structure corresponding to the CC connection portions CCT of the word lines WL7 to WL14 in the upper stacked wiring U is provided across all the blocks BLK of the memory cell array 10. Meanwhile, similar to the second embodiment, the multi-stage processing is performed for every two blocks BLK adjacent to each other in the Y direction with the member SLTe in between. Multi-stage processing boundaries MSBD1, MSBD2, and MSBD3 are provided for each lead-out portion HP.

[0239] In the configuration shown in the second modified example, the word lines WL14 and WL15 are divided into first portions WL14_1 and WL15_1 connected to the memory area MA1, second portions WL14_2 (not shown) and WL15_2 connected to the memory area MA2, and third portions WL14_3 and WL15_3 not connected to either the memory areas MA1 or MA2. The first portion WL14_1 and the second portion WL14_2 are connected to each other via upper layer wiring (not shown). The third portion WL14_3 may be connected to the first portion WL14_1 and the second portion WL14_2 via upper layer wiring (not shown). The first portion WL15_1 and the second portion WL15_2 are connected to each other via upper layer wiring (not shown). The third portion WL15_3 may be connected to the first portion WL15_1 and the second portion WL15_2 via upper layer wiring (not shown).

[0240] Although not shown, the lower stacked wiring L also has a different height staircase structure corresponding to the CC connection portions CCT of the select gate lines SGS and the word lines WL0 to WL6, which is provided across all the blocks BLK of the memory cell array 10. Meanwhile, similar to the second embodiment, the multi-stage processing is performed for every two blocks BLK adjacent to each other in the Y direction with the member SLTe in between. Multi-stage processing boundaries MSBD4, MSBD5, and MSBD6 are provided for each lead-out portion HP.

[0241] Some wiring layers included in the lower multilayer wiring L are divided into a first portion connected to memory region MA1, a second portion connected to memory region MA2, and a third portion connected to neither memory region MA1 nor MA2. In each divided wiring layer, the first portion and the second portion are connected to each other via upper layer wiring (not shown). In addition, in each divided wiring layer, the third portion may be connected to the first and second portions via upper layer wiring (not shown).

[0242] 2.4.3 Third variant 48 is a schematic diagram showing an example of a cross-sectional structure in a lead-out region HA of a memory cell array 10 included in a semiconductor memory device 3 according to a third modification of the second embodiment. For simplicity of explanation, memory pillars MP, contacts CV and wiring layers provided above stacked wiring, contacts CC, etc. are omitted from FIG.

[0243] 48, in this modification, two different height staircase structures corresponding to the CC connection portions CCT of the word lines WL7 to WL14 in the upper stacked wiring U are provided so that the staircase structure near the boundary region MBDY corresponds to the CC connection portion CCT of the upper wiring layer. Specifically, for example, the CC connection portions CCT of the word lines WL13 to WL15 are provided in the back staircase region USTP1b. The CC connection portions CCT of the word lines WL11 and WL12 are provided in the front staircase region USTP2a. The CC connection portions CCT of the word lines WL9 and WL10 are provided in the back staircase region USTP2b. The CC connection portions CCT of the word lines WL7 and WL8 are provided in the front staircase region USTP1a.

[0244] In the lower multilayer wiring L, two different height staircase structures corresponding to the CC connection portions CCT of the select gate line SGS and the word lines WL0 to WL6 are provided so that the staircase structure near the boundary region MBDY corresponds to the CC connection portion CCT of the upper wiring layer. Specifically, for example, in the back staircase region USTP1b, the CC connection portions CCT of the word lines WL5 and WL6 are provided. In the front staircase region USTP2a, the CC connection portions CCT of the word lines WL3 and WL4 are provided. In the back staircase region USTP2b, the CC connection portions CCT of the word lines WL1 and WL2 are provided. In the front staircase region USTP1a, the CC connection portion CCT of the select gate line SGS and the word line WL0 is provided.

[0245] 2.4.4 Fourth Variant 49 is a plan view showing an example of a planar layout of the upper stacked wiring U in the lead-out region HA of the memory cell array 10 included in the semiconductor memory device 3 according to the fourth modification of the second embodiment. In addition to the lead-out region HA corresponding to one block BLK, parts of the nearby memory regions MA1 and MA2 are also shown in FIG. 49. For the sake of simplicity, the stacked portion LYR and terrace portion TER of each wiring layer are omitted in FIG.

[0246] 49 shows a memory cell array 10 according to the fourth modification of the second embodiment having 31 word lines WL. In this case, the lower multilayer wiring L includes the select gate lines SGS and the word lines WL0 to WL14, and the upper multilayer wiring U includes the word lines WL15 to WL30.

[0247] 49, the word lines WL15 to WL30 included in the upper multilayer wiring U are arranged in two rows in the Y direction, with one step in the Y direction and a double-sided staircase structure in the X direction. Although not shown, the select gate lines SGS and word lines WL0 to WL14 included in the lower multilayer wiring L are also arranged in two rows in the Y direction, with one step in the Y direction and a double-sided staircase structure in the X direction.

[0248] In the fourth modification of the second embodiment, the terrace portions TER of each wiring layer are arranged in two rows in the Y direction, but the number of rows in the Y direction may be three or more.

[0249] 2.4.5 Other Variations Although the first to fourth modified examples of the second embodiment have been described above, various other modified examples are also conceivable.

[0250] For example, the shape of the contacts CC may be changed in the same manner as in the first and second modifications of the first embodiment, and the difference in the structure of the memory cell array 10 in this case is in accordance with the first and second modifications of the first embodiment.

[0251] Furthermore, similarly to the third modification of the first embodiment, the stacked wiring may be divided into three or more parts, and each part may be provided with a staircase region STP. In this case, the difference in the structure of the memory cell array 10 is in accordance with the third modification of the first embodiment.

[0252] 3. Other In the first and second embodiments and their modified examples described above, four or six staircase regions STP are provided, but the number of staircase regions STP is not limited to this. For example, seven or more staircase regions STP may be provided.

[0253] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0254] 1. Memory system 2...Memory controller 3...Semiconductor memory device 10...Memory cell array 11...Command register 12...Address register 13...Sequencer 14...Driver module 15...Row decoder module 16...Sense amplifier module 20...Semiconductor substrate 21~26, 28, 29...wiring layer 27, 27a, 27b...Conductor 30...Core membrane 31...Semiconductor film 32...Laminated film 33...Tunnel insulating film 34...Charge storage film 35...Block insulating film 41, 43, 45, 47, 49, 50, INS...Insulator layers 42, 44, 46, 48, 52...Sacrificial members 51, 53...Insulator B_SP…back stairs BDY, MBDY…boundary area BL...bit line BLK...Block BRG: Bridge section CC, CC1, CC2, CC3, CV, LI…Contact CH…Hall CU: Cell unit F_SP…front stairs HA…Drawer area HP…Drawer part HPA…Processing area L: Lower layered wiring LMP...lower pillar LSTP1a, LSTP2a, MSTP1a, MSTP2a, USTP1a, USTP2a...Table stairs area LSTP1b, LSTP2b, MSTP1b, MSTP2b, USTP1b, USTP2b...Back staircase area LYR...Laminated part M: Middle laminated wiring MA, MA1, MA2...Memory area MP…Memory Pillar MS…Multi-stage machining section MSBD1, MSBD2, MSBD3, MSBD4, MSBD5, MSBD6...Multi-stage machining boundary MT...Memory cell transistor NS...NAND string SGD, SGS...Select gate lines SH...Slit SHE, SLT, SLTe, SLTo...components SL...Source line SP...Spacer SPF: Stopping member ST: Select transistor STP (LSTP1, LSTP2, MSTP1, MSTP2, USTP1, USTP2)...Stairs area SU...String unit TER…Terrace area U: Upper layer wiring UMP...Upper pillar WL...word line

Claims

1. a first wiring layer having a first region and a second region aligned in a second direction intersecting the first direction when viewed in a first direction; a plurality of second wiring layers provided above the first wiring layer and spaced apart from one another in the first direction, the second wiring layers including a first staircase region in the first region; wherein each of the plurality of second wiring layers has a plurality of first terrace portions provided in the first staircase region so as not to overlap with an upper second wiring layer in the first direction; a plurality of third wiring layers provided above the plurality of second wiring layers and spaced apart from one another in the first direction, the third wiring layers including second staircase regions aligned with the first staircase region in the first direction in the first region and having portions overlapping the first staircase region; wherein each of the plurality of third wiring layers has a plurality of second terrace portions provided in the second staircase region so as not to overlap with an upper third wiring layer in the first direction; a first memory pillar extending in the first direction in the second region, one end of which contacts the first wiring layer, and which passes through the plurality of second wiring layers and the plurality of third wiring layers; a first contact extending in the first direction at a position in the first region where the first staircase region and the second staircase region overlap, one end of which is located between the first wiring layer and the plurality of second wiring layers, passing through one of the plurality of second terrace portions, and electrically connected to one of the plurality of first terrace portions; A semiconductor memory device comprising:

2. a second contact extending in the first direction at a position in the first region where the first staircase region and the second staircase region overlap, one end of which is located between the first wiring layer and the plurality of second wiring layers, passing through one of the plurality of first terrace portions, and electrically connected to one of the plurality of second terrace portions; 2. The semiconductor memory device according to claim 1.

3. the first staircase region includes a first sub-staircase region and a second sub-staircase region aligned in the second direction, The plurality of first terrace portions are a plurality of third terrace portions provided in the first sub-staircase region so as to descend from the second region in the second direction; a plurality of fourth terrace portions provided in the second sub-staircase region so as to ascend from the second region in the second direction; Including, the second staircase region includes a third sub-staircase region and a fourth sub-staircase region aligned in the second direction, The plurality of second terrace portions are a plurality of fifth terrace portions provided in the third sub-staircase region so as to descend in a direction away from the second region in the second direction; a plurality of sixth terrace portions provided in the fourth sub-staircase region so as to ascend in a direction away from the second region in the second direction; Including, a third terrace portion and a fourth terrace portion corresponding to one of the plurality of second wiring layers are electrically insulated from each other; a fifth terrace portion and a sixth terrace portion corresponding to one of the plurality of third wiring layers are electrically insulated from each other; 2. The semiconductor memory device according to claim 1.

4. the first sub-staircase region and the second sub-staircase region are arranged in this order in a direction away from the second region in the second direction, the third sub-staircase region and the fourth sub-staircase region are arranged in this order in a direction away from the second region in the second direction; 4. The semiconductor memory device according to claim 3.

5. The first sub-staircase region and the fourth sub-staircase region are provided at positions overlapping each other in the first direction.

4. The semiconductor memory device according to claim 3.

6. The second sub-staircase region and the third sub-staircase region are provided at positions overlapping each other in the first direction.

4. The semiconductor memory device according to claim 3.

7. each of the plurality of first terrace portions is thicker in the first direction than other portions of the plurality of second wiring layers; each of the second terrace portions is thicker in the first direction than other portions of the third wiring layers; 2. The semiconductor memory device according to claim 1.

8. the first contact is electrically connected to one of the plurality of third terrace portions and one of the plurality of sixth terrace portions at a position where the first sub-staircase region and the fourth sub-staircase region overlap in the first direction; 6. The semiconductor memory device according to claim 5.

9. a second contact extending in the first direction at a position in the first region where the first staircase region and the second staircase region overlap, one end of which is located between the first wiring layer and the plurality of second wiring layers, passing through one of the plurality of first terrace portions, and electrically connected to one of the plurality of second terrace portions; the second contact is electrically connected to one of the plurality of fourth terrace portions and one of the plurality of fifth terrace portions at a position where the second sub-staircase region and the third sub-staircase region overlap in the first direction; 7. The semiconductor memory device according to claim 6.

10. the fifth terrace portion and the sixth terrace portion corresponding to the wiring layer provided in the lowest layer of the plurality of third wiring layers are electrically connected to each other; 4. The semiconductor memory device according to claim 3.

11. a first wiring layer having a first region and a second region aligned in a second direction intersecting the first direction when viewed in a first direction; wherein the first region includes a third region and a fourth region aligned in a third direction intersecting the first direction and the second direction, a plurality of second wiring layers provided above the first wiring layer and spaced apart from one another in the first direction, the second wiring layers including a first staircase region in the third region; wherein each of the plurality of second wiring layers has a plurality of first terrace portions provided in the first staircase region so as not to overlap with an upper second wiring layer in the first direction; a plurality of third wiring layers provided above the plurality of second wiring layers and spaced apart from one another in the first direction, the third wiring layers including second staircase regions aligned with the first staircase region in the first direction in the third region and having a portion overlapping the first staircase region; wherein the second staircase region includes a first sub-staircase region, a second sub-staircase region, and a first boundary region provided so as to be sandwiched between the first sub-staircase region and the second sub-staircase region in the second direction; each of the plurality of third wiring layers has a plurality of second terrace portions provided in the second staircase region so as not to overlap with an upper third wiring layer in the first direction; the plurality of second terrace portions include a plurality of third terrace portions provided in the first sub-staircase region so as to descend from the second region in the second direction, and a plurality of fourth terrace portions provided in the second sub-staircase region so as to ascend from the second region in the second direction, some consecutive wiring layers among the plurality of third wiring layers have cut surfaces that intersect with the second direction in the first boundary region; a first memory pillar extending in the first direction in the second region, one end of which contacts the first wiring layer, and which passes through the plurality of second wiring layers and the plurality of third wiring layers; a first contact extending in the first direction at a position in the third region where the first staircase region and the first boundary region overlap, one end of which is located between the first wiring layer and the plurality of second wiring layers, which passes through the plurality of third wiring layers, and which is electrically connected to one of the plurality of first terrace portions; Equipped with Semiconductor memory device.

12. the first staircase region includes a third sub-staircase region, a fourth sub-staircase region, and a second boundary region provided so as to be sandwiched between the third sub-staircase region and the fourth sub-staircase region in the first direction, The plurality of first terrace portions are a plurality of fifth terrace portions provided in the third sub-staircase region so as to descend in a direction away from the second region in the second direction; a plurality of sixth terrace portions provided in the fourth sub-staircase region so as to ascend in a direction away from the second region in the second direction; Including, some consecutive wiring layers among the plurality of second wiring layers have cut surfaces that intersect with the second direction in the second boundary region; a second contact extending in the first direction at a position in the third region where the second boundary region and the second staircase region overlap, one end of which is located between the first wiring layer and the plurality of second wiring layers, passing through the plurality of second wiring layers, and electrically connected to one of the plurality of second terrace portions; 12. The semiconductor memory device according to claim 11.

13. the first wiring layer further includes a fifth region located on the opposite side of the first region from the second region; the plurality of second wiring layers and the plurality of third wiring layers extend in the second direction from the second region to the fifth region via the fourth region; a second memory pillar extending in the first direction in the fifth region, one end of which contacts the first wiring layer, and which passes through the plurality of second wiring layers and the plurality of third wiring layers; 12. The semiconductor memory device according to claim 11.

14. the plurality of third terrace portions and the plurality of fourth terrace portions are arranged in this order in a direction away from the second region in the second direction, the plurality of fifth terrace portions and the plurality of sixth terrace portions are arranged in this order in a direction away from the second region in the second direction; 13. The semiconductor memory device according to claim 12.

15. the first sub-staircase region and the second boundary region are provided at positions overlapping in the first direction, The fourth sub-staircase region and the first boundary region are provided at positions overlapping in the first direction.

13. The semiconductor memory device according to claim 12.

16. the second sub-staircase region and the second boundary region are provided at positions overlapping in the first direction, The third sub-staircase region and the first boundary region are provided at positions overlapping in the first direction.

13. The semiconductor memory device according to claim 12.

17. each of the plurality of first terrace portions is thicker in the first direction than other portions of the plurality of second wiring layers; each of the second terrace portions is thicker in the first direction than other portions of the third wiring layers; 12. The semiconductor memory device according to claim 11.

18. The plurality of third wiring layers are In the third area, a third staircase area is provided next to the second staircase area in the second direction; a third boundary region provided between the second staircase region and the third staircase region in the second direction; Further comprising: each of the third wiring layers has a plurality of seventh terrace portions provided in the third staircase region so as not to overlap with an upper third wiring layer in the first direction; some consecutive wiring layers among the plurality of third wiring layers have cut surfaces that intersect with the second direction in the third boundary region; a third contact extending in the first direction at a position in the third region where the first staircase region and the third boundary region overlap, one end of which is located between the first wiring layer and the plurality of second wiring layers, passing through the plurality of third wiring layers, and electrically connected to one of the plurality of first terrace portions; 12. The semiconductor memory device according to claim 11.

19. The plurality of second wiring layers include: In the third area, a fourth staircase area is provided adjacent to the first staircase area in the second direction; a fourth boundary region provided between the first staircase region and the fourth staircase region in the second direction; Further comprising: each of the second wiring layers has a plurality of eighth terrace portions provided in the fourth staircase region so as not to overlap with an upper second wiring layer in the first direction; some consecutive wiring layers among the plurality of second wiring layers have cut surfaces that intersect with the second direction in the fourth boundary region; a fourth contact extending in the first direction at a position in the third region where the second staircase region and the fourth boundary region overlap, one end of which is located between the first wiring layer and the plurality of second wiring layers, passing through the plurality of second wiring layers, and electrically connected to one of the plurality of second terrace portions; 12. The semiconductor memory device according to claim 11.

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