Semiconductor memory device

Abstract

To provide a semiconductor memory device that allows high integration.SOLUTION: A semiconductor memory device includes a semiconductor substrate 200 in which a semiconductor region 203 constituting three word line switches WLSW(2), WLSW(1), WLSW(2) is formed from a positive side to a negative side in a Y direction. There are provided three electrode gc extending in an X direction on the upper surface of the semiconductor region 203. Each electrode gc includes a gate insulating layer 204 provided on the upper surface of the semiconductor region 203, a gate electrode 206 provided on the upper surface of the gate insulating layer 204, and a gate insulating film 205 provided on both side surfaces of the gate insulating layer 204 and the gate electrode 206 in the Y-direction. Via-contact electrodes C41, C31, C21, C11, CS1 and connecting portions d31, d21, d11, d01 are connected immediately below or approximately immediately below from a wiring line CGI to a first region RCGI overlapping a source region of the semiconductor region 203.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that includes a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, a semiconductor layer facing the plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layer. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage layer made of silicon nitride (SiN) or a conductive charge storage layer such as a floating gate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2024-031772 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that can be highly integrated is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a semiconductor substrate, a plurality of transistors provided on one surface of the semiconductor substrate and aligned in a first direction and a second direction intersecting the first direction, a stacked body provided on one side of the semiconductor substrate in a third direction intersecting the first and second directions and having a plurality of conductive layers aligned in the third direction, and a plurality of wiring layers provided between the semiconductor substrate and the stacked body and connecting the plurality of conductive layers to the plurality of transistors. The semiconductor memory device also includes a first circuit region in which the plurality of transistors are arranged as viewed from the third direction, and a hook-up region that overlaps with the first circuit region as viewed from the third direction and has a smaller width in the first direction than the first circuit region. The stacked body has a first stacked structure and a second stacked structure aligned in the second direction. The first stacked structure has a plurality of first conductive layers aligned in the third direction. The second stacked structure has a plurality of second conductive layers aligned in the third direction. The plurality of transistors includes a plurality of first transistors and a plurality of second transistors aligned in the first direction. The wiring layer includes a plurality of first wirings connecting the plurality of first conductive layers and the plurality of first transistors, and a plurality of second wirings connecting the plurality of second conductive layers and the plurality of second transistors. A first portion of the plurality of first wirings extending in a first direction from the hookup region toward the first circuit region and a second portion of the second wirings extending in the first direction from the hookup region toward the first circuit region are disposed at different positions in a third direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic block diagram showing the configuration of a memory die MD according to the first embodiment. [Figure 2] FIG. 2 is a schematic circuit diagram showing the configuration of a portion of a memory die MD. [Figure 3] 2 is a schematic circuit diagram showing the configurations of a voltage generating circuit VG, a driver circuit DRV, and a row decoder RD. FIG. [Figure 4] FIG. 2 is a schematic circuit diagram showing a configuration of a part of a peripheral circuit PC. [Figure 5] 1 is a schematic exploded perspective view showing an example of the configuration of a memory die MD. FIG. [Figure 6] FIG. 2 is a schematic bottom view showing an example of the configuration of a chip CM. [Figure 7] 2 is a schematic cross-sectional view showing the configuration of a portion of a memory die MD. FIG. [Figure 8] 2 is a schematic cross-sectional view showing the configuration of a portion of a memory die MD. FIG. [Figure 9] FIG. 2 is a schematic bottom view showing the configuration of a portion of the chip CM. [Figure 10] 2 is a schematic cross-sectional view showing the configuration of a part of the chip CM. FIG. [Figure 11] 10 is a schematic plan view showing a configuration example of a hook-up area RHU. FIG. [Figure 12] FIG. 2 is a schematic plan view showing a configuration example of a chip CP. [Figure 13] FIG. 13 is a schematic enlarged view of a portion indicated by A in FIG. [Figure 14] FIG. 2 is a schematic plan view showing a control circuit SYN and a feed-through wiring TW. [Figure 15] 10 is a schematic plan view showing a configuration example of a word line switch WLSW. FIG. [Figure 16] 10 is a schematic cross-sectional view showing paths between the conductive layer 110 and the word line switch WLSW and the select gate line switch SGSW. FIG. [Figure 17] 10 is a schematic cross-sectional view showing the structure of a word line switch WLSW, a connection portion, and a via contact electrode. FIG. [Figure 18] 10 is a schematic plan view showing the position of a laminated electrode PI2 in a hook-up region RHU. FIG. [Figure 19] FIG. 10 is a schematic plan view showing the positions of the wiring CGI and the connection portion d42 provided in the wiring layer D4. [Figure 20] FIG. 10 is a schematic plan view showing an example of a wiring pattern in a wiring layer D3. [Figure 21] FIG. 10 is a schematic plan view showing an example of a wiring pattern in a wiring layer D2. [Figure 22] FIG. 2 is a schematic plan view showing an example of a wiring pattern in a wiring layer D1. [Figure 23] FIG. 2 is a schematic plan view showing an example of a wiring pattern in a wiring layer D0. [Figure 24] FIG. 24 is an enlarged plan view of a portion of FIG. 23. [Figure 25] FIG. 10 is a plan view showing still another example of the wiring layer D1. [Figure 26] FIG. 10 is a plan view showing still another example of the wiring layer D1. [Figure 27] 10 is a schematic plan view of a hookup wiring W1 provided in a first row RO1 of a wiring layer D1 of a comparative example. FIG. [Figure 28] 10 is a schematic plan view of hookup wirings W1 and W2 provided in a first row RO1 of wiring layers D1 and D2 of the first embodiment. FIG. [Figure 29] FIG. 10 is a schematic plan view showing the positions of the connection portions d32 to d02 of the wiring layers D3 to D0 according to the second embodiment. [Figure 30] FIG. 10 is a schematic plan view showing the positions of connection portions d32 to d02 of wiring layers D3 to D0 according to a first modified example of the second embodiment. [Figure 31] FIG. 10 is a schematic plan view showing the positions of connection portions d32 to d02 of wiring layers D3 to D0 according to a second modification of the second embodiment. [Figure 32] 10 is a schematic plan view showing an example of the configuration of a semiconductor wafer 500 according to a third embodiment. FIG. [Figure 33] FIG. 10 is a schematic plan view showing a configuration example of a word line switch WLSW according to a fourth embodiment. [Figure 34] FIG. 10 is a schematic plan view showing an example of a wiring pattern in a wiring layer D2. [Figure 35] FIG. 2 is a schematic plan view showing an example of a wiring pattern in a wiring layer D1. [Figure 36] FIG. 2 is a schematic plan view showing an example of a wiring pattern in a wiring layer D0. [Figure 37] FIG. 11 is a schematic plan view showing a configuration example of a word line switch WLSW according to a fifth embodiment. [Figure 38] FIG. 10 is a schematic plan view showing the wiring patterns of hookup wirings W2, W1, and W0 arranged in a first row RO1. [Figure 39] FIG. 10 is a diagram showing a schematic configuration of a semiconductor memory device according to a sixth embodiment. [Figure 40] FIG. 10 is a diagram showing a schematic configuration of a semiconductor memory device according to a sixth embodiment. [Figure 41] FIG. 13 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a seventh embodiment. [Figure 42] 13 is a schematic plan view showing an example of the arrangement of via contact electrodes CC in a semiconductor memory device according to the eighth embodiment, and an example of the arrangement of corresponding connection parts dn2 of wiring layers and word line switches WLSW. FIG. [Figure 43] 10 is a schematic plan view showing an example of assignment of word line WL numbers of via contact electrodes CC and word line switches WLSW. FIG. [Figure 44] 13 is a schematic plan view showing an example of the arrangement of via contact electrodes CC in a semiconductor memory device according to a ninth embodiment, and an example of the arrangement of corresponding connection parts dn2 of wiring layers and word line switches WLSW. FIG. [Figure 45] 10 is a schematic plan view showing an example of assignment of word line WL numbers of via contact electrodes CC and word line switches WLSW. FIG. [Figure 46] 19 is a schematic plan view showing an example of the arrangement of via contact electrodes CC in a semiconductor memory device according to a tenth embodiment, and an example of the arrangement of corresponding connection parts dn2 of wiring layers and word line switches WLSW. FIG. [Figure 47] 10 is a schematic plan view showing an example of assignment of word line WL numbers of via contact electrodes CC and word line switches WLSW. FIG. [Figure 48] 16 is a schematic plan view showing an example of the arrangement of via contact electrodes CC in a semiconductor memory device according to an eleventh embodiment, and an example of the arrangement of corresponding connection parts dn2 of wiring layers and word line switches WLSW. FIG. [Figure 49] 10 is a schematic plan view showing an example of assignment of word line WL numbers of via contact electrodes CC and word line switches WLSW. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Next, semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. The following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Furthermore, parts common to multiple embodiments are given the same reference numerals, and explanations thereof may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0010] Furthermore, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in the current path between the two wirings, and that the transistor or the like is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] In addition, in this specification, a direction along a predetermined plane may be referred to as the first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as the second direction, and a direction that intersects with this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as "up," and the direction approaching the substrate along the Z direction is referred to as "lower." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are referred to as side surfaces, etc.

[0015] Furthermore, in this specification, when referring to a configuration, component, etc., "width," "length," or "thickness" in a specific direction, this may mean the width, length, or thickness in a cross section observed using SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy), or the like.

[0016] In addition, in this specification, the term "wiring" may include wiring, via contact electrodes, connection portions for connecting wiring and via contact electrodes, adhesive electrodes, and the like.

[0017] [First embodiment] [Circuit configuration of memory die MD] Fig. 1 is a schematic block diagram showing the configuration of a memory die MD according to the first embodiment. Fig. 2 is a schematic circuit diagram showing the configuration of a portion of the memory die MD. Fig. 3 is a schematic circuit diagram showing the configurations of a voltage generation circuit VG, a driver circuit DRV, and a row decoder RD. Fig. 4 is a schematic block diagram showing the configurations of a row control circuit RowC and a block decoder BLKD.

[0018] FIG. 1 illustrates a plurality of control terminals, etc. These control terminals may be represented as control terminals corresponding to high-active signals (positive logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to low-active signals (negative logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to both high-active signals and low-active signals. In FIG. 1, the reference numerals of control terminals corresponding to low-active signals include an overline. In this specification, the reference numerals of control terminals corresponding to low-active signals include a slash (" / "). Note that the illustration in FIG. 1 is an example, and specific embodiments can be adjusted as appropriate. For example, it is possible to make some or all of the high-active signals low-active signals, or some or all of the low-active signals high-active signals.

[0019] 1, the memory die MD includes a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC also includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. The peripheral circuit PC also includes an input / output control circuit I / O and a logic circuit CTR.

[0020] [Circuit configuration of memory cell array MCA] As shown in FIG. 2, the memory cell array MCA includes the above-mentioned multiple memory blocks BLK. Each of the multiple memory blocks BLK includes multiple string units SU. Each of the multiple string units SU includes multiple memory strings MS. One end of each of the multiple memory strings MS is connected to the peripheral circuit PC via a bit line BL. The other end of each of the multiple memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0021] The memory string MS includes a drain-side select transistor STD, a plurality of memory cells MC (memory transistors), and a source-side select transistor STS. The drain-side select transistor STD, the plurality of memory cells MC, and the source-side select transistor STS are connected in series between a bit line BL and a source line SL. Hereinafter, the drain-side select transistor STD and the source-side select transistor STS may be simply referred to as select transistors (STD, STS).

[0022] The memory cells MC are field-effect transistors. Each memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage film. Each memory cell MC stores one or more bits of data. A word line WL is connected to the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all memory strings MS in one memory block BLK.

[0023] The select transistors (STD, STS) are field-effect transistors. The select transistors (STD, STS) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may include a charge storage layer. A select gate line (SGD, SGS) is connected to the gate electrode of each of the select transistors (STD, STS). One drain-side select gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source-side select gate line SGS is commonly connected to all memory strings MS in one memory block BLK. The drain-side select gate line SGD and the source-side select gate line SGS may be referred to as select gate lines SG, respectively.

[0024] [Circuit configuration of voltage generation circuit VG] The voltage generating circuit VG (FIG. 1) includes a plurality of voltage generating units vg1 to vg3, as shown in FIG. 3. The voltage generating units vg1 to vg3 generate voltages of predetermined magnitudes in read, write, and erase operations, and supply the voltages to the voltage supply line L VG For example, the voltage generation unit vg1 outputs a program voltage in a write operation. The voltage generation unit vg2 outputs a read pass voltage in a read operation. The voltage generation unit vg2 outputs a write pass voltage in a write operation. The voltage generation unit vg3 outputs a read voltage in a read operation. The voltage generation unit vg3 outputs a verify voltage in a write operation. The voltage generation units vg1 to vg3 may be, for example, boost circuits such as charge pump circuits or step-down circuits such as regulators. These step-down circuits and boost circuits are connected to the voltage supply line L P Connected to the voltage supply line L P is the power supply voltage V CC or ground voltage V SS (Figure 1) are supplied. These voltage supply lines L Pis connected to, for example, a pad electrode P. The operating voltage output from the voltage generating circuit VG is adjusted appropriately in accordance with a control signal from the sequencer SQC.

[0025] The voltage generation circuit VG (FIG. 1) described with reference to FIG. 3 generates a program voltage, a read pass voltage, a write pass voltage, a read voltage, and a verify voltage that are applied to the word lines WL via the wiring CGI. However, the voltage generation circuit VG can generate not only the operating voltages applied to the word lines WL, but also multiple operating voltages that are applied to the bit lines BL, the source lines SL, and the select gate lines (SGD, SGS) during read, write, and erase operations on the memory cell array MCA, and output them to multiple voltage supply lines. These operating voltages are adjusted appropriately according to control signals from the sequencer SQC.

[0026] [Circuit configuration of row decoder RD] The row decoder RD includes a row control circuit RowC, a word line decoder WLD, a driver circuit DRV, and an address decoder (not shown), as shown in Fig. 3. The row control circuit RowC includes a plurality of block decoder units blkd and a block decoder BLKD, as shown in Fig. 4.

[0027] The plurality of block decoder units blkd correspond to the plurality of memory blocks BLK in the memory cell array MCA. The block decoder unit blkd includes a plurality of word line switches WLSW and a plurality of select gate line switches SGSW. The plurality of word line switches WLSW correspond to the plurality of word lines WL in the memory blocks BLK. The plurality of select gate line switches SGSW correspond to the drain side select gate lines SGD and source side select gate lines SGS in the memory blocks BLK.

[0028] The word line switch WLSW and the select gate line switch SGSW are, for example, field effect NMOS transistors. The drain electrode of the word line switch WLSW is connected to the word line WL. The drain electrode of the select gate line switch SGSW is connected to the drain side select gate line SGD and the source side select gate line SGS. The source electrodes of the word line switch WLSW and the select gate line switch SGSW are connected to a wiring CGI. The wiring CGI is connected to all the block decoder units blkd in the row control circuit RowC. The gate electrodes of the word line switch WLSW and the select gate line switch SGSW are connected to a signal line BLKSEL. A plurality of signal lines BLKSEL are provided corresponding to all the block decoder units blkd. Furthermore, the signal line BLKSEL is connected to all the word line switches WLSW and select gate line switches SGSW in the block decoder unit blkd.

[0029] The block decoder BLKD decodes a block address during a read operation, a write operation, etc. During a read operation, a write operation, etc., for example, one signal line BLKSEL corresponding to the block address in the address register ADR (FIG. 1) goes to the "H" state, and the other signal lines BLKSEL go to the "L" state. For example, a predetermined drive voltage having a positive magnitude is supplied to one signal line BLKSEL, and a ground voltage V SS As a result, all word lines WL and select gate lines SG in one memory block BLK corresponding to this block address become conductive with all wirings CGI. Also, all word lines WL and select gate lines SG in other memory blocks BLK become floating.

[0030] The word line decoder WLD includes a plurality of word line decode units wld. The plurality of word line decode units wld correspond to a plurality of memory cells MC in the memory string MS. In the example of FIG. 3, the word line decode unit wld includes two transistors T WLS ,T WLU Transistor TWLS ,T WLU is, for example, a field-effect NMOS transistor. WLS ,T WLU The drain electrode of the transistor T is connected to the wiring CGI. WLS The source electrode is wired CGI S Transistor T WLU The source electrode is wired CGI U Transistor T WLS The gate electrode of the signal line WLSEL S Transistor T WLU The gate electrode of the signal line WLSEL U Signal line WLSEL is connected to S is one of the transistors T included in all the word line decode units wld. WLS A plurality of signal lines WLSEL are provided corresponding to the respective U is the other transistor T included in all word line decode units wld WLU A plurality of such sensors are provided corresponding to the respective sensors.

[0031] In a read operation, a write operation, etc., for example, a signal line WLSEL corresponding to one word line decode unit wld corresponding to a page address in the address register ADR (FIG. 1) is S becomes "H" state, and the corresponding WLSEL U The signal lines WLSEL corresponding to the other word line decode units wld are set to the "L" state. S goes to the "L" state, and the corresponding WLSEL U becomes "H" state. Also, wiring CGI S A voltage corresponding to the selected word line WL is supplied to the line CGI U A voltage corresponding to the unselected word lines WL is supplied to one word line WL corresponding to the page address. As a result, a voltage corresponding to the selected word line WL is supplied to one word line WL corresponding to the page address. Furthermore, voltages corresponding to the unselected word lines WL are supplied to the other word lines WL.

[0032] The driver circuit DRV is, for example, composed of six transistors T DRV1 ~T DRV6 Transistor T DRV1 ~T DRV6 is, for example, a field-effect NMOS transistor. DRV1 ~T DRV4 The drain electrode is wired CGI S Transistor T DRV5 ,T DRV6 The drain electrode is wired CGI U Transistor T DRV1 The source electrode of the voltage supply line L VG1 is connected to the output terminal of the voltage generating unit vg1 via the transistor T DRV2 ,T DRV5 The source electrode of the voltage supply line L VG2 is connected to the output terminal of the voltage generating unit vg2 via the transistor T DRV3 The source electrode of the voltage supply line L VG3 is connected to the output terminal of the voltage generating unit vg3 via the transistor T DRV4 ,T DRV6 The source electrode of the voltage supply line L P The transistor T DRV1 ~T DRV6 The gate electrodes of these transistors are connected to signal lines VSEL1 to VSEL6, respectively.

[0033] In the read operation, write operation, etc., for example, the wiring CGI S One of the signal lines VSEL1 to VSEL4 corresponding to the wiring CGI U One of the two corresponding signal lines VSEL5 and VSEL6 goes to the "H" state, and the other goes to the "L" state.

[0034] An address decoder (not shown) sequentially references the row address RA of the address register ADR (FIG. 1) in accordance with a control signal from the sequencer SQC (FIG. 1). The row address RA includes the above-mentioned block address and page address. The address decoder uses the signal lines BLKSEL and WLSEL S ,WLSEL U The voltage is controlled to either the "H" state or the "L" state.

[0035] 3, the row decoder RD is provided with one block decoder unit blkd for each memory block BLK. However, this configuration can be modified as appropriate. For example, one block decoder unit blkd may be provided for two or more memory blocks BLK.

[0036] [Circuit configuration of the sense amplifier module SAM] The sense amplifier module SAM (Figure 1) detects the ON / OFF state of the memory cell MC and acquires data indicating the state of this memory cell MC. This type of operation is sometimes called a sense operation. The sense amplifier module SAM includes multiple sense amplifier units. The multiple sense amplifier units correspond to multiple bit lines BL. Each of the multiple sense amplifier units includes a sense amplifier circuit and a latch circuit.

[0037] [Circuit configuration of cache memory CM] The cache memory CM (Figure 1) includes multiple latch circuits. The multiple latch circuits are connected to latch circuits in the sense amplifier module SAM via wiring DBUS. Data DAT contained in these multiple latch circuits is sequentially transferred to the sense amplifier module SAM or the input / output control circuit I / O.

[0038] In addition, a decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes the column address CA held in the address register ADR. The switch circuit connects the latch circuit corresponding to the column address CA to the bus BUS (FIG. 1) in response to the output signal of the decode circuit.

[0039] [Circuit configuration of sequencer SQC] The sequencer SQC (Fig. 1) reads the command data D held in the command register CMR. CMD In accordance with the above, the sequencer SQC outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generating circuit VG. In addition, the sequencer SQC outputs status data D indicating its own state as appropriate. ST is output to the status register STR.

[0040] The sequencer SQC also generates a ready / busy signal and outputs it to the terminal RY / / BY. While the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is basically prohibited. Meanwhile, while the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted.

[0041] [Circuit configuration of input / output control circuit I / O] The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS and / DQS, a plurality of input circuits, a plurality of output circuits, a shift register, and a buffer circuit. The plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are each connected to a power supply voltage V CCQ and ground voltage V SS is connected to the terminal at which the

[0042] The data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in response to the internal control signal from the logic circuit CTR. Also, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in response to the internal control signal from the logic circuit CTR.

[0043] The input circuits may include, for example, comparators connected to any one of the data signal input / output terminals DQ0 to DQ7 or both of the toggle signal input / output terminals DQS and / DQS. The output circuits may include, for example, OCD (Off Chip Driver) circuits connected to any one of the data signal input / output terminals DQ0 to DQ7 or either of the toggle signal input / output terminals DQS and / DQS.

[0044] [Circuit configuration of logic circuit CTR] The logic circuit CTR (Fig. 1) receives external control signals from the controller die CD via external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O in response.

[0045] [Memory die MD structure] 5 is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to the first embodiment. As shown in FIG. 5, the memory die MD includes a chip C on the memory cell array MCA side. M and peripheral circuit PC side chip C P And, it is equipped with.

[0046] Chip C M On the upper surface of the X Also, chip C M On the underside of I1 Also, chip C P On the top surface of I2 Hereafter, Chip C MRegarding the multiple bonded electrodes P I1 The surface on which the external pad electrodes P are provided is called the front surface. X The surface on which the chip C is provided is called the back surface. P Regarding the multiple bonded electrodes P I2 The surface on which the chip C is provided is called the front surface, and the surface opposite to the front surface is called the back surface. P The surface of the chip C P and the chip C M The back side of the chip C M The surface of the casing is provided above the surface of the casing.

[0047] Chip C M and Chip C P is Chip C M Surface and chip C P The surfaces of the plurality of laminated electrodes P are arranged to face each other. I1 is a plurality of laminated electrodes P I2 are provided corresponding to the plurality of bonded electrodes P I2 The electrode P is placed in a position where it can be attached to the I1 and laminated electrode P I2 That is, Chip C M and Chip C P and functions as a bonding electrode for electrically connecting them.

[0048] In the example of FIG. 5, chip C M The corners a1, a2, a3, and a4 are the chip C P These correspond to the corners b1, b2, b3, and b4.

[0049] Figure 6 shows the chip C M 6 is a schematic bottom view showing a configuration example of the laminated electrode P I1 7 and 8 are schematic cross-sectional views showing the configuration of a part of the memory die MD. M9 is a schematic bottom view showing a part of the configuration of the chip C. In FIG. 9, the left side area shows an XY cross section at the position of the word line WL, and the right side area shows an XY cross section at the position of the drain side select gate line SGD. In addition, in the right side area of ​​FIG. 9, via contact electrodes ch, Vy and bit lines BL are also shown to show the connection parts between the semiconductor layer 120 and the bit lines BL. In the left side area of ​​FIG. 9, via contact electrodes ch, Vy and bit lines BL are also provided. FIG. 10 shows the chip C. M 10 shows a YZ cross section, but when a cross section other than the YZ cross section along the central axis of the semiconductor layer 120 (for example, an XZ cross section) is observed, a structure similar to that shown in FIG. 10 is also observed. FIG. 11 shows the hook-up region R HU 12 is a schematic plan view showing a configuration example of the chip C. P 12 is a schematic plan view showing a configuration example of the laminated electrode P I2 13 is a schematic enlarged view of the portion indicated by A in FIG. 12. In FIG. 13, chip C P Chip C corresponding to the configuration (the XY plane portion shown by A in Figure 12) M The structure (XZ cross section) is also shown.

[0050] [Chip C M Structure of In the example of FIG. 6, chip C M The memory device 100 includes four memory planes MP0 to MP3 aligned in the X direction. Note that the four memory planes MP0 to MP3 may be simply referred to as memory planes MP. Each of the four memory planes MP0 to MP3 includes a plurality of memory blocks BLK aligned in the Y direction. In the example of FIG. 6, each of the four memory planes MP0 to MP3 includes a hookup region R HU and a memory hole region R MH (memory area). In the example of FIG. 6, the memory hole area R MH There are four regions R in the X direction. MHU These four regions R MHUThe widths of the chips C in the X direction may or may not be the same. M is a peripheral region R provided on one end side in the Y direction from the four memory planes MP0 to MP3. P Equipped with.

[0051] In the illustrated example, the hook-up region R HU are provided at both ends of the memory plane MP in the X direction. However, this configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, the hook-up region R HU The hook-up region R may be provided at one end in the X direction of the memory plane MP, not at both ends in the X direction. HU may be provided at the center position or near the center in the X direction of the memory plane MP.

[0052] Chip C M For example, as shown in FIG. SB and the substrate layer L SB The memory cell array layer L MCA and the memory cell array layer L MCA a via contact electrode layer CH provided below the via contact electrode layer CH, a plurality of wiring layers M0 and M1 provided below the via contact electrode layer CH, and a chip laminating electrode layer MB provided below the wiring layers M0 and M1.

[0053] [Chip C M Base layer L SB Structure of For example, as shown in FIG. SB is the memory cell array layer L MCA The semiconductor device includes a conductive layer 100 provided on the upper surface thereof, an insulating layer 101 provided on the upper surface of the conductive layer 100, a back surface wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back surface wiring layer MA.

[0054] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) doped with an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B), or may include a metal such as tungsten (W), or may include a silicide such as tungsten silicide (WSi).

[0055] The conductive layer 100 functions as part of the source line SL (FIG. 1). Four conductive layers 100 are provided corresponding to the four memory planes MP0 to MP3 (FIG. 6). Regions VZ that do not include the conductive layer 100 are provided at the ends of the memory plane MP in the X and Y directions.

[0056] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0057] The back wiring layer MA includes a plurality of wirings ma, which may include, for example, aluminum (Al).

[0058] Some of the multiple wirings ma function as part of the source lines SL (FIG. 2). Four of these wirings ma are provided corresponding to the four memory planes MP0 to MP3 (FIG. 6). Each of these wirings ma is electrically connected to the conductive layer 100.

[0059] In addition, some of the wirings ma are connected to the external pad electrodes P X This wiring ma functions as a P The wiring ma is provided in the memory cell array layer L in the region VZ that does not include the conductive layer 100. MCA The wiring ma is connected to a via contact electrode CC in the insulating layer 102. A part of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0060] The insulating layer 102 is a passivation layer made of an insulating material such as polyimide.

[0061] [Chip C M The memory cell array layer LMCA Memory hole region R MH Structure in As described with reference to FIG. 6, the memory cell array layer L MCA 7, a plurality of memory blocks BLK arranged in the Y direction are provided. An inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided between two memory blocks BLK adjacent to each other in the Y direction. A plurality of stacked structures arranged in the Y direction, each including a plurality of conductive layers 110 arranged in the Z direction, correspond to a plurality of memory blocks BLK.

[0062] 7, the memory block BLK includes a plurality of conductive layers 110 aligned in the Z direction and a plurality of semiconductor layers 120 extending in the Z direction. Furthermore, as shown in FIG. 10, a gate insulating film 130 is provided between each of the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0063] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or molybdenum (Mo). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 111 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction.

[0064] Of the multiple conductive layers 110, one or more conductive layers 110 located in the uppermost layer function as the gate electrode of the source-side select transistor STS (FIG. 2) and the source-side select gate line SGS (see FIG. 7). These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0065] Additionally, the plurality of conductive layers 110 positioned below these function as gate electrodes of memory cells MC (FIG. 2) and word lines WL. These plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0066] Furthermore, one or more conductive layers 110 located below the above function as the gate electrodes of the drain side select transistors STD and the drain side select gate lines SGD. For example, as shown in FIG. 9, the width Y SGD is the width Y in the Y direction of the conductive layer 110 that functions as the word line WL. WL Furthermore, an inter-string unit insulating layer SHE made of silicon oxide (SiO 2 ) or the like is provided between two conductive layers 110 adjacent to each other in the Y direction.

[0067] The semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions, as shown in FIG. 9, for example. Each of the semiconductor layers 120 functions as a channel region for a plurality of memory cells MC and select transistors (STD, STS) included in one memory string MS (FIG. 2). The semiconductor layer 120 includes, for example, polycrystalline silicon (Si). The semiconductor layer 120 has a substantially cylindrical shape, and an insulating layer 125 made of silicon oxide or the like is provided in the center. The outer peripheral surfaces of the semiconductor layers 120 are surrounded by a plurality of conductive layers 110, and face these conductive layers 110.

[0068] Furthermore, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. This impurity region is connected to the conductive layer 100 (see FIG. 7). This impurity region contains, for example, an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B).

[0069] Furthermore, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the bit line BL via a via contact electrode ch and a via contact electrode Vy. This impurity region contains an N-type impurity such as phosphorus (P).

[0070] 9, the gate insulating film 130 has a substantially cylindrical shape that covers the outer peripheral surface of the semiconductor layer 120. As shown in FIG. 10, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 that are stacked between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), or the like. The charge storage film 132 includes, for example, a film capable of storing charges, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 excluding the contact portion between the semiconductor layer 120 and the conductive layer 100.

[0071] 10 shows an example in which the gate insulating film 130 includes a charge storage film 132 made of silicon nitride or the like. However, the gate insulating film 130 may include a floating gate made of polycrystalline silicon or the like containing N-type or P-type impurities, for example.

[0072] [Chip C M The memory cell array layer L MCA Hookup Area R HU Structure in As shown in Figure 8, the hook-up area R HU A plurality of via contact electrodes CC are provided in the conductive layer 110. Each of the plurality of via contact electrodes CC extends in the Z direction, and is connected at its upper end to the conductive layer 110 (WL, SGD, SGS).

[0073] As shown in Figure 11, the hook-up area R HU are provided on the negative side and the positive side of the X direction of the memory plane MP, and two hook-up regions R HU Between the memory hole region R MH The memory hole area R MH In this example, the first to eighth memory blocks counting from the positive side in the Y direction are memory blocks BLK(1) to BLK(8). HUcorresponds to the memory blocks BLK(1) to BLK(8), and the hookup area R HU (N1)~R HU (N8). Also, the hook-up area R HU corresponds to the memory blocks BLK(1) to BLK(8), and the hookup area R HU (P1)~R HU (P8)

[0074] Hookup Area R HU (N1)~R HU (N8) and R HU (P1)~R HU In each of (P8), a plurality of rows of three via contact electrodes CC aligned in the Y direction are aligned in the X direction.

[0075] Hookup Area R HU (N1)~R HU The plurality of via contact electrodes CC in (N8) are connected to half of the conductive layers 110 in the memory blocks BLK(1) to BLK(8), respectively. HU (P1)~R HU The plurality of via contact electrodes CC of (P8) are connected to the remaining half of the conductive layers 110 in the memory blocks BLK(1) to BLK(8), respectively.

[0076] [Chip C M The memory cell array layer L MCA The surrounding area R P Structure in Surrounding area R P For example, as shown in FIG. 7, an external pad electrode P X A plurality of via contact electrodes CC are provided corresponding to the external pad electrodes P. X is connected to.

[0077] [Structure of via contact electrode layer CH] 7 to 9, the via contact electrode layer CH includes a plurality of via contact electrodes ch as a plurality of wirings. The plurality of via contact electrodes ch are, for example, MCA Internal configuration and chip C P The device is electrically connected to at least one of the components.

[0078] These via contact electrodes ch may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are provided corresponding to the semiconductor layers 120 and connected to the lower ends of the semiconductor layers 120.

[0079] [Chip C M [Structure of wiring layers M0 and M1] The wirings included in the wiring layers M0 and M1 are, for example, the memory cell array layer L MCA Internal configuration and chip C P The device is electrically connected to at least one of the components.

[0080] The wiring layer M0 includes a plurality of wirings m0, as shown in FIG. 7. These wirings m0 may include a barrier conductive film such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu). Some of the wirings m0 function as bit lines BL. The bit lines BL are aligned in the X direction and extend in the Y direction, as shown in FIG. 9.

[0081] The wiring layer M1 includes a plurality of wirings m1, as shown in Fig. 7. These wirings m1 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The wiring pattern in the wiring layer M1 will be described later.

[0082] [Chip bonding electrode layer MB structure] The plurality of wirings included in the chip bonding electrode layer MB are, for example, MCAInternal configuration and chip C P The device is electrically connected to at least one of the components.

[0083] The chip bonding electrode layer MB is made up of a plurality of bonding electrodes P I1 (adhesive pad). These plural adhesive electrodes P I1 is a barrier conductive film p such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta). I1B and metal films such as copper (Cu) I1M The film may include a laminated film of the above.

[0084] [Chip C P Structure of Chip C P 12, includes regions MP0' to MP3' that overlap with four memory planes MP0 to MP3 aligned in the X direction. At both ends in the X direction of these four regions MP0' to MP3', row control circuit regions R RC In addition, these two row control circuit regions R RC Between them, there are two block decoder regions R aligned in the X direction. BD In addition, these two block decoder regions R BD Between them is the peripheral circuit region R PC The peripheral circuit region R PC In the figure, four column control circuit regions R are arranged in the X and Y directions. CC Although not shown, a peripheral circuit region R PC Other areas of the chip also contain circuits. M The surrounding area R P (Fig. 6) P In the area of, the circuit area R C is provided.

[0085] Row control circuit area R RC 3 and 4, a plurality of block decoder units blkd are provided in the row control circuit region R. RCA plurality of word line switches WLSW and a plurality of select gate line switches SGSW that constitute a plurality of block decoder units blkd are provided in the block decoder region R. BD The block decoder BLKD described with reference to FIG. 4 is provided in the column control circuit region R CC The sense amplifier module SAM described with reference to FIG. C An input / output circuit (not shown) is provided in the external pad electrode P. This input / output circuit is connected to the external pad electrode P via the via contact electrode CC etc. described with reference to FIG. X is connected to.

[0086] 12 and 13 show the hook-up region R HU The overlapping area with the row control circuit area R (FIG. 6) is shown by a dotted line. RC A part of the hook-up area R HU (Fig. 6). RC A part of the memory hole region R MH 12 and 13, the row control circuit region R RC The width in the X direction of the hook-up area R HU (Fig. 6) in the X direction. RC The plurality of word line switches WLSW and select gate line switches are arranged in a hook-up region R HU and memory hole region R MH It is located at a position overlapping with a part of the

[0087] In the example of FIG. 12, the column control circuit region R CC The center position in the X direction of the first and second regions R MHU The boundary of the area R, or the third and fourth area R counting from the negative side of the X direction MHU The column control circuit region R CCThe center position in the X direction of the first and second regions R MHU The boundary of the area R, or the third and fourth area R counting from the negative side of the X direction MHU It does not have to coincide with the boundary of

[0088] Also, Chip C P As shown in FIG. 7, for example, the semiconductor device includes a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, and D4 provided above the electrode layer GC, and a chip bonding electrode layer DB provided above the wiring layers D0, D1, D2, D3, and D4.

[0089] [Chip C P Structure of semiconductor substrate 200] 7 and 8, the semiconductor substrate 200 includes P-type silicon (Si) containing P-type impurities such as boron (B). The surface of the semiconductor substrate 200 is provided with an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S in which the N-type well region 200N and the P-type well region 200P are not provided, and an insulating region STI. A portion of the P-type well region 200P is provided in the semiconductor substrate region 200S, and a portion of the P-type well region 200P is provided in the N-type well region 200N. The N-type well region 200N, the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as part of a plurality of transistors Tr and a plurality of capacitors that constitute the peripheral circuit PC. Some of the transistors Tr function as word line switches WLSW and select gate line switches SGSW.

[0090] [Chip C P Electrode layer GC structure] 7, an electrode layer GC is provided on the upper surface of the semiconductor substrate 200 with an insulating layer 200G interposed therebetween. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are connected to a via contact electrode CS, respectively.

[0091] The N-type well region 200N of the semiconductor substrate 200, the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as channel regions of a plurality of transistors Tr constituting the peripheral circuit PC and one electrode of a plurality of capacitors, etc.

[0092] The plurality of electrodes gc included in the electrode layer GC function as gate electrodes of the plurality of transistors Tr constituting the peripheral circuit PC, the other electrodes of the plurality of capacitors, and the like.

[0093] The via contact electrode CS extends in the Z direction, and its lower end is connected to the upper surface of the semiconductor substrate 200 or the electrode gc. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the via contact electrode CS and the semiconductor substrate 200. The via contact electrode CS may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0094] [Chip C P [Structure of wiring layers D0, D1, D2, D3, D4] For example, as shown in FIG. 7, a plurality of connection parts and a plurality of wirings included in D0, D1, D2, D3, and D4 are, for example, a memory cell array layer L MCA Internal configuration and chip C P The device is electrically connected to at least one of the components.

[0095] The wiring layers D0, D1, and D2 each include a plurality of connection portions d0, d1, and d2 and a plurality of wirings (e.g., hookup wirings W0, W1, and W2, passing wiring TW2, and shield wiring s2, which will be described later). These connection portions d0, d1, and d2 and the plurality of wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0096] The wiring layers D3 and D4 each include a plurality of connection portions d3 and d4 and a plurality of wirings (for example, a hookup wiring W3, a passing wiring TW3, a shield wiring s3, and a wiring CGI, which will be described later). The plurality of connection portions d3 and d4 and the plurality of wirings may include, for example, a barrier conductive film such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu).

[0097] The configuration of the connection portions d0, d1, d2, d3, and d4 and the plurality of wirings in the wiring layers D0, D1, D2, D3, and D4 will be described later.

[0098] [Chip bonding electrode layer DB structure] The plurality of wirings included in the chip bonding electrode layer DB are, for example, MCA Internal configuration and chip C P The device is electrically connected to at least one of the components.

[0099] The chip bonding electrode layer DB is made up of a plurality of bonding electrodes P I2 These multiple laminated electrodes P I2 is a barrier conductive film p such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta). I2B and metal films such as copper (Cu) I2M The film may include a laminated film of the above.

[0100] In addition, the bonded electrode P I1 and laminated electrode P I2 In particular, metal films such as copper (Cu) I1M ,p I2MWhen using the metal film p I1M and metal film p I2M However, the bonded electrode P due to the misalignment of the bonding position is I1 and laminated electrode P I2 Distortion of the bonded shape, barrier conductive film p I1B ,p I2B The bonded structure can be confirmed by the positional misalignment (the occurrence of discontinuous areas on the side). I1 and adhesive electrode P I2 When the laminated electrode P is formed by the damascene method, each side surface has a tapered shape. I1 and laminated electrode P I2 The cross section of the bonded electrode P along the Z direction has a non-rectangular shape, with the side walls not being linear. I1 and laminated electrode P I2 When these are bonded together, the bottom, side, and top surfaces of each Cu that forms them are covered with barrier metal. In contrast, in a typical wiring layer using Cu, an insulating layer (such as SiN or SiCN) that functions to prevent oxidation of Cu is provided on the top surface of the Cu, and no barrier metal is provided. For this reason, it is possible to distinguish it from a typical wiring layer even if there is no misalignment in the bonding.

[0101] [Wiring pattern in wiring layer M1] As explained with reference to FIG. 4 etc., word lines WL are connected to word line switches WLSW, respectively. Also, select gate line switches SGSW are connected to select gate lines SG, respectively. Here, since a relatively large voltage may be supplied to the word lines WL and select gate lines SG, high-voltage transistors are used as the word line switches WLSW and select gate line switches SGSW. Here, high-voltage transistors may be relatively large. In view of this relationship, the row control circuit region R explained with reference to FIG. RC The area of ​​the slit may be relatively large.

[0102] Here, the row control circuit region R RC The area of ​​the hookup area RHU If the area of ​​the row control circuit region R RC A part of the hook-up area R HU The remaining part is located in the memory hole area R when viewed from the Z direction. MH However, in this case, the area of ​​the entire area MP' may become large, which may increase the circuit area of ​​the memory die MD.

[0103] Therefore, in this embodiment, as described with reference to FIGS. 12 and 13, the row control circuit region R RC A part of the hook-up area R HU The remaining part is located in the memory hole area R when viewed from the Z direction. MH It is located in the area overlapping with.

[0104] When such a structure is adopted, some of the bit lines BL are arranged in the column control circuit region R when viewed from the Z direction. CC Instead, the row control circuit region R RC and block decoder region R BD It will be placed at a position that overlaps with the

[0105] Therefore, in this embodiment, wiring m1a extending in the X direction is provided in the wiring layer M1, and some of the bit lines BL and the column control circuit region R are connected via this wiring m1a. CC With this configuration, the row control circuit region R RC It is possible to provide a semiconductor memory device that allows for high integration by suppressing an increase in the circuit area of ​​the memory die MD that accompanies an increase in the area of ​​the memory die MD.

[0106] In addition, the row control circuit region R RC The area of ​​the hookup area R HU If the area is the same as the hook-up area R HU In this case, the wiring layer M1 may have an area smaller than that of the bit lines BL and the column control circuit region R. CCThere is no need to provide wiring m1a for electrically connecting the internal configuration.

[0107] [Control circuit SYN and passing wiring TW] Fig. 14 is a schematic plan view showing the control circuit SYN and the feed-through wiring TW. In Fig. 14, the same components as those in Fig. 12 are denoted by the same reference numerals, and redundant explanations will be omitted.

[0108] The control circuit SYN controls the chip C P 14, the control circuit SYN is a module that outputs control signals to various peripheral circuits PC in the peripheral circuit area R of the area MP3'. The control circuit SYN may include the sequencer SQC described with reference to FIG. 1, etc. The control signals output from the control circuit SYN may include voltage control signals (input to a charge pump circuit, a regulator, etc.), address signals, etc. In the example of FIG. 14, the control circuit SYN controls the peripheral circuit area R of the area MP3'. PC 14. The control circuit SYN may be provided in a position different from that shown in FIG.

[0109] The plurality of through wirings TW connect the peripheral circuits PC of the plurality of regions MP'. As shown in FIG. 14, the plurality of through wirings TW extending in the X direction and the Y direction are provided across the plurality of regions MP'. The plurality of through wirings TW transmit various signals including control signals. Some of the plurality of through wirings TW are connected to the control circuit SYN and transmit control signals from the control circuit SYN. ​​These plurality of through wirings TW are connected to the chip C, for example. P These are formed in the wiring layers D2, D3, and D4.

[0110] As shown in FIG. 14, a plurality of through wirings TW provided across a plurality of regions MP′ are arranged in the row control circuit region R RC and the block decoder region R BD passes above.

[0111] [Structure of word line switch WLSW and select gate line switch SGSW] Fig. 15 is a schematic plan view showing an example of the configuration of word line switches WLSW. Note that Fig. 15 corresponds to, for example, the portion indicated by B in Fig. 14. For ease of explanation, Fig. 15 also shows an example in which the number of word line switches WLSW (i.e., the number of word lines WL) in one memory block BLK is 24. However, the number of word line switches WLSW is not limited to this number.

[0112] 15 shows two word line switches WLSW (transistors) having a common source region. Hereinafter, such two word line switches WLSW (transistors) will be referred to as a "transistor group TG1."

[0113] 15, the transistor group TG1 includes a semiconductor region (diffusion region) 203 extending in the Y direction. The semiconductor regions 203 are aligned in both the Y direction and the X direction. A via contact electrode CS2 functioning as a drain terminal of the word line switch WLSW is provided at each end of the semiconductor region 203 in the Y direction. A via contact electrode CS1 functioning as a common source terminal of the two word line switches WLSW is provided between the via contact electrodes CS2. A gate insulating layer 204 (see FIG. 17) and a gate electrode 206 are provided between the via contact electrode CS2 functioning as a drain terminal and the via contact electrode CS1 functioning as a source terminal.

[0114] In this embodiment, the pitch Ypitch of the word line switches WLSW in the Y direction is smaller than the pitch of the memory blocks BLK in the Y direction. More specifically, the ratio of the pitch of the word line switches WLSW to the pitch of the memory blocks BLK in the Y direction is 2:3. In other words, the length in the Y direction of three word line switches WLSW aligned in the Y direction is equal to the length in the Y direction of two memory blocks BLK aligned in the Y direction. Hereinafter, this arrangement pattern of word line switches WLSW may be referred to as "3Tr / 2BLK."

[0115] 15, when attention is focused on four memory blocks BLK(1), BLK(2), BLK(3), and BLK(4) arranged in the Y direction, the space between a pair of transistor groups TG1 arranged in the center in the Y direction corresponds to the position of the central inter-block insulating layer ST. Positions on both sides of the central inter-block insulating layer ST, spaced 3 / 4 of the length of the transistor group TG1 in the Y direction, correspond to the positions of the other inter-block insulating layers ST. Positions half the Y direction away from the transistor groups TG1 adjacent to the central pair of transistor groups TG1 on both sides in the Y direction correspond to the positions of further other inter-block insulating layers ST.

[0116] In this embodiment, multiple sets of three word line switches WLSW aligned in the Y direction are aligned in the X direction corresponding to two memory blocks BLK adjacent in the Y direction. Of the multiple word line switches WLSW aligned in the X direction, one row is composed of word line switches WLSW of one memory block BLK, another row is composed of word line switches WLSW of the other memory block BLK, and the remaining rows are composed of word line switches WLSW of two memory blocks BLK arranged alternately.

[0117] For example, in the case of memory blocks BLK(1) and BLK(2) adjacent in the Y direction shown in FIG. 15, word line switch WLSW(1) is connected to word line WL(1) of memory block BLK(1), and word line switch WLSW(2) is connected to word line WL(2) of memory block BLK(2). In the first row RO1, multiple word line switches WLSW(1) and multiple word line switches WLSW(2) are alternately arranged two by two in the X direction. In the second row RO2, multiple word line switches WLSW(1) are arranged in the X direction. In the third row RO3, multiple word line switches WLSW(2) are arranged in the X direction.

[0118] In the first row RO1, two word line switches WLSW(1) adjacent to each other in the X direction are connected by a common gate electrode 206 to form one transistor group TG2. Also, in the first row RO1, two word line switches WLSW(2) adjacent to each other in the X direction are connected by a common gate electrode 206 to form one transistor group TG2. A transistor group TG2 consisting of word line switches WLSW(1) and a transistor group TG2 consisting of word line switches WLSW(2) are alternately arranged in the X direction. Also, in the second row RO2 and the third row RO3, two word line switches WLSW(1) and two word line switches WLSW(2) are connected by a common gate electrode 206 to form one transistor group TG2, in order to achieve pattern consistency with the first row RO1. The word line switches WLSW(1) in the second row RO2 and the word line switches WLSW(2) in the third row RO3 may each be connected to a single gate electrode 206 that is continuous in the X direction.

[0119] Between the semiconductor regions 203 constituting the word line switches WLSW included in the same transistor group TG2, an insulating region STI1 is provided to insulate the semiconductor regions 203 from each other. Between the semiconductor regions 203 constituting the word line switches WLSW included in different transistor groups TG2, an insulating region STI2 is provided to insulate the semiconductor regions 203 of different transistor groups TG2 from each other. The insulating region STI2 may insulate the word line switches WLSW for different memory blocks BLK from each other. For this reason, the width of the insulating region STI2 in the X direction is larger than the width of the insulating region STI1 in the X direction. Furthermore, the width of the insulating region STI2 in the Y direction is larger than the width of the insulating region STI1 in the X direction.

[0120] The layout pattern of the word line switches WLSW of the memory blocks BLK(3) and BLK(4) is symmetrical to the layout pattern of the word line switches WLSW of the memory blocks BLK(1) and BLK(2) with respect to the inter-block insulating layer ST between the memory blocks BLK(2) and BLK(3).

[0121] Although FIG. 15 shows the structure of the word line switch WLSW, the structure of the select gate line switch SGSW may also be the same as the structure of the word line switch WLSW.

[0122] [Paths between the conductive layer 110 and the word line switch WLSW and select gate line switch SGSW]

[0123] 16 is a diagram showing a simplified wiring path from the conductive layer 110 of the memory cell array MCA to the word line switch WLSG and the select gate line switch SGSW. M The memory cell array layer L MCA The word lines WL and the select gate lines SG (SGD, SGS) are connected to the via contact electrodes CC and the laminated electrodes P I1 ,P I2 , the word line switch WLSW and the select gate line switch SGSW are electrically connected to the via contact electrode CS2 that functions as the drain terminal of the word line switch WLSW and the select gate line switch SGSW via the connection portion d42 of the wiring layer D4, the via contact electrode C42, the connection portion d32 of the wiring layer D3, the via contact electrode C32, the connection portion d22 of the wiring layer D2, the via contact electrode C22, the connection portion d12 of the wiring layer D1, the via contact electrode C12, and the connection portion d02 of the wiring layer D0. Note that the via contact electrode layer CH is omitted in Figure 16. The path from the word line WL and the select gate line SG to the word line switch WLSW and the select gate line switch SGSW as described above is denoted as path RT in Figure 16.

[0124] As shown in FIG. 16, the memory cell array layer L MCA The source side select gate line SGS in the top layer in the RCThe word line WL2 below the source side select gate line SGS is connected, via a path RT2, to a word line switch WLSW (this word line switch WLSW is referred to as WLSW2) on the positive side in the X direction of the select gate line switch SGSW1. The word line WL3 below the word line WL2 is connected, via a path RT3, to a word line switch WLSW (this word line switch WLSW is referred to as WLSW3) on the positive side in the X direction of the word line switch WLSW2.

[0125] In the above-mentioned paths RT1, RT2, and RT3, although not shown in FIG. 16, the connection portion d02 and the connection portion d02b of the wiring layer D0 are connected by a hookup wiring (hookup wiring W0 described later), and the connection portion d02b is connected to the via contact electrode CS2.

[0126] The word line WL4 below the word line WL3 is connected via a path RT4 to a word line switch WLSW (this word line switch WLSW is referred to as WLSW4) located on the positive side in the X direction of the word line switch WLSW3.

[0127] In the above-mentioned path RT4, although not shown in FIG. 16, the connection portion d12 and the connection portion d12b of the wiring layer D1 are connected by a hookup wiring (the hookup wiring W1 described later), the connection portion d12b is connected to the connection portion d02b via the via contact electrode C12b, and the connection portion d02b is connected to the via contact electrode CS2.

[0128] The word line WL5 below the word line WL4 is connected via a path RT5 to a word line switch WLSW (this word line switch WLSW is referred to as WLSW5) located on the positive side in the X direction of the word line switch WLSW4.

[0129] 16, in the above-mentioned path RT5, the connection portion d22 of the wiring layer D2 and the connection portion d22 located on the positive side in the X direction from the connection portion d22 are connected by a hookup wiring (hookup wiring W2 described later). The connection portion d22 is connected to the connection portion d12 through a via contact electrode C22, the connection portion d12 and the connection portion d12b are connected by a hookup wiring (hookup wiring W1 described later), the connection portion d12b is connected to the connection portion d02b through the via contact electrode C12b, and the connection portion d02b is connected to the via contact electrode CS2.

[0130] The drain side select gate line SGD below the word line WL5 is connected via a path RT6 to a select gate line switch SGSW6 located on the positive side in the X direction relative to the word line switch WLSW5.

[0131] 16, in the above-described path RT6, the connection portion d32 of the wiring layer D3 and the connection portion d32 located on the positive side of the connection portion d32 in the X direction are connected by a hookup wiring (hookup wiring W3 described later). The connection portion d32 is connected to the connection portion d22 through the via contact electrode C32, the connection portion d22 is connected to the connection portion d12 through the via contact electrode C22, and the connection portion d12 is connected to the connection portion d02 through the via contact electrode C12. The connection portion d02 and the connection portion d02b are connected by a hookup wiring (hookup wiring W0 described later), and the connection portion d02b is connected to the via contact electrode CS2.

[0132] As shown in FIG. 16, the multiple connection portions d42, d32, d22, d12, and d02 are formed spaced apart in the X and Y directions, regardless of whether they are connected to via contact electrodes and wiring. The connection portions d42, d32, d22, d12, and d02 that are not connected to via contact electrodes and wiring are dummy connection portions that do not form electrical connection paths. Furthermore, the multiple connection portions d12b and d02b shown in FIG. 16 are formed spaced apart in the X and Y directions, regardless of whether they are connected to via contact electrodes and wiring. The connection portions d12b and d02b that are not connected to via contact electrodes and wiring are dummy connection portions that do not form electrical connection paths. However, dummy connection portions do not necessarily have to be formed.

[0133] Also, a plurality of pasted electrodes P are connected to the word lines WL and the select gate lines SG through via contact electrodes CC. I1 ,P I2 The hookup area R HU These multiple laminated electrodes P I1 ,P I2 The number of the overlapping electrodes P is determined according to the number of the word lines WL and the select gate lines SG. I1 ,P I2 Among them, the dummy pasted electrodes P that are not connected to the word lines WL and the select gate lines SG I1 ,P I2 may be provided.

[0134] 16, the select gate line switch SGSW1, word line switches WLSW2, WLSW3, WLSW4, WLSW5, and select gate line switch SGSW6 are arranged in this order on the positive side in the X direction. However, this arrangement of the select gate line switches SGSW1 and SGSW6 and word line switches WLSW2, WLSW3, WLSW4, WLSW5 is just an example, and is not limited to the arrangement shown in FIG.

[0135] 16, the paths on the positive side in the X direction (e.g., RT5 and RT6) electrically connect the connection parts using hook-up wiring in an upper wiring layer more than the paths on the negative side in the X direction (e.g., paths RT1 and RT2). However, such paths RT1 to RT6 are merely examples, and are not limited to the paths shown in FIG.

[0136] For example, in the above-described path RT5, the connection portion d22 of the wiring layer D2 and the connection portion d22 located on the positive side of the connection portion d22 in the X direction are connected by a hookup wiring (hookup wiring W2 described later). The connection portion d22 is connected to the connection portion d12 of the wiring layer D1 through a via contact electrode C22, and the connection portion d12 is connected to the connection portion d02 of the wiring layer D0 through a via contact electrode C12. The connection portion d02 and the connection portion d02b may be connected by a hookup wiring (hookup wiring W0 described later), and the connection portion d02b may be connected to the via contact electrode CS2.

[0137] Furthermore, for example, in the above-described path RT6, the connection portion d22 of the wiring layer D2 and the connection portion d22 located on the positive side of the connection portion d22 in the X direction are connected by a hookup wiring (hookup wiring W2 described later). The connection portion d22 is connected to the connection portion d12 through a via contact electrode C22, and the connection portion d12 is connected to the connection portion d02 through the via contact electrode C12. The connection portion d02 and the connection portion d02b may be connected by a hookup wiring (hookup wiring W0 described later), and the connection portion d02b may be connected to the via contact electrode CS2.

[0138] Furthermore, for example, in the above-mentioned path RT6, the connection portion d22 of the wiring layer D2 is connected to the connection portion d12 through the via contact electrode C22, the connection portion d12 and the connection portion d12b are connected by a hookup wiring (a hookup wiring W1 described later), and the connection portion d12b is connected to the connection portion d02b through the via contact electrode C12. The connection portion d02b may be connected to the via contact electrode CS2.

[0139] In addition, the memory hole area R MHThe bit line BL arranged in the wiring layer M0 below the drain side select gate line SGD of the semiconductor layer 120 formed in the memory hole and the column control circuit region R CC As shown in FIG. 16, the area including these bit lines BL is a row control circuit area R RC It overlaps with part of

[0140] Fig. 17 is a schematic cross-sectional view showing the structure of the word line switch WLSW, the connection portion, and the via contact electrode, taken along line CC' in Fig. 15, including the upper wiring layers D4 to D0 in Fig. 15, and viewed in the direction of the arrow.

[0141] 17, a semiconductor region 203 constituting three word line switches WLSW(2), WLSW(1), and WLSW(2) is formed on a semiconductor substrate 200 from the positive side to the negative side in the Y direction. Three electrodes gc extending in the X direction are provided on the upper surface of the semiconductor region 203. The electrodes gc include a gate insulating layer 204 provided on the upper surface of the semiconductor region 203, a gate electrode 206 provided on the upper surface of the gate insulating layer 204, and gate insulating films 205 provided on both side surfaces of the gate insulating layer 204 and the gate electrode 206 in the Y direction.

[0142] The gate insulating layer 204 may include, for example, at least one of silicon oxide (SiO2) and silicon nitride (SiN), or may include aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films. The gate electrode 206 may include, for example, polycrystalline silicon (Si) containing N-type or P-type impurities, a metal such as tungsten (W), a silicide such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), cobalt silicide (CoSi), or tungsten silicide (WSi), or a stacked film combining two or more of these. The gate insulating film 205 may include, for example, at least one of silicon oxide (SiO2) and silicon nitride (SiN).

[0143] The source region R of the semiconductor region 203 SO is the region between the two electrodes gc that share the semiconductor region 203. The drain region R of the semiconductor region 203 DR is a region between the insulating region STI arranged between the semiconductor regions 203 and each electrode gc.

[0144] The via contact electrodes C41, C31, C21, C11, and CS1 and the connection portions d31, d21, d11, and d01 are connected to the wiring CGI and the source region R of the semiconductor region 203. SO The via contact electrodes C41, C31, C21, C11, CS1 and the connection parts d31, d21, d11, d01 for connecting the wiring CGI are via contact electrodes and connection parts for connecting the wiring CGI. When viewed from the Z direction, the via contact electrodes C41, C31, C21, C11, CS1 and the connection parts d31, d21, d11, d01 are connected to the plurality of source regions R arranged in the X direction. SO The first region R overlaps with the region spanning CGI It is set up in.

[0145] As shown in FIG. 17, in the wiring layer D4, the wiring CGI extends in the Y direction. The via contact electrode C41 is connected to the wiring CGI at its upper end and to the connection portion d31 of the wiring layer D3 at its lower end. In FIG. 17, the wiring CGI and the via contact electrode C41 are deviated in the X direction from the connection portion d31 and the via contact electrode C31, and therefore the wiring CGI and the via contact electrode C41 are indicated by dotted lines. The via contact electrode C31 is connected to the connection portion d31 at its upper end and to the connection portion d21 of the wiring layer D2 at its lower end. The via contact electrode C21 is connected to the connection portion d21 at its upper end and to the connection portion d11 of the wiring layer D1 at its lower end. The via contact electrode C11 is connected to the connection portion d11 at its upper end and to the connection portion d01 of the wiring layer D0 at its lower end. The via contact electrode CS1 is connected to the connection portion d01 at its upper end and to the source region R of the semiconductor region 203 at its lower end. SO is connected to.

[0146] In this way, the via contact electrodes C41, C31, C21, C11, CS1 and the connection portions d31, d21, d11, d01 are connected from the wiring CGI to the source region R of the semiconductor region 203. SO Connect directly or almost directly below the

[0147] The via contact electrodes C42, C32, C22 (C22b), C12 (C12b), and CS2 and the connection portions d42, d32, d22 (d22b (not shown)), d12 (d12b), and d02 (d02b) are formed by the bonding electrode P I2 and the drain region R of the semiconductor region 203 DR The via contact electrode and connection part for connecting the laminated electrode P I2 The via contact electrodes C42, C32, C22, and C12 for connection and the connection portions d42, d32, d22, d12, and d02 are located in the source region R of the semiconductor region 203 when viewed from the Z direction. SO The first region R overlapping with CGI A pair of second regions R in the vicinity of WLHU1 The second region R WLHU1 is the first region R CGI The second region R is adjacent to both sides of the first region R in the Y direction. WLHU1 is the first region R CGI The bonding electrode P may be a region adjacent to both sides in the X direction. In the example of FIG. 17, the via contact electrode C12 is not provided. The via contact electrode C12 is shown in FIG. 16 etc. I2 The via contact electrodes C12b, CS2 and the connection portions d12b, d02b are formed on the pair of drain regions R of the semiconductor region 203 when viewed from the Z direction. DR The third region R overlaps with WLHU2 It is set up in.

[0148] In the wiring layer D0, a hookup wiring W0 is provided between the connection portion d02 and the connection portion d02b, connecting them. In the wiring layer D1, a hookup wiring W1 is provided between the connection portion d12 and the connection portion d12b, connecting them. In the wiring layer D2, a hookup wiring W2 is provided between the connection portion d22 and the connection portion d22b (not shown), connecting the connection portion d22 and the connection portion d22b, respectively. A pair of shield wirings s2 is provided between the connection portion d22b and the connection portion d22b. A passing wiring TW2 is provided between the shield wirings s2. In the wiring layer D3, a pair of shield wirings s3 is provided between the connection portion d32 and the connection portion d32. A passing wiring TW3 is provided between the shield wirings s3. Hookup wirings W3 may be provided between the shield wiring s3 and the connection portion d32 and between the shield wiring s2 and the connection portion d22b, connecting the connection portion d32 and the connection portion d32, respectively.

[0149] As shown in FIG. 17, the chip bonding electrode layer DB has a bonding electrode P I2 is connected to the connection portion d42 of the wiring layer D4. I2 17. The via contact electrode C42 is connected to the connection portion d42 at its upper end and to the connection portion d32 of the wiring layer D3 at its lower end. The via contact electrode C32 is connected to the connection portion d32 at its upper end and to the connection portion d22 of the wiring layer D2 at its lower end. The via contact electrode C22 is connected to the connection portion d22 at its upper end and to the connection portion d12 of the wiring layer D1 at its lower end. The connection portion d12 and the connection portion d12b of the wiring layer D1 are connected by a hook-up wiring W1 in FIG. 17. The via contact electrode C12b is connected to the connection portion d12b at its upper end and to the connection portion d02b of the wiring layer D0 at its lower end. The via contact electrode CS2 is connected to the connection portion d02b at its upper end and to the drain region R of the semiconductor region 203 at its lower end. DR is connected to.

[0150] In FIG. 17, the connection portion d12 and the connection portion d12b of the wiring layer D1 are connected by a hookup wiring W1. In this case, a via contact electrode C12 is not provided. The connection portion d02 of the wiring layer D0 is a dummy connection portion (wiring) that is not electrically connected to the connection portion d12 of the wiring layer D1. That is, the connection portion d02 is electrically insulated and floating. From the viewpoint of lithography, the dummy connection portion d02 is formed in the wiring layer D0. Furthermore, in order to reduce the risk of short circuits with adjacent wiring due to the influence of dust, the connection portion d02 is not connected to the connection portion d12. However, there are cases where the connection portion d02 and the connection portion d02b of the wiring layer D0 are connected by a hookup wiring W0. In this case, a via contact electrode C12 is provided, but a via contact electrode C12b is not provided. In this case as well, the connection portion d12b of the wiring layer D1 is a dummy connection portion (wiring) that is not electrically connected to the connection portion d02b of the wiring layer D0 because the via contact electrode C12b is not provided. That is, in this case, the connection portion d12b is electrically insulated and floating.

[0151] In this way, the second region R WLHU1 a via contact electrode and a connection portion provided in the third region R WLHU2 The via contact electrode and the connection portion are used to form the bonded electrode P I2 and the drain region R of the semiconductor region 203 DR In this case, the second region R WLHU1 The connection part d12 and the third region R WLHU2 The connection portion d12b of the wiring layer D1 is connected to the hook-up wiring W1 of the wiring layer D1, or the second region R WLHU1 The connection part d02 and the third region R WLHU2 The connection portion d02b is connected to the hookup wiring W0 of the wiring layer D0.

[0152] 17, the connection portion d42 of the wiring layer D4 corresponds to the connection portion d4 in FIGS. 7 and 8. The connection portions d31 and d32 of the wiring layer D3 correspond to the connection portion d3 in FIGS. 7 and 8. The connection portions d21 and d22 (d22b) of the wiring layer D2 correspond to the connection portion d2 in FIGS. 7 and 8. The connection portions d11 and d12 (d12b) of the wiring layer D1 correspond to the connection portion d1 in FIGS. 7 and 8. The connection portions d01 and d02 (d02b) of the wiring layer D0 correspond to the connection portion d0 in FIGS. 7 and 8.

[0153] [Chip bonding electrode layer DB bonding electrode P I2 Position Figure 18 shows the hook-up area R HU The adhesive electrode P I2 18 is a schematic plan view showing the position of the hook-up region R on the negative side in the X direction in the region MP'. HU (the upper region corresponding to the region indicated by D in FIG. 15).

[0154] As shown in FIG. 18, multiple bonded electrodes P I2 are arranged at predetermined intervals in the X and Y directions. 12 The arrangement pattern of the bonding electrodes P may be arranged at equal intervals in the X and Y directions, or may be arranged at unequal intervals in consideration of the routing of the connection wiring with the via contact electrodes CC. In this example, three bonding electrodes P are arranged per width in the X direction of one word line switch WLSW and per width in the Y direction of one memory block BLK. 12 Three bonded electrodes P 12 are located at different positions in the Y direction.

[0155] [Position of wiring CGI and connection part d42 on wiring layer D4] 19 is a schematic plan view showing the positions of the wiring CGI and the connection portion d42 provided in the wiring layer D4. In FIG. 19, the semiconductor region 203 and the gate electrode 206 are shown by dotted lines. In addition, in FIG. 19, the laminated electrode P shown in FIG. I2The position of the hook-up region R on the negative side of the X direction in the region MP' is shown by a dotted line. HU (the upper region corresponding to the region indicated by D in FIG. 15).

[0156] As shown in FIG. 19, two wirings CGI extending in the Y direction are arranged side by side for each word line switch WLSW. Of the two wirings CGI, the wiring on the negative side in the X direction is wiring CGI(1), and the wiring on the positive side in the X direction is wiring CGI(2). One or two connection parts d42 extending in the Y direction are provided in the space between the wirings CGI(1) and CGI(2). One end of the connection part d42 is connected to the bonding electrode P 12 and the other end is connected to the second region R of the wiring layer D3 through a via contact electrode C42. WLHU1 It is connected to the connection part d32 provided on the

[0157] [Positions of the connection parts d31 and d32 of the wiring layer D3 and the wiring pattern in the wiring layer D3] FIG. 20 is a schematic plan view showing an example of a wiring pattern in the wiring layer D3. In FIG. 20, the semiconductor region 203 and the gate electrode 206 are indicated by dotted lines. In FIG. 20, among the connection portions d31 and d32, the connection portions d31 and d32 in which the via contact electrodes C31 and C32 are written indicate that the via contact electrodes C31 and C32 are connected below them, while the connection portions d31 and d32 in which the via contact electrodes C31 and C32 are not written indicate that the via contact electrodes C31 and C32 are not connected below them. In FIG. 20, the pitch of the word line switches WLSW in the X direction is indicated as Xpitch, and the pitch of the word line switches WLSW in the Y direction is indicated as Ypitch. In FIG. 20, the area corresponding to the area shown in FIG. 15 is shown.

[0158] 20, one connection portion d31 is provided in line in the X direction per pitch Xpitch of one word line switch WLSW in the X direction. That is, the connection portions d31 are arranged at equal intervals or at predetermined intervals for each Xpitch. The connection portion d31 is connected to the source region R of the semiconductor region 203.SO The first region R overlapping with CGI The connection portion d31 is connected to the wiring CGI through a via contact electrode C41.

[0159] Furthermore, two connection portions d32 are arranged side by side in the X direction per pitch Xpitch of one word line switch WLSW in the X direction. That is, the connection portions d32 are arranged at equal intervals or predetermined intervals, such as a pitch dXpitch that is half the Xpitch, two for each Xpitch. The connection portions d32 are arranged in the first region R CGI The second region R is located on both sides of the Y direction. WLHU1 It is set up in.

[0160] Hookup Area R HUThe 16 connection portions d32 arranged in are active connection portions connected to via contact electrodes CC on the memory cell array MCA side and are sometimes called "word line hookup pads." Of these connection portions d32, connection portion d32(1) is connected to the hookup wirings W0 to W3 of memory block BLK(1), connection portion d32(2) is connected to the hookup wirings W0 to W3 of memory block BLK(2), connection portion d32(3) is connected to the hookup wirings W0 to W3 of memory block BLK(3), and connection portion d32(4) is connected to the hookup wirings W0 to W3 of memory block BLK(4). The connection portions d32 are connected to connection portion d42 via via contact electrodes C42, to connection portion d22 via via contact electrodes C32, or to no connection. The connection portions d32(1) and d32(2) in the first row RO1 of the memory block BLK(1) region are alternately arranged one by one in the X direction. The connection portions d32(3) and d32(4) of the sixth row RO6 in the area of ​​the memory block BLK(4) are alternately arranged one by one in the X direction. The connection portion d32(1) of the second row RO2 and the connection portion d32(2) of the third row RO3 arranged in the area of ​​the memory block BLK(2), and the connection portion d32(3) of the fourth row RP4 and the connection portion d32(4) of the fifth row RP4 arranged in the area of ​​the memory block BLK(3) are each arranged consecutively in the X direction. In this embodiment, in FIGS. 18 and 19, the bonding electrode P 12 The connection portion d42 and the wirings CGI(1) and CGI(2) are formed in a repeated pattern with the width of the word line switch WLSW in the X direction as a unit. 12 The connection portion d42 and the wirings CGI(1), CGI(2) may be a linearly symmetrical pattern (mirror pattern) with the width of the word line switch WLSW in the X direction as a unit. In this case, the connection portions d32(1) and d32(2) in the first row RO1 of the memory block BLK(1) area are arranged as follows: d32(1), d32(2), d32(2), d32(1), d32(1), d32(2), d32(2)...

[0161] Hookup Area R HU The row control circuit region R outside (positive side of the X direction)RC The 16 connection portions d32 (dummy) arranged in the above figure are dummy connection portions in a floating state that are not connected to anything. However, these connection portions d32 (dummy) may be connected to the via contact electrode C42 in the layer below them. Note that the connection portions d22, d12, and d02 arranged below the connection portions d32 (dummy) in the Z direction are also dummy.

[0162] As shown in FIG. 20 , a pair of shield wirings s3 extending in the X direction is provided between the connection points d32(1) and d32(2) of the first row RO1 in the memory block BLK(1) region and the connection point d32(1) of the second row RO2 in the boundary region between memory blocks BLK(1) and BLK(2); between the connection point d32(2) of the third row RO3 in the memory block BLK(2) region and the connection point d32(3) of the fourth row RO4 in the memory block BLK(3) region; and between the connection point d32(4) of the fifth row RO5 in the boundary region between memory blocks BLK(3) and BLK(4) and the connection points d32(3) and d32(4) of the sixth row RO6 in the memory block BLK(4) region. A plurality of passing wirings TW3 are provided between the pair of shield wirings s3. The passing wirings TW3 extend in the X direction and are aligned in the Y direction.

[0163] Although not shown in FIG. 20 , multiple hookup wirings W3 may be provided between the multiple connection portions d32 and the shield wiring s3. The multiple hookup wirings W3 extend in the X direction and are aligned in the Y direction. Each hookup wiring W3 connects one connection portion d32 to another connection portion d32 that is positioned differently in the X direction from the first connection portion d32. For example, the hookup wiring W3 connects one connection portion d32 to another connection portion d32 that is positioned on the positive side of the first connection portion d32 in the X direction.

[0164] Depending on the wiring pattern, the connection portion d32 is connected to the connection portion d42 of the wiring layer D4 via the via contact electrode C42, or to the connection portion d22 of the wiring layer D2 via the via contact electrode C32, or to neither.

[0165] The wiring patterns formed in the areas corresponding to memory blocks BLK(1) and BLK(2) and the wiring patterns formed in the areas corresponding to memory blocks BLK(3) and BLK(4) are linearly symmetrical with respect to the line corresponding to the central inter-block insulating layer ST in the Y direction in the figure.

[0166] 20, a wiring area in which the passing wiring TW3 is arranged is provided, but there may be cases in which no wiring area is provided. In this case, the wiring area of ​​the hookup wiring W3 can be expanded by the amount of the wiring area eliminated.

[0167] The shield wiring s3 is a wiring for shielding the hook-up wiring W3 and the passing wiring TW3. During a read operation, a write operation, an erase operation, etc., the hook-up wiring W3 is supplied with a read pass voltage V READ and write voltage V PGM , erase voltage V ERA In contrast, many of the wires in the passing wiring TW3 are connected to the ground voltage V SS to power supply voltage V CC A relatively low voltage of about 1000 volts is applied to the wiring adjacent to the wiring to which a high voltage is applied. The voltage is likely to increase unintentionally due to capacitive coupling. In order to suppress the voltage fluctuation of the passing wiring TW3, the shield wiring s3 is W3 and the passing wiring area R TW3 The shield wiring s3 is provided between the hook-up wiring W3 and the passing wiring TW3, and shields the hook-up wiring W3 and the passing wiring TW3. SS However, the shield wiring s3 is supplied with the voltage V generated by the voltage generator VG. DD In this case, the voltage V DD may be used as a power supply voltage for a given wiring.

[0168] [Positions of the connection portions d21 and d22 of the wiring layer D2 and the wiring pattern in the wiring layer D2] 21 is a schematic plan view showing an example of a wiring pattern in the wiring layer D2. In FIG. 21, among the connection portions d21, d22, and d22b, the connection portions d21, d22, and d22b in which the via contact electrodes C21 and C22 are written indicate that the via contact electrodes C21 and C22 are connected below them, and the connection portions d21, d22, and d22b in which the via contact electrodes C21 and C22 are not written indicate that the via contact electrodes C21 and C22 are not connected below them. Also, in FIG. 21, the pitch of the word line switches WLSW in the Y direction is written as Ypitch. Also, FIG. 21 shows an area corresponding to the area shown in FIG. 15.

[0169] 21, of the 32 connection parts d22 arranged in the first row RO1 of the memory block BLK(1) area, the 16 connection parts d22 arranged on the positive side in the X direction are dummy connection parts d22 arranged below the dummy connection parts d32 (dummy) of the wiring layer D3 in the Z direction. HU The remaining 16 connection portions d22(1), d22(2) arranged in the first row RO1 of the memory block BLK(1) region of the wiring layer D3 are connected to the connection portions d32(1), d32(2) arranged in the first row RO1 of the memory block BLK(1) region of the wiring layer D3 through via contact electrodes C32, and are arranged alternately in the X direction. One end of the hook-up wiring W2 is connected to some of these 16 connection portions d22(1), d22(2), in this example, the four connection portions d22(1) arranged at the 9th, 11th, 13th, and 15th positions counting from the negative side in the X direction. The other end of the hook-up wiring W2 is connected to the drain regions R of the four word line switches WLSW(1) arranged at the 9th, 10th, 13th, and 14th positions counting from the negative side in the X direction among the 16 word line switches WLSW(1), WLSW(2) arranged on the positive side in the Y direction of the memory block BLK(1) region. DR The hookup wiring W2 is connected to the connection portion d22b(1) disposed in the hookup region R. The hookup wiring W2 includes a portion extending from the connection portion d22(1) to the negative side in the Y direction, a portion extending in the X direction, and a portion extending to the negative side in the Y direction toward the connection portion d22b(1), and is formed, for example, in a stepped shape.HU At the positive end of the X direction of the row control circuit region R RC The overlapping area, i.e., the hook-up area R HU and memory hole region R MH The boundary area (hook-up area R HU and row control circuit region R RC Out of hookup area R HU The first portion E1 is the densest in the Y direction in the boundary portion with the area excluding the first portion E1.

[0170] Of the 32 connection parts d22 arranged in the second row RO2 of the boundary region between the memory blocks BLK(1) and BLK(2), the 16 connection parts d22 arranged on the positive side in the X direction are dummy connection parts d22 arranged below in the Z direction the dummy connection parts d32 (dummy) of the wiring layer D3. HU The remaining 16 connection portions d22(1) arranged in the second row RO2 of the boundary region between the memory blocks BLK(1) and BLK(2) of the wiring layer D3 are connected via via contact electrodes C32 to connection portions d32(1) arranged in the second row RO2 of the boundary region between the memory blocks BLK(1) and BLK(2). One end of the hookup wiring W2 is connected to some of these 16 connection portions d22(1), in this example, the four connection portions d22(1) arranged at the 13th to 16th positions counting from the negative side in the X direction. The other end of the hookup wiring W2 is connected to the drain regions R of the four word line switches WLSW(1) arranged at the 13th to 16th positions counting from the negative side in the X direction out of the 16 word line switches WLSW(1) arranged in the second row RO2 of the boundary region between the memory blocks BLK(1) and BLK(2). DR The hookup wiring W2 is connected to the connection portion d22b(1) disposed on the wiring board 1. The hookup wiring W2 is formed, for example, in a stepped shape, and includes a portion extending from the connection portion d22(1) to the positive side in the Y direction, a portion extending in the X direction, and a portion extending to the positive side in the Y direction toward the connection portion d22b(1).

[0171] Of the 32 connection parts d22 arranged in the third row RO3 of the memory block BLK(2) area, the 16 connection parts d22 arranged on the positive side in the X direction are dummy connection parts d22 arranged below the dummy connection parts d32 (dummy) of the wiring layer D3 in the Z direction. HU The remaining 16 connection portions d22(2) arranged in the third row RO3 of the memory block BLK(2) region of the wiring layer D3 are connected to the connection portions d32(2) arranged in the third row RO3 of the memory block BLK(2) region of the wiring layer D3 through via contact electrodes C32. One end of the hookup wiring W2 is connected to some of these 16 connection portions d22(2), in this example, the four connection portions d22(2) arranged at the 13th to 16th positions counting from the negative side in the X direction. The other end of the hookup wiring W2 is connected to the drain regions R of the four word line switches WLSW(2) arranged at the 13th to 16th positions counting from the negative side in the X direction out of the 16 word line switches WLSW(2) arranged at the negative side in the Y direction of the memory block BLK(2) region. DR The hookup wiring W2 is connected to the connection portion d22b(2) disposed on the wiring board 1. The hookup wiring W2 is formed, for example, in a stepped shape, and includes a portion extending from the connection portion d22(2) to the negative side in the Y direction, a portion extending in the X direction, and a portion extending to the positive side in the Y direction toward the connection portion d22b(2).

[0172] 21, a pair of shield wirings s2 extending in the X direction is provided in each of the three wiring spaces between the connection portions d32b(1) to d32b(4) on each row, on the side where no hookup wirings W2 are arranged. A plurality of passing wirings TW2 are provided between the pair of shield wirings s2. The plurality of passing wirings TW2 extend in the X direction and are aligned in the Y direction.

[0173] The wiring patterns formed in the areas corresponding to memory blocks BLK(1) and BLK(2) and the wiring patterns formed in the areas corresponding to memory blocks BLK(3) and BLK(4) are linearly symmetrical with respect to the line corresponding to the central inter-block insulating layer ST in the Y direction in the figure.

[0174] [Positions of the connection parts d11, d12, and d12b of the wiring layer D1, and the wiring pattern in the wiring layer D1] 22 is a schematic plan view showing an example of a wiring pattern in the wiring layer D1. In FIG. 22, among the connection portions d11, d12, and d12b, the connection portions d11, d12, and d12b in which the via contact electrodes C11 and C12 are written indicate that the via contact electrodes C11 and C12 are connected below, and the connection portions d11, d12, and d12b in which the via contact electrodes C11 and C12 are not written indicate that the via contact electrodes C11 and C12 are not connected below. Also, in FIG. 22, the pitch of the word line switches WLSW in the Y direction is written as Ypitch. Also, FIG. 22 shows an area corresponding to the area shown in FIG. 15.

[0175] 22, of the 32 connection parts d12 arranged in the first row RO1 of the memory block BLK(1) area, the 16 connection parts d12 arranged on the positive side in the X direction are dummy connection parts d12 arranged below the dummy connection parts d32 (dummy) of the wiring layer D3 in the Z direction. HUOf the remaining 16 connection portions d12(1) and d12(2) arranged in the wiring layer D2, the connection portions d12(1) that overlap in the Z direction with the 9th, 11th, 13th, and 15th connection portions d22(1) counting from the negative side in the X direction, which are already connected to the hookup wiring W2, are dummy connection portions that are not connected anywhere. The remaining 12 connection portions d12(1) and d12(2) are connected to the connection portions d22(1) and d22(2) arranged in the first row RO1 of the memory block BLK(1) region of the wiring layer D2 through via contact electrodes C32, and are arranged alternately in the X direction. In this wiring layer D1, one end of the hookup wiring W1 is connected to eight connection portions d12(2) that are arranged in even positions, 2nd to 16th, counting from the negative side in the X direction, of the 16 connection portions d12(1) and d12(2), i.e., all of the connection portions d12(2) arranged in this row. The other end of the hook-up wiring W1 is connected to the drain regions R of all eight word line switches WLSW(2), the third, fourth, seventh, eighth, eleventh, twelfth, fifteenth, and sixteenth word line switches WLSW(2) counting from the negative side in the X direction, of the 16 word line switches WLSW(1), WLSW(2) arranged in the first row RO1 of the memory block BLK(1) area. DR The hookup wiring W1 is connected to the connection portion d12b(2) disposed in the hookup region R. The hookup wiring W1 includes a portion extending from the connection portion d12(2) to the negative side in the Y direction, a portion extending in the X direction, and a portion extending to the negative side in the Y direction toward the connection portion d12b(2), and is formed, for example, in a stepped shape. HU At the positive end of the X direction of the row control circuit region R RC The overlapping area, i.e., the hook-up area R HU and memory hole region R MH The second portion E2 is the most densely packed in the Y direction at the boundary portion with the first portion E1.

[0176] Of the 32 connection parts d12 arranged in the second row RO2 of the boundary region between the memory blocks BLK(1) and BLK(2), the 16 connection parts d12 arranged on the positive side in the X direction are dummy connection parts d12 arranged below in the Z direction the dummy connection parts d32 (dummy) of the wiring layer D3. HUOf the remaining 16 connection portions d12(1) arranged in the wiring layer D2, the connection portions d12(1) that overlap in the Z direction with the 13th to 16th connection portions d22(1) counting from the positive side in the X direction that are already connected to the hookup wiring W2 in the wiring layer D2 are dummy connection portions that are not connected anywhere. The remaining 12 connection portions d12(1) are connected to the connection portions d22(1) arranged in the second row RO2 of the wiring layer D2 through via contact electrodes C22. One end of the hookup wiring W1 is connected to some of these 12 connection portions d12(1), in this example, the eight connection portions d12(1) arranged in the fifth to twelfth positions counting from the negative side in the X direction. The other end of the hookup wiring W1 is connected to the drain regions R of the fifth to twelfth word line switches WLSW(1) counting from the negative side in the X direction that are arranged in the second row RO2 in the Y direction of the memory block BLK(1) area. DR The hookup wiring W1 is connected to the connection portion d12b(1) disposed at the terminal d12b(1). The hookup wiring W1 is formed, for example, in a stepped shape, including a portion extending from the connection portion d12(1) to the positive side in the Y direction, a portion extending in the X direction, and a portion extending to the positive side in the Y direction toward the connection portion d22b(1).

[0177] Of the 32 connection parts d12 arranged in the third row RO3 of the memory block BLK(2) area, the 16 connection parts d12 arranged on the positive side in the X direction are dummy connection parts d12 arranged below the dummy connection parts d32 (dummy) of the wiring layer D3 in the Z direction. HUOf the remaining 16 connection parts d12(2) arranged in the wiring layer D2, the connection parts d12(2) that overlap in the Z direction with the 13th to 16th connection parts d22(2) counting from the positive side in the X direction, which are already connected to the hookup wiring W2, are dummy parts that are not connected anywhere. The remaining 12 connection parts d12(2) are connected to connection parts d22(2) arranged in the third row RO3 of the memory block BLK(2) region of the wiring layer D2 through via contact electrodes C22. One end of the hookup wiring W2 is connected to some of these 12 connection parts d12(2), in this example, the eight connection parts d12(2) arranged in the fifth to twelfth positions counting from the negative side in the X direction. The other end of the hookup wiring W2 is connected to the drain regions R of the word line switches WLSW(2) that are arranged in the third row RO3 of the memory block BLK(2) region and are located in the fifth to twelfth positions counting from the negative side in the X direction. DR The hookup wiring W1 is connected to the connection portion d12b(2) disposed on the wiring board 11. The hookup wiring W1 is formed, for example, in a stepped shape, and includes a portion extending from the connection portion d12(2) to the negative side in the Y direction, a portion extending in the X direction, and a portion extending to the negative side in the Y direction toward the connection portion d12b(2).

[0178] The wiring patterns formed in the areas corresponding to memory blocks BLK(1) and BLK(2) and the wiring patterns formed in the areas corresponding to memory blocks BLK(3) and BLK(4) are linearly symmetrical with respect to the line corresponding to the central inter-block insulating layer ST in the Y direction in the figure.

[0179] [Positions of the connection parts d01, d02, and d02b on the wiring layer D0, and the wiring pattern on the wiring layer D0] FIG. 23 is a schematic plan view showing an example of a wiring pattern in the wiring layer D0. FIG. 24 is an enlarged plan view of the region indicated by F in FIG. 23. In FIGS. 23 and 24, among the connection portions d01, d02b, and d03, the connection portions d01, d02b, and d03 in which the via contact electrodes CS1, CS2, and CS3 are written indicate that the via contact electrodes CS1, CS2, and CS3 are connected below them, while the connection portions d01, d02b, and d03 in which the via contact electrodes CS1, CS2, and CS3 are not written indicate that the via contact electrodes CS1 and CS2 are not connected below them. In FIG. 23, the pitch of the word line switches WLSW in the Y direction is indicated as Ypitch. FIG. 23 also shows a region corresponding to the region shown in FIG. 15.

[0180] 23 and 24, of the 32 connection parts d02 arranged in the first row RO1 of the memory block BLK(1) region, 16 connection parts d02 arranged on the positive side in the X direction are dummy connection parts d02 arranged below the dummy connection parts d32 (dummy) of the wiring layer D3 in the Z direction. HU Of the remaining 16 connection portions d02(1) and d02(2) arranged in the wiring layer D0, the ninth, eleventh, thirteenth, and fifteenth connection portions d02(1) and even-numbered connection portions d02(2), counting from the negative side in the X direction, that are already connected to the hookup wiring W2 in the wiring layer D1, are dummy connection portions that are not connected anywhere. The remaining first, third, fifth, and seventh connection portions d02(1) are connected to the connection portion d12(1) arranged in the first row RO1 of the wiring layer D1 through the via contact electrode C12 and are arranged in the X direction. In this wiring layer D0, one end of the hookup wiring W0 is connected to the remaining four connection portions d02(1). The other end of the hook-up wiring W0 is connected to the drain regions R of the first, second, fifth, and sixth word line switches WLSW(1) from the negative side in the X direction among the 16 word line switches WLSW(1) and WLSW(2) arranged in the first row RO1 of the memory block BLK(1) area. DRThe hookup wiring W0 is connected to a connection portion d02b(1) disposed on the wiring board 1. The hookup wiring W0 is formed, for example, in a stepped shape, and includes a portion extending from the connection portion d02(1) to the negative side in the Y direction, a portion extending in the X direction, and a portion extending to the negative side in the Y direction toward the connection portion d02b(1).

[0181] Of the 32 connection parts d02 arranged in the second row RO2 of the boundary region between the memory blocks BLK(1) and BLK(2), the 16 connection parts d02 arranged on the positive side in the X direction are dummy connection parts d02 arranged below in the Z direction the dummy connection parts d32 (dummy) of the wiring layer D3. HU Of the remaining 16 connection portions d02(1) arranged in the wiring layer D2, the connection portions d02(1) that overlap in the Z direction with the 9th, 11th, 13th, and 15th connection portions d22(1) counting from the negative side in the X direction that are already connected to the hookup wiring W2 on the wiring layer D2, and the connection portions d02(2) that overlap in the Z direction with the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th connection portions d12(2) counting from the negative side in the X direction that are already connected to the hookup wiring W1 on the wiring layer D1 are dummy and not connected anywhere. The remaining four connection portions d02(1) are connected to connection portions d12(1) arranged in the second row RO2 of the wiring layer D1 through via contact electrodes C12. One end of the hookup wiring W0 is connected to these four connection portions d02(1). The other end of the hook-up wiring W0 is connected to the drain region R of the first to fourth word line switches WLSW(1) counting from the negative side in the X direction, which are arranged in the second row RO2 of the memory block BLK(1). DR The hookup wiring W0 is connected to a connection portion d02b(1) disposed on the wiring board 1. The hookup wiring W0 is formed, for example, in a stepped shape, including a portion extending from the connection portion d02(1) to the positive side in the Y direction, a portion extending in the X direction, and a portion extending to the positive side in the Y direction toward the connection portion d02b(1).

[0182] Of the 32 connection parts d02 arranged in the third row RO3 of the memory block BLK(2) area, the 16 connection parts d02 arranged on the positive side in the X direction are dummy connection parts d02 arranged below the dummy connection parts d32 (dummy) of the wiring layer D3 in the Z direction. HU Of the remaining 16 connection portions d02(2) arranged in the wiring layer D2, the connection portions d02(2) that overlap in the Z direction with the 9th, 11th, 13th, and 15th connection portions d22(2) counting from the negative side in the X direction that are already connected to the hookup wiring W2 on the wiring layer D2, and the connection portions d02(2) that overlap in the Z direction with the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th connection portions d12(2) counting from the negative side in the X direction that are already connected to the hookup wiring W1 on the wiring layer D1 are dummy and not connected anywhere. The remaining four connection portions d02(2) are connected to the connection portion d12(2) arranged in the third row RO3 of the wiring layer D1 through the via contact electrode C12. One end of the hookup wiring W0 is connected to these four connection portions d02(2). The other end of the hook-up wiring W0 is connected to the drain regions R of the first to fourth word line switches WLSW(2) counting from the negative side in the X direction, which are arranged in the third row RO3 of the memory block BLK(2) area. DR The hookup wiring W0 is connected to a connection portion d02b(2) disposed on the wiring board 1. The hookup wiring W0 is formed, for example, in a stepped shape, including a portion extending from the connection portion d02(2) to the positive side in the Y direction, a portion extending in the X direction, and a portion extending to the positive side in the Y direction toward the connection portion d02b(2).

[0183] As shown in FIGS. 23 and 24, all the connection portions d01 are connected to the source regions R of the word line switches WLSW(1) to WLSW(4) through via contact electrodes CS1. SO In addition, all the connection parts d02b are connected to the drain regions R of the word line switches WLSW(1) to WLSW(4) through via contact electrodes CS2. DR is connected to.

[0184] In addition, in the first row RO1 of the wiring layer D0, a pair of word-line switches WLSW(1) and a pair of word-line switches WLSW(2) are arranged alternately in the X direction, two by two. For this reason, a signal line BLKSEL(1) is provided that connects the gate electrodes 206 of the word-line switches WLSW(1) arranged every other word-line switch in the X direction, and a connection portion d03(1) and a via contact electrode CS3 that connect this signal line BLKSEL(1) to the gate electrode 206 of the word-line switch WLSW(1). In addition, a signal line BLKSEL(2) is provided that connects the gate electrodes 206 of the word-line switches WLSW(2) arranged every other word-line switch in the X direction, and a connection portion d03(2) and a via contact electrode CS3 that connect this signal line BLKSEL(2) to the gate electrode 206 of the word-line switch WLSW(2). The signal lines BLKSWL(1) and BLKSEL(2) are wired to bypass the STI2 side of the word line switches WLSW(1) and WLSW(2) and surround the negative Y-side of the word line switches WLSW(1) and WLSW(2). The positive Y-side of the signal lines BLKSEL(1) and BLKSEL(2) is open, ensuring wiring space for the hook-up wiring W0.

[0185] In the second row RO2 of the wiring layer D0, pairs of word-line switches WLSW(1) are arranged consecutively in the X direction. For this reason, a signal line BLKSEL(1) is provided that connects the gate electrodes 206 of the word-line switches WLSW(1) adjacent to each other in the X direction, and a connection portion d03(1) and a via contact electrode CS3 are provided that connect this signal line BLKSEL(1) to the gate electrode 206 of the word-line switch WLSW(1). Note that all of the word-line switches WLSW(1) in the second row RO2 may be connected by a single gate electrode 206 extending in the X direction.

[0186] Furthermore, in the third row RO3 of the wiring layer D0, pairs of word-line switches WLSW(2) are arranged consecutively in the X direction. For this reason, a signal line BLKSEL(2) is provided that connects the gate electrodes 206 of the word-line switches WLSW(2) adjacent to each other in the X direction, and a connection portion d03(2) and a via contact electrode CS3 are provided that connect this signal line BLKSEL(2) to the gate electrode 206 of the word-line switch WLSW(2). Note that all of the word-line switches WLSW(2) in the third row RO3 may be connected by a single gate electrode 206 extending in the X direction.

[0187] The wiring patterns formed in the areas corresponding to memory blocks BLK(1) and BLK(2) and the wiring patterns formed in the areas corresponding to memory blocks BLK(3) and BLK(4) are linearly symmetrical with respect to the line corresponding to the central inter-block insulating layer ST in the Y direction in the figure.

[0188] FIG. 25 is a plan view showing yet another example of the wiring layer D1. In the wiring region where the hookup wires W0, W1, and W2 are formed, it is desirable to form the hookup wires W0 to W3 at a substantially constant pitch during exposure such as photolithography. Furthermore, when forming multiple wiring layers, CMP (Chemical Mechanical Polishing) is performed. It is desirable that the arrangement density of the wiring layers D0 to D3 be uniform when performing CMP. Therefore, as shown in the example of the wiring layer D1 in FIG. 25, in order to arrange the hookup wires W0 to W3 (only the hookup wire W1 is shown) at a substantially constant interval in the wiring region, dummy wires that are not connected to any of the connection portions d02 to d32 may be provided as the hookup wires W0 to W3.

[0189] Fig. 26 is a plan view showing yet another example of the wiring layer D1. The difference from the wiring layer D1 of Fig. 25 is that the hookup wiring W1b has an inclined portion T that is inclined at a predetermined angle with respect to the X direction and the Y direction. The other configurations are the same as those of the first embodiment, so detailed description will be omitted.

[0190] [Effects of the first embodiment] 27 and 28 are schematic plan views of hookup wirings W1 and W2 provided in the first row RO1 of wiring layers D1 and D2. Fig. 27 is a schematic plan view showing the hookup wiring W1 of a comparative example. Figs. 28(a) and 28(b) are schematic plan views showing the hookup wirings W1 and W2 of this embodiment.

[0191] In the comparative example shown in FIG. 27, the hookup wiring W1 connected to the connection part d12(1) connected to the word line WL(1) of the memory block BLK(1) and the connection part d12(2) connected to the word line WL(2) of the memory block BLK(2) are wired in the same wiring layer D1. In this case, the hookup wirings W1 of the different memory blocks BLK(1) and BLK(2) are close to each other. The hookup wiring W1 connected to the word line WL of the selected memory block BLK is normally supplied with a read pass voltage V during read and write operations. READ , write voltage V PGM In contrast to this, the hookup wire W1 connected to the word line WL of the unselected memory block BLK is in a floating state, and therefore an undefined low voltage is applied to it. Also, during an erase operation, the hookup wire W1 connected to the word line WL of the selected memory block BLK is supplied with a ground voltage V SS A low voltage of about 1000 V is applied to the source line SL and the bit line BL. era Therefore, the erase voltage V is applied to the hookup wiring W1 connected to the word line WL of the unselected memory block BLK. era In this way, if a low-voltage hookup wiring W1 is adjacent to a high-voltage hookup wiring W1, problems such as time-dependent dielectric breakdown (TDDB) may occur. For this reason, the arrangement pitch of the hookup wiring W1 cannot be made too small, and the hookup region R HU and row control circuit region R RD As a result, the number of hookup wirings W1 near the boundary of the memory hole region R MHThere is a problem that the number of lower word line switches WLSW cannot be increased. Furthermore, if a short circuit occurs between adjacent hookup wires W1 due to the influence of dust or the like, there is a possibility that the two memory blocks BLK(1) and BLK(2) will fail.

[0192] In contrast, in the first embodiment, as shown in FIGS. 28(a) and 28(b), the wiring layer D2 (and D0) to which the memory block BLK(1) is wired is different from the wiring layer D1 to which the memory block BLK(2) is wired. As a result, in the same wiring layer D1 or D2 (and D0), adjacent hookup wirings W1 or W2 are connected to the word lines WL of the same memory block BLK(1) or BLK(2), respectively, so that no high potential difference occurs between adjacent hookup wirings W1 or W2. As a result, the arrangement pitch of the hookup wirings W1 or W2 can be made smaller, and the hookup region R HU and row control circuit region R RD As a result, the number of hookup wirings W1 near the boundary of the memory hole region R MH The number of lower word line switches WLSW can be further increased. In addition, even if a short circuit occurs between the hookup wirings W1 or W2 due to dust or the like, only one memory block BLK is affected, so the impact of the short circuit is also reduced.

[0193] [Second embodiment] [Positions of the connection parts d32 to d02 of the wiring layers D3 to D0] Fig. 29 is a schematic plan view showing the positions of the connection portions d32 to d02 in the wiring layers D3 to D0 according to the second embodiment. In Fig. 29, the connection portions d32, d22, d12, and d02 in the wiring layers D3 to D0 shown in Figs. 20 to 24 are collectively referred to as the connection portion dn2. The other configurations are the same as those in the first embodiment, and therefore a description of the overlapping portions will be omitted.

[0194] In this embodiment, the order of the numbers of the word lines connected to the connection portion dn2(1) of the second row RO2 of the wiring layers D3-D0 is the same as the order of the numbers of the word lines connected to the connection portion dn2(2) of the third row RO3 of the wiring layers D3-D0. In other words, the order of the numbers of the conductive layers 110 of the memory block BLK(1) connected to the connection portion dn2(1) of the second row RO2 of the wiring layers D3-D0 is the same as the order of the numbers of the conductive layers 110 of the memory block BLK(2) connected to the connection portion dn2(2) of the third row RO3 of the wiring layers D3-D0.

[0195] 29 as an example, the numbers of the word lines WL connected to the connection portions dn2(1) arranged in the second row RO2 are set to 0, 1, 6, 7, 12, 13, 18, 19, 24, 25, ... in order from the negative side in the X direction. On the other hand, the numbers of the word lines WL connected to the connection portions dn2(2) arranged in the third row RO3 are also set to 0, 1, 6, 7, 12, 13, 18, 19, 24, 25, ... in order from the negative side in the X direction. Note that the numbers of the word lines WL correspond to the physical positions of the conductive layers 110 in the Z direction, and may be counted from the bit line BL side or the source line SL side.

[0196] [Effects of the second embodiment] In this arrangement, the drain regions R of the word line switches WLSW(1) and WLSW(2) that share the semiconductor region 203 DR Since the numbers of the word lines WL connected to the source region R SO This has the advantage that there is no need to provide a switching circuit or the like between the wiring CGI connected to the wiring CGI and the control circuit that supplies voltage to the wiring CGI, and the circuit configuration is simplified.

[0197] [First Modification of Second Embodiment] FIG. 30 is a schematic plan view showing the positions of the connection portions d32 to d02 of the wiring layers D3 to D0 according to the first modification of the second embodiment.

[0198] In the first modification, of the multiple connection portions dn2(1) arranged in the second row RO2 of the wiring layers D3 to D0, the 11th and 20th connection portions dn2(1) counting from the negative side in the X direction are dummy portions that are not connected to anything. Also, of the multiple connection portions dn2(2) arranged in the third row RO3 of the wiring layers D3 to D0, the 1st and 12th connection portions dn2(2) counting from the negative side in the X direction are dummy portions that are not connected to anything.

[0199] As a result, the numbers of the word lines WL connected to the connection part dn2(1) of the second row RO2 and the numbers of the word lines WL connected to the connection part dn2(2) of the third row RO3 are shifted by one in the X direction. However, the order of the numbers of the word lines WL connected to the connection part dn2(1) of the second row RO2 and the order of the numbers of the word lines WL connected to the connection part dn2(2) of the third row RO3 are the same, so the order of the numbers of the word lines WL connected to the word line switches WLSW(1) and WLSW(2) is the same as in the second embodiment. Therefore, even if the numbers of the connected word lines WL are shifted in this way, the effects of the second embodiment can be obtained.

[0200] [Second Modification of the Second Embodiment] FIG. 31 is a schematic plan view showing the positions of the connection portions d32 to d02 of the wiring layers D3 to D0 according to a second modification of the second embodiment.

[0201] In the second modification, of the multiple connection portions dn2(1) arranged in the second row RO2 of the wiring layers D3 to D0, the second, eighth, eleventh, and twelfth connection portions dn2(1) counting from the negative side in the X direction are dummy portions that are not connected to anything. Also, of the multiple connection portions dn2(2) arranged in the third row RO3 of the wiring layers D3 to D0, the first, sixth, seventh, and fifteenth connection portions dn2(2) counting from the negative side in the X direction are dummy portions that are not connected to anything.

[0202] As a result, the numbers of the word lines WL connected to the connection portion dn2(1) of the second row RO2 and the numbers of the word lines WL connected to the connection portion dn2(2) of the third row RO3 are partially offset in the X direction and partially match. However, the order of the numbers of the word lines WL connected to the connection portion dn2(1) of the second row RO2 and the order of the numbers of the word lines WL connected to the connection portion dn2(2) of the third row RO3 are the same, so the order of the numbers of the word lines WL connected to the word line switches WLSW(1) and WLSW(2) is the same as in the second embodiment. Therefore, the effects of the second embodiment can be obtained even if the numbers of the connected word lines WL are offset or match.

[0203] [Third embodiment] 32 is a schematic plan view showing a configuration example of a semiconductor wafer 500 according to the third embodiment. Note that in the third embodiment, a description of the same configuration as in the first embodiment will be omitted.

[0204] 32, the semiconductor substrate 500 is provided with four memory planes MP20 to MP23 aligned in the X and Y directions. In the center of each of these four memory planes MP20 to MP23, two row control circuit regions R aligned in the X direction are provided. RC In addition, these two row control circuit regions R RC Two block decoder regions R BD In addition, these two block decoder regions R BD Two peripheral circuit regions R PC In addition, two peripheral circuit regions R PC Each of the two column control circuit regions R CC is provided.

[0205] In the example of FIG. 32, two row control circuit regions R are provided at the center of each of the memory planes MP20 to MP23 in the X direction. RC The inner part of the hook-up area HU2 The memory hole area R MH2The inner end of the row control circuit region R RC and the block decoder region R BD It overlaps with the peripheral circuit area R PC is the memory hole region R MH2 The control circuit SYN is provided in the center of the four memory planes MP20 to MP23. The control circuit SYN has a plurality of through wirings TW that connect the peripheral circuits PC inside the memory planes MP and connect the peripheral circuits PC between the plurality of memory planes MP.

[0206] In this embodiment, the row control circuit regions R provided in the center of each of the memory planes MP20 to MP23 are RC The layout pattern of the word line switch WLSW and the hook-up region R HU2 By making the arrangement patterns of the connecting portions d31 to d01, d32 to d02, hookup wirings W2 to W0, etc. similar to those of the first embodiment, it is possible to obtain the same effects as those of the first embodiment.

[0207] [Fourth embodiment] [Structure of word line switch WLSW and select gate line switch SGSW] Fig. 33 is a schematic plan view showing an example of the configuration of word line switches WLSW according to the fourth embodiment. Note that Fig. 33 corresponds to, for example, the portion indicated by B in Fig. 14. For ease of explanation, Fig. 33 also shows an example in which the number of word line switches WLSW (i.e., the number of word lines WL) in one memory block BLK is 24. However, the number of word line switches WLSW is not limited to this number.

[0208] 15, two word line switches WLSW adjacent in the X direction are connected by a common gate electrode 206 to form one transistor group TG2. In contrast, in the fourth embodiment, four word line switches WLSW adjacent in the X direction are connected by a common gate electrode 206 to form one transistor group TG3.

[0209] In the first row RO1, four word line switches WLSW(1) adjacent in the X direction are connected by a common gate electrode 206 to form one transistor group TG3. Also, in the first row RO1, four word line switches WLSW(2) adjacent in the X direction are connected by a common gate electrode 206 to form one transistor group TG3. Then, transistor groups TG3 consisting of word line switches WLSW(1) and transistor groups TG3 consisting of word line switches WLSW(2) are arranged alternately in the X direction. In the second row RO2 and the third row RO3, the arrangement patterns of the four word line switches WLSW(1) and WLSW(2) are also the same to ensure consistency with the pattern in the first row RO1. The four word line switches WLSW(1) and four word line switches WLSW(2) are connected by a common gate electrode 206 to form one transistor group TG3. However, all the word line switches WLSW(1) in the second row RO2 and all the word line switches WLSW(2) in the third row RO3 may be connected by a single gate electrode 206 extending in the X direction.

[0210] Between the semiconductor regions 203 constituting the word line switches WLSW included in the same transistor group TG3, an insulating region STI1 is provided to insulate the semiconductor regions 203. Between the semiconductor regions 203 constituting the word line switches WLSW included in different transistor groups TG3, an insulating region STI2 is provided to insulate the semiconductor regions 203 of different memory blocks BLK. The width of the insulating region STI2 in the X direction is larger than the width of the insulating region STI1 in the X direction. Furthermore, the width of the insulating region STI2 in the Y direction is larger than the width of the insulating region STI1 in the X direction.

[0211] In the fourth embodiment, the number of insulating regions STI2 is smaller than that in the first embodiment, so that the row control circuit region R RD The length in the X direction can be made smaller than that of the first embodiment.

[0212] [Positions of the connection portions d21 and d22 of the wiring layer D2 and the wiring pattern in the wiring layer D2] Fig. 34 is a schematic plan view showing an example of a wiring pattern in the wiring layer D2. The only difference from the wiring pattern of the first embodiment shown in Fig. 21 is the connection point of the hookup wiring W2 on the word line switch WLSW side, and the other configurations are the same as those of the first embodiment. Therefore, a description of the overlapping parts will be omitted, and only the different parts will be described.

[0213] As shown in Figure 34, the hook-up area R HU One end of the hookup wiring W2 is connected to some of the 16 connection parts d22(1), d22(2) arranged in the first row RO1 of the memory block BLK(1) area, in this example, four connection parts d22(1) arranged every other on the positive side in the X direction (the 9th, 11th, 13th, and 15th connection parts d22(1)). The other end of the hookup wiring W2 is connected to the drain regions R of the four consecutive word line switches WLSW(1) that are arranged in the first row RO1 of the memory block BLK(1) area and are located 5th to 8th from the most positive side in the X direction. DR 22b(1) and the connecting portion d22b(2) arranged at the same position.

[0214] [Positions of the connection parts d11, d12, and d12b of the wiring layer D1, and the wiring pattern in the wiring layer D1] Fig. 35 is a schematic plan view showing an example of a wiring pattern in the wiring layer D1. The only difference from the wiring pattern of the first embodiment shown in Fig. 22 is the connection point of the hookup wiring W1 on the word line switch WLSW side, and the other configurations are the same as those of the first embodiment. Therefore, a description of the overlapping parts will be omitted, and only the different parts will be described.

[0215] 35, of the 32 connection parts d12 arranged in the first row RO1 of the region of the memory block BLK(1), the 16 connection parts d12 arranged on the positive side in the X direction are dummy connection parts d12 arranged below the dummy connection parts d32 (dummy) of the wiring layer D3 in the Z direction. HUOf the remaining 16 connection parts d12(1), d12(2) arranged in the first row RO1 of the memory block BLK(1), one end of the hookup wiring W1 is connected to the eight connection parts d12(2) arranged in even positions, i.e., to all connection parts d12(2) arranged in this row. The other end of the hookup wiring W1 is connected to the drain regions R of all eight word line switches WLSW(2) arranged in the fifth to eighth and thirteenth to sixteenth positions, counting from the negative side in the X direction, of the 16 word line switches WLSW(1), WLSW(2) arranged in the first row RO1 of the memory block BLK(1). DR The connecting portion d12b(2) is connected to the connecting portion d12b(2) arranged at the

[0216] [Positions of the connection parts d01, d02, and d02b on the wiring layer D0, and the wiring pattern on the wiring layer D0] Fig. 36 is a schematic plan view showing an example of a wiring pattern in the wiring layer D0. The only difference from the wiring pattern of the first embodiment shown in Fig. 22 is the connection point of the hookup wiring W1 on the word line switch WLSW side, and the other configurations are the same as those of the first embodiment. Therefore, a description of the overlapping parts will be omitted, and only the different parts will be described.

[0217] 36, of the 32 connection parts d02 arranged in the first row RO1 of the memory block BLK(1) area, 16 connection parts d02 arranged on the positive side in the X direction are dummy connection parts d02 arranged below the dummy connection part d32 (dummy) of the wiring layer D3 in the Z direction. HU Of the remaining 16 connection parts d02(1), d02(2) arranged in the first row RO1 of the area of ​​the memory block BLK(1), one end of the hook-up wiring W0 is connected to the first to fourth connection parts d02(1) from the negative side in the X direction. The other end of the hook-up wiring W0 is connected to the drain region R of the first to fourth word line switches WLSW(1) from the negative side in the X direction from the 16 word line switches WLSW(1), WLSW(2) arranged in the first row RO1 of the area of ​​the memory block BLK(1). DR It is connected to the connection part d02b(1) arranged at

[0218] According to this embodiment, the connection destinations of the hookup wires W2 to W0 on the drain side of the word line switches WLSW can be grouped close together, which makes the wiring design easier.

[0219] [Fifth embodiment] Fig. 37 is a schematic plan view showing an example of the configuration of word line switches WLSW according to the fifth embodiment. Note that Fig. 37 corresponds to, for example, the portion indicated by B in Fig. 14. For ease of explanation, Fig. 37 also shows an example in which the number of word line switches WLSW (i.e., the number of word lines WL) in one memory block BLK is 16. However, the number of word line switches WLSW is not limited to this number.

[0220] In this embodiment, the pitch ratio in the Y direction between the word line switches WLSW and the memory blocks BLK is 3:4. That is, the Y direction length of four word line switches WLSW aligned in the Y direction is equal to the Y direction length of three memory blocks BLK aligned in the Y direction. Hereinafter, this arrangement pattern of word line switches WLSW may be referred to as "4Tr / 3BLK."

[0221] As shown in FIG. 37, in this embodiment, multiple sets of four word line switches WLSW aligned in the Y direction are aligned in the X direction, corresponding to the three memory blocks BLK aligned in the Y direction. Of the multiple word line switches WLSW aligned in the X direction, in the first row RO1, a word line switch WLSW(1) connected to the word line WL of memory block BLK(1), a word line switch WLSW(2) connected to the word line WL of memory block BLK(2), and a word line switch WLSW(3) connected to the word line WL of memory block BLK(3) are repeatedly arranged in this order in the X direction. In the second row RO2, the word line switches WLSW(1) connected to the word line WL of memory block BLK(1) are consecutively arranged in the X direction. In the third row RO3, the word line switches WLSW(2) connected to the word line WL of memory block BLK(2) are consecutively arranged in the X direction. In the fourth row RO4, the word line switches WLSW(3) connected to the word line WL of memory block BLK(3) are consecutively arranged in the X direction.

[0222] Fig. 38 is a schematic plan view showing the wiring patterns of the hookup wirings W2, W1, and W0 arranged in the first row RO1, in which Fig. 38(a) shows the wiring layer D2, Fig. 38(b) shows the wiring layer D1, and Fig. 38(c) shows the wiring layer D0.

[0223] As shown in FIG. 38(a), in the wiring layer D2, only the hookup wiring W2 is arranged, which connects the connection part d22(1) connected to the word line WL(1) of the memory block BLK(1) and the word line switch WLSW(1).

[0224] As shown in FIG. 38(b), in the wiring layer D1, only the hookup wiring W1 is arranged, which connects the connection part d12(2) connected to the word line WL(2) of the memory block BLK(2) with the word line switch WLSW(2).

[0225] As shown in FIG. 38(c), in the wiring layer D0, only the hookup wiring W0 is arranged, which connects the connection part d02(3) connected to the word line WL(3) of the memory block BLK(3) with the word line switch WLSW(3).

[0226] In this embodiment, the hook-up wirings W2, W1, or W0 connected to the word lines WL of different memory blocks BLK(1), BLK(2), or BLK(3) are not arranged close to each other in the same wiring layer D2, D1, or D0, and the same effect as in the first embodiment can be achieved.

[0227] [Sixth embodiment] 39 and 40 are diagrams showing a schematic configuration of a semiconductor memory device according to the sixth embodiment. In the sixth embodiment, the above-described first to fifth embodiments are applied to a semiconductor memory device having a multi-stack array structure.

[0228] The semiconductor memory device shown in FIG. P And Chip C P Multiple chips C mounted on M1 , C M2 Chip C P The chip C includes a semiconductor substrate 200 and various circuits and wiring layers provided on the semiconductor substrate 200. M The chip C includes a plurality of memory cell arrays MCA. P and multiple chips C M1 ,C M2 The adhesive electrode P 11 , P 12 Chip C is bonded via P Regarding the configuration of the wiring layer in this embodiment, any one of the first to fifth embodiments can be applied.

[0229] The semiconductor memory device shown in FIG. P1 , C P2 and multiple chips C P1 , C P2 One chip C mounted on top of M Chip CP1 The chip C has various circuits and wiring layers on a semiconductor substrate 2001. P2 The chip C has various circuits and wiring layers on a semiconductor substrate 2002. P1 The chip C may not have the semiconductor substrate 2001. M The chip C includes a plurality of memory cell arrays MCA. P1 , C P2 And Chip C M The adhesive electrode P 11 ,P 12 Chip C is bonded via P1 or Chip C P2 Regarding the configuration of the wiring layer in this embodiment, any one of the first to fifth embodiments can be applied.

[0230] [Seventh embodiment] 41 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device according to the seventh embodiment. M Only the configuration of chip C is shown. P This is the same as in the first to sixth embodiments, and therefore a detailed description thereof will be omitted.

[0231] In the first to sixth embodiments, the hook-up region R HU In the seventh embodiment, the conductive layers 110 (word lines WL and select gate lines SG) of each layer are formed in a stepped shape, and one end of the via contact electrode CC is connected to the conductive layer 110 of each layer formed in a stepped shape. HU In the above, the conductive layer 110 is not formed in a stepped shape but extends in the Z direction, and has a plurality of via contact electrodes CC that are directly connected to the conductive layer 110 or that penetrate one or more conductive layers 110 in the Z direction and connect to any of the conductive layers 110. One end of the via contact electrode CC is connected to the conductive layer 110, and an insulating layer 103 is provided between the conductive layer 110 through which the via contact electrode CC penetrates and the side surface of the via contact electrode CC.

[0232] The structure of the seventh embodiment can be manufactured by the following steps. For example, a plurality of contact holes are formed, reaching the conductive layer 110 of each layer. The formation time of each contact hole is controlled to vary the depth of the contact holes. An insulating layer 103 such as silicon oxide (SiO2) is formed on the outer peripheral surfaces of the plurality of contact holes. Next, the insulating layer 103 formed on the outer surfaces of the contact holes is removed, and a via contact electrode CC is formed inside the insulating layer 103, the via contact electrode CC being made of a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0233] The same wiring structure as in the first to sixth embodiments can also be applied to a semiconductor memory device having such via contact electrodes CC.

[0234] [Eighth embodiment] 42 is a schematic plan view showing an example of the arrangement of via contact electrodes CC in a semiconductor memory device according to the eighth embodiment, and an example of the arrangement of corresponding connection portions dn2 of wiring layers and word line switches WLSW. Note that the same reference numerals are used for the same configurations as those in the first to seventh embodiments, and detailed description thereof will be omitted.

[0235] In the eighth embodiment, the relationship between the word line switches WLSW and the memory blocks BLK is a 3Tr / 2BLK relationship. In this example, four memory blocks BLK are used as a unit, and the relationship between the arrangement pattern of the word line switches WLSW and the via contact electrodes CC in 6Tr / 4BLK (M=6, N=4) is shown.

[0236] A total of eight word line switches WLSW arranged in four columns in the X direction and two rows in the Y direction constitute a transistor group TG2. The transistor group TG2 is made up of four transistor groups TG1 arranged in the X direction, which share a gate electrode 206. In this example, three transistor groups TG2 are arranged in the X direction, and one on each side of the center in the Y direction, forming half of the group. When the transistor group TG2 is viewed in units obtained by dividing it in the Y direction into two halves, starting from the negative side in the X direction, the word line switches WLSW(1), WLSW(1), and WLSW(2) are arranged in this order in the first row RO1 and the second row RO2. The word line switches WLSW(2) and WLSW(3) are arranged in this order in the third row RO3 and the fourth row RO4. The word line switches WLSW(4), WLSW(4), and WLSW(3) are arranged in this order in the fifth row RO5 and the sixth row RO6.

[0237] The order of the word line switches WLSW in the Y direction from the first column CL1 to the fourth column CL4, starting from the positive side in the Y direction, is WLSW(1), WLSW(1), WLSW(2), WLSW(2), WLSW(4), WLSW(4). From the fifth column CL5 to the eighth column CL8, the order from the positive side in the Y direction is WLSW(1), WLSW(1), WLSW(3), WLSW(3), WLSW(4), WLSW(4). From the ninth column CL9 to the twelfth column CL12, the order from the positive side in the Y direction is WLSW(2), WLSW(2), WLSW(3), WLSW(3). The word line switches WLSW in the fifth column CL5 to the eighth column CL8 in the third row RO3 and the fourth row RO4 are unused dummy switches.

[0238] On the other hand, a total of 24 via contact electrodes CC are arranged in 2 rows and 12 columns per memory block BLK, of which 8 are dummy in 2 rows and 4 columns. Therefore, the number of active via contact electrodes CC per memory block BLK is 16. Here, the "dummy via contact electrodes CC" refers to the via contact electrodes CC that are located in the drain region R of any of the word line switches WLSW. DR41. For example, since the via contact electrode Vy connecting the electrode of the via contact electrode layer CH and the wiring m0 shown in FIG. 41 is not provided, the via contact electrode CC that is not connected to the wiring m0 becomes a dummy. Note that providing such a dummy via contact electrode CC is not essential in this embodiment. The effect of this embodiment can be achieved even without providing the dummy via contact electrode CC.

[0239] In the memory block BLK(1) (first row ro1, second row ro2), the first column cl1 to the eighth column cl8 are active via contact electrodes CC, and the ninth column cl9 to the twelfth column cl12 are dummy.

[0240] In the memory block BLK(2) (third row ro3, ​​fourth row ro4), the first column cl1 to the fourth column cl4 and the ninth column cl9 to the twelfth column cl12 are active via contact electrodes CC, and the fifth column cl5 to the eighth column cl8 are dummy.

[0241] In the memory block BLK(3) (fifth row ro5, sixth row ro6), the fifth column cl5 to the twelfth column cl12 are active via contact electrodes CC, and the first column cl1 to the fourth column cl4 are dummy.

[0242] In the memory block BLK(4) (seventh row ro7, eighth row ro8), the first column cl1 to the eighth column cl8 are active via contact electrodes CC, and the ninth column cl9 to the twelfth column cl12 are dummy.

[0243] In this way, by distributing the dummy via contact electrodes CC in the X and Y directions, when the dummy electrodes are shifted in the Y direction, 12 active via contact electrodes CC are lined up in the X direction and 6 active via contact electrodes CC are lined up in the Y direction, so that the number of via contact electrodes CC in the X and Y directions matches the number of word line switches WLSW in the X and Y directions.

[0244] The order of memory blocks BLK including active via contact electrodes CC in the Y direction from the first column cl1 to the fourth column cl4 is memory blocks BLK(1), BLK(1), BLK(2), BLK(2), BLK(4), BLK(4) from the positive side of the Y direction. The order of memory blocks BLK from the fifth column cl5 to the eighth column cl8 is memory blocks BLK(1), BLK(1), BLK(3), BLK(3), BLK(4), BLK(4) from the positive side of the Y direction. The order of memory blocks from the ninth column cl9 to the twelfth column cl12 is memory blocks BLK(2), BLK(2), BLK(3), BLK(3) from the positive side of the Y direction.

[0245] In this manner, in this embodiment, the arrangement order of the plurality of word-line switches WLSW in the Y direction and the arrangement order of the plurality of via contact electrodes CC connected to the plurality of word-line switches WLSW in the Y direction are the same at each position in the X direction. In the structure shown in Fig. 41, the arrangement of the via contact electrodes CC can be selected relatively freely, and therefore, a pattern in which dummies are arranged at such arbitrary positions can be obtained.

[0246] [effect] According to this embodiment, as shown in Fig. 42, by arranging dummy via contact electrodes CC in the arrangement pattern of the via contact electrodes CC, the positional relationship between the active via contact electrodes CC and the word line switches WLSW corresponds, and the positional relationship between the via contact electrodes CC, the pasted electrodes P12, and the connection portions d32 connected to the hook-up wirings W2 to W0 can be aligned in each column. 12 This simplifies the pattern of the hookup wirings W2 to W0 from the connecting portion d32 to the connecting portion d42, and further from the connecting portion d32 to the word line switch WLSW, thereby shortening the wiring path.

[0247] 43 is a schematic plan view showing an example of assignment of word line WL numbers of via contact electrodes CC and word line switches WLSW. In memory block BLK(1), word line numbers 1, 3, 5, 7, 9, 11, 13, and 15 are assigned to the first column cl1 to the eighth column cl8 of the first row ro1. Word line numbers 0, 2, 4, 6, 8, 10, 12, and 14 are assigned to the first column cl1 to the eighth column cl8 of the second row ro2. Memory blocks BLK(2), BLK(3), and BLK(4) are also assigned as shown in FIG.

[0248] The order in the Y direction of the allocation pattern of word line WL numbers to the via contact electrodes CC is the same as the order in the Y direction of the allocation pattern to the drain regions of the word line switches WLSW. Furthermore, the word line numbers of the word line switches WLSW that share the semiconductor region 203 are the same. This facilitates the layout of the wiring CGI. In this embodiment, the allocation pattern of word line numbers to the via contact electrodes CC and the allocation pattern of word line numbers to the drain regions of the word line switches WLSW are completely consistent. However, as long as the order in the Y direction is the same, the allocation patterns of the via contact electrodes CC and the word line switches WLSW may be different within the range of four word line switches WLSW that share the gate electrode 206. [Ninth embodiment] 44 is a schematic plan view showing an example of the arrangement of via contact electrodes CC and the corresponding arrangement of connection portions dn2 of wiring layers and word line switches WLSW in a semiconductor memory device according to the ninth embodiment. Note that the same reference numerals are used for the same configurations as those in the first to eighth embodiments, and detailed description thereof will be omitted.

[0249] In the ninth embodiment, the relationship between the word line switches WLSW and the memory blocks BLK is a 3Tr / 2BLK relationship. In this example, four memory blocks BLK are used as a unit, and the relationship between the arrangement pattern of the word line switches WLSW and the via contact electrodes CC in 6Tr / 4BLK (M=6, N=4) is shown.

[0250] In the ninth embodiment, a total of 12 word line switches WLSW arranged in six columns in the X direction and two rows in the Y direction constitute a transistor group TG2. The transistor group TG2 is made up of six transistor groups TG1 arranged in the X direction and sharing a gate electrode 206. In this example, two transistor groups TG2 are arranged in the X direction. The transistor groups TG2 arranged in the X direction are offset from each other in the Y direction by one transistor Tr. Therefore, the transistor group TG2 on the left side of the figure is arranged with one and a half transistors on both sides of the center in the Y direction, and the transistor group TG2 on the right side of the figure is arranged with three transistors in the Y direction.

[0251] The order of the word line switches WLSW in the Y direction from the first column CL1 to the sixth column CL6, starting from the positive side in the Y direction, is word line switches WLSW(1), WLSW(1), WLSW(2), WLSW(3), WLSW(4), WLSW(4). Also, the order of the word line switches WLSW from the seventh column CL7 to the twelfth column CL12, starting from the positive side in the Y direction, is word line switches WLSW(1), WLSW(2), WLSW(2), WLSW(3), WLSW(3), WLSW(4).

[0252] On the other hand, a total of 24 via contact electrodes CC are arranged in 2 rows and 12 columns per memory block BLK, of which 6 are dummy electrodes in 1 row and 6 columns, resulting in a total of 18 active via contact electrodes CC per memory block BLK.

[0253] In the first row ro1 of the memory block BLK(1), the first column cl1 to the twelfth column cl12 are active via contact electrodes CC, and in the second row ro2, the first column cl1 to the sixth column cl6 are active via contact electrodes CC, and the seventh column cl7 to the twelfth column cl12 are dummy.

[0254] In the third row ro3 of the memory block BLK(2), the first column cl1 to the sixth column cl6 are dummy, and the seventh column cl7 to the twelfth column cl12 are active via contact electrodes CC.

[0255] In the fifth row ro5 of the memory block BLK(3), the first column cl1 to the twelfth column cl12 are active via contact electrodes CC. In the sixth row ro6, the first column cl1 to the sixth column cl6 are dummy, and the seventh column cl7 to the twelfth column cl12 are active.

[0256] In the seventh row ro7 of the memory block BLK(4), the first column cl1 to the sixth column cl6 are active via contact electrodes CC, and the seventh column cl7 to the twelfth column cl12 are dummy. In the eighth row ro8, the first column cl1 to the twelfth column cl12 are active via contact electrodes CC.

[0257] In this way, by distributing the dummy via contact electrodes CC in the X and Y directions, when the dummy via contact electrodes are shifted in the Y direction, 12 active via contact electrodes CC are arranged in the X direction and 6 active via contact electrodes CC are arranged in the Y direction. As a result, the number of via contact electrodes CC in the X and Y directions matches the number of word line switches WLSW in the X and Y directions. Furthermore, the order of the memory blocks BLK including active via contact electrodes CC in the Y direction from the first column cl1 to the sixth column cl6 is memory blocks BLK(1), BLK(1), BLK(2), BLK(3), BLK(4), BLK(4) in order from the positive side in the Y direction. Furthermore, the order of the memory blocks BLK from the seventh column cl7 to the twelfth column cl12 is memory blocks BLK(1), BLK(2), BLK(2), BLK(3), BLK(3), BLK(4) in order from the positive side in the Y direction.

[0258] In this embodiment, by arranging dummy via contact electrodes CC in the arrangement pattern of the via contact electrodes CC, the positional relationship between the active via contact electrodes CC and the word line switches WLSW corresponds to each other, and the via contact electrodes CC and the pasted electrodes P 12 The positional relationship between the via contact electrodes CC and the connecting portions d32 connected to the hook-up wirings W2 to W0 can be aligned in each row. 12This simplifies the pattern of the hookup wirings W2 to W0 from the connecting portion d32 to the connecting portion d42, and further from the connecting portion d32 to the word line switch WLSW, thereby shortening the wiring path.

[0259] 45 is a schematic plan view showing an example of assignment of word line WL numbers of via contact electrodes CC and word line switches WLSW. In memory block BLK(1), word line numbers 1, 3, 5, 7, 9, 11, 12, 13, 14, 15, 16, and 17 are assigned to the first column cl1 to the twelfth column cl12 of the first row ro1. Word line numbers 0, 2, 4, 6, 8, and 10 are assigned to the first column cl1 to the sixth column cl6 of the second row ro2. Memory blocks BLK(2), BLK(3), and BLK(4) are also assigned as shown in FIG.

[0260] The order in the Y direction of the allocation pattern of the word line WL numbers to the via contact electrodes CC is the same as the order in the Y direction of the allocation pattern to the drain regions of the word line switches WLSW. Also, the word line numbers of the word line switches WLSW that share the semiconductor region 203 are the same. This makes it easier to arrange the wiring CGI.

[0261] [Tenth embodiment] 46 is a schematic plan view showing an example of the arrangement of via contact electrodes CC and the corresponding connection portions dn2 of the wiring layer and word line switches WLSW in the semiconductor memory device according to the tenth embodiment. Note that the same reference numerals are used for the same components as those in the first to ninth embodiments, and detailed description thereof will be omitted.

[0262] In the tenth embodiment, the relationship between the word line switches WLSW and the memory blocks BLK is 4Tr / 3BLK (M=4, N=3). In the tenth embodiment, a total of eight word line switches WLSW arranged in four columns in the X direction and two rows in the Y direction constitute a transistor group TG2. The transistor group TG2 is made up of four transistor groups TG1 arranged in the X direction and sharing a gate electrode 206. In this example, three transistor groups TG2 are arranged in the X direction, one in the Y direction, and half on each side.

[0263] The order of the word line switches WLSW in the Y direction from the first column CL1 to the fourth column CL4, starting from the positive side in the Y direction, is word line switches WLSW(1), WLSW(1), WLSW(2), WLSW(2). Also, from the fifth column CL5 to the eighth column CL8, the order of the word line switches WLSW(2), WLSW(2), WLSW(3), WLSW(3). Also, from the ninth column CL9 to the twelfth column CL12, the order of the word line switches WLSW(1), WLSW(1), WLSW(3), WLSW(3).

[0264] On the other hand, a total of 24 via contact electrodes CC are arranged in 2 rows and 12 columns per memory block BLK, of which 8 are dummy electrodes in 2 rows and 4 columns, resulting in a total of 16 active via contact electrodes CC per memory block BLK.

[0265] In the memory block BLK(1) (first row ro1, second row ro2), the first column cl1 to the fourth column cl4 and the eighth column cl8 to the twelfth column cl12 are active via contact electrodes CC, and the fifth column cl5 to the eighth column cl8 are dummy.

[0266] In the memory block BLK(2) (third row ro3, ​​fourth row ro4), the first column cl1 to the ninth column cl9 are active via contact electrodes CC, and the ninth column cl9 to the twelfth column cl12 are dummy.

[0267] In the memory block BLK(3) (fifth row ro5, sixth row ro6), the fifth column cl5 to the twelfth column cl12 are active via contact electrodes CC, and the first column cl1 to the fourth column cl4 are dummy.

[0268] In this way, by distributing the dummy via contact electrodes CC in the X and Y directions, when the dummy electrodes are shifted in the Y direction, 12 active via contact electrodes CC are lined up in the X direction and 4 active via contact electrodes CC are lined up in the Y direction, so that the number of via contact electrodes CC in the X and Y directions matches the number of word line switches WLSW in the X and Y directions.

[0269] The order of the memory blocks BLK including active via contact electrodes CC in the Y direction from the first column cl1 to the fourth column cl4 is memory blocks BLK(1), BLK(1), BLK(2), BLK(2) from the positive side in the Y direction. The order of the memory blocks BLK from the fifth column cl5 to the eighth column cl8 is memory blocks BLK(2), BLK(2), BLK(3), BLK(3) from the positive side in the Y direction. The order of the memory blocks from the ninth column cl9 to the twelfth column cl12 is memory blocks BLK(1), BLK(1), BLK(3), BLK(3) from the positive side in the Y direction.

[0270] In this embodiment, by arranging dummy via contact electrodes CC in the arrangement pattern of the via contact electrodes CC, the positional relationship between the active via contact electrodes CC and the word line switches WLSW corresponds to each other, and the via contact electrodes CC and the pasted electrodes P 12 The positional relationship between the via contact electrodes CC and the connecting portions d32 connected to the hook-up wirings W2 to W0 can be aligned in each row. 12 This simplifies the pattern of the hookup wirings W2 to W0 from the connecting portion d32 to the connecting portion d42, and further from the connecting portion d32 to the word line switch WLSW, thereby shortening the wiring path.

[0271] 47 is a schematic plan view showing an example of assignment of word line WL numbers of via contact electrodes CC and word line switches WLSW. In memory block BLK(1), the word line numbers assigned to the first column cl1 to the twelfth column cl12 of the first row ro1 are 8, 9, 10, 11, dummy, dummy, dummy, dummy, 12, 13, 14, and 15. The word line numbers assigned to the first column cl1 to the twelfth column cl12 of the second row ro2 are 0, 1, 2, 3, dummy, dummy, dummy, dummy, 4, 5, 6, and 7. The memory blocks BLK(2) and BLK(3) are also assigned as shown in FIG.

[0272] The order in the Y direction of the allocation pattern of the word line WL numbers to the via contact electrodes CC is the same as the order in the Y direction of the allocation pattern to the drain regions of the word line switches WLSW. Also, the word line numbers of the word line switches WLSW that share the semiconductor region 203 are the same. This makes it easier to arrange the wiring CGI.

[0273] [Eleventh embodiment] 48 is a schematic plan view showing an example of the arrangement of via contact electrodes CC and the corresponding connection portions dn2 of the wiring layer and word line switches WLSW in the semiconductor memory device according to the eleventh embodiment. Note that the same reference numerals are used for the same configurations as those in the first to ninth embodiments, and detailed description thereof will be omitted.

[0274] In the eleventh embodiment, the relationship between the word line switch WLSW and the memory block BLK is 4Tr / 3BLK (M=4, N=3). In the eleventh embodiment, the word line switch WLSW is composed of a transistor group TG2 consisting of eight transistor groups TG1 aligned in the X direction and a transistor group TG4 consisting of four transistor groups TG1, which share a gate electrode 206. In this example, the transistor groups TG2 and TG4 are aligned in the X direction.

[0275] The order of the word line switches WLSW in the Y direction from the first column CL1 to the eighth column CL8, starting from the positive side in the Y direction, is word line switches WLSW(1), WLSW(1), WLSW(2), WLSW(2). Also, the order of the word line switches WLSW from the ninth column CL9 to the twelfth column CL12, starting from the positive side in the Y direction, is word line switches WLSW(2), WLSW(2), WLSW(3), WLSW(3).

[0276] On the other hand, a total of 24 via contact electrodes CC are arranged in 2 rows and 12 columns per memory block BLK, of which 8 electrodes in 2 rows and 4 columns or 8 electrodes in 1 row and 8 columns are dummy. Therefore, the number of active via contact electrodes CC per memory block BLK is 16.

[0277] In the memory block BLK(1) (first row ro1, second row ro2), the first column cl1 to the eighth column cl8 are active via contact electrodes CC, and the ninth column cl9 to the twelfth column cl12 are dummy.

[0278] In the third row ro3 of the memory block BLK(2), the first column cl1 to the eighth column cl8 are dummy, and the ninth column cl9 to the twelfth column cl12 are active via contact electrodes CC. In the fourth row ro4 of the memory block BLK(2), the first column cl1 to the twelfth column cl12 are active via contact electrodes CC.

[0279] The memory block BLK(3) is similar to the memory block BLK(2).

[0280] In this way, by distributing the dummy via contact electrodes CC in the X and Y directions, when the dummy electrodes are shifted in the Y direction, 12 active via contact electrodes CC are lined up in the X direction and 4 active via contact electrodes CC are lined up in the Y direction, so that the number of via contact electrodes CC in the X and Y directions matches the number of word line switches WLSW in the X and Y directions.

[0281] The order of the memory blocks BLK including active via contact electrodes CC in the Y direction is memory blocks BLK(1), BLK(1), BLK(2), BLK(3) from the first column cl1 to the eighth column cl8, starting from the positive side in the Y direction. The order of the memory blocks BLK including active via contact electrodes CC in the ninth column cl9 to the twelfth column cl12 is memory blocks BLK(2), BLK(2), BLK(3), BLK(3) from the positive side in the Y direction.

[0282] In this embodiment, by arranging dummy via contact electrodes CC in the arrangement pattern of the via contact electrodes CC, the positional relationship between the active via contact electrodes CC and the word line switches WLSW corresponds to each other, and the via contact electrodes CC and the pasted electrodes P 12 The positional relationship between the via contact electrodes CC and the connecting portions d32 connected to the hook-up wirings W2 to W0 can be aligned in each row. 12 This simplifies the pattern of the hookup wirings W2 to W0 from the connecting portion d32 to the connecting portion d42, and further from the connecting portion d32 to the word line switch WLSW, thereby shortening the wiring path.

[0283] 49 is a schematic plan view showing an example of assignment of word line WL numbers of via contact electrodes CC and word line switches WLSW. In memory block BLK(1), the word line numbers assigned to the first column cl1 to the twelfth column cl12 of the first row ro1 are 1, 3, 5, 7, 9, 11, 13, 15, dummy, dummy, dummy, and dummy. The word line numbers assigned to the first column cl1 to the twelfth column cl12 of the second row ro2 are 0, 2, 4, 6, 8, 10, 12, 14, dummy, dummy, dummy, and dummy. Memory blocks BLK(2) and BLK(3) are also assigned as shown in FIG.

[0284] The order in the Y direction of the allocation pattern of the word line WL numbers to the via contact electrodes CC is the same as the order in the Y direction of the allocation pattern to the drain regions of the word line switches WLSW. Also, the word line numbers of the word line switches WLSW that share the semiconductor region 203 are the same. This makes it easier to arrange the wiring CGI.

[0285] As described above, the eighth to eleventh embodiments are configured as follows. That is, in the arrangement pattern of a plurality of word line switches WLSW (transistors) in the X and Y directions, numbers are assigned to the positions in the Y direction of the memory blocks BLK connected to each word line switch WLSW. Also, in the arrangement pattern of a plurality of via contact electrodes CC in the X and Y directions, numbers are assigned to the positions in the Y direction of the memory blocks BLK to which each via contact electrode CC connected to each word line switch WLSW belongs. In this case, the order in the Y direction of the numbers assigned to the plurality of word line switches WLSW and the order in the Y direction of the numbers assigned to the plurality of via contact electrodes CC match at each position in the X direction.

[0286] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0287] 110...conductive layer, 120...semiconductor layer (semiconductor pillar), 200, 500...semiconductor substrate, C M ...Chip (1st chip), C P...chip (second chip), BL...bit line, WL...word line, SG...select gate line, CC, C400...via contact electrode (first via contact electrode), CS1...via contact electrode (second via contact electrode), CS2...via contact electrode (third via contact electrode), C11, C12, C12b, C21, C22, C31, C32, C41, C42...via contact electrodes, d01, d02, d02b, d11, d12, d 12b, d21, d22, d31, d32, d42...connection portion, CGI...wiring (voltage supply wiring), MC...memory cell, M0, M1, D0, D1, D2, D3, D4...wiring layer, MB, DB...chip bonding electrode layer, W0, W1, W2, W3...hook-up wiring, s2, s3...shield wiring, TW2, TW3...passing wiring (first wiring), WLSW...word line switch (transistor), SGSW...select gate line switch (transistor), P I1 ,P I2 ...Laminated electrode, R MH ,R MH2 …Memory hole area (memory area), R HU ,R HU2 …Hookup area, R CGI …first region, R WLHU1 …Second area, R WLHU2 ...Third area.

Claims

1. a semiconductor substrate; a plurality of transistors provided on one surface of the semiconductor substrate and arranged in a first direction and a second direction intersecting the first direction; a stacked body provided on the one side of the semiconductor substrate in a third direction intersecting the first direction and the second direction, the stacked body including a plurality of conductive layers aligned in the third direction; a plurality of wiring layers provided between the semiconductor substrate and the stacked body, the wiring layers connecting the plurality of conductive layers and the plurality of transistors; Equipped with a first circuit area in which the plurality of transistors are arranged as viewed from the third direction; and a hookup area that overlaps the first circuit area as viewed from the third direction and has a width in the first direction smaller than that of the first circuit area, the laminate has a first laminate structure and a second laminate structure aligned in the second direction, the first laminate structure having a plurality of first conductive layers aligned in the third direction, and the second laminate structure having a plurality of second conductive layers aligned in the third direction; the plurality of transistors include a plurality of first transistors and a plurality of second transistors aligned in the first direction, the plurality of wiring layers include a plurality of first wirings connecting the plurality of first conductive layers and the plurality of first transistors, and a plurality of second wirings connecting the plurality of second conductive layers and the plurality of second transistors; First portions of the plurality of first wirings extending in the first direction from the hookup region toward the first circuit region and second portions of the second wirings extending in the first direction from the hookup region toward the first circuit region are disposed at different positions in the third direction. Semiconductor memory device.

2. The first portions of the plurality of first wirings and the second portions of the plurality of second wirings are arranged in wiring regions that overlap in the third direction.

2. The semiconductor memory device according to claim 1.

3. The laminate is a plurality of semiconductor layers extending in the third direction and facing the plurality of conductive layers; a plurality of via contact electrodes, one ends of which are connected to the plurality of conductive layers in the hook-up region and the other ends of which extend in the third direction toward the plurality of wiring layers; Equipped with 2. The semiconductor memory device according to claim 1.

4. each of the plurality of transistors has a source region and a drain region aligned in the second direction; The plurality of wiring layers include: a plurality of first connection parts provided in a first region corresponding to the source region in the first circuit region, the first connection parts being aligned in the first direction and the third direction; a plurality of second connection parts provided in a second region adjacent to the first region in the hook-up region, the second connection parts being aligned in the first direction and the third direction at a pitch smaller than the arrangement pitch of the plurality of transistors in the first direction; a plurality of third connection parts provided in a third region corresponding to drain regions of the plurality of transistors in the first circuit region, the third connection parts being aligned in the first direction and the third direction; a first via extending in the third direction and connecting the plurality of first connection portions aligned in the third direction to a source region of the transistor; a second via extending in the third direction and connecting the second connection portions arranged in the third direction; a third via extending in the third direction and connecting the third connection portions arranged in the third direction and the drain region of the transistor; have 2. The semiconductor memory device according to claim 1.

5. the second connection portions include a plurality of fourth connection portions connected to the plurality of first conductive layers and a plurality of fifth connection portions connected to the plurality of second conductive layers; the first wiring connects the fourth connection portion and the third connection portion corresponding to the drain region of the first transistor; The second wiring connects the fifth connection portion and the third connection portion corresponding to the drain region of the second transistor.

5. The semiconductor memory device according to claim 4.

6. The plurality of transistors include: the first transistors and the second transistors are provided in a first row aligned in the first direction and in a second row adjacent to the first row in the second direction, and a plurality of third transistors are provided in the first direction; a plurality of fourth transistors arranged in the first direction, the fourth transistors being provided in a third row adjacent to the second row on the opposite side to the first row, the fourth transistors sharing a semiconductor region with the third transistors; Further comprising: The plurality of wiring layers include: a plurality of third wirings connecting the plurality of first conductive layers and the plurality of third transistors; a plurality of fourth wirings connecting the plurality of second conductive layers and the plurality of fourth transistors; Further comprising: The width in the second direction of a region in which the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged is equal to the width in the second direction of a region in which the first stacked structure and the second stacked structure are arranged.

2. The semiconductor memory device according to claim 1.

7. The plurality of transistors include: the first transistors and the second transistors are provided in a first row aligned in the first direction and in a second row adjacent to the first row in the second direction, and a plurality of third transistors are provided in the first direction; a plurality of fourth transistors arranged in the first direction, the fourth transistors being provided in a third row adjacent to the second row on the opposite side to the first row, the fourth transistors sharing a semiconductor region with the third transistors; Further comprising: the second connection portions include a plurality of sixth connection portions connected to the plurality of first conductive layers and a plurality of seventh connection portions connected to the plurality of second conductive layers, the sixth connection portions being aligned in the first direction, and the seventh connection portions being aligned in the first direction at positions different from the sixth connection portions in the second direction; the third wiring connects the sixth connection portion and the third connection portion corresponding to the drain region of the third transistor; The fourth wiring connects the seventh connection portion and the third connection portion corresponding to the drain region of the fourth transistor.

5. The semiconductor memory device according to claim 4.

8. The order of the numbers of the positions in the third direction of the first conductive layer connected to the sixth connection portion is equal to the order of the numbers of the positions in the third direction of the second conductive layer connected to the seventh connection portion.

8. The semiconductor memory device according to claim 7.

9. The position number in the third direction of the first conductive layer connected to one of the pair of second connection portions adjacent in the first direction is equal to the position number in the third direction of the second conductive layer connected to the other of the pair of second connection portions.

8. The semiconductor memory device according to claim 7.

10. the laminate further includes a third laminate structure arranged on a side of the second laminate structure opposite to the first laminate structure in the second direction, the third laminate structure including a plurality of third conductive layers arranged in the third direction; The plurality of transistors include: the first transistors and the second transistors are arranged in a first row aligned in the first direction, and a fifth transistor is aligned in the first direction together with the first transistors and the second transistors; a plurality of sixth transistors arranged in the first direction and provided in a second row adjacent to the first row in the second direction; a plurality of seventh transistors arranged in the first direction, the seventh transistors being provided in a third row adjacent to the second row on the opposite side to the first row, the seventh transistors sharing a semiconductor region with the sixth transistors; a plurality of eighth transistors arranged in the first direction and provided in a fourth row adjacent to the third row on the opposite side to the second row; Further comprising: The plurality of wiring layers include: a plurality of fifth wirings connecting the plurality of third conductive layers and the plurality of fifth transistors; a plurality of sixth wirings connecting the plurality of first conductive layers and the plurality of sixth transistors; a plurality of seventh wirings connecting the plurality of second conductive layers and the plurality of seventh transistors; a plurality of eighth wirings connecting the plurality of third conductive layers and the plurality of eighth transistors; Including, a width in the second direction of a region in which the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are arranged is equal to a width in the second direction of a region in which the first stacked structure, the second stacked structure, and the third stacked structure are arranged; Third portions of the plurality of fifth wirings extending in the first direction from the hookup region toward the first circuit region are disposed at positions different from the first portions of the first wirings and the second portions of the second wirings in the third direction.

2. The semiconductor memory device according to claim 1.

11. The first portions of the plurality of first wirings, the second portions of the plurality of second wirings, and the third portions of the plurality of fifth wirings are arranged in wiring regions that overlap in the third direction.

11. The semiconductor memory device according to claim 10.

12. the first transistor has a first gate electrode; the second transistor has a second gate electrode; the first gate electrode and the second gate electrode are aligned in the first direction, The plurality of wiring layers include: a ninth wiring that connects the plurality of first gate electrodes arranged in the first direction; a tenth wiring that connects the plurality of second gate electrodes that are arranged in the first direction; 2. The semiconductor memory device according to claim 1, comprising:

13. the stacked body includes a plurality of eleventh wirings that extend in the second direction and are aligned in the first direction and are connected to ends of the semiconductor layers on the wiring layer side, The plurality of eleventh wirings overlap a part of the first circuit region when viewed from the third direction.

4. The semiconductor memory device according to claim 3.

14. a semiconductor substrate; a plurality of transistors provided on one surface of the semiconductor substrate and arranged in a first direction and a second direction intersecting the first direction; a stacked body provided on the one side of the semiconductor substrate in a third direction intersecting the first direction and the second direction, the stacked body including a plurality of conductive layers aligned in the third direction; a plurality of wiring layers provided between the semiconductor substrate and the stacked body, the wiring layers connecting the plurality of conductive layers and the plurality of transistors; Equipped with a first circuit area in which the plurality of transistors are arranged as viewed from the third direction; and a hookup area that overlaps the first circuit area as viewed from the third direction and has a width in the first direction smaller than that of the first circuit area, the laminate has a first laminate structure and a second laminate structure aligned in the second direction, the first laminate structure having a plurality of first conductive layers aligned in the third direction, and the second laminate structure having a plurality of second conductive layers aligned in the third direction; the plurality of transistors include a plurality of first transistors and a plurality of second transistors aligned in the first direction, The plurality of wiring layers include: a first wiring layer; a second wiring layer that is different in position from the first wiring layer in the third direction; a plurality of first wirings connecting the plurality of first conductive layers and the plurality of first transistors; a plurality of second wirings connecting the plurality of second conductive layers and the plurality of second transistors; Including, all wirings passing through a boundary between the hookup region of the first wiring layer and a region of the first circuit region excluding the hookup region are the first wirings; All of the wirings passing through the boundary between the hook-up region of the second wiring layer and the region of the first circuit region excluding the hook-up region are the second wirings. Semiconductor memory device.

15. semiconductor substrate, a plurality of transistors provided on one surface of the semiconductor substrate and arranged in a first direction and a second direction intersecting the first direction; a plurality of stacked structures provided on the one side of the semiconductor substrate in a third direction intersecting the first direction and the second direction, each having a plurality of conductive layers aligned in the third direction; a wiring layer provided between the semiconductor substrate and the plurality of stacked structures, the wiring layer connecting the plurality of conductive layers and the plurality of transistors; Equipped with a first circuit area in which the plurality of transistors are arranged when viewed from the third direction, and a hook-up area overlapping the first circuit area when viewed from the third direction; each of the plurality of stacked structures includes a plurality of via contact electrodes, one end of which is connected to the plurality of conductive layers in the hook-up region, the other end of which extends in the third direction toward the wiring layer, and a side surface of which faces the plurality of conductive layers via an insulator; assigning numbers to positions in the second direction of the stacked structure connected to each of the transistors in an arrangement pattern of the plurality of transistors in the first direction and the second direction; In the arrangement pattern of the plurality of via contact electrodes in the first direction and the second direction, when numbers are assigned to positions in the second direction of the stacked structure to which the via contact electrodes connected to the plurality of transistors belong, The arrangement order of the numbers assigned to the plurality of transistors in the second direction and the arrangement order of the numbers assigned to the plurality of via contact electrodes in the second direction are the same at each position in the first direction. Semiconductor memory device.

16. The plurality of laminated structures are a memory region at a position aligned with the hook-up region in the first direction, the memory region including a plurality of semiconductor layers extending in the third direction and facing the plurality of conductive layers; 16. The semiconductor memory device according to claim 15.

17. The total width of the N stacked structures in the second direction (N is a natural number) is equal to the total width of the M transistors in the second direction (M>N, M is a natural number).

16. The semiconductor memory device according to claim 15.

18. a plurality of dummy via contact electrodes not connected to the plurality of transistors are further provided in the hook-up region of each of the stacked structures; the plurality of via contact electrodes and the plurality of dummy via contact electrodes are arranged in the hook-up region of the N stacked structures in the first direction and the second direction, the dummy via contact electrodes are present in all rows of the via contact electrodes and the dummy via contact electrodes of the N stacked structures arranged in the second direction, the number of the plurality of via contact electrodes in the second direction is N; The number of the via contact electrodes in each of the plurality of stacked structures is equal.

18. The semiconductor memory device according to claim 17.

19. each of the plurality of transistors has a source region and a drain region aligned in the second direction; an arrangement order in the second direction of the position numbers of the conductive layers connected to the plurality of via contact electrodes in the third direction and an arrangement order in the second direction of the position numbers of the conductive layers connected to drain regions of the plurality of transistors in the third direction are consistent at each position in the first direction; 16. The semiconductor memory device according to claim 15.

20. a pair of the transistors adjacent in the second direction share a semiconductor region; The number of the conductive layer connected to the drain of one transistor sharing the semiconductor region is equal to the number of the conductive layer connected to the drain of the other transistor.

20. The semiconductor memory device according to claim 19.

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