Data storage device for erasing by grouping memory blocks and method of operating the same
By grouping memory blocks into superblocks and erasing them at regular intervals based on write operation type, the data storage device minimizes peak power consumption and maintains consistent performance.
Patent Information
- Application Number
- JP2024224791
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-03-22
- Filing Date
- 2024-12-20
- Publication Date
- 2025-10-03
AI Technical Summary
Flash memory devices experience increased peak power consumption during erasure operations when multiple memory blocks are accessed simultaneously, leading to inconsistent performance.
A data storage device that groups memory blocks into superblocks and manages them as a unit, erasing these blocks at regular intervals based on the type of write operation, minimizing simultaneous erasures and maintaining consistent performance by determining the number of blocks per erase unit and the erase interval.
This approach reduces peak power consumption and ensures consistent performance by uniformly distributing erase intervals, thereby maintaining efficient operation.
Smart Images
Figure 2025146653000001_ABST
Abstract
Description
[Technical Field]
[0001] The present technology relates to a data storage device, and more particularly to a data storage device and method for erasing memory blocks in groups. [Background technology]
[0002] A semiconductor memory device includes a plurality of memory cells connected between word lines and bit lines.
[0003] In a flash memory device, a typical nonvolatile memory device, a set of cells sharing a word line is defined as a page, and a set of multiple pages is defined as a memory block. Data programming and reading operations for flash memory can be performed in units of pages, and erasure can be performed in units of blocks. In addition, access speed can be improved by combining multiple memory blocks that can be accessed simultaneously and managing them as a superblock.
[0004] When erasing in units of super-blocks, the peak power increases. Therefore, a method of grouping a plurality of memory blocks in a super-block and erasing in units of groups may be considered. Summary of the Invention [Problem to be solved by the invention]
[0005] A data storage device according to an embodiment of the present technology may include a storage medium including a plurality of memory blocks, and a storage controller that manages the plurality of simultaneously accessible memory blocks as a superblock. The storage controller may be configured to erase a spare superblock for a next write operation during a write time set according to the type of write operation currently being processed, divide the plurality of memory blocks in the spare superblock into any number of erase units, and erase the erase units at regular intervals.
[0006] A data storage device according to one embodiment of the present technology may include a storage controller configured to combine multiple memory blocks included in a storage medium so that they can be accessed simultaneously and manage them as a superblock, erase a spare superblock for a next write operation to be processed during a write time corresponding to the type of write operation currently being processed on the storage medium, and determine the number of memory blocks per erase unit and the erase interval between erase units based on the number of erase units into which multiple memory blocks in the spare superblock are grouped and the erase time per erase unit so that all erase units are erased within the write time.
[0007] A method for operating a data storage device according to one embodiment of the present technology is a method for operating a data storage device including a storage medium and a storage controller that combines multiple memory blocks included in the storage medium so that they can be accessed simultaneously and manages them as a superblock, and may be configured to include the steps of: determining a write time according to the type of write operation currently being processed by the storage controller; dividing multiple memory blocks in a spare superblock for the next write operation to be processed into any number of erase units by the storage controller; and erasing the erase units at regular intervals by the storage controller. [Effects of the Invention]
[0008] This technology allows for grouping and erasing blocks in a superblock prepared for a subsequent write operation according to the type of current write operation, with uniform intervals, thereby minimizing peak power consumption and ensuring consistent performance of the data storage device. [Brief explanation of the drawings]
[0009] [Figure 1] FIG. 1 is a configuration diagram of a data processing system according to an embodiment. [Figure 2] 1 is a diagram illustrating a management concept of a storage medium including a nonvolatile memory device according to an embodiment; [Figure 3] FIG. 2 is a block diagram of an erasure management circuit according to an embodiment. [Figure 4] FIG. 10 is a diagram for explaining the concept of grouping memory blocks and determining erase intervals according to the type of write operation. [Figure 5a] 10 is a graph illustrating peak power due to an erase operation of a spare super-block. [Figure 5b] 10 is a graph illustrating peak power due to an erase operation of a spare super-block. [Figure 6] FIG. 10 is a diagram for explaining the concept of grouping memory blocks and determining erase intervals according to the type of write operation. [Figure 7a] 10 is a graph illustrating peak power due to an erase operation of a spare super-block. [Figure 7b] 10 is a graph illustrating peak power due to an erase operation of a spare super-block. [Figure 8] FIG. 10 is a diagram for explaining the concept of grouping memory blocks and determining erase intervals according to the type of write operation. [Figure 9a] 10 is a graph illustrating peak power due to an erase operation of a spare super-block. [Figure 9b] 10 is a graph illustrating peak power due to an erase operation of a spare super-block. [Figure 10] 10 is a flowchart illustrating an operation method of a data storage device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0010] Hereinafter, embodiments of the present technology will be described in more detail with reference to the accompanying drawings.
[0011] FIG. 1 is a diagram illustrating a configuration of a data processing system according to an embodiment.
[0012] Referring to FIG. 1, a data processing system 10 may include an external device 100 and a data storage device 200 .
[0013] The external device 100 may include at least one processor, which may be the processor itself or an electronic device or system that includes a processor.
[0014] The data storage device 200 may include a storage controller 210, a buffer memory device 220, and a storage medium 260. The storage medium 260 may include at least a plurality of non-volatile memory devices 230, 240, and 250.
[0015] To write data, the external device 100 may transmit a write request including a write command (WT), an address (ADD), and write data (DATA) to the data storage device 200. In response, the data storage device 200 may control the storage medium 260 to program the write data.
[0016] To read data, the external device 100 can transmit a read request including a read command (RD) and an address (ADD) to the data storage device 200. The data storage device 200 can read the requested data (DATA) from the storage medium 260 and transmit it to the external device 100.
[0017] The data storage device 200 may read or write data from or to the storage medium 260 in order to perform internal operations as well as in response to read and write requests from the external device 100. The internal operations may include housekeeping operations, such as garbage collection, wear leveling, and read reclaim, that are performed independently of requests from the external device 100 to efficiently use the storage space of the storage medium 260 or to ensure the reliability of data stored in the storage medium 260.
[0018] The buffer memory device 220 can temporarily store data transmitted and received between the external device 100 and the data storage device 200 during a write or read operation.
[0019] The storage controller 210 provides interfacing between the external device 100 and the data storage device 200. The storage controller 210 may include an erase management circuit 30.
[0020] The data storage device 200 operates in superblock units and is configured to erase a superblock for the next write operation depending on the type of write operation currently being processed.
[0021] The write time for a write operation varies depending on the type of write operation currently being processed, and the superblock for the next write operation must be erased within the write time for the current write operation.
[0022] The types of write operations can be classified into sequential write operations requested by the external device 100 or by an internal operation of the data storage device 200, random write operations requested by the external device 100, and random write operations requested by an internal operation of the data storage device 200. As shown in Table 1, the write time varies depending on the type of write operation, and the write time for each type of write operation can vary depending on the data storage device 200.
[0023] [Table 1]
[0024] The erase management circuit 30 can determine the number of memory blocks per erase unit and the erase interval between erase units in order to erase spare superblocks for the next write operation (second write operation) in erase unit units, which are groups of spare superblocks for the next write operation (first write operation) during the write time corresponding to the type of write operation currently being processed (first write operation).
[0025] In one embodiment, the erase management circuit 30 can group memory blocks based on the number of memory blocks in a spare superblock and the erase time per memory block, so that the erase interval between erase units is uniform.
[0026] A detailed description of the erase management circuit 30 will be given later with reference to FIG.
[0027] FIG. 2 is a diagram illustrating a management concept of a storage medium including a nonvolatile memory device according to an embodiment.
[0028] The storage medium 260 may include any number of dies (DIE0, DIE1), and each die (DIE0, DIE1) may include any number of planes (PLANE00 / PLANE01, PLANE10 / PLANE11). Each plane (PLANE00 / PLANE01, PLANE10 / PLANE11) may include multiple memory blocks (BLOCK000-BLOCK00N, BLOCK010-BLOCK01N, BLOCK100-BLOCK10N, BLOCK110-BLOCK11N). Each of the multiple memory blocks (BLOCK000-BLOCK00N, BLOCK010-BLOCK01N, BLOCK100-BLOCK10N, BLOCK110-BLOCK11N) may consist of multiple pages (PAGE0-PAGEM).
[0029] The nonvolatile memory device 260 can input / output data through channels (CHa, CHb). Each channel (CHa, CHb) can input / output data using an interleaving method. Each channel (CHa, CHb) can branch into multiple paths (WAY0, WAY1, WAY2, WAY3) that share the channel (CHa, CHb), and can be connected to each plane (PLANE00 / PLANE01, PLANE10 / PLANE11), for example.
[0030] FIG. 2 shows an example in which each die (DIE0, DIE1) is connected to an independent channel (CHa, CHb), and each plane (PLANE00 / PLANE01, PLANE10 / PLANE11) is connected to a path (WAY0, WAY1, WAY2, WAY3) branching from each channel (CHa, CHb), but the configuration of the nonvolatile memory device 260 is not limited to this.
[0031] The storage controller 210 can group together a group of simultaneously selectable blocks from among a plurality of memory blocks to form a superblock.
[0032] A superblock can be composed of a combination of simultaneously selectable blocks, such as a group (A1, A2) of memory blocks contained in different planes within the same die, or a group (B) of memory blocks contained in different planes within multiple dies.
[0033] FIG. 3 is a block diagram of an erasure management circuit according to one embodiment.
[0034] Referring to FIG. 3, the erase management circuit 30 may include a write type determination circuit 310, a grouping circuit 320, an erase interval determination circuit 330, and an erase control circuit 340.
[0035] When writing data in superblock units, a spare superblock can be erased during a current write operation to reserve a superblock to be used for the next write operation.
[0036] Since the write time varies depending on the type of write operation, it is desirable to erase the spare superblock within the write time of the current write operation.
[0037] In addition, since power consumption increases in proportion to the number of memory blocks erased simultaneously, the memory blocks in the spare superblock are grouped to form erase units to minimize the number of memory blocks erased simultaneously, and the erase intervals between erase units are made uniform, thereby maintaining consistent performance of the data storage device.
[0038] The write type determination circuit 310 determines the write time according to the type of write operation currently being processed. The write operation type can be classified into a sequential write operation requested by the external device 100 or by an internal operation of the data storage device 200, a random write operation requested by the external device 100, and a random write operation requested by an internal operation of the data storage device 200.
[0039] The grouping circuit 320 can group memory blocks within a spare super-block into erase units so that the number of memory blocks erased simultaneously is minimized.
[0040] For example, when the write time is T, the erase time per memory block is E, and the number of memory blocks in the spare superblock is B, the number of memory blocks in the erase unit to be simultaneously erased, X, can be determined by the following equation 1.
[0041] [Number 1] T>E*(B / X) (X is the smallest natural number that satisfies the formula in equation 1)
[0042] Therefore, the number of erase units in the spare super-block can be determined as (B / X).
[0043] The erase interval determination circuit 330 can determine the erase interval (IG) between erase units based on the following equation (3), for example, so that the idle time (I) satisfying the equation (2) is uniformly distributed among the erase units.
[0044] [Number 2] T=I+E*(B / X)
[0045] [Number 3] IG=I / (B / X) or IG=I / ((B / X)-1)
[0046] The erase control circuit 340 can control the storage medium 260 so that the spare super-blocks are erased in erase unit units determined by the grouping circuit 320 at the erase interval (IG) determined by the erase interval determination circuit 330 .
[0047] FIG. 4 is a diagram for explaining the concept of grouping memory blocks and determining erase intervals according to the type of write operation, and shows a case where the type of the current write operation is a sequential write operation.
[0048] For example, if the write time (T) of the sequential write operation (WT) is 5 seconds, the number of memory blocks in the spare superblock (B) is 4, and the erase time per memory block (E) is 1 second, the number of memory blocks per erase unit (X) can be determined as 1 based on equation 1.
[0049] Since the idle time (I) is 1 second based on equation (2), the erase interval (IG) can be determined as, for example, 0.25 seconds.
[0050] Therefore, the first erase unit containing one memory block is erased within 1 second (TE11), and after an erase interval of 0.25 seconds (TI11), the next erase unit is erased. This process is repeated four times (TE11 → TI11 → TE12 → TI12 → TE13 → TI13 → TE14 → TI14), and all spare superblocks can be erased (ER) within the write time (5 seconds) of the sequential write operation currently being written.
[0051] If the erase interval (IG) is determined as I / ((B / X)-1), the last erase interval (TI14) may be omitted.
[0052] 5a and 5b are graphs illustrating peak power due to an erase operation of a spare super-block.
[0053] Figure 5a shows the peak power when four memory blocks included in a spare super-block are simultaneously erased in the example described with reference to Figure 4. Figure 5b shows the peak power when the spare super-block is grouped into erase units and erased at regular intervals.
[0054] If the erase power per memory block is, for example, 10 mW, erasing four memory blocks in the spare superblock simultaneously consumes a peak power of 40 mW during the erase time per block (1 second), as shown in Figure 5a.
[0055] If the spare superblock is divided into four erase units and erased at regular intervals (0.25 seconds), the peak power per erase operation is reduced to 10 mW, as shown in Figure 5b, thereby reducing instantaneous power consumption.
[0056] FIG. 6 is a diagram for explaining the concept of memory block grouping and erasure interval determination according to the type of write operation, and shows a case where the type of the current write operation is a random write operation by an internal operation (internal random write operation).
[0057] For example, if the write time (T) of the internal random write operation (WT) is 10 seconds, the number of memory blocks in the spare superblock (B) is 8, and the erase time per memory block (E) is 1 second, the number of memory blocks per group (X) can be determined as 1 based on equation 1.
[0058] Since the idle time (I) is 2 seconds based on equation (2), the erase interval (IG) can be determined as, for example, 0.25 seconds.
[0059] Therefore, the first erase unit containing one memory block is erased within 1 second (TE21), and after an erase interval of 0.25 seconds (TI21), the next erase unit is erased. This process is repeated eight times (TE21 → TI21 → TE22 → TI22 → TE23 → TI23 → TE24 → TI24 → TE25 → TI25 → TE26 → TI26 → TE27 → TI27 → TE28 → TI28), and all eight memory blocks in the spare superblock can be erased (ER) within the write time (10 seconds) of the internal random write operation currently being written.
[0060] If the erasure interval (IG) is determined as I / ((B / X)-1), the last erasure interval (TI28) may be omitted.
[0061] 7a and 7b are graphs illustrating peak power due to an erase operation of a spare super-block.
[0062] Figure 7a shows the peak power when eight memory blocks included in a spare super-block are simultaneously erased in the example described with reference to Figure 6. Figure 7b shows the peak power when the spare super-block is grouped into erase units and erased at regular intervals.
[0063] If the erase power per memory block is, for example, 10 mW, erasing eight memory blocks in the spare superblock simultaneously consumes a peak power of 80 mW during the erase time per block (1 second), as shown in Figure 7a.
[0064] If the spare superblock is divided into eight erase units and erased at regular intervals (0.25 seconds), the peak power per erase operation is reduced to 10 mW, as shown in Figure 7b, thereby reducing instantaneous power consumption.
[0065] FIG. 8 is a diagram for explaining the concept of grouping memory blocks and determining erase intervals according to the type of write operation, and shows a case where the type of the current write operation is a random write operation requested by the external device 100 (external random write operation).
[0066] For example, if the write time (T) of the external random write operation (WT) is 30 seconds, the number of memory blocks in the spare superblock (B) is 16, and the erase time per memory block (E) is 2 seconds, the number of memory blocks per erase unit (X) can be determined as 2 based on equation 1.
[0067] Since the idle time (I) is 14 seconds based on equation (2), the erase interval (IG) can be determined as, for example, 1.75 seconds.
[0068] Therefore, the first erase unit containing two memory blocks is erased within 2 seconds (TE31), and after an erase interval of 1.75 seconds (TI31), the next erase unit is erased. This process is repeated eight times (TE31 → TI31 → TE32 → TI32 → TE33 → TI33 → TE34 → TI34 → TE35 → TI35 → TE36 → TI36 → TE37 → TI37 → TE38 → TI38), and all spare superblocks can be erased (ER) within the write time (30 seconds) of the internal random write operation currently being written.
[0069] If the erase interval (IG) is determined as I / ((B / X)-1), the last erase interval (TI38) may be omitted.
[0070] 9a and 9b are graphs illustrating peak power due to an erase operation of a spare super-block.
[0071] Figure 9a shows the peak power when simultaneously erasing 16 memory blocks included in a spare super-block in the example described with reference to Figure 8. Figure 9b shows the peak power when the spare super-block is grouped into erase units and erased at regular intervals.
[0072] If the erase power per memory block is, for example, 10 mW, erasing 16 memory blocks in the spare superblock simultaneously consumes a peak power of 160 mW during the erase time per block (2 seconds), as shown in Figure 9a.
[0073] If the spare superblocks are grouped into eight erase units, each containing two memory blocks, and erased at regular intervals (1.75 seconds), the peak power per erase operation can be reduced to 20 mW, as shown in Figure 9b, thereby reducing instantaneous power consumption.
[0074] FIG. 10 is a flowchart illustrating an operation method of a data storage device according to an embodiment.
[0075] The erasure management circuit 30 of the storage controller 210 can monitor whether a write operation is being processed (S101, S101:N).
[0076] If a write operation is being processed (S101: Y), the erasure management circuit 30 can determine the type of write operation currently being processed (S103).
[0077] If the determination result indicates that the current write operation is a sequential write operation (S103: sequential write), the erase management circuit 30 can set a write time (a) accordingly (S105). The write time may be the erase time of a spare superblock to be erased for the subsequent write operation.
[0078] If the current write operation is an external random write operation (S103: external random write), the erase management circuit 30 can set the write time (b) accordingly (S107).
[0079] If the current write operation is an internal random write operation (S103: internal random write), the erasure management circuit 30 can set a write time (c) according to the internal random write operation (S109).
[0080] After the write time is set (S105, S107, S109), the erase management circuit 30 can group memory blocks in the spare super-block to form erase units (S111) so that the number of memory blocks erased simultaneously is minimized.
[0081] Thus, once the number of erase units is determined, the erase management circuit 30 can determine the erase intervals so that the erase intervals between the erase units are uniform (S113).
[0082] The erase management circuit 30 can control the storage medium 260 so that the spare superblocks are erased in units of erase units determined in the grouping step S111 according to the erase interval determined in the erase interval determination step S113 (S115).
[0083] Since peak power consumption increases in proportion to the number of memory blocks erased simultaneously, the performance of the data storage device can be maintained constant by grouping memory blocks in a spare superblock to form erase units and uniforming the erase intervals between erase units to minimize the number of memory blocks erased simultaneously.
[0084] The performance consistency of the data storage device 200 can be measured as the minimum IOPS (Input Output Per Second) relative to the average IOPS, and the consistency can be evaluated based on how uniformly the IOPS is measured when measuring the IOPS over a specific period of time.
[0085] After the data storage device enters the sustain state, the program time (tPROG) or erase time may change, and frequent internal operations (such as garbage collection) may cause uneven IOPS, resulting in reduced performance consistency.
[0086] This technique minimizes peak power and ensures consistent performance by erasing blocks in a superblock prepared for subsequent write operations in a way that minimizes the number of simultaneous erases and keeps the erase interval between groups as large and consistent as possible.
[0087] As such, those skilled in the art will recognize that the present invention can be embodied in different specific forms without changing the technical concept or essential features thereof, and therefore the above-described embodiments are illustrative in all respects and not limiting. The scope of the present invention is defined by the claims below rather than the above detailed description, and all modifications and variations derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the present invention. [Explanation of symbols]
[0088] 10 Data Processing System 30 Erase management circuit 100 External device 200 Data storage device 210 Storage Controller 220 Buffer memory device 230,240,250 Non-volatile memory devices 260 Storage medium 310 Type judgment circuit 320 Grouping Circuit 330 Erasing interval determination circuit 340 Erase control circuit
Claims
1. a storage medium including a plurality of memory blocks; a storage controller that combines the plurality of simultaneously accessible memory blocks and manages them as a superblock; The storage controller During a write time set according to the type of write operation currently being processed, a spare superblock for the write operation to be next processed is erased; The data storage device is configured to divide the memory blocks in the spare superblock into any number of erase units, and erase the erase units at regular intervals.
2. The data storage device of claim 1 , wherein the storage controller configures the erase units to minimize the number of memory blocks that are erased simultaneously.
3. 2. The data storage device of claim 1, wherein the storage controller is configured to divide the spare superblock based on a write time of the currently processed write operation such that all erase units are erased within the write time.
4. The data storage device of claim 1 , wherein the types of write operations include sequential write operations, random write operations requested by an external device, and random write operations performed by an internal operation of the data storage device.
5. The power consumption during an erase operation is determined as the product of the erase power per memory block and the number of memory blocks to be erased simultaneously, 2. The data storage device of claim 1, wherein power consumption during an erase operation per erase unit is configured to be less than power consumption during a simultaneous erase operation of all memory blocks in the spare super-block.
6. A plurality of memory blocks included in the storage medium are combined so as to be simultaneously accessible and managed as a superblock; erasing a spare superblock for a next write operation during a write time corresponding to the type of write operation currently being performed on the storage medium; A data storage device configured to include a storage controller configured to determine the number of memory blocks per erase unit and the erase interval between erase units based on the number of erase units that group multiple memory blocks in the spare superblock and the erase time per erase unit so that all erase units are erased within the write time.
7. 1. A method for operating a data storage device including a storage medium and a storage controller that combines a plurality of memory blocks included in the storage medium so that the memory blocks can be accessed simultaneously and manages the combined memory blocks as a superblock, comprising: The storage controller determines a write time according to the type of write operation currently being processed; The storage controller divides a plurality of memory blocks in a spare superblock for a next write operation into an arbitrary number of erase units; The method for operating a data storage device is configured to include a step in which the storage controller erases the erase unit at regular intervals.
8. 8. The method of claim 7, wherein the dividing step comprises dividing the memory blocks so as to minimize the number of memory blocks that are erased simultaneously.
9. 8. The method of claim 7, wherein the dividing step includes dividing the erase units based on a write time of the currently processed write operation so that all erase units are erased within the write time.
10. 8. The method of claim 7, wherein the types of write operations include a sequential write operation, a random write operation requested by an external device, and a random write operation performed by an internal operation of the data storage device.
11. The power consumption during an erase operation is determined as the product of the erase power per memory block and the number of memory blocks to be erased simultaneously, 8. The method of claim 7, wherein power consumption during an erase operation per erase unit is configured to be less than power consumption during a simultaneous erase operation of all memory blocks in the spare super-block.