Semiconductor optical element and method of manufacturing semiconductor optical element

Abstract

To provide a semiconductor optical element that can be prevented from being etched from a junction interface, and a method of manufacturing the semiconductor optical element.SOLUTION: There is provided a semiconductor optical element that comprises a substrate having a silicon layer and a semiconductor element formed of a group III-V compound semiconductor and joined to the silicon layer of the substrate, and is provided with grooves in the silicon layer, wherein the grooves extend from where they overlap the joined semiconductor element to outside the joined semiconductor element, and each have one communication port for communicating a groove part, overlapping the joined semiconductor element, with the part outside the joined semiconductor element.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor optical device and a method for manufacturing the semiconductor optical device. [Background technology]

[0002] A hybrid semiconductor optical device can be formed by bonding a semiconductor element made of a compound semiconductor and having optical gain to a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) on which a waveguide is formed. When hydrophilic bonding is performed during the bonding process, water is generated. When water evaporates at the bonding interface, bubbles are generated, resulting in poor bonding. Technology has been developed to provide grooves in the substrate to allow water to escape (e.g., Non-Patent Documents 1 and 2). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Yiding Lin et al. “Geometry and Thermal Stress Analysis of In-plane Outgassing Channels in Al2O3-Intermediated InP(Die)-to-Si(Wafer) Bonding” ECS Journal of Solid State Science and Technology,5(2) P117-P123(2016) [Non-patent document 2] Jiajie Lin et al. “Wafer-scale heterogeneous integration InP on trenched Si with a bubble-free interface” APL Materials 8,051110(2020) Summary of the Invention [Problem to be solved by the invention]

[0004] Bonded semiconductor elements are processed by wet etching or the like. However, there is a risk that etchant may seep in through the dehydration grooves and etch the semiconductor element from the bonding interface. This may result in peeling of the semiconductor element or a decrease in performance. Therefore, the objective is to provide a semiconductor optical element and a method for manufacturing a semiconductor optical element that can prevent etching of the semiconductor element from the bonding interface. [Means for solving the problem]

[0005] The semiconductor optical device according to the present disclosure comprises a substrate having a silicon layer, and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer of the substrate, wherein a groove is provided in the silicon layer, the groove extending from a position overlapping the bonded semiconductor element to an outside of the bonded semiconductor element, and the groove has a communication opening connecting the portion of the groove overlapping the bonded semiconductor element to a portion outside the bonded semiconductor element, and each groove has one communication opening. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to provide a semiconductor optical device and a method for manufacturing a semiconductor optical device that can prevent etching of the semiconductor device from the bonding interface. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1A is a plan view illustrating the semiconductor optical device according to the first embodiment. [Figure 1B] FIG. 1B is a plan view illustrating the substrate. [Figure 2A] FIG. 2A is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 2B] FIG. 2B is a cross-sectional view illustrating the substrate. [Figure 2C] FIG. 2C is a cross-sectional view illustrating the substrate. [Figure 2D] FIG. 2D is a cross-sectional view illustrating the substrate. [Figure 3A]FIG. 3A is a schematic view illustrating a method for manufacturing a semiconductor optical device. [Figure 3B] FIG. 3B is a schematic view illustrating a method for manufacturing a semiconductor optical device. [Figure 4A] FIG. 4A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 4B] FIG. 4B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 4C] FIG. 4C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 4D] FIG. 4D is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 5A] FIG. 5A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 5B] FIG. 5B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 5C] FIG. 5C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 5D] FIG. 5D is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 6A] FIG. 6A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 6B] FIG. 6B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 6C] FIG. 6C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 6D] FIG. 6D is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 7A] FIG. 7A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 7B] FIG. 7B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 7C] FIG. 7C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 7D] FIG. 7D is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 8A] FIG. 8A is a plan view illustrating a method for manufacturing a semiconductor optical device according to Comparative Example 1. FIG. [Figure 8B] FIG. 8B is a cross-sectional view illustrating a cross section along line DD in FIG. 8A. [Figure 9A] FIG. 9A is a plan view illustrating the method for manufacturing the semiconductor optical device according to the second embodiment. [Figure 9B] FIG. 9B is a plan view illustrating the substrate. [Figure 10A] FIG. 10A is a plan view illustrating the method for manufacturing the semiconductor optical device according to the third embodiment. [Figure 10B] FIG. 10B is a plan view illustrating the substrate. [Figure 11] FIG. 11 is a plan view illustrating a method for manufacturing a semiconductor optical device according to Comparative Example 2. In FIG. [Figure 12A] FIG. 12A is a plan view illustrating the method for manufacturing the semiconductor optical device according to the fourth embodiment. [Figure 12B] FIG. 12B is a plan view illustrating the substrate. [Figure 13] FIG. 13 is a plan view illustrating a method for manufacturing a semiconductor optical device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0009] One aspect of the present disclosure is a semiconductor optical device comprising: (1) a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer of the substrate, wherein a groove is formed in the silicon layer, the groove extending from a position overlapping the bonded semiconductor element to outside the bonded semiconductor element, and the groove has a communication opening connecting the portion of the groove overlapping the bonded semiconductor element to a portion outside the bonded semiconductor element, and each groove has one communication opening. Since there is one communication opening, an etchant is less likely to enter the groove. This makes it possible to prevent etching of the semiconductor element from the bonded interface. (2) In the above (1), the silicon layer may have a plurality of the grooves, each of which may have one of the communication holes. Moisture can be discharged from the bonding interface through the plurality of grooves. Since each of the plurality of grooves has one communication hole, etchant is less likely to enter. Etching of the semiconductor element from the bonding interface can be prevented. (3) In the above (1) or (2), the silicon layer may have a waveguide, one side of the silicon layer relative to the waveguide may be a first portion, and the other side may be a second portion, and at least one groove may be provided in each of the first portion and the second portion. Both the first portion and the second portion may be able to expel moisture and prevent intrusion of an etchant. (4) In any of the above (1) to (3), the groove may be located within a range of 50 μm from any position on the bonding interface between the substrate and the semiconductor element. Because the distance to the groove is short, moisture can easily reach the groove and be discharged. (5) In any of the above (1) to (4), the planar shape of the groove may be U-shaped, ladder-shaped, or lattice-shaped. Since the grooves are arranged over a wide area of ​​the bonding interface, moisture can be easily discharged from the grooves. (6) In any of the above (1) to (5), the semiconductor element may be in contact with the silicon layer. This improves the performance of the semiconductor optical element. By discharging moisture generated at the bonding interface through the groove, air bubbles are less likely to be generated at the bonding interface. (7) A method for manufacturing a semiconductor optical device, comprising the steps of bonding a semiconductor element formed of a III-V compound semiconductor to a silicon layer of a substrate by hydrophilic bonding, and wet etching the bonded semiconductor element, wherein the silicon layer has a groove, the groove extends from a position overlapping the bonded semiconductor element to outside the bonded semiconductor element, and has a communication opening connecting the portion of the groove overlapping the bonded semiconductor element to the portion outside the bonded semiconductor element, and each groove has one communication opening. Since there is one communication opening, etchant is less likely to enter the groove. It is possible to prevent etching of the semiconductor element from the bonding interface. Moisture generated by hydrophilic bonding can be discharged from the groove. (8) In the above (7), a step of forming a mask may be included before the step of performing the wet etching, and the mask may be embedded in the portion of the groove outside the bonded semiconductor element, and the communication opening may be blocked by the mask. In the step of performing the wet etching, the portion of the semiconductor element exposed through the mask may be wet etched. There is a risk of holes being formed in the mask. Since each groove has only one communication opening, etchant is less likely to penetrate through the communication opening. This can prevent etching of the semiconductor element from the bonded interface side. (9) In the above (7) or (8), after the bonding step, the groove may be present within a range of 50 μm from any position on the bonding interface between the substrate and the semiconductor element. Because the distance to the groove is short, moisture can easily reach the groove and be discharged. (10) In any of the above (7) to (9), the bonding step may be performed at a temperature higher than room temperature and at a pressure lower than atmospheric pressure. Increasing the temperature generates moisture. Lowering the pressure makes it easier for the moisture to be drawn out of the bonding interface and discharged.

[0010] [Details of the embodiments of the present disclosure] Specific examples of semiconductor optical devices and methods for manufacturing semiconductor optical devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0011] First Embodiment FIG. 1A is a plan view illustrating a semiconductor optical device 100 according to the first embodiment. FIG. 1B is a plan view illustrating a substrate 10. FIG. 2A is a cross-sectional view illustrating the semiconductor optical device 100, taken along line AA in FIG. 1A. FIGS. 2B to 2D are cross-sectional views illustrating the substrate 10, showing the silicon layer 16 of the substrate 10 and omitting other layers of the substrate 10. FIG. 2B is a cross-sectional view taken along line BB in FIG. 1B. FIG. 2C is a cross-sectional view taken along line CC in FIG. 1B. FIG. 2D is a cross-sectional view taken along line DD in FIG. 1B.

[0012] 1A, the semiconductor optical device 100 is a hybrid device and includes a substrate 10 and a semiconductor element 20. The semiconductor element 20 is formed of, for example, a III-V compound semiconductor and has optical gain. The semiconductor optical device 100 functions as a semiconductor laser element, an optical modulator, or the like.

[0013] Two sides of the substrate 10 are parallel to the X-axis. Two other sides of the substrate 10 are parallel to the Y-axis. The top surface of the substrate 10 is parallel to the XY plane. The normal to the top surface of the substrate 10 is parallel to the Z-axis. The X-axis, Y-axis, and Z-axis are perpendicular to each other. As shown in FIG. 1A, the length L1 of the substrate 10 in the X-axis direction is, for example, 1500 μm. The length L2 of the substrate 10 in the Y-axis direction is, for example, 500 μm.

[0014] As shown in FIGS. 1A and 1B, the substrate 10 has a waveguide 30, a recess 32, a terrace 34, and two grooves 36. The recess 32 is provided on both sides of the waveguide 30 in the Y-axis direction. The waveguide 30 and the recess 32 are parallel to the X-axis direction. The width of the waveguide 30 is, for example, 0.5 μm. The width of the recess 32 is, for example, 2 μm. The terrace 34 is provided on the opposite side of the recess 32 from the waveguide 30.

[0015] In the example of FIGS. 1A and 1B, the waveguide 30 is located at the center of the substrate 10 in the Y-axis direction. One terrace 34a (first portion) is located on one side of the waveguide 30, and another terrace 34b (second portion) is located on the opposite side. One of the two grooves 36 is groove 36a and the other is groove 36b. Groove 36a is provided in terrace 34a. Groove 36b is provided in terrace 34b. Groove 36 is a dehydration groove for draining moisture.

[0016] 1A and 1B, the planar shape of the groove 36 is U-shaped. The groove 36 includes a groove 50, a groove 52, and a groove 54. The grooves 50 and 52 are parallel to the X-axis direction. The groove 54 is parallel to the Y-axis direction. The groove 52 is located closer to the waveguide 30 than the groove 50. The groove 54 is connected to one end of the groove 50 and one end of the groove 52. The grooves 50, 52, and 54 form a U-shape.

[0017] 1B, the width W1 of the groove 36 is, for example, 3 μm. The distance D1 between the groove 50 and the groove 52 in the Y-axis direction is, for example, 50 μm or less. The distance D2 between the groove 52 and the recess 32 is, for example, 50 μm or less.

[0018] As shown in FIG. 1A, the semiconductor device 20 has a mesa 21 and a tapered portion 23. The mesa 21 is parallel to the X-axis and is located on a waveguide 30 of the substrate 10. Both ends of the mesa 21 in the X-axis direction are tapered. The semiconductor device 20 has one tapered portion 23 on each end in the X-axis direction. One tapered portion 23 is located on the waveguide 30 and tapers along the X-axis direction. The other tapered portion 23 is located on the waveguide 30 and tapers in the opposite direction of the X-axis direction.

[0019] As shown in FIG. 1A , the portion of groove 36 that overlaps semiconductor element 20 is designated as portion 40. The portion of groove 36 that is located outside semiconductor element 20 is designated as portion 42. Groove 50 of groove 36 extends from below semiconductor element 20 to the outside of semiconductor element 20. One end of groove 50 is located outside semiconductor element 20, for example, at the edge of substrate 10. A portion of groove 50, the entirety of groove 52, and the entirety of groove 54 are located below semiconductor element 20. That is, portion 40 of groove 36 includes a portion of groove 50, groove 52, and groove 54, and has a U-shape. Portion 42 of groove 36 includes another portion of groove 50.

[0020] The groove 36 has a communication opening 44. A portion 40 of the groove 36 that overlaps the semiconductor element 20 and a portion 42 outside the semiconductor element 20 communicate with each other at the communication opening 44. The communication opening 44 overlaps an end of the semiconductor element 20. The position of the communication opening 44 is determined depending on the shape and size of the semiconductor element 20. One groove 36 has one communication opening 44.

[0021] As shown in FIG. 2A, substrate 10 is, for example, an SOI (Silicon on Insulator) substrate, and includes substrate 12, box layer 14, and silicon layer 16. Substrate 12 is formed of, for example, silicon (Si). Box layer 14 is formed of, for example, silicon oxide (SiO2). Silicon layer 16 has a refractive index of 3.45. Box layer 14 has a refractive index of 1.45, which is lower than that of silicon layer 16. Box layer 14 has a thickness of, for example, 3 μm. Silicon layer 16 has a thickness of, for example, 220 nm. The total thickness of substrate 10 is, for example, 750 μm.

[0022] In the Z-axis direction, a box layer 14 and a silicon layer 16 are stacked in this order on one surface of the substrate 12. In the Z-axis direction, where the surface of the silicon layer 16 opposite to the box layer 14 is surface 17, the waveguide 30 and the terrace 34 are located at the same height and form surface 17 of the silicon layer 16. A semiconductor element 20 is bonded to surface 17.

[0023] 2B and 2C, the recess 32 and the groove 36 are recessed in the Z-axis direction relative to the surface 17. The depth D3 of the groove 36 is, for example, 200 nm. The recess 32 and the groove 36 may extend partway through the silicon layer 16 in the Z-axis direction, or may extend to the surface of the box layer 14.

[0024] As shown in FIG. 2A , the semiconductor device 20 has a cladding layer 22, an active layer 24, a cladding layer 26, and a contact layer 28. The cladding layer 22 is in contact with the surface 17 of the silicon layer 16. The active layer 24, the cladding layer 26, and the contact layer 28 are stacked in this order on the surface of the cladding layer 22 opposite the silicon layer 16. The mesa 21 includes the cladding layer 26 and the contact layer 28, and protrudes in the Z-axis direction. The cladding layer 22 and the active layer 24 are provided over a wider area than the mesa 21 in the XY plane. The tapered portion 23 includes the cladding layer 22 and the active layer 24.

[0025] The insulating film 25 covers the side surfaces of the mesa 21 and covers the upper surface of the active layer 24. The insulating film 25 has an opening above the mesa 21. An electrode 29 is provided in the opening. The electrode 29 is electrically connected to the contact layer 28. The insulating film 25 has an opening (not shown) at a position spaced apart from the mesa 21. An electrode (not shown) is provided in the opening, which is electrically connected to the cladding layer 22. The electrode is made of metal.

[0026] The insulating film 25 covers the portion of the substrate 10 that is located outside the semiconductor element 20, and fills the recess 32 of the substrate 10 and the portion of the groove 36 that is located outside the semiconductor element 20. The insulating film 25 is made of silicon oxide (SiO2) with a thickness of 1 μm, for example.

[0027] The cladding layer 22 is formed of, for example, n-type indium phosphide (n-InP) with a thickness of 0.4 μm. The active layer 24 has a quantum well structure (MQW: Multiple Quantum Well) and includes barrier layers and well layers. Multiple barrier layers and multiple well layers are alternately stacked. The barrier layers and well layers are formed of, for example, i-type gallium indium arsenide phosphide (GaInAsP). The cladding layer 26 is formed of, for example, p-type indium phosphide (p-InP). The contact layer 28 is formed of, for example, p-type gallium indium arsenide (p-GaInAs). The semiconductor layers of the semiconductor element 20 may be formed of III-V compound semiconductors other than those mentioned above.

[0028] A voltage is applied to the semiconductor element 20 using the electrodes, and carriers are injected into the active layer 24. The active layer 24 has optical gain, and generates light through carrier injection. The wavelength of the light is, for example, 1.55 μm. The semiconductor element 20 and the substrate 10 are evanescently coupled. The light generated in the semiconductor element 20 is concentrated and distributed near the mesa 21 of the semiconductor element 20. In the tapered portion 23, the light transfers from the semiconductor element 20 to the waveguide 30 and propagates through the waveguide 30.

[0029] To prevent light loss, a mesa 21 and a tapered portion 23 are formed on the bonded semiconductor element 20 by etching or the like. The mode shape is stabilized because the semiconductor element 20 has the mesa 21. At the tapered portion 23 of the semiconductor element 20, light gradually transitions between the semiconductor element 20 and the waveguide 30.

[0030] In order to improve characteristics such as the above-mentioned improvement in the efficiency of light transition via tapered portion 23 and the improvement in optical output, semiconductor element 20 is brought into contact with surface 17 of silicon layer 16 without providing an adhesive or the like between semiconductor element 20 and silicon layer 16 of substrate 10. As will be described later, semiconductor element 20 is bonded to silicon layer 16 by hydrophilic bonding.

[0031] (Manufacturing method) 3A and 3B are schematic diagrams illustrating a method for manufacturing the semiconductor optical device 100, showing the bonding process. 4A, 5A, 6A, and 7A are plan views illustrating a method for manufacturing the semiconductor optical device 100. 4B to 4D, 5B to 5D, 6B to 6D, and 7B to 7D are cross-sectional views illustrating a method for manufacturing the semiconductor optical device 100. In cross-sectional views such as FIG. 4B, the silicon layer 16 of the substrate 10 is shown, and the box layer 14 and the substrate 12 are omitted.

[0032] The silicon layer 16 of the substrate 10 is dry-etched to form recesses 32 and grooves 36 as shown in FIG. 1B. A contact layer 28, a cladding layer 26, an active layer 24, and a cladding layer 22 are epitaxially grown on an indium phosphide (InP) substrate, which is separate from the substrate 10, by, for example, metal organic chemical vapor deposition (MOCVD). The InP substrate is diced to produce the semiconductor device 20. Immediately after dicing, the semiconductor device 20 has, for example, a rectangular parallelepiped shape, and does not have a mesa or tapered portion.

[0033] As shown in Figures 3A and 3B, a semiconductor element 20 is bonded to a substrate 10. As shown in Figure 3A, the bonding process is performed in a chamber 18. In the atmosphere, ultraviolet (UV) rays are irradiated onto one surface 19 of the semiconductor element 20 and a surface 17 of the silicon layer 16 of the substrate 10. The UV rays generate ozone from oxygen in the atmosphere. The surfaces 19 and 17 are then washed with water. The surface 19 of the semiconductor element 20 and the surface 17 of the substrate 10 are made hydrophilic. Hydrophilization generates hydroxyl groups (OH) on the surfaces 19 and 17.

[0034] The surface 19 of the semiconductor element 20 is brought into contact with the surface 17 of the substrate 10, and a load is applied. After the contact, heating and evacuation are performed. The temperature inside the chamber 18 is set to, for example, 150°C. By evacuation, the pressure inside the chamber 18 is reduced to, for example, 1×10 -2 As shown in Figure 3B, heating causes a water molecule (H2O) to leave the hydroxyl group, leaving an oxygen atom (O). The oxygen atom connects face 19 and face 17.

[0035] 4A, a semiconductor element 20 is bonded to a substrate 10. The length L3 of the semiconductor element 20 in the X-axis direction is, for example, 800 μm, and the length L4 in the Y-axis direction is, for example, 300 μm.

[0036] FIG. 4B shows a cross section taken along line BB in FIG. 4A. FIG. 4C shows a cross section taken along line CC in FIG. 4A. FIG. 4D shows a cross section taken along line DD in FIG. 4A. After bonding and before etching, semiconductor element 20 has substrate 27. Substrate 27 is made of, for example, InP. As shown in FIGS. 4A, 4B, and 4D, portion 40 of groove 36 is located under semiconductor element 20. As shown in FIGS. 4A, 4C, and 4D, portion 42 of groove 36 is located outside semiconductor element 20. As shown in FIGS. 4A and 4D, a communication hole 44 is formed at the boundary between portion 40 and portion 42.

[0037] 4A, the distance D3 from groove 52 of groove 36 to the semiconductor element 20 in the Y-axis direction is, for example, 50 μm or less. The distance D4 from groove 54 of groove 36 to the end of the semiconductor element 20 in the X-axis direction is, for example, 50 μm or less. The distance D5 from the end of groove 52 to the end of the semiconductor element 20 in the X-axis direction is, for example, 50 μm or less. After bonding and before wet etching, groove 36 exists within a range of, for example, 50 μm from any position on the bonding interface.

[0038] As described above, moisture is generated by performing hydrophilic bonding. If moisture remains at the bonding interface, it may evaporate and generate bubbles. The moisture moves from the bonding interface to the groove 36 and is discharged from the groove 36. By lowering the air pressure inside the chamber 18 below atmospheric pressure, the moisture moves across the bonding interface, reaches the groove 36, and is discharged to the outside of the semiconductor element 20 through the communication port 44 and the portion 42.

[0039] Figure 5B shows a cross section taken along line BB in Figure 5A. Figure 5C shows a cross section taken along line CC in Figure 5A. Figure 5D shows a cross section taken along line DD in Figure 5A. As shown in Figures 5A to 5D, an insulating film 56 is formed by, for example, plasma enhanced chemical vapor deposition (PECVD). The insulating film 56 is made of an insulator such as silicon oxide (SiO2) and covers the surface 17 of the substrate 10 and the semiconductor element 20.

[0040] The insulating film 56 is covered with a resist mask (not shown), and resist patterning is performed. Openings are formed in the resist mask at positions that overlap the semiconductor element 20 in the Z-axis direction. Portions of the insulating film 56 that are exposed from the resist mask are removed using hydrofluoric acid. After etching with hydrofluoric acid, the resist mask is removed. As shown in FIGS. 5B and 5D, the substrate 27 of the semiconductor element 20 is exposed from the insulating film 56.

[0041] As shown in Figures 5B and 5D, insulating film 56 is not embedded in portion 40 of groove 36 that overlaps with semiconductor element 20. As shown in Figures 5C and 5D, insulating film 56 is embedded in portion 42 of groove 36 that is located outside semiconductor element 20. As shown in Figure 5D, communication opening 44 is closed with insulating film 56. As shown in Figure 5B, insulating film 56 is not embedded in portion of recess 32 that overlaps with semiconductor element 20. As shown in Figure 5C, insulating film 56 is embedded in portion of recess 32 that is located outside semiconductor element 20.

[0042] Wet etching is performed using the insulating film 56 as a mask, and the substrate 27 of the semiconductor element 20 is removed by wet etching. A hydrochloric acid (HCl) based solution is used as the etchant.

[0043] FIG. 6B shows a cross section taken along line BB in FIG. 6A. FIG. 6C shows a cross section taken along line CC in FIG. 6A. FIG. 6D shows a cross section taken along line DD in FIG. 6A. As shown in FIGS. 6A to 6D, the substrate 27 is removed by wet etching. Layers from the contact layer 28 to the cladding layer 22 remain. After wet etching, the contact layer 28 is exposed. After wet etching, the insulating film 56 used as a mask is removed. The surface 17 of the substrate 10 is exposed.

[0044] FIG. 7B shows a cross section taken along line BB in FIG. 7A. FIG. 7C shows a cross section taken along line CC in FIG. 7A. FIG. 7D shows a cross section taken along line DD in FIG. 7A. As shown in FIGS. 7A to 7D, an insulating film 58 is provided by a PECVD method or the like. In the steps following FIG. 7A, a resist pattern is transferred to form a pattern in the insulating film 58. Dry etching and wet etching are performed using the insulating film 58 as a mask. Another mask is then provided, and wet etching is performed on the portions of the semiconductor element 20 exposed through the mask. The semiconductor element 20 is etched to form the mesa 21 and tapered portion 23 shown in FIG. 1A. Electrodes are formed by vacuum deposition or the like.

[0045] As described above, multiple wet etching processes are performed in the manufacturing process. These wet etching processes use a hydrochloric acid-based etchant or the like. Since each groove 36 has only one communication opening 44, the etchant is less likely to enter the portion 40 of the groove 36. This prevents etching of the semiconductor element 20 from the bonding interface.

[0046] (Comparative Example 1) Fig. 8A is a plan view illustrating a method for manufacturing a semiconductor optical device according to Comparative Example 1. Fig. 8B is a cross-sectional view illustrating a cross section taken along line DD in Fig. 8A. Fig. 8A and Fig. 8B show steps corresponding to Fig. 5A to Fig. 5D.

[0047] As shown in Figure 8A, the substrate 10 has four grooves 37. Two grooves 37 are provided on terrace 34a. Two grooves 37 are provided on terrace 34b. The grooves 37 are linear, parallel to the X-axis direction, and extend from one end of the substrate 10 to the other end in the X-axis direction. Each groove 37 has one portion 40, two portions 42, and two communication ports 44.

[0048] As shown in FIG. 8B , the two communication holes 44 are covered with an insulating film 56. However, tiny holes may appear in the insulating film 56, resulting in insufficient coverage by the insulating film 56. In such cases, the communication holes 44 are not blocked by the insulating film 56 and may serve as entry points for etchant. One groove 37 has two communication holes 44. The substrate 10 has eight communication holes 44. Because there are so many communication holes 44, etchant easily enters the portion 40 of the groove 37 through the communication holes 44. When the etchant enters the portion 40 of the groove 37, the semiconductor element 20 is etched from the bonding interface side. This unintended etching may cause peeling of the semiconductor element 20 and result in poor performance.

[0049] According to the first embodiment, as shown in FIG. 4A and other figures, one groove 36 has one communication opening 44. The substrate 10 has two communication openings 44, which is fewer than the eight in Comparative Example 1. Because there are fewer communication openings 44, the etchant is less likely to enter the portion 40 of the groove 36. Etching of the semiconductor element 20 from the bonding interface can be prevented. Peeling of the semiconductor element 20 and performance defects are less likely to occur, reducing the number of defective products.

[0050] As shown in FIGS. 5A to 5D and 7A to 7D, mask formation and wet etching are repeated multiple times. The portions covered with the mask do not come into contact with the etchant and are not etched. However, holes may be formed in the mask. According to the first embodiment, each groove 36 has only one communication opening 44, which makes it difficult for the etchant to penetrate into the portion 40 of the groove 36. This prevents etching of the semiconductor element 20 from the bonding interface.

[0051] As shown in FIGS. 1A and 4A, the substrate 10 has two grooves 36. Moisture can be discharged from the bonding interface through the two grooves 36. Each of the two grooves 36 has a communication port 44. Etchant is less likely to enter the two grooves 36. This makes it possible to prevent the semiconductor element 20, which is made of a III-V compound semiconductor, from being etched from the bonding interface.

[0052] Terrace 34a is located on one side of waveguide 30. Terrace 34b is located on the opposite side. A groove 36a is provided in terrace 34a. A groove 36b is provided in terrace 34b. Groove 36a and groove 36b each have one communication opening 44. Both terrace 34a and terrace 34b can discharge moisture and prevent the intrusion of etchant.

[0053] 1A and 1B, the planar shape of portion 40 of groove 36 is U-shaped. Groove 52 is located near waveguide 30. Groove 50 is located near the end of semiconductor element 20. Because groove 36 is disposed over a wide range of the bonding interface, moisture is easily discharged from groove 36. As will be described later, the number of grooves 36 may be two or more. The planar shape of groove 36 may be other than U-shaped.

[0054] The shorter the distance from the location where moisture is generated to the groove 36, the easier it is for the moisture to reach the groove 36 and be discharged. Distances D3, D4, and D5 between the groove 36 and the end of the semiconductor element 20 are all, for example, 50 μm or less. Distance D1 between groove 50 and groove 52 of the groove 36 is, for example, 50 μm or less. Distance D2 between the recess 32 and the groove 36 is, for example, 50 μm. In the XY plane, the groove 36 is located within a range of, for example, 50 μm from any position on the bonding interface. Moisture can easily reach the groove 36 and be discharged. This makes it difficult for moisture to remain at the bonding interface.

[0055] The distances D1, D2, D3, D4, and D5 may be, for example, 40 μm or less, 50 μm or less, 60 μm or less, or 100 μm or less. That is, the groove 36 may be located within, for example, 40 μm, 50 μm, 60 μm, or 100 μm of any position on the bonding interface.

[0056] As shown in Figure 2A, the semiconductor element 20 is in contact with the surface 17 of the substrate 10. This improves the performance of the semiconductor optical element 100. To directly bond the semiconductor element 20 to the substrate 10, hydrophilic bonding is performed. By discharging moisture generated during hydrophilic bonding through the grooves 36, air bubbles are less likely to form at the bonding interface.

[0057] The hydrophilic bonding process is carried out at a temperature higher than room temperature and at a pressure lower than atmospheric pressure. When the temperature reaches, for example, 100°C or higher, or 150°C or higher, moisture is generated from the bonding interface. By lowering the pressure, the moisture is sucked out of the bonding interface and is easily discharged. The pressure in the chamber 18 is set to, for example, 1×10 -2 Pa or less, 5×10 -2 Pa or less, 10×10 -2 Pa or less.

[0058] Second Embodiment Fig. 9A is a plan view illustrating a method for manufacturing a semiconductor optical device according to the second embodiment, and illustrates a step corresponding to Fig. 4A. Fig. 9B is a plan view illustrating a substrate 10. Descriptions of the same configuration as in the first embodiment will be omitted.

[0059] 9A and 9B, the silicon layer 16 of the substrate 10 has two grooves 60. Of the two grooves 60, groove 60a is provided in terrace 34a. Of the two grooves 60, groove 60b is provided in terrace 34b.

[0060] The groove 60 includes a groove 50, a groove 52, and a plurality of grooves 54. One end of each groove 54 is connected to a groove 50. The other end of each groove 54 is connected to a groove 52. Each groove 54 extends in the Y-axis direction. The plurality of grooves 54 are aligned along the X-axis direction. The grooves 50, 52, and the plurality of grooves 54 form a ladder shape. The number of grooves 54 in one groove 60 may be six or more, or six or less. As shown in FIG. 9B , the distance D6 between the groove 50 and the groove 52 in the Y-axis direction is, for example, 50 μm or less. The distance D7 between two adjacent grooves 54 in the X-axis direction is, for example, 50 μm or less.

[0061] 9A , groove 50 of groove 60 extends from below semiconductor element 20 to outside semiconductor element 20. A portion of groove 50, the entire groove 52, and the entire plurality of grooves 54 are located below semiconductor element 20. That is, portion 40 of groove 60 includes a portion of groove 50, the entire groove 52, and the entire plurality of grooves 54, and has a ladder shape. Portion 42 includes another portion of groove 50. One groove 60 has one communication opening 44.

[0062] According to the second embodiment, one groove 60 has one communication opening 44. The substrate 10 has two communication openings 44. Because the number of communication openings 44 is small, the etchant is less likely to enter the portion 40 of the groove 60. This makes it possible to prevent etching of the semiconductor element 20 from the bonding interface.

[0063] 9A, the planar shape of portion 42 of groove 60 is ladder-shaped. Groove 50 of groove 60 is located near the edge of semiconductor element 20. Groove 52 is located near waveguide 30. A plurality of grooves 54 connect grooves 50 and grooves 52. Because grooves 60 are arranged over a wide range of the bonding interface, moisture can be easily discharged from grooves 60.

[0064] Third Embodiment Fig. 10A is a plan view illustrating a method for manufacturing a semiconductor optical device according to the third embodiment, and illustrates a step corresponding to Fig. 4A. Fig. 10B is a plan view illustrating the substrate 10. Descriptions of the same configurations as those in the first or second embodiment will be omitted.

[0065] 10A and 10B, the silicon layer 16 of the substrate 10 has eight grooves 62. Of the eight grooves 62, four grooves 62a are provided on the terrace 34a. The four grooves 62a are aligned in the X-axis direction. Of the eight grooves 62, four grooves 62b are provided on the terrace 34b. The four grooves 62b are aligned in the X-axis direction.

[0066] Groove 62 includes groove 63, groove 64, and groove 65. Groove 63 and groove 65 are parallel to the Y-axis direction. Groove 64 is parallel to the X-axis direction and is located between groove 63 and groove 65. Groove 64 is connected to one end of groove 63 and one end of groove 65. As shown in FIG. 10B, a distance D8 between groove 63 and groove 65 is, for example, 50 μm or less. A distance D9 between two adjacent grooves 62 is, for example, 50 μm or less.

[0067] 10A , groove 63 of groove 62 extends from below semiconductor element 20 to outside semiconductor element 20. Groove 64 and groove 65 are entirely located below semiconductor element 20. That is, portion 40 of groove 62 includes part of groove 63, groove 64, and groove 65, and has a U-shape. Portion 42 includes another part of groove 63. One groove 62 has one communication opening 44.

[0068] (Comparative Example 2) 11 is a plan view illustrating a method for manufacturing a semiconductor optical device according to Comparative Example 2, illustrating a step corresponding to FIG. 4A. The silicon layer 16 of the substrate 10 has eight grooves 66. Four of the grooves 66 are provided in the terrace 34a and are aligned in the X-axis direction. Four of the grooves 66 are provided in the terrace 34a and are aligned in the X-axis direction. Each groove 66 has two communication openings 44. The substrate 10 has 16 communication openings.

[0069] Moisture generated during hydrophilic bonding is discharged through the grooves 66. However, the large number of communication holes 44 makes it easy for etchant to penetrate, which may result in etching of the semiconductor element 20 from the bonding interface side.

[0070] According to the third embodiment, one groove 62 has one communication opening 44. The substrate 10 has eight communication openings 44, which is fewer than that of Comparative Example 2. Because the number of communication openings 44 is small, the etchant is less likely to enter the portion 40 of the groove 62. This makes it possible to prevent etching of the semiconductor element 20 from the bonding interface side.

[0071] The substrate 10 has eight grooves 62. Moisture can be discharged from the bonding interface through the eight grooves 62. Four grooves 62a are provided on the terrace 34a. Four grooves 62b are provided on the terrace 34b. Moisture can be discharged and etchant can be prevented from entering both the terrace 34a and the terrace 34b. The number of grooves 62 may be eight or more, or eight or less.

[0072] The planar shape of the groove 62 is U-shaped. Since the groove 62 is arranged over a wide range of the bonding interface, moisture can be easily discharged from the groove 62.

[0073] (Fourth embodiment) Fig. 12A is a plan view illustrating a method for manufacturing a semiconductor optical device according to the fourth embodiment, and illustrates a step corresponding to Fig. 4A. Fig. 12B is a plan view illustrating a substrate 10. Descriptions of the same configurations as those of any of the first to third embodiments will be omitted.

[0074] 12A and 12B, the silicon layer 16 of the substrate 10 has two grooves 70. Of the two grooves 70, groove 70a is provided in terrace 34a. Of the two grooves 70, groove 70b is provided in terrace 34b.

[0075] Groove 70 includes groove 72, groove 73, groove 74, and multiple grooves 75. Groove 72, groove 73, and groove 74 are parallel to the X-axis direction. Groove 75 is parallel to the Y-axis direction. Groove 72 is located closer to the end of semiconductor element 20 than grooves 73 and 74. Groove 74 is located closer to waveguide 30 than grooves 72 and 73. Groove 73 is located between grooves 72 and 74. Groove 75 is connected to grooves 72, 73, and 74.

[0076] 12B, the distance D10 between groove 72 and groove 73 in the Y-axis direction is, for example, 50 μm or less. The distance D11 between groove 73 and groove 74 is, for example, 50 μm or less. The distance D12 between groove 74 and recess 32 is, for example, 50 μm or less. The distance D13 between adjacent grooves 75 in the X-axis direction is, for example, 50 μm or less.

[0077] Groove 75a, one of the multiple grooves 75, extends from a position overlapping with the semiconductor element 20 to outside the semiconductor element 20. Except for groove 75a, the entire multiple grooves 75 are located below the semiconductor element 20. Groove 72, groove 73, and groove 74 are all located below the semiconductor element 20. Portion 40 of groove 70 includes part of groove 75a, the multiple grooves 75, groove 72, groove 73, and groove 74, and has a lattice shape. Portion 42 includes another part of groove 75a. One groove 70 has one communication opening 44.

[0078] According to the fourth embodiment, one groove 70 has one communication opening 44. The substrate 10 has two communication openings 44, which is fewer than that of Comparative Example 2. The etchant is less likely to enter the portion 40 of the groove 70. Etching of the semiconductor element 20 from the bonding interface side can be prevented.

[0079] The substrate 10 has two grooves 70. Groove 70a is provided in terrace 34a. Groove 70b is provided in terrace 34b. The planar shape of the grooves 70 is a lattice shape. Because the grooves 70 are arranged over a wide area of ​​the bonding interface, moisture is easily discharged from the grooves 70. The planar shape of the grooves may be U-shaped, ladder-shaped, or lattice-shaped, or may be other than these.

[0080] Fifth Embodiment 13 is a plan view illustrating a method for manufacturing a semiconductor optical device according to the fifth embodiment, illustrating steps corresponding to those in FIG. 4A. Descriptions of configurations that are the same as those in any of the first to fourth embodiments will be omitted. The length L5 of the semiconductor device 20 in the X-axis direction is, for example, 800 μm. The length L6 of the semiconductor device 20 in the Y-axis direction is smaller than the length L4 in FIG. 4A, and is, for example, 200 μm or less.

[0081] 13, the silicon layer 16 of the substrate 10 has two grooves 76. Of the two grooves 76, groove 76a is provided in terrace 34a. Of the two grooves 76, groove 76b is provided in terrace 34b.

[0082] The groove 76 is linear and parallel to the X-axis direction. The groove 76 extends from a position overlapping the semiconductor element 20 to outside the semiconductor element 20. One end of the groove 76 is located below the semiconductor element 20. The other end is located outside the semiconductor element 20. One groove 76 has one communication opening 44.

[0083] The distance D14 between the groove 76 and the end of the semiconductor element 20 in the Y-axis direction is, for example, 50 μm or less. The distance D15 between the groove 76 and the recess 32 is, for example, 50 μm or less. The distance D16 between the groove 76 and the end of the semiconductor element 20 in the X-axis direction is, for example, 50 μm or less.

[0084] According to the fifth embodiment, one groove 76 has one communication opening 44. The substrate 10 has two communication openings 44. Because the number of communication openings 44 is small, the etchant is less likely to enter the portion 40 of the groove 76. This makes it possible to prevent etching of the semiconductor element 20 from the bonding interface side.

[0085] As in the first to fifth embodiments, the number and shape of the grooves can be changed. Changing the number of grooves, etc., also changes the drainage performance and bonding strength. Increasing the number of grooves improves drainage performance and reduces the area of ​​the bonding interface. The smaller the area of ​​the bonding interface, the lower the bonding strength. The larger the area of ​​the bonding interface, the higher the bonding strength. Reducing the number of grooves reduces drainage performance, increases the bonding area, and increases the bonding strength.

[0086] For example, the number and shape of the grooves are determined according to the size of the semiconductor element 20 during bonding so that the grooves are positioned within 50 μm of any position on the bonding interface. Water can be effectively drained by keeping the water travel distance to the grooves within 50 μm. The larger the semiconductor element 20 in the XY plane, the wider the bonding interface. As in the first to fourth embodiments, the grooves have a U-shape, ladder shape, or lattice shape. Multiple grooves may be provided. This shortens the water travel distance to the grooves. When the semiconductor element 20 is small, the grooves may be linear, as in the fifth embodiment. This achieves both dewatering performance and bonding strength.

[0087] The first to fifth embodiments may be combined. A groove according to any one of the first to fifth embodiments is provided in a portion of the bonding interface that is included in the terrace 34a. Another groove according to any one of the first to fifth embodiments is provided in a portion of the bonding interface that is included in the terrace 34b.

[0088] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure as described in the claims. [Explanation of symbols]

[0089] 10, 12 board 14 Box Layer 16 Silicon Layer 17, 19 sides 18 Chamber 20 Semiconductor elements 21 Mesa 22, 26 Cladding layer 23 Tapered section 24 Active layer 28 Contact layer 29 electrode 30 Waveguide 32 recess 34, 34a, 34b Terrace 36, 36a, 36b, 37, 50, 52, 54, 60, 60a, 60b, 62, 62a, 62b, 63, 64, 65, 66, 70, 70a, 70b, 72, 73, 74, 75, 75a76, 76a, 76b groove 40, 42 parts 44 Connecting port 100 Semiconductor optical element

Claims

1. a substrate having a silicon layer; a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer of the substrate; a groove is provided in the silicon layer; the groove extends from a position overlapping the bonded semiconductor element to an outside of the bonded semiconductor element, and has a communication opening that communicates the portion of the groove overlapping the bonded semiconductor element with a portion outside the bonded semiconductor element, The semiconductor optical element has one communication opening per groove.

2. the silicon layer has a plurality of the grooves; 2. The semiconductor optical device according to claim 1, wherein each of the plurality of grooves has one of the communication openings.

3. the silicon layer has a waveguide; one side of the silicon layer with respect to the waveguide as a reference is defined as a first portion, and a portion opposite to the first portion is defined as a second portion; 3. The semiconductor optical device according to claim 1, wherein at least one groove is provided in each of the first portion and the second portion.

4. 3. The semiconductor optical device according to claim 1, wherein the groove is present within a range of 50 [mu]m from any position on the bonding interface between the substrate and the semiconductor device.

5. 3. The semiconductor optical device according to claim 1, wherein the planar shape of the groove is U-shaped, ladder-shaped or lattice-shaped.

6. 3. The semiconductor optical device according to claim 1, wherein the semiconductor element is in contact with the silicon layer.

7. bonding a semiconductor element formed of a III-V compound semiconductor to a silicon layer of a substrate by hydrophilic bonding; and wet etching the bonded semiconductor element, the silicon layer has a groove; the groove extends from a position overlapping the bonded semiconductor element to an outside of the bonded semiconductor element, and has a communication opening that communicates the portion of the groove overlapping the bonded semiconductor element with a portion outside the bonded semiconductor element, A method for manufacturing a semiconductor optical device, wherein one of the grooves has one communication opening.

8. a step of forming a mask before the step of performing the wet etching; the mask is embedded in a portion of the groove outside the bonded semiconductor element; The communication port is blocked by the mask, 8. The method for manufacturing a semiconductor optical device according to claim 7, wherein in the step of performing wet etching, a portion of the semiconductor device exposed from the mask is wet etched.

9. 9. The method for manufacturing a semiconductor optical device according to claim 7, wherein after the bonding step, the grooves are present within a range of 50 [mu]m from any position on the bonding interface between the substrate and the semiconductor device.

10. 9. The method for manufacturing a semiconductor optical device according to claim 7, wherein the bonding step is carried out at a temperature higher than room temperature and at a pressure lower than atmospheric pressure.

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