Inverter device

Abstract

To reduce the self-inductance of an inverter device.SOLUTION: An inverter device 1 includes: a wiring board including a first wiring layer and a second wiring layer; and a plurality of transistors Q arranged in an intermediate layer and having a source provided on one surface and a drain provided on the other surface. The plurality of transistors Q include: a first transistor disposed with one surface facing the first wiring layer; and a second transistor disposed with the other surface facing the first wiring layer. A source of the first transistor and a drain of the second transistor are connected with each other through a first wire in the first wiring layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed herein belongs to the technical field of inverter devices. [Background technology]

[0002] As the power density of inverter devices increases, higher output power is being achieved, and there is a demand for technology to reduce the inductance of inverter devices.

[0003] Patent Document 1 discloses a technology for reducing wiring inductance in a DC-AC inverter by placing two wiring conductors close to each other and parallel to each other, and passing currents in different directions through each of them, thereby using mutual inductance to reduce wiring inductance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-259656 Summary of the Invention [Problem to be solved by the invention]

[0005] Conventional inverter devices are configured by mounting transistors on the surface of a substrate, but when the transistors are mounted on the surface of the substrate, there is a problem in that self-inductance cannot be sufficiently reduced due to the influence of bonding wires connecting the transistors to the substrate.

[0006] The technique disclosed herein has been made in view of the above points, and aims to provide an inverter device with reduced inductance. [Means for solving the problem]

[0007] In order to solve the above problem, the technology disclosed herein is directed to an inverter device, and includes a wiring substrate having a first wiring layer and a second wiring layer, and a plurality of transistors arranged side by side on an intermediate layer between the first wiring layer and the second wiring layer, each having a source on one side and a drain on the other side, the plurality of transistors including a first transistor arranged with the one side facing the first wiring layer and a second transistor arranged with the other side facing the first wiring layer, and the source of the first transistor and the drain of the second transistor are connected by a first wiring of the first wiring layer.

[0008] In this way, by arranging one side of the first transistor and the other side of the second transistor facing each other on the first wiring layer, i.e., by arranging the first transistor and the second transistor facing in opposite directions, the first wiring connecting the source of the first transistor and the drain of the second transistor can be made short and wide, thereby reducing wiring inductance.

[0009] Furthermore, since the first wiring can be made wider, the number of vias connecting the source of the first transistor and the drain of the second transistor to the first wiring can be increased, thereby reducing the effect of self-inductance caused by the vias. [Effects of the Invention]

[0010] As described above, according to the technique disclosed herein, the inductance of the inverter device can be reduced. [Brief explanation of the drawings]

[0011] [Figure 1] Inverter device circuit diagram [Figure 2] FIG. 1 is a cross-sectional side view showing an example of the configuration of an inverter device; [Figure 3] Plan view of the inverter device seen from above the second wiring layer [Figure 4] Bottom view of the inverter device seen from below the fifth wiring layer [Figure 5] FIG. 1 is a diagram for explaining a current flow in an inverter device according to an embodiment. [Figure 6] FIG. 10 is a diagram for explaining a current flow in an inverter device according to a comparative example. [Figure 7] 2 showing another example of the configuration of the inverter device; DETAILED DESCRIPTION OF THE INVENTION

[0012] Exemplary embodiments will be described in detail below with reference to the drawings. Note that the following description of the embodiments is essentially merely illustrative and will focus on configurations related to the subject matter of the disclosed technology. Furthermore, technical elements that are not related to the subject matter of the disclosed technology may be illustrated or described in a simplified manner or omitted from the description, but this is not intended to limit the scope of the disclosed technology. In this disclosure, the term "connection" is used as a concept that broadly encompasses electrical connection. For example, the term "connection" includes not only direct connection between elements, but also indirect connection between elements via vias or the like.

[0013] Fig. 1 is a circuit diagram of an inverter device 1 according to an embodiment. Fig. 2 is a side cross-sectional view (for example, a cross-sectional view taken along line II-II in Fig. 3) showing the configuration of the inverter device 1.

[0014] 1, in this example, the inverter device 1 is a three-level inverter that outputs three-phase (U-phase, V-phase, W-phase) AC from a DC power supply such as a battery (not shown). The use of the inverter device 1 is not particularly limited, but it is used, for example, for driving automobiles and starting engines (for example, ISG: Integrated Starter Generator).

[0015] 1 and 2, the inverter device 1 includes a wiring board 2 and three-phase (U-phase, V-phase, and W-phase) inverter circuits 3 mounted on the wiring board 2. Each inverter circuit 3 includes transistors Q1 to Q6, a first capacitor C1, and a second capacitor C2. In the following description, when the transistors Q1 to Q6 are not distinguished from one another, they may be referred to as "transistor Q."

[0016] -Wiring board- The wiring board 2 is, for example, a multilayer wiring board (e.g., a printed circuit board) having six wiring layers. For convenience of explanation, as shown in FIG. 2, the thickness direction of the wiring board 2 is defined as the up-down direction, and the wiring layer (first wiring layer) on the main surface (top surface) on which the first capacitor C1 and the second capacitor C2 are arranged is referred to as wiring layer L1. Then, wiring layers L2 to L6 (second to sixth wiring layers) are formed in this order downward from the wiring layer L1, with insulating layers (e.g., layers formed of resin) sandwiched between them. From the viewpoint of improving heat dissipation performance, the insulating layer between the wiring layer L5 and the wiring layer L6 is preferably made of glass epoxy resin or highly thermally conductive resin.

[0017] -capacity- The first capacitor C1 is provided between a first power supply wiring 11 to which a positive power supply voltage P(+) is supplied from a battery (not shown) or the like, and a ground wiring GND connected to the ground. The second capacitor C2 is provided between the ground wiring GND and a second power supply wiring 12 to which a negative power supply voltage N(-) is supplied from a battery (not shown) or the like.

[0018] -Transistor- FIG. 3 is a plan view of the inverter device 1 as viewed from above the wiring layer L2, and FIG. 4 is a bottom view of the inverter device 1 as viewed from below the wiring layer L5. In FIGS. 3 and 4, the positions of the transistors Q1 to Q6 are indicated by dashed lines. As shown in FIGS. 3 and 4, the X and Y directions are defined as directions that are orthogonal to the up-down direction and perpendicular to each other. In the X directions, the leftward direction in FIG. 3 is referred to as the X1 direction, and the rightward direction in FIG. 3 is referred to as the X2 direction. In the Y directions, the upward direction in FIG. 3 is referred to as the Y1 direction, and the downward direction in FIG. 3 is referred to as the Y2 direction. The X direction corresponds to the first direction, and the Y direction corresponds to the second direction.

[0019] As shown in FIGS. 2 to 4, the three-phase transistors Q1 to Q6 are arranged in an intermediate layer between the wiring layer L2 and the wiring layer L5. In this example, the wiring layer L3, the wiring layer L4, and the insulating layer X3 between L3 and L4 correspond to the "intermediate layer." The three-phase transistors Q1 to Q6 are arranged in the XY direction on the intermediate layer in a plan view. More specifically, the transistors Q1 to Q6 for each phase are arranged in the X2 direction on the intermediate layer in the order Q1, Q2, Q3, Q5, Q4, and Q6. Furthermore, a set of U-phase transistors Q1 to Q6, a set of V-phase transistors Q1 to Q6, and a set of W-phase transistors Q1 to Q6 are arranged in the Y2 direction in the order of U-phase, V-phase, and W-phase. That is, in the inverter circuit 3 for each phase, the transistors Q1 to Q6 are arranged linearly in the X direction in a plan view. Moreover, the three-phase (U-phase, V-phase, W-phase) inverter circuits 3 are arranged side by side in the Y direction in plan view.

[0020] The transistor Q is an N-type power MOSFET with a vertical structure, and in this example, it is composed of a semiconductor chip Qa (simply referred to as "chip" in the drawings) and a lead frame Qb. The semiconductor chip Qa has a source on one side and a drain on the other side. The lead frame Qb is made of copper, for example, and is configured to be U-shaped in cross-sectional side view (see Figure 2) so as to cover the other side (drain) of the semiconductor chip Qa, and is connected to the drain of the semiconductor chip Qa. In other words, the lead frame Qb and the drain of the semiconductor chip Qa are at the same potential.

[0021] In other words, the transistor Q has a source region S and a drain region D surrounding the source region S on one surface, and a drain region D on the other surface. In the following description, the one surface is referred to as the "source-drain surface," and the other surface is referred to as the "drain surface." Note that the "one surface (source-drain surface)" and the "other surface (drain surface)" mentioned here are not limited to flat surfaces. Specifically, for example, as shown in FIG. 7 (described later), in the source-drain surface, there may be a step (a vertical step in FIG. 7) between the surface on which the source is provided and the surface on which the drain is provided. For example, the surface on which the source is provided and / or the surface on which the drain is provided may be partially bulged or recessed. Furthermore, although not shown because it is not the subject of the disclosed technology, the gate of the transistor Q is formed in the source-drain surface of the semiconductor chip Qa.

[0022] The source or drain of the transistor Q is connected to each of the wirings formed in the wiring layers L2 and L5 via multiple vias V and lead frames Qb. However, in the following description, for the sake of convenience, the description of the connection via the vias V and lead frames Qb may be omitted. The same applies to the connection between the wirings in each wiring layer, and the illustration and / or description of the connection via the vias V and lead frames Qb may be omitted. Also, in FIG. 2, to make the drawing easier to understand, wirings to which a common signal or voltage is applied are commonly hatched. In other words, in FIG. 2, the wirings that are commonly hatched are connected to each other via vias or the like (including those not shown).

[0023] The transistors Q1 to Q6 are each described below. The configuration of the transistors Q1 to Q6 is common to the U-phase, V-phase, and W-phase, and only one phase will be described here.

[0024] 2, the transistor Q1 is disposed so that its source-drain surface faces the wiring layer L5 and its drain surface faces the wiring layer L2. That is, the transistor Q1 is disposed so that its drain surface faces upward. In the transistor Q1, the source terminal (hereinafter simply referred to as "source") is connected to the wiring 21 of the wiring layer L5, and the drain terminal (hereinafter simply referred to as "drain") of the drain surface is connected to the first power supply wiring 11 of the wiring layer L2.

[0025] The transistor Q2 is arranged with its drain surface facing the wiring layer L5 and its source-drain surface facing the wiring layer L2. That is, the transistor Q2 is arranged with its source-drain surface facing upward. The source of the transistor Q2 is connected to the ground wiring GND of the wiring layer L2, and the drain of the drain surface is connected to the wiring 21 of the wiring layer L5.

[0026] The transistor Q3 is arranged with its source-drain surface facing the wiring layer L5 and its drain surface facing the wiring layer L2. That is, the transistor Q3 is arranged with its drain surface facing upward. The source of the transistor Q3 is connected to the output wiring OUT of the wiring layer L5, and the drain on the X1 direction side of the source-drain surface (on the transistor Q2 side) is connected to the wiring 21 of the wiring layer L5.

[0027] The transistor Q5 is arranged with its source-drain surface facing the wiring layer L5 and its drain surface facing the wiring layer L2. That is, the transistor Q5 is arranged with its drain surface facing upward. The source of the transistor Q5 is connected to the wiring 22 of the wiring layer L5, and the drain on the X1 direction side of the source-drain surface (on the transistor Q3 side) is connected to the output wiring OUT of the wiring layer L5.

[0028] The transistor Q4 is arranged with its source-drain surface facing the wiring layer L5 and its drain surface facing the wiring layer L2. That is, the transistor Q4 is arranged so that its drain surface faces upward. The source of the transistor Q4 is connected to the wiring 22 of the wiring layer L5, and the drain of the drain surface is connected to the ground wiring GND of the wiring layer L2.

[0029] The transistor Q6 is arranged with its drain surface facing the wiring layer L5 and its source-drain surface facing the wiring layer L2. That is, the transistor Q6 is arranged with its source-drain surface facing upward. The source of the transistor Q6 is connected to the second power supply wiring 12 of the wiring layer L2, and the drain of the drain surface is connected to the wiring 22 of the wiring layer L5.

[0030] -wiring- The first power supply wiring 11 is connected to the terminal C11 of the first capacitor C1 in the wiring layer L1. As described above, the first power supply wiring 11 in the wiring layer L2 is connected to the drain of the transistor Q1. That is, the first power supply wiring 11 is a wiring formed in the wiring layer L1 and the wiring layer L2. As shown in FIG. 3, in the wiring layer L2, the wiring length is d11 and the wiring width is w1. The wiring width w1 is not particularly limited, but is set, for example, to be equal to or greater than the width of the U-phase, V-phase, and W-phase transistors Q1 arranged in the Y direction. The wiring length d11 is not particularly limited, but is set, for example, to be equal to or greater than the length of the transistor Q1 in the X direction. In this example, the wiring length d11 is longer than the length of the transistor Q1 in the X direction. Although not shown, the wiring layer L1 is formed so as to cover the wiring in the wiring layer L2 in a plan view. The first power supply wiring 11 of the wiring layer L1 has a wiring length that is longer than d11 in the X2 direction in order to generate a current in the X2 direction in the wiring layer L1 (see FIG. 2). The width of the first power supply wiring 11 of the wiring layer L1 is w1. The wiring width of the first power supply wiring 11 may differ between the wiring layers L1 and L2.

[0031] The second power supply wiring 12 is connected to the terminal C21 of the second capacitor C2 in the wiring layer L1. As described above, the second power supply wiring 12 in the wiring layer L2 is connected to the source of the transistor Q6. That is, the second power supply wiring 12 is a wiring formed in the wiring layer L1 and the wiring layer L2. As shown in FIG. 3, in the wiring layer L2, the wiring length is d12 and the wiring width is w1. The wiring length d12 is not particularly limited, but is set to, for example, equal to or greater than the length of the transistor Q6 in the X direction. In this example, the wiring length d12 is longer than the length of the transistor Q6 in the X direction. Although not shown, in the wiring layer L1, the second power supply wiring 12 is formed so as to cover the wiring in the wiring layer L2 in a planar view. In order to generate a current in the X1 direction in the wiring layer L1, the second power supply wiring 12 in the wiring layer L1 has a wiring length that is longer than d12 in the X1 direction (see FIG. 2). The width of the first power supply wiring 11 in the wiring layer L1 is w1. The wiring width of the second power supply wiring 12 may be different between the wiring layer L1 and the wiring layer L2.

[0032] The ground wiring GND is connected to the terminal C12 of the first capacitor C1 and the terminal C22 of the second capacitor C2 in the wiring layer L1. As described above, the ground wiring GND in the wiring layer L2 is connected to the source of the transistor Q2 and the drain of the transistor Q4. The ground wiring GND is mainly formed in the wiring layers L1 and L2. As shown in FIG. 3, the ground wiring GND has a length d13 and a width w1 in the wiring layer L2. The length d13 of the ground wiring GND is not particularly limited, but may extend, for example, from a position in the X1 direction beyond the X1-direction end of the transistor Q2 to a position in the X2 direction beyond the X2-direction end of the transistor Q4. That is, in the plan view of FIG. 3, the ground wiring GND is formed so as to cover the transistors Q2, Q3, Q5, and Q4. The length of the ground wiring GND in the wiring layer L1 is shorter than d13, and the wiring width is w1. The width of the ground wiring GND may differ between the wiring layers L1 and L2. Furthermore, a ground wiring GND may be provided in the wiring layer L3 and / or the wiring layer L4.

[0033] The wiring 21 is formed in the wiring layer L5 and the wiring layer L6 and extends, for example, from the end of the transistor Q1 in the X1 direction to the drain region D (the region where the drain is provided) on the X1 side (transistor Q2 side) of the source-drain plane of the transistor Q3. The wiring 21 connects the source of the transistor Q1, the drain of the transistor Q2, and the drain of the transistor Q3 to one another. As shown in FIG. 4, in the wiring layer L5, the wiring 21 has a length d21 and a width w2. Note that the wiring length d21 is not limited to the length shown in FIG. 4. For example, the length of the wiring 21 in the X1 direction may be longer than that shown in FIG. 4 or may be shortened to the middle of the transistor Q1. However, from the viewpoint of reducing the influence of the inductance of the via V connecting the transistor Q1 and the wiring 21, it is preferable to increase the area where the wiring 21 overlaps with the source of the transistor Q1, the drain of the transistor Q2, and the drain of the transistor Q3 in a plan view.

[0034] The output wiring OUT is a wiring formed in wiring layers L5 and L6, and extends, for example, from the end of the source of transistor Q3 in the X1 direction to the drain region D on the X1 side (transistor Q3 side) of the source-drain plane of transistor Q5. The output wiring OUT connects the source of transistor Q3 and the drain of transistor Q4 to each other. The output of each phase of inverter device 1 is output from the output wiring OUT.

[0035] The wiring 22 is formed in the wiring layer L5 and the wiring layer L6 and extends, for example, from the X1 end of the source region S (region where the source is provided) of the transistor Q5 to the X2 end of the transistor Q6. The wiring 22 connects the source of the transistor Q5, the source of the transistor Q4, and the drain of the transistor Q6 to one another. As shown in FIG. 4, the length of the wiring 22 is d22 and the width of the wiring 22 is w2. Note that the length d22 of the wiring 22 is not limited to the length shown in FIG. 4. For example, the length of the wiring 22 in the X2 direction may be longer than that shown in FIG. 4 or may be shortened to the middle of the transistor Q6. However, from the viewpoint of reducing the influence of the inductance of the via V connecting the transistor Q6 and the wiring 22, it is preferable to increase the area where the wiring 22 overlaps with the source of the transistor Q5, the source of the transistor Q4, and the drain of the transistor Q6 in a plan view.

[0036] Although not shown in the figure, the size and shape of the wiring 21 in the wiring layer L5 and the wiring layer L6 in a plan view are the same, and the wiring 21 in the wiring layer L5 and the wiring 21 in the wiring layer L6 are connected to each other through vias V. The same applies to the output wiring OUT and the wiring 22.

[0037] -Effects of the embodiment- As described above, the inverter device 1 of the above embodiment includes a wiring substrate 2 having a first wiring layer and a second wiring layer, and a plurality of transistors Q each having a source on one surface (source-drain surface) and a drain on the other surface (drain surface). The plurality of transistors Q are arranged side by side in an intermediate layer between the first wiring layer and the second wiring layer of the wiring substrate 2. The plurality of transistors Q includes a first transistor arranged with one surface facing the first wiring layer and a second transistor arranged with the other surface facing the first wiring layer, and the source of the first transistor and the drain of the second transistor are connected by a first wire in the first wiring layer.

[0038] Specifically, for example, in the above embodiment, when viewed in terms of the relationship between transistors Q1 and Q2 and wiring layer L5, transistor Q1 is arranged with its source-drain surface facing wiring layer L5, and transistor Q2 is arranged with its drain surface facing wiring layer L5. The source of transistor Q1 and the drain of transistor Q2 are connected by wiring 21 in wiring layer L5. In this case, transistor Q1 corresponds to the first transistor, transistor Q2 corresponds to the second transistor, wiring layer L5 corresponds to the first wiring layer, and wiring 21 corresponds to the first wiring.

[0039] In this way, by staggering the opposing surfaces of transistor Q1 and transistor Q2 with respect to wiring layer L5, the wiring 21 between the source of transistor Q1 and the drain of transistor Q2 can be made short and wide. As shown in the following approximate formula, the wiring inductance of wiring substrate 2 is proportional to the wiring length L and inversely proportional to the wiring width W. In other words, by using the configuration of this embodiment, the wiring inductance can be reduced. In the formula below, H is the thickness of the wiring (e.g., copper foil) formed in the wiring layer.

[0040]

number

[0041] Furthermore, since the width of the wiring 21 can be increased, it is possible to increase the number of vias that connect the transistors Q1 and Q2 to the wiring 21. This reduces the influence of self-inductance due to the connection through the vias.

[0042] Similarly, in the above embodiment, when viewed in terms of the relationship between transistors Q4 and Q6 and wiring layer L5, transistor Q4 is arranged with its source-drain surface facing wiring layer L5, and transistor Q6 is arranged with its drain surface facing wiring layer L5. The source of transistor Q4 and the drain of transistor Q6 are connected by wiring 22 on wiring layer L5. In this case, transistor Q4 corresponds to the first transistor, transistor Q6 corresponds to the second transistor, wiring layer L5 corresponds to the first wiring layer, and wiring 22 corresponds to the first wiring. This provides the same effect as in the relationship between transistors Q1 and Q2 and wiring layer L5 described above.

[0043] Furthermore, in terms of the relationship between transistors Q4, Q5, and Q6 and wiring layer L5, transistor Q5 is arranged so that its source-drain surface faces wiring layer L5. Furthermore, transistors Q4, Q5, and Q6 are arranged in a straight line. This allows the wiring 22 connecting the source of transistor Q5, the drain of transistor Q6, and the source of transistor Q4 to be short and wide. In this case, transistor Q5 corresponds to the third transistor.

[0044] In order to reduce self-inductance, it is important to use wiring that does not use vias as current paths. Regarding this point, for example, in the above embodiment, when considering the relationship between transistors Q2 and Q4 and the wiring layer L2, transistor Q2 is arranged with its source-drain surface facing the wiring layer L2, and transistor Q4 is arranged with its drain surface facing the wiring layer L2. The source of transistor Q2 and the drain of transistor Q4 are connected by the ground wiring GND of the wiring layer L2. The wiring for transistors Q3 and Q5, which are arranged between transistors Q2 and Q4, uses wiring layer L5.

[0045] In this way, by staggering the opposing surfaces of transistors Q2 and Q4 with respect to the wiring layer L2, the ground wiring connected to the source of transistor Q2 and the drain of transistor Q4 in the same wiring layer can be made wide by making maximum use of the width of the wiring board 2 in the Y direction. This point will be explained in detail with reference to the drawings. FIG. 6 shows an example in which the source-drain surfaces of transistors Q1 to Q6 are embedded in the wiring board 2 with their source-drain surfaces facing upward. Since the output wiring OUT is connected to the source of transistor Q3 and the drain of transistor Q5, in this example, the output wiring OUT must be provided in the wiring layer L2. Therefore, if the ground wiring connected to the source of transistor Q2 and the drain of transistor Q4 is formed in the same wiring layer, a detour path must be set as shown in FIG. 6. Alternatively, a different wiring layer (e.g., L6) must be used. As a result, compared to the configuration of this embodiment, a sufficient self-inductance reduction effect cannot be obtained.

[0046] In the above embodiment, the transistors Q1, Q2, Q3, Q5, Q4, and Q6 are arranged in the above-described order on the intermediate layer of the wiring substrate 2 in the X2 direction.

[0047] This allows the current paths flowing between the source and drain of each transistor Q to be wired in parallel, thereby achieving low inductance through differential connection. Furthermore, the configuration of this embodiment achieves parallel wiring and a wide parallel current path. This point will be explained with reference to FIGS. 5 and 6.

[0048] 5 shows a configuration in which the diagrams corresponding to FIGS. 3, 2, and 4 for one phase of this embodiment are arranged one above the other, and the direction of current flow is indicated by a hollow arrow in the middle cross-sectional side view. As indicated by the bidirectional arrows in FIG. 5, the current flowing through the wiring in wiring layer L2 and the current flowing through the wiring in wiring layer L5 are opposite in direction. This results in a differential connection, and the mutual inductance is subtracted from the self-inductance, thereby reducing the value of the combined inductance.

[0049] In contrast, in the comparative example shown in Figure 6, in wiring layer L2, currents flow in opposite directions between the ground wiring and the wiring laid between them. However, because the wiring is loop wiring and not parallel wiring between wiring layers, the cross-sectional area contributing to inductance reduction is narrow, and the effect of reducing the combined inductance value by differential connection is limited. Furthermore, in the configuration of Figure 6, the number of vias between the drain and wiring is reduced compared to this embodiment, resulting in increased self-inductance. In contrast, in this embodiment, for example, in transistors Q1, Q2, Q4, and Q6, vias V can be provided over the entire drain surface, thereby reducing self-inductance.

[0050] As described above, the inverter device 1 of this embodiment includes the wiring board 2 having the wiring layer L5 and the wiring layer L2, and a plurality of transistors Q each having a source on one surface (source-drain surface) and a drain on the other surface (drain surface). The plurality of transistors Q includes transistors Q1 to Q6 arranged side by side on an intermediate layer between the wiring layer L5 and the wiring layer L2 of the wiring board 2. The source-drain surface of the transistor Q1 is arranged opposite the wiring layer L5, the drain on the drain surface is connected to the first power supply wiring 11 of the wiring layer L2, and the source on the source-drain surface is connected to the wiring 21 of the wiring layer L5. The drain surface of the transistor Q2 is arranged opposite the wiring layer L5, the source on the source-drain surface is connected to the ground wiring GND of the wiring layer L2, and the drain on the drain surface is connected to the wiring 21 of the wiring layer L5. The transistor Q3 is disposed with its source-drain surface facing the wiring layer L5, its source connected to the output wiring OUT of the wiring layer L5, and its drain connected to the wiring 21 of the wiring layer L5. The transistor Q5 is disposed with its source-drain surface facing the wiring layer L5, its source connected to the wiring 22 of the wiring layer L5, and its drain connected to the output wiring OUT of the wiring layer L5. The transistor Q4 is disposed with its source-drain surface facing the wiring layer L5, its source connected to the wiring 22 of the wiring layer L5, and its drain connected to the ground wiring GND of the wiring layer L2. The transistor Q6 is disposed with its drain surface facing the wiring layer L5, its drain connected to the wiring 22 of the wiring layer L5, and its source connected to the second power supply wiring 12 of the wiring layer L2. In this case, transistor Q1 corresponds to the first transistor, transistor Q2 corresponds to the second transistor, transistor Q3 corresponds to the third transistor, transistor Q5 corresponds to the fourth transistor, transistor Q4 corresponds to the fifth transistor, and transistor Q6 corresponds to the sixth transistor. Also, wiring layer L5 corresponds to the first wiring layer, wiring layer L2 corresponds to the second wiring layer, wiring 21 corresponds to the first wiring, ground wiring GND corresponds to the second wiring, and wiring 22 corresponds to the third wiring.

[0051] With this configuration, as described above, the wiring 21 between the source and drain of the transistor Q1 and the transistor Q2 and the wiring 21 between the source and drain of the transistor Q4 and the transistor Q6 can be made shorter and wider, thereby reducing the wiring inductance of the inverter device 1.

[0052] Furthermore, in the above embodiment, the inverter device 1 includes three-phase (U-phase, V-phase, and W-phase) inverter circuits 3 each including transistors Q1 to Q6. As shown in Fig. 3, the transistors Q1 to Q6 of each phase are linearly arranged in the X direction in plan view. The U-phase, V-phase, and W-phase inverter circuits 3 are also arranged in the Y direction in the order shown in plan view, with the ground wirings GND connected to each other in the wiring layer L2.

[0053] By sharing the ground wiring in this way, the wiring inductance can be further reduced. Also, a current path is formed between the phases of the inverter circuit 3, connecting the grounds of the phases to each other, so the inductance of the inverter device 1 is further reduced.

[0054] <Other embodiments> As mentioned above, the above embodiments are merely examples and should not be interpreted as limiting the scope of the present disclosure. The scope of the present disclosure is defined by the claims, and all modifications and variations that fall within the scope of the claims equivalents are within the scope of the present disclosure.

[0055] For example, the technology of the present disclosure can be applied to inverter devices having circuit configurations other than those shown in Fig. 1. For example, in the above embodiment, the transistors Q2 and Q4 may be replaced with diodes (not shown).

[0056] In this case, the diode (first diode) replacing the transistor Q2 has its cathode connected to the wiring 21 of the wiring layer L5 and its anode connected to the ground wiring GND of the wiring layer L2. Similarly, the diode (second diode) replacing the transistor Q4 has its cathode connected to the ground wiring GND of the wiring layer L2 and its anode connected to the wiring 22 of the wiring layer L2.

[0057] In the above configuration using the first and second diodes, for example, when viewed in terms of the relationship between transistors Q5 and Q6 and wiring layer L5, transistor Q5 is arranged with its source-drain surface facing wiring layer L5, and transistor Q6 is arranged with its drain surface facing wiring layer L5. The source of transistor Q5 and the drain of transistor Q6 are connected by wiring 22 on wiring layer L5. In this case, transistor Q5 corresponds to the first transistor, transistor Q6 corresponds to the second transistor, wiring layer L5 corresponds to the first wiring layer, and wiring 22 corresponds to the first wiring. This allows wiring 21 between the source and drain of transistor Q5 and transistor Q6 to be short and wide, thereby reducing wiring inductance.

[0058] In the above embodiment, the transistor Q includes a lead frame Qb that is U-shaped in cross-sectional side view as shown in Fig. 2, but this is not limiting. For example, as shown in Fig. 7, the lead frame Qb may have a rectangular shape in cross-sectional side view that is longer on both sides in the X direction than the semiconductor chip Qa. In this case, the width in the Y direction may be wider than both sides in the Y direction, as in the above embodiment, or may be the same width as the semiconductor chip Qa.

[0059] In the configuration of FIG. 7, for example, the drain (lead frame Qb) of the drain-source surface of transistor Q3 is connected to wire 21 of wiring layer L5 through a via V. Similarly, the drain (lead frame Qb) of the drain-source surface of transistor Q5 is connected to output wire OUT of wiring layer L5 through a via V. The rest of the configuration is the same as in FIG. 2. The configuration of FIG. 7 also provides the same effects as the above-described embodiment. Specifically, for example, wire 21 and wire 22 can be made shorter and wider, thereby reducing wiring inductance. [Industrial Applicability]

[0060] The technique disclosed herein is extremely useful because it can reduce the self-inductance of an inverter device. [Explanation of symbols]

[0061] 1. Inverter device 21 Wiring (1st wiring) 22 Wiring (1st wiring, 3rd wiring) GND Ground wiring (second wiring) Q transistor Q1 transistor (first transistor) Q2 transistor (second transistor) Q3 transistor (third transistor) Q4 transistor (5th transistor, 1st transistor) Q5 Transistor (4th Transistor, 3rd Transistor, 1st Transistor) Q6 transistor (sixth transistor, second transistor) L2 wiring layer (2nd wiring layer) L5 wiring layer (1st wiring layer)

Claims

1. a wiring substrate having a first wiring layer and a second wiring layer; a plurality of transistors arranged side by side in an intermediate layer between the first wiring layer and the second wiring layer, each having a source on one side and a drain on the other side; the plurality of transistors include a first transistor arranged with the one surface facing the first wiring layer and a second transistor arranged with the other surface facing the first wiring layer, an inverter device, wherein the source of the first transistor and the drain of the second transistor are connected by a first wiring in the first wiring layer;

2. 2. The inverter device according to claim 1, the plurality of transistors include a third transistor arranged with the one surface facing the first wiring layer, an inverter device, wherein the source of the first transistor and the drain of the second transistor are connected to the source of the third transistor by the first wiring;

3. 3. The inverter device according to claim 2, The inverter device, wherein the first transistor, the second transistor, and the third transistor are arranged linearly in a plan view.

4. a wiring substrate having a first wiring layer and a second wiring layer; a plurality of transistors arranged side by side in an intermediate layer between the first wiring layer and the second wiring layer, each transistor having a source and a drain surrounding the source on one side and a drain on the other side; The plurality of transistors include: a first transistor, the one surface of which is disposed opposite the first wiring layer and the source of which is connected to a first wiring of the first wiring layer; a second transistor, the other surface of which is disposed opposite to the first wiring layer, the source of which is connected to a second wiring of the second wiring layer, and the drain of which is connected to the first wiring; a third transistor, the one surface of which is disposed opposite the first wiring layer, the source of which is connected to an output wiring of the first wiring layer, and the drain of which is connected to the first wiring; a fourth transistor, the one surface of which is disposed opposite the first wiring layer, the source of which is connected to a third wiring of the first wiring layer, and the drain of which is connected to the output wiring; a fifth transistor, the one surface of which is disposed opposite the first wiring layer, the source of which is connected to the third wiring, and the drain of which is connected to the second wiring; a sixth transistor, the other surface of which is arranged opposite to the first wiring layer and the drain of which is connected to the third wiring.

5. 5. The inverter device according to claim 4, the inverter device includes three-phase inverter circuits each including the plurality of transistors, In each of the inverter circuits, the plurality of transistors are arranged linearly in a first direction in a plan view, The three-phase inverter circuits are arranged side by side in a second direction perpendicular to the first direction in a plan view, and the second wirings are connected to each other in the second wiring layer.

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