Inverter device

Abstract

To reduce the self-inductance of an inverter device.SOLUTION: An inverter device 1 includes: a wiring board 2 where a wiring layer L1 is formed on a surface; transistors Q1 to Q6 incorporated in the wiring board 2; a first capacitor C1 provided between a first power source wire 11 in the wiring layer L1 and a ground wire GND; and a second capacitor C2 provided between the ground wire GND in the wiring layer L1 and a second power source wire 12. In the wiring layer L1, the ground wire GND is provided between the first power source wire 11 provided at a position overlapping with the transistor Q1 and the second power source wire 12 provided at a position overlapping with the fourth transistor in a plan view.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed herein belongs to the technical field of inverter devices. [Background technology]

[0002] As the power density of inverter devices increases, higher output power is being achieved, and there is a demand for technology to reduce the inductance of inverter devices.

[0003] Patent Document 1 discloses a technology for reducing wiring inductance in a DC-AC inverter by placing two wiring conductors close to each other and parallel to each other, and passing currents in different directions through each of them, thereby using mutual inductance to reduce wiring inductance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-259656 Summary of the Invention [Problem to be solved by the invention]

[0005] Conventional inverter devices are configured by mounting transistors on the surface of a wiring board, but when the transistors are mounted on the surface of the wiring board, there is a problem in that self-inductance cannot be sufficiently reduced due to the influence of bonding wires connecting the transistors to the wiring board.

[0006] The technique disclosed herein has been made in view of the above points, and aims to reduce the inductance of the inverter device. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems, the technology disclosed herein is directed to an inverter device, and includes a wiring substrate having a first wiring layer formed on its surface, a plurality of transistors built into the wiring substrate, a first capacitor provided between a first power supply wiring and a ground wiring of the first wiring layer, and a second capacitor provided between the ground wiring and a second power supply wiring of the first wiring layer, wherein the plurality of transistors include a first transistor having a drain connected to the first power supply wiring and a source connected to the first wiring, and a second transistor arranged in a first direction perpendicular to the thickness direction of the wiring substrate of the first transistor, and having a drain connected to a second wiring and a source connected to the second power supply wiring, and the first wiring layer has the ground wiring between the first power supply wiring and the second power supply wiring and the second transistor, and the ground wiring is provided in the first wiring layer between the first power supply wiring and the second power supply wiring and the second transistor, in a planar view.

[0008] This configuration allows the wiring between the first power supply wiring and the ground wiring of the inverter device and the wiring between the second power supply wiring and the ground wiring to be shortened, thereby reducing the inductance of the inverter device. Furthermore, since the terminals of the first capacitor and the second capacitor on the ground wiring side can be arranged close to each other, the first capacitor and the second capacitor can be consolidated and arranged efficiently, thereby achieving a compact inverter device. [Effects of the Invention]

[0009] As described above, according to the technique disclosed herein, the inductance of the inverter device can be reduced. [Brief explanation of the drawings]

[0010] [Figure 1] Inverter device circuit diagram [Figure 2] Plan view of inverter device [Figure 3] A plan view of one phase of the inverter device, seen from above the second wiring layer [Figure 4]Bottom view of one phase of the inverter device, seen from below the fifth wiring layer [Figure 5] Cross section of line VV in Figure 3 [Figure 6] Cross section of Figure 3 taken along line VI-VI [Figure 7] FIG. 10 is a diagram illustrating the area reduction effect of the inverter device according to the present embodiment. [Figure 8] A diagram to explain the effect of using common wiring for the three-phase ground wiring [Figure 9] A diagram to explain the effect of using a common wiring for the three-phase ground wiring [Figure 10] 5A and 5B are cross-sectional side views showing other configuration examples of the inverter device; [Figure 11] 6A and 6B are cross-sectional side views showing other configuration examples of the inverter device; DETAILED DESCRIPTION OF THE INVENTION

[0011] Exemplary embodiments will be described in detail below with reference to the drawings. Note that the following description of the embodiments is essentially merely illustrative and will focus on configurations related to the subject matter of the disclosed technology. Furthermore, technical elements that are not related to the subject matter of the disclosed technology may be illustrated or described in a simplified manner or omitted from the description, but this is not intended to limit the scope of the disclosed technology. In this disclosure, the term "connection" is used as a concept that broadly encompasses electrical connection. For example, the term "connection" includes not only direct connection between elements, but also indirect connection between elements via vias or the like.

[0012] Fig. 1 is a circuit diagram of an inverter device 1 according to an embodiment. Fig. 2 is a plan view of the inverter device 1, showing the wiring of the wiring layer L2 as the wiring layer. In other words, the wiring layer L1 is omitted.

[0013] 1, in this example, the inverter device 1 is a three-level inverter that outputs three-phase (U-phase, V-phase, W-phase) AC from a DC power supply such as a battery (not shown). The use of the inverter device 1 is not particularly limited, but it is used, for example, for driving automobiles and starting engines (for example, ISG: Integrated Starter Generator).

[0014] 1 and 2, the inverter device 1 includes a wiring board 2 and inverter circuits 3 for three phases (U phase, V phase, and W phase) mounted on the wiring board 2. Each inverter circuit 3 for each phase includes transistors Q1 to Q6, a first capacitor C1, and a second capacitor C2. In the following description, when the transistors Q1 to Q6 are not to be distinguished from one another, they may be referred to as "transistor Q."

[0015] -Wiring board- The wiring board 2 is, for example, a multilayer wiring board (e.g., a printed circuit board) having six wiring layers. For convenience of explanation, as shown in FIG. 5, the thickness direction of the wiring board is defined as the up-down direction, and the wiring layer (first wiring layer) on the main surface (top surface) on which the first capacitor C1 and the second capacitor C2 are arranged is referred to as wiring layer L1. Then, wiring layers L2 to L6 (second to sixth wiring layers) are formed in order from the wiring layer L1 downward, with insulating layers (e.g., layers formed of resin) sandwiched between them. From the viewpoint of improving heat dissipation performance, it is preferable to use glass epoxy resin or highly thermally conductive resin for the insulating layer between the wiring layer L5 and the wiring layer L6.

[0016] -Transistor- FIG. 3 is a plan view of the inverter device 1 as viewed from above the wiring layer L2, and FIG. 4 is a bottom view of one phase of the inverter device 1 as viewed from below the wiring layer L5. In FIGS. 3 and 4, the positions of the transistors Q1 to Q6 are indicated by dashed lines. The X and Y directions are defined as directions that are orthogonal to the up-down direction and perpendicular to each other. In the X directions, the left direction in FIG. 3 is referred to as the X1 direction, and the right direction in FIG. 3 is referred to as the X2 direction. In the Y directions, the top direction in FIG. 3 is referred to as the Y1 direction, and the bottom direction in FIG. 3 is referred to as the Y2 direction.

[0017] The transistor Q is an N-type power MOSFET with a vertical structure, and in this example, it is composed of a semiconductor chip Qa (simply referred to as "chip" in the drawings) and a lead frame Qb. The semiconductor chip Qa has a source on one side and a drain on the other side. The lead frame Qb is made of copper, for example, and is configured to be U-shaped in cross-sectional side view (see FIG. 5) so as to cover the other side (drain) of the semiconductor chip Qa, and is connected to the drain of the semiconductor chip Qa. In other words, the lead frame Qb and the drain of the semiconductor chip Qa are at the same potential.

[0018] In other words, the transistor Q has, on one surface thereof, a source region S where a source terminal is provided and a drain region D where a drain terminal is provided so as to surround the source region S, and on the other surface thereof, a drain region D. Here, the term "terminal" is used to mean an inlet / outlet of current, and its specific form and mode are not particularly limited.

[0019] In the following description, one surface will be referred to as the "source-drain surface," and the other surface will be referred to as the "drain surface." Note that the "one surface (source-drain surface)" and the "other surface (drain surface)" referred to here are not limited to flat surfaces. Specifically, for example, as shown in FIGS. 10 and 11 described later, in the source-drain surface, there may be a step (a vertical step in FIGS. 10 and 11) between the surface on which the source is provided and the surface on which the drain is provided, or, for example, the surface on which the source is provided and / or the surface on which the drain is provided may be partially bulged or recessed. Furthermore, although not shown in the drawings because it is not the subject of the disclosed technology, the gate of the transistor Q is formed in the source-drain surface of the semiconductor chip Qa.

[0020] The source or drain of the transistor Q is connected to each of the wirings formed in the wiring layers L2 and L5 through multiple vias V and lead frames Qb. However, in the following description, for the sake of convenience, the description of the connection through the vias V and lead frames Qb may be omitted. The same applies to the connection between the wirings in each wiring layer, and the illustration and / or description of the connection through the vias V and lead frames Qb may be omitted. In addition, in Figures 5 and 6, wirings to which a common signal or voltage is applied are commonly hatched to facilitate understanding of the drawings. In other words, in Figure 2, the wirings that are commonly hatched are connected to each other through vias, etc. (including those not shown).

[0021] The following describes each of the transistors Q1 to Q6.

[0022] As shown in FIGS. 3 to 6, the transistors Q1 to Q6 for three phases are arranged in an intermediate layer between the wiring layer L2 and the wiring layer L5. That is, the transistors Q1 to Q6 for three phases are arranged side by side in the XY directions on the intermediate layer in a plan view. In this example, the layer including the wiring layer L3, the wiring layer L4, and the insulating layer X3 between L3 and L4 corresponds to the "intermediate layer." The configuration of the transistors Q1 to Q6 is common to the U-phase, V-phase, and W-phase, and the following explanation will be given for one phase.

[0023] The transistor Q1 (corresponding to the first transistor) is arranged with its drain surface facing the wiring layer L2 and its source-drain surface facing the wiring layer L5. That is, it is arranged so that its drain surface faces upward. In the transistor Q1, the drain terminal (hereinafter simply referred to as "drain") of the drain surface is connected to the first power supply wiring 11 of the wiring layer L2, and the source terminal (hereinafter simply referred to as "source") is connected to the wiring 21 (corresponding to the first wiring) of the wiring layer L5.

[0024] Transistor Q6 (corresponding to the second transistor) is arranged in the Y2 direction (corresponding to the first direction) of transistor Q1, with its source-drain surface facing the wiring layer L2 and its drain surface facing the wiring layer L5. That is, it is arranged so that its source-drain surface faces upward. The source of transistor Q6 is connected to second power supply wiring 12 of wiring layer L2, and the drain of the drain surface is connected to wiring 22 (corresponding to the second wiring) of wiring layer L5.

[0025] Transistor Q2 (corresponding to the third transistor) is arranged in the X2 direction (corresponding to the second direction) of transistor Q1, with its source-drain surface facing the wiring layer L2 and its drain surface facing the wiring layer L5. That is, it is arranged so that its source-drain surface faces upward. The source of transistor Q2 is connected to the ground wiring GND of wiring layer L2, and the drain of its drain surface is connected to wiring 21 of wiring layer L5.

[0026] Transistor Q4 (corresponding to the fourth transistor) is arranged in the Y2 direction of transistor Q2 and the X2 direction of transistor Q6, with its drain surface facing the wiring layer L2 and its source-drain surface facing the wiring layer L5. That is, it is arranged so that its drain surface faces upward. The source of transistor Q4 is connected to wiring 22 of wiring layer L5, and the drain of the drain surface is connected to the ground wiring GND of wiring layer L2.

[0027] Transistor Q3 (corresponding to the fifth transistor) is arranged in the X2 direction of transistor Q2, with its drain surface facing the wiring layer L2 and its source-drain surface facing the wiring layer L5. That is, it is arranged so that its drain surface faces upward. The source of transistor Q3 is connected to output wiring OUT of wiring layer L5, and the drain on the X1 direction side of the source-drain surface is connected to wiring 21 of wiring layer L5.

[0028] Transistor Q5 (corresponding to the sixth transistor) is arranged in the Y2 direction of transistor Q3 and in the X2 direction of transistor Q4, with its drain surface facing the wiring layer L2 and its source-drain surface facing the wiring layer L5. That is, it is arranged so that its drain surface faces upward. The source of transistor Q5 is connected to the wiring 22 of the wiring layer L5, the drain on the X2 direction side of the source-drain surface is connected to the output wiring OUT of the wiring layer L5, and the drain on the drain surface is connected to the output wiring OUT of the wiring layer L2.

[0029] -capacity- The first capacitor C1 is provided between a first power supply wiring 11 to which a positive power supply voltage P(+) is supplied from a battery (not shown) or the like, and a ground wiring GND connected to the ground. The second capacitor C2 is provided between the ground wiring GND and a second power supply wiring 12 to which a negative power supply voltage N(-) is supplied from a battery (not shown) or the like.

[0030] Specifically, the first capacitor C1 and the second capacitor C2 are mounted on the surface of the wiring layer L1. In the wiring layer L1, a ground wiring GND is provided between a first power supply wiring 11 provided at a position overlapping the transistor Q1 and a second power supply wiring 12 provided at a position overlapping the transistor Q6 in a plan view. The first capacitor C1 is arranged such that a terminal C11 overlaps the first power supply wiring 11 and a terminal C12 overlaps the ground wiring GND in a plan view. In the wiring layer L1, the terminal C11 and the first power supply wiring 11 are connected, and the terminal C12 and the ground wiring GND are connected. In the second capacitor C2, a terminal C21 overlaps the second power supply wiring 12 and a terminal C22 overlaps the ground wiring GND in a plan view. In the wiring layer L1, the terminal C21 and the second power supply wiring 12 are connected, and the terminal C22 and the ground wiring GND are connected.

[0031] 5 and 6, in this embodiment, in the wiring layer L1, the first power supply wiring 11 extends in the X2 direction from a position overlapping with the transistor Q1 to a position overlapping with the transistor Q2, and the second power supply wiring 12 extends in the X2 direction to a position overlapping with the transistor Q4. In addition, in the wiring layer L1, the ground wiring GND extends in the X2 direction to between the first power supply wiring 11 provided at a position overlapping with the transistor Q2 and the second power supply wiring 12 provided at a position overlapping with the transistor Q4. A part of the first capacitor C1 is arranged so that the terminal C11 overlaps with the first power supply wiring 11 at a position overlapping with the transistor Q2 in a plan view, and the terminal C12 overlaps with the ground wiring GND provided in the X2 direction of the transistor Q2, and they are connected to each other. Similarly, a portion of the second capacitor C2 is arranged and connected such that, in a plan view, terminal C21 overlaps with the second power supply wiring 12 at a position overlapping with the transistor Q4, and terminal C22 overlaps with the ground wiring GND provided in the X1 direction of the transistor Q4. Note that if sufficient installation space is secured for the first capacitor C1 and the second capacitor C2, the first capacitor C1 does not need to be arranged at a position overlapping with the transistor Q2, and similarly, the second capacitor C2 does not need to be arranged at a position overlapping with the transistor Q4.

[0032] -wiring- As described above, the first power supply wiring 11 is connected to the terminal C11 (see FIG. 2) of the first capacitor C1 in the wiring layer L1. The first power supply wiring 11 in the wiring layer L2 is also connected to the drain of the transistor Q1. That is, the first power supply wiring 11 is a wiring formed in the wiring layers L1 and L2. The first power supply wiring 11 in the wiring layer L2 is further connected to the first power supply wiring 11 in the wiring layer L5 through a via or the like (not shown). The first power supply wiring 11 in the wiring layer L5 is then connected to the drain of the transistor Q1 through the source-drain surface of the transistor Q1. Specifically, the first power supply wiring 11 is connected to the drain of the transistor Q1 in a C-shaped region where the first power supply wiring 11 and the drain region D of the transistor Q1 overlap in the plan view of FIG. 4. In other words, the first power supply wiring 11 overlaps the drain region D of the source-drain surface of the transistor Q1 in a C-shape in plan view, and has a recess 11a that recesses in a rectangular shape in the X1 direction from the opening of the C-shape toward the source region S of the transistor Q1.

[0033] The wiring 21 is formed in the wiring layer L5 and extends, for example, from the source region S of the transistor Q1 to the drain region D of the transistor Q3. The wiring 21 connects the source of the transistor Q1, the drain of the transistor Q2, and the drain of the transistor Q3 to one another. As shown in FIG. 4 , the wiring 21 has a protrusion 21a that protrudes in the X1 direction toward the recess 11a of the first power supply wiring 11 in a plan view and overlaps with the source region S of the transistor Q1. The wiring 21 is connected to the source of the transistor Q1 at the position where the protrusion 21a and the source region S of the transistor Q1 overlap. The wiring 21 also has a recess 21b that overlaps in a C-shape with the drain region D of the source-drain surface of the transistor Q3 in a plan view and is recessed in a rectangular shape in the X1 direction from the opening of the C-shape toward the source region S of the transistor Q1.

[0034] The output wiring OUT is a wiring formed in the wiring layer L5, and connects the source of the transistor Q3 and the drain of the transistor Q5 to each other. The output of each phase of the inverter device 1 is output from the output wiring OUT. Specifically, in a plan view, the output wiring OUT includes a protruding portion OUTa that protrudes in the X1 direction toward the recessed portion 21b of the wiring 21 and overlaps with the source region S of the transistor Q3, and a rectangular wiring OUTb that is formed integrally with the protruding portion OUTa and extends in the Y direction. Furthermore, in a plan view, the output wiring OUT includes a recessed portion OUTc that extends in the X1 direction from the wiring OUTb, overlaps with the drain region D of the source-drain surface of the transistor Q5 in a C-shape, and is recessed in a rectangular shape in the X2 direction from the opening of the C-shape toward the source region S of the transistor Q5.

[0035] The wiring 22 is formed in the wiring layer L5 and extends, for example, from the source region S of the transistor Q5 to a position beyond the end of the transistor Q6 in the X1 direction. The wiring 22 connects the source of the transistor Q5, the source of the transistor Q4, and the drain of the transistor Q6 to each other. In a plan view, the wiring 22 protrudes in the X2 direction toward the recess OUTc of the output wiring OUT and has a protrusion 22a that overlaps with the source region S of the transistor Q5. The wiring 22 is connected to the source of the transistor Q5 at the position where the protrusion 22a and the source region S of the transistor Q5 overlap.

[0036] In the wiring layer L1, the ground wiring GND is connected to the terminal C12 of the first capacitor C1 (see FIG. 2) and the terminal C22 of the second capacitor C2 (see FIG. 2). As described above, the ground wiring GND of the wiring layer L2 is connected to the source of the transistor Q2 and the drain of the transistor Q4. Furthermore, as shown in FIG. 2, the ground wirings GND of the three-phase inverter circuits 3 are connected to each other by a common ground wiring GND (corresponding to a common ground wiring) extending in the Y direction across the three phases. While FIG. 2 illustrates the wiring layer L2, a common ground wiring GND extending in the Y direction across the three phases may also be provided in the wiring layer L1. For example, the common ground wiring is provided so as to overlap the transistors Q3 and Q5 and extend in the Y direction. That is, the ground wirings GND of the wiring layer L1 in FIGS. 5 and 6 are connected to each other and extend across the three-phase inverter circuits 3.

[0037] 3, the ground wiring GND has a protrusion GNDa that protrudes toward the space between the first power supply wiring 11 and the second power supply wiring 12 in a plan view. In other words, as described above, the ground wiring GND is provided between the first power supply wiring 11 that is provided at a position overlapping with the transistor Q1 and the second power supply wiring 12 that is provided at a position overlapping with the transistor Q6 in a plan view.

[0038] The second power supply wiring 12 is connected to the terminal C21 (see FIG. 2) of the second capacitor C2 in the wiring layer L1. As described above, the second power supply wiring 12 in the wiring layer L2 is connected to the source of the transistor Q6. That is, the second power supply wiring 12 is a wiring formed in the wiring layers L1 and L2.

[0039] -Effects of the embodiment- As described above, the inverter device 1 of this embodiment includes the wiring substrate 2 having the wiring layer L1 formed on its surface, a plurality of transistors Q built into the wiring substrate 2, a first capacitor C1, and a second capacitor C2. The first capacitor C1 is provided between the first power supply wiring 11 and the ground wiring GND on the wiring layer L1. The second capacitor C2 is provided between the ground wiring GND and the second power supply wiring 12 on the wiring layer L1. The plurality of transistors Q include transistors Q1 to Q6. The transistor Q1 has a drain connected to the first power supply wiring 11 and a source connected to the wiring 21. The transistor Q2 is disposed in the X2 direction of the transistor Q1, a drain connected to the wiring 21, and a source connected to the ground wiring GND. The transistor Q3 is disposed in the X2 direction of the transistor Q2, a drain connected to the wiring 21, and a source connected to the output wiring OUT. The transistor Q6 is disposed in the Y2 direction of the transistor Q1, a drain connected to the wiring 22, and a source connected to the second power supply wiring 12. Transistor Q4 is arranged in the X2 direction of transistor Q6 and in the Y2 direction of transistor Q2, with its drain connected to ground wiring GND and its source connected to wiring 22. Transistor Q5 is arranged in the X2 direction of transistor Q4 and in the Y2 direction of transistor Q3, with its drain connected to output wiring OUT and its source connected to wiring 22. In addition, in wiring layer L1, a convex portion GNDa of the ground wiring GND is provided between a first power supply wiring 11 provided at a position overlapping with transistor Q1 and a second power supply wiring 12 provided at a position overlapping with transistor Q6 in plan view.

[0040] This configuration can shorten the wiring between the first power supply wiring 11 and the ground wiring GND of the inverter device 1 and the wiring between the second power supply wiring 12 and the ground wiring GND, thereby reducing the inductance of the inverter device 1.

[0041] Furthermore, the configuration of this embodiment allows the inverter device 1 to be miniaturized. This will be described with reference to the drawings. Fig. 7 is a diagram showing (a) the module configuration of the inverter device 1 according to this embodiment and (b) the module configuration of the inverter device 1 (comparative example) in which the transistors Q1 to Q6 of each phase are linearly arranged, arranged one above the other. In Figs. 7(a) and 7(b), capacitor modules 6 of the same size are arranged side by side on the wiring board 2. The capacitor modules 6 are used to stabilize the DC voltage.

[0042] 7, the configuration of this embodiment allows the terminals (terminals C12 and C22) of the first capacitor C1 and the second capacitor C2 on the ground wiring side to be arranged close to each other, so that the first capacitor C1 and the second capacitor C2 can be concentrated and arranged efficiently. This allows the wiring board 2 to be made smaller, and ultimately the inverter device 1 to be made smaller.

[0043] Furthermore, in the above embodiment, the transistors Q1 to Q6, the first capacitor C1, and the second capacitor C2 for three phases (U phase, V phase, and W phase) are arranged in the Y2 direction for each phase on the wiring board 2. The ground wiring GND for each of the three phases (U phase, V phase, and W phase) is connected to one another by a common ground wiring GND that extends in the Y2 direction across the three phases.

[0044] With this configuration, a current path is formed between the U phase and the V phase via a common ground wiring, thereby reducing the inductance of the inverter device 1. This will be described with reference to FIGS. 8 and 9.

[0045] Under certain conditions, current may flow through the U-phase and V-phase along the path indicated by the dashed arrow in the circuit diagram of Fig. 8. In this case, if the U-phase ground wiring GND and the V-phase ground wiring GND are not connected by a common ground wiring GND, the current will flow along the path indicated by the dashed arrow in Fig. 9. In contrast, if the U-phase and V-phase ground wiring GND are connected to each other by a common ground wiring GND, the current will flow along the path indicated by the solid line in Fig. 9. This shortens the current path, and the inductance of the inverter device 1 can be reduced.

[0046] <Other embodiments> As mentioned above, the above embodiments are merely examples and should not be interpreted as limiting the scope of the present disclosure. The scope of the present disclosure is defined by the claims, and all modifications and variations that fall within the scope of the claims equivalents are within the scope of the present disclosure.

[0047] For example, the technology of the present disclosure can be applied to inverter devices having circuit configurations other than those shown in Fig. 1. For example, in the above embodiment, the transistors Q2 and Q4 may be replaced with diodes (not shown).

[0048] In this case, the diode (first diode) replacing the transistor Q2 has its cathode connected to the wiring 21 of the wiring layer L5 and its anode connected to the ground wiring GND of the wiring layer L2. Similarly, the diode (second diode) replacing the transistor Q4 has its cathode connected to the ground wiring GND of the wiring layer L2 and its anode connected to the wiring 22 of the wiring layer L2.

[0049] The above configuration using the first and second diodes also achieves the same effects as the above embodiment. Specifically, the wiring between the first power supply wiring 11 and the ground wiring GND of the inverter device 1 and the wiring between the second power supply wiring 12 and the ground wiring GND can be shortened. This reduces the inductance of the inverter device 1. Furthermore, the terminals (terminals C12 and C22) on the ground wiring side of the first capacitance C1 and the second capacitance C2 can be arranged close to each other, allowing the first capacitance C1 and the second capacitance C2 to be concentrated and arranged efficiently. This allows the wiring board 2 to be made smaller, and ultimately the inverter device 1 to be made smaller.

[0050] 5 and 6, the transistor Q includes a lead frame Qb that is U-shaped in cross-sectional side view, but this is not limiting. For example, as shown in FIGS. 10 and 11, the lead frame Qb may have a rectangular shape in cross-sectional side view that is longer on both sides in the X direction than the semiconductor chip Qa. In this case, the width in the Y direction may be wider than both sides in the Y direction, as in the above embodiment, or may be the same width as the semiconductor chip Qa.

[0051] 10, for example, the drain (lead frame Qb) of the source-drain surface of transistor Q3 is connected to the wiring 21 of wiring layer L5 through a via V. Similarly, in the configuration of FIG. 11, the drain (lead frame Qb) of the source-drain surface of transistor Q5 is connected to the output wiring OUT of wiring layer L5 through a via V. The rest of the configuration is the same as in FIGS. 5 and 6. The configurations of FIGS. 10 and 11 also achieve the same effects as the above-described embodiment. That is, the inductance of inverter device 1 can be reduced, and the inverter device 1 can be made smaller. [Industrial Applicability]

[0052] The technique disclosed herein is extremely useful because it can reduce the self-inductance of an inverter device. [Explanation of symbols]

[0053] 1. Inverter device 2. Wiring board 3. Inverter circuit 11 1st power supply wiring 12 2nd power supply wiring 21 Wiring (1st wiring) 22 Wiring (2nd wiring) C1 1st capacity C2 2nd capacity GND Ground wiring L1 wiring layer (1st wiring layer) OUT Output wiring Q transistor Q1 transistor (first transistor) Q2 transistor (third transistor) Q3 transistor (5th transistor) Q4 transistor (fourth transistor) Q5 transistor (6th transistor) Q6 transistor (second transistor)

Claims

1. a wiring substrate having a first wiring layer formed on a surface thereof; a plurality of transistors built into the wiring substrate; a first capacitor provided between a first power supply wiring and a ground wiring of the first wiring layer; a second capacitor provided between the ground wiring and a second power supply wiring of the first wiring layer; The plurality of transistors include: a first transistor having a drain connected to the first power supply wiring and a source connected to a first wiring; a second transistor disposed in a first direction perpendicular to a thickness direction of the wiring substrate of the first transistor, the drain of which is connected to a second wiring and the source of which is connected to the second power supply wiring; In the first wiring layer, the ground wiring is provided between the first power supply wiring provided at a position overlapping the first transistor and the second power supply wiring provided at a position overlapping the second transistor in a planar view.

2. 2. The inverter device according to claim 1, The plurality of transistors include: a third transistor arranged in the thickness direction of the first transistor and in a second direction perpendicular to the first direction, the third transistor having a drain connected to the first wiring and a source connected to the ground wiring; a fourth transistor arranged in the first direction of the third transistor and in the second direction of the second transistor, the drain of which is connected to the ground wiring and the source of which is connected to the second wiring.

3. 3. The inverter device according to claim 2, The plurality of transistors include: a fifth transistor arranged in the second direction of the third transistor, the fifth transistor having a drain connected to the first wiring and a source connected to an output wiring; a sixth transistor arranged in the first direction of the fifth transistor and in the second direction of the third transistor, the drain of which is connected to the output wiring and the source of which is connected to the second wiring.

4. 3. The inverter device according to claim 2, the first power supply wiring extends in the second direction to a position where it overlaps with the third transistor; the second power supply wiring extends in the second direction to a position where it overlaps with the fourth transistor; the ground wiring extends in the second direction to between the first power supply wiring provided at a position overlapping with the third transistor and the second power supply wiring provided at a position overlapping with the fourth transistor.

5. a wiring substrate having a first wiring layer formed on a surface thereof; a plurality of transistors built into the wiring substrate; a first capacitor provided between a first power supply wiring and a ground wiring of the first wiring layer; a second capacitor provided between the ground wiring and a second power supply wiring of the first wiring layer; The plurality of transistors include: a first transistor having a drain connected to the first power supply wiring and a source connected to a first wiring; a second transistor arranged in a first direction perpendicular to a thickness direction of the wiring substrate of the first transistor, the second transistor having a drain connected to a second wiring and a source connected to the second power supply wiring; a third transistor arranged in the thickness direction of the first transistor and in a second direction perpendicular to the first direction, the third transistor having a drain connected to the first wiring and a source connected to the ground wiring; a fourth transistor arranged in the first direction of the second transistor and in the second direction of the third transistor, the drain of which is connected to the ground wiring and the source of which is connected to the second wiring; a fifth transistor arranged in the first direction of the second transistor, the fifth transistor having a drain connected to the first wiring and a source connected to an output wiring; a sixth transistor arranged in the first direction of the fifth transistor and in the second direction of the third transistor, the drain of which is connected to the output wiring and the source of which is connected to the second wiring.

6. The inverter device according to claim 1 or 5, the plurality of transistors, the first capacitor, and the second capacitor constitute one phase of an inverter circuit, and the inverter circuits for three phases are arranged in the first direction for each phase on the wiring board; an inverter device, wherein the ground wiring of the inverter circuits of each phase is connected to one another by a common ground wiring that extends in the first direction across the inverter circuits of the three phases;

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