Inverter device

Abstract

To improve the self-inductance of an inverter device.SOLUTION: An inverter device 1 includes: a wiring board including a first wiring layer and a second wiring layer; and a plurality of transistors Q arranged in an intermediate layer and having a source region and a drain region that surrounds the source region on one surface. The plurality of transistors Q include a first transistor disposed with one surface facing the first wiring layer, with a drain connected to a first wire in the first wiring layer, and with a source connected to a second wire in the first wiring layer. The first wire is overlapped in a shape like a letter C on the drain region of the first transistor in a plan view. The second wire extends to a position from an opening of the second wire to a position overlapping with the source region of the first transistor in the plan view.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed herein belongs to the technical field of inverter devices. [Background technology]

[0002] As inverter devices become more powerful due to their improved power density, there is a demand for technology to reduce the inductance of the inverter devices. In addition, as the output power increases, there is a demand for improved heat dissipation performance of the inverter devices.

[0003] Patent Document 1 discloses a technology that employs flip mounting in order to shorten the current loop and improve heat dissipation. Specifically, in Patent Document 1, the high-side IGBT and FWD have their collector and cathode electrodes, which are electrodes on the back surface of the chip, soldered to the power supply pattern on the insulating substrate. On the other hand, the low-side IGBT and FWD have their emitter and anode electrodes, which are electrodes on the front surface of the chip, soldered to the ground pattern on the insulating substrate, resulting in flip mounting.

[0004] Patent Document 2 discloses a manufacturing technique for a printed wiring board with built-in electronic components. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-234690 [Patent Document 2] Japanese Patent Application Publication No. 2020-150096 Summary of the Invention [Problem to be solved by the invention]

[0006] In conventional inverter devices, transistors are mounted on the surface of a substrate. However, when transistors constituting an inverter device are built into a substrate as in Patent Document 2, heat dissipation measures have not been sufficiently considered, and there is room for further consideration.

[0007] The technique disclosed herein has been made in view of the above points, and aims to improve the heat dissipation performance of an inverter device that uses a wiring board configured so that components can be built in. [Means for solving the problem]

[0008] In order to solve the above problem, the technology disclosed herein is directed to an inverter device and includes a wiring substrate having a first wiring layer and a second wiring layer, and a plurality of transistors each having a source region on one side and a drain region surrounding the source region, and arranged side by side in an intermediate layer between the first wiring layer and the second wiring layer, the plurality of transistors including a first transistor having one side facing the first wiring layer, a drain connected to a first wiring of the first wiring layer, and a source connected to a second wiring of the first wiring layer, the first wiring overlapping the drain region of the first transistor in a C-shape in a planar view and having a recess extending from the opening of the C-shape toward the source region, and the second wiring having a convex portion protruding into the recess in a planar view and overlapping the source region of the first transistor.

[0009] This configuration improves electrical conductivity and thermal conductivity. Specifically, the difference in heat dissipation resistance is related to the contact area. While the source and drain are in contact across their entire surface, the source and wiring are connected through multiple vias. Because the ease of heat transfer (thermal conductivity) is proportional to the contact area, the thermal conductivity relationship is "drain (large contact area) > source (small contact area)." Therefore, by providing the first wiring so that it overlaps the drain region of the first transistor in a C-shape, the contact area of ​​the drain, through which heat is easily transferred, can be increased, improving thermal conductivity. Furthermore, the increased contact area of ​​the drain can reduce electrical resistance and improve electrical conductivity. Furthermore, by providing a recess in the first wiring and a protrusion in the second wiring that overlaps the source region of the first transistor, the electrical conductivity and thermal conductivity can be improved while the first wiring connected to the drain of the first transistor and the second wiring connected to the source of the first transistor can be formed in the same wiring layer. [Effects of the Invention]

[0010] As described above, the technology disclosed herein can improve the heat dissipation performance of an inverter device. [Brief explanation of the drawings]

[0011] [Figure 1] Inverter device circuit diagram [Figure 2] FIG. 1 is a side cross-sectional view showing a configuration example of an inverter device according to a first embodiment; [Figure 3] 1 is a plan view of the inverter device of the first embodiment as seen from above the second wiring layer; [Figure 4] FIG. 10 is a bottom view of the inverter device of the first embodiment, seen from below the fifth wiring layer; [Figure 5] FIG. 10 is a bottom view of a modified example of the inverter device of the first embodiment, seen from below the fifth wiring layer; [Figure 6] 10 is a comparative example of a bottom view of the inverter device of the first embodiment as seen from below the fifth wiring layer. [Figure 7]FIG. 3 is a cross-sectional side view corresponding to FIG. 2, showing a modified example of the inverter device of the first embodiment; [Figure 8] FIG. 10 is a plan view of an inverter device according to a second embodiment; [Figure 9] FIG. 10 is a plan view of one phase of the inverter device of the second embodiment, seen from above the second wiring layer. [Figure 10] FIG. 10 is a bottom view of one phase of the inverter device of the second embodiment, seen from below the fifth wiring layer. [Figure 11] Cross section of line XI-XI in Figure 9 [Figure 12] Cross section of Figure 9 along line XII-XII DETAILED DESCRIPTION OF THE INVENTION

[0012] Exemplary embodiments will be described in detail below with reference to the drawings. Note that the following description of the embodiments is essentially merely illustrative and will focus on configurations related to the subject matter of the disclosed technology. Furthermore, technical elements that are not related to the subject matter of the disclosed technology may be illustrated or described in a simplified manner or omitted from the description, but this is not intended to limit the scope of the disclosed technology. In this disclosure, the term "connection" is used as a concept that broadly encompasses electrical connection. For example, in addition to direct connection between elements, it also includes indirect connection between elements via vias or the like.

[0013] First Embodiment Fig. 1 is a circuit diagram of an inverter device according to this embodiment, and Fig. 2 is a side cross-sectional view (for example, a cross-sectional view taken along line II-II in Fig. 3) showing the configuration of the inverter device.

[0014] 1, in this example, the inverter device 1 is a three-level inverter that outputs three-phase (U-phase, V-phase, W-phase) AC from a DC power supply such as a battery (not shown). The use of the inverter device 1 is not particularly limited, but it is used, for example, for driving automobiles and starting engines (for example, ISG: Integrated Starter Generator).

[0015] 1 and 2, the inverter device 1 includes a wiring board 2 and three-phase (U-phase, V-phase, and W-phase) inverter circuits 3 mounted on the wiring board 2. Each inverter circuit 3 includes transistors Q1 to Q6, a first capacitor C1, and a second capacitor C2. In the following description, when the transistors Q1 to Q6 are not distinguished from one another, they may be referred to as "transistor Q."

[0016] -Wiring board- The wiring board 2 is, for example, a multilayer wiring board (e.g., a printed circuit board) having six wiring layers. For convenience of explanation, as shown in FIG. 2, the thickness direction of the wiring board is defined as the up-down direction, and the wiring layer (first wiring layer) on the main surface (top surface) on which the first capacitor C1 and the second capacitor C2 are arranged is referred to as wiring layer L1. Then, wiring layers L2 to L6 (second to sixth wiring layers) are formed in order from the wiring layer L1 downward, with an insulating layer (e.g., a layer formed of resin) sandwiched between them. From the viewpoint of improving heat dissipation performance, it is preferable to use glass epoxy resin or high thermal conductive resin for the insulating layer between the wiring layer L5 and the wiring layer L6.

[0017] -capacity- The first capacitor C1 is provided between a first power supply wiring 11 to which a positive power supply voltage P(+) is supplied from a battery (not shown) or the like, and a ground wiring GND connected to the ground. The second capacitor C2 is provided between the ground wiring GND and a second power supply wiring 12 to which a negative power supply voltage N(-) is supplied from a battery (not shown) or the like.

[0018] -Transistor- FIG. 3 is a plan view of the inverter device 1 as viewed from above the wiring layer L2, and FIG. 4 is a bottom view of the inverter device 1 as viewed from below the wiring layer L5. In FIGS. 3 and 4, the positions of the transistors Q1 to Q6 are indicated by dashed lines. The X and Y directions are defined as directions that are orthogonal to the up-down direction and perpendicular to each other. In the X directions, the leftward direction in FIG. 3 is referred to as the X1 direction, and the rightward direction in FIG. 3 is referred to as the X2 direction. In the Y directions, the upward direction in FIG. 3 is referred to as the Y1 direction, and the downward direction in FIG. 3 is referred to as the Y2 direction.

[0019] As shown in FIGS. 2 to 4, the U-phase, V-phase, and W-phase transistors Q1 to Q6 are arranged in an intermediate layer between the wiring layer L2 and the wiring layer L5. In this example, the layers including the wiring layer L3, the wiring layer L4, and the insulating layer X3 between L3 and L4 correspond to the "intermediate layer." Specifically, the three-phase transistors Q1 to Q6 are arranged in the XY direction on the intermediate layer in a plan view. More specifically, the transistors Q1 to Q6 for each phase are arranged in the X2 direction on the intermediate layer in the order Q1, Q2, Q3, Q5, Q4, and Q6. Furthermore, a set of U-phase transistors Q1 to Q6, a set of V-phase transistors Q1 to Q6, and a set of W-phase transistors Q1 to Q6 are arranged in the Y2 direction in the order of U-phase, V-phase, and W-phase. That is, in the inverter circuit 3 for each phase, the transistors Q1 to Q6 are arranged linearly in the X direction in a plan view. Moreover, the three-phase (U-phase, V-phase, W-phase) inverter circuits 3 are arranged side by side in the Y direction in plan view.

[0020] The transistor Q is an N-type power MOSFET with a vertical structure, and in this example, it is composed of a semiconductor chip Qa (simply referred to as "chip" in the drawings) and a lead frame Qb. The semiconductor chip Qa has a source on one side and a drain on the other side. The lead frame Qb is made of copper, for example, and is configured to be U-shaped in cross-sectional side view (see Figure 2) so as to cover the other side (drain) of the semiconductor chip Qa, and is connected to the drain of the semiconductor chip Qa. In other words, the lead frame Qb and the drain of the semiconductor chip Qa are at the same potential.

[0021] In other words, the transistor Q has, on one surface, a source region S where a source terminal is provided and a drain region D where a drain terminal is provided so as to surround the source region S, and on the other surface, the drain region D is formed over the entire surface. In this example, the source region S is rectangular, and a drain region D with a rectangular frame is provided so as to surround the source region S. However, the shape of the source region S is not limited to a rectangular shape. Similarly, the drain region D does not have to surround the entire periphery of the source region S, and may be partially interrupted. In the following description, one surface will be referred to as the "source-drain surface," and the other surface will be referred to as the "drain surface." Note that the "one surface (source-drain surface)" and the "other surface (drain surface)" mentioned here are not limited to flat surfaces. Specifically, for example, as shown in Fig. 7 described later, in the source-drain plane, there may be a step (a vertical step in Fig. 7) between the plane where the source is provided and the plane where the drain is provided, or, for example, the plane where the source is provided and / or the plane where the drain is provided may be partially bulged or recessed. Furthermore, although not shown in the drawings because it is different from the subject matter of the technology disclosed, the gate of transistor Q is provided in the source-drain plane.

[0022] The source or drain of the transistor Q is connected to each of the wires formed in the wiring layers L2 and L5 via multiple vias V and lead frames Qb. However, in the following description, for the sake of convenience, the description of the connection via the vias V and lead frames Qb may be omitted. The same applies to the connection between the wires in each wiring layer, and the illustration and / or description of the connection via the vias V and lead frames Qb may be omitted. In FIG. 2, wires to which a common signal or voltage is applied are commonly hatched to facilitate understanding of the drawing. In other words, in FIG. 2, the wires that are commonly hatched are connected to each other via vias V and the like (including those not shown).

[0023] The transistors Q1 to Q6 are each described below. The configuration of the transistors Q1 to Q6 is common to the U-phase, V-phase, and W-phase, and only one phase will be described here.

[0024] As shown in FIG. 2, the transistor Q1 is disposed with its source-drain surface facing the wiring layer L5 and its drain surface facing the wiring layer L2. That is, the transistor Q1 is disposed with its drain surface facing upward. In the transistor Q1, the source terminal (hereinafter simply referred to as "source") is connected to the wiring 21 of the wiring layer L5, and the drain terminal (hereinafter simply referred to as "drain") of the drain surface is connected to the first power supply wiring 11 of the wiring layer L2. Here, in the present disclosure, the term "terminal" is used to mean an inlet / outlet for current, and the specific shape and form of the terminal are not particularly limited.

[0025] The transistor Q2 is arranged with its drain surface facing the wiring layer L5 and its source-drain surface facing the wiring layer L2. That is, the transistor Q2 is arranged with its source-drain surface facing upward. The source of the transistor Q2 is connected to the ground wiring GND of the wiring layer L2, and the drain of the drain surface is connected to the wiring 21 of the wiring layer L5.

[0026] The transistor Q3 is disposed such that its source-drain surface faces the wiring layer L5 and its drain surface faces the wiring layer L2. That is, the transistor Q3 is disposed so that its drain surface faces upward. The source of the transistor Q3 is connected to the output wiring OUT of the wiring layer L5, and the drain of the source-drain surface is connected to the wiring 21 of the wiring layer L5. Specifically, as shown in FIG. 4 , the wiring 21 overlaps the drain region of the source-drain surface of the transistor Q3 in a C-shape in a plan view and is connected to the drain of the transistor Q3 at the overlapping portion. The output wiring OUT extends from an opening formed in the C-shape of the wiring 21 to a position overlapping the source region of the transistor Q3 in a plan view and is connected to the source of the transistor Q3 at the overlapping position. In other words, the wiring 21 overlaps the drain region D of the source-drain surface of the transistor Q3 in a C-shape in a plan view and has a recess 21a extending from the C-shaped opening toward the source region of the transistor Q3. In plan view, the output wiring OUT protrudes in the X1 direction toward the recess 21a and has a protrusion OUTa that overlaps with the source region S of the transistor Q3. The output wiring OUT is connected to the source of the transistor Q3 at the position where the protrusion OUTa and the source region S of the transistor Q3 overlap.

[0027] The transistor Q5 is disposed such that its source-drain surface faces the wiring layer L5 and its drain surface faces the wiring layer L2. That is, the transistor Q5 is disposed so that its drain surface faces upward. The source of the transistor Q5 is connected to a wiring 22 in the wiring layer L5, and the drain of the source-drain surface is connected to an output wiring OUT in the wiring layer L5. Specifically, as shown in FIG. 4, the output wiring OUT overlaps the drain region of the source-drain surface of the transistor Q5 in a C-shape in a plan view and is connected to the drain of the transistor Q5 at the overlapping portion. The wiring 21 extends in the X1 direction from an opening formed in the C-shape of the output wiring OUT to a position overlapping the source region of the transistor Q5 in a plan view and is connected to the source of the transistor Q5 at the overlapping position. In other words, the output wiring OUT overlaps the drain region D of the source-drain surface of the transistor Q5 in a C-shape in a plan view and has a recess OUTb extending from the C-shaped opening toward the source region of the transistor Q5. In plan view, the wiring 22 protrudes in the X1 direction toward the recess OUTb and has a protruding portion 22a that overlaps with the source region S of the transistor Q5. The wiring 22 is connected to the source of the transistor Q5 at the position where the protruding portion 22a and the source region S of the transistor Q5 overlap.

[0028] The transistor Q4 is arranged with its source-drain surface facing the wiring layer L5 and its drain surface facing the wiring layer L2. That is, the transistor Q4 is arranged so that its drain surface faces upward. The source of the transistor Q4 is connected to the wiring 22 of the wiring layer L5, and the drain of the drain surface is connected to the ground wiring GND of the wiring layer L2.

[0029] The transistor Q6 is arranged with its drain surface facing the wiring layer L5 and its source-drain surface facing the wiring layer L2. That is, the transistor Q6 is arranged with its source-drain surface facing upward. The source of the transistor Q6 is connected to the second power supply wiring 12 of the wiring layer L2, and the drain of the drain surface is connected to the wiring 22 of the wiring layer L5.

[0030] -wiring- The first power supply wiring 11 is connected to the terminal C11 of the first capacitor C1 in the wiring layer L1. As described above, the first power supply wiring 11 in the wiring layer L2 is connected to the drain of the transistor Q1. That is, the first power supply wiring 11 is a wiring formed in the wiring layers L1 and L2. Although not shown, the first power supply wiring 11 is formed in the wiring layer L1 so as to cover the wiring in the wiring layer L2 in a plan view. The first power supply wiring 11 in the wiring layer L1 extends longer in the X2 direction than the first power supply wiring 11 in the wiring layer L2, from the viewpoint of generating a current in the X2 direction in the wiring layer L1.

[0031] The second power supply wiring 12 is connected to the terminal C21 of the second capacitor C2 in the wiring layer L1. As described above, the second power supply wiring 12 in the wiring layer L2 is connected to the source of the transistor Q6. That is, the second power supply wiring 12 is a wiring formed in the wiring layers L1 and L2. Although not shown, in the wiring layer L1, the second power supply wiring 12 is formed so as to cover the wiring in the wiring layer L2 in a plan view. From the viewpoint of generating a current in the X1 direction in the wiring layer L1, the second power supply wiring 12 in the wiring layer L1 extends longer in the X1 direction than the second power supply wiring 12 in the wiring layer L2.

[0032] The ground wiring GND is connected to the terminal C12 of the first capacitor C1 and the terminal C22 of the second capacitor C2 in the wiring layer L1. As described above, the ground wiring GND in the wiring layer L2 is connected to the source of the transistor Q2 and the drain of the transistor Q4. The ground wiring GND is mainly formed in the wiring layers L1 and L2, and is formed to cover the transistors Q2, Q3, Q5, and Q4 in a plan view. The ground wiring GND may also be provided in the wiring layer L3 and / or the wiring layer L4.

[0033] The wiring 21 is formed in the wiring layers L5 and L6, and extends, for example, from the X1-direction end of the transistor Q1 to the drain region D in the source-drain surface of the transistor Q3. Specifically, as described above, the X1-direction end of the wiring 21 overlaps the drain region D in the source-drain surface of the transistor Q3 in a C-shape in plan view. In other words, the wiring 21 has a rectangular recess 21a recessed in the X1 direction toward the portion overlapping with the source region S in the source-drain surface of the transistor Q3 in plan view. The wiring 21 connects the source of the transistor Q1, the drain of the transistor Q2, and the drain of the transistor Q3 to one another.

[0034] The output wiring OUT is a wiring formed in the wiring layers L5 and L6, and extends, for example, from the source region of transistor Q3 to the drain region of transistor Q5. Specifically, the X1-side end of the output wiring OUT extends with a predetermined line width to the boundary of transistor Q3 in the X2 direction in a plan view. The width then narrows to the width of the source region S, and a protrusion OUTa protruding into the recess 21a of the wiring 21 extends to a position overlapping the source region of transistor Q3. Furthermore, the X2-side end of the output wiring OUT overlaps the drain region of the source-drain surface of transistor Q5 in a C-shape in a plan view. In other words, the output wiring OUT has a recess OUTb recessed in a rectangular shape in the X1 direction toward the portion overlapping the source region S of the source-drain surface of transistor Q5 in a plan view. The output wiring OUT connects the source of transistor Q3 to the drain of transistor Q5. The output of each phase of the inverter device 1 is output from the output wiring OUT.

[0035] The wiring 22 is formed in the wiring layers L5 and L6 and extends, for example, from the source region S of the transistor Q5 to the end of the transistor Q6 in the X1 direction. Specifically, the end of the wiring 22 on the X1 side extends with a predetermined line width to the boundary of the transistor Q5 in the X2 direction in a plan view, then narrows to the width of the source region, and a protrusion 22a protruding into the recess OUTb of the output wiring OUT extends to a position overlapping the source region of the transistor Q5. The wiring 22 then connects the source of the transistor Q5, the source of the transistor Q4, and the drain of the transistor Q6 to one another.

[0036] Although not shown in the figure, the size and shape of the wiring 21 in the wiring layer L5 and the wiring layer L6 in a plan view are the same, and the wiring 21 in the wiring layer L5 and the wiring 21 in the wiring layer L6 are connected to each other through vias V. The same applies to the output wiring OUT and the wiring 22.

[0037] -Effects of the first embodiment- As described above, the inverter device 1 of this embodiment includes the wiring board 2 having the first wiring layer and the second wiring layer, and a plurality of transistors Q arranged side by side on an intermediate layer between the first wiring layer and the second wiring layer of the wiring board 2. Each of the plurality of transistors Q has a source region S on one surface and a drain region D surrounding the source region S. In the above embodiment, the wiring layer L5 corresponds to the first wiring layer, the wiring layer L2 corresponds to the second wiring layer, and the source-drain surface corresponds to one surface.

[0038] Furthermore, the plurality of transistors Q include a first transistor whose source-drain surface is disposed opposite the wiring layer L5, whose drain is connected to a first wiring in the wiring layer L5, and whose source is connected to a second wiring in the wiring layer L5. The first wiring overlaps the drain region of the first transistor in a C-shape in plan view and has a recess extending from the C-shaped opening toward the source region, and the second wiring has a protrusion that protrudes into the recess of the first wiring in plan view and overlaps the source region of the first transistor.

[0039] 4, for example, focusing on transistor Q3 (corresponding to the first transistor), in a plan view, wiring 21 (corresponding to the first wiring) overlaps the drain region of transistor Q3 in a C-shape and has a recess 21a extending from the C-shaped opening toward the source region S of transistor Q3, and output wiring OUT (corresponding to the second wiring) has a protrusion OUTa that protrudes into the recess 21a of wiring 21 and overlaps with the source region S of transistor Q3. The source of transistor Q1 (corresponding to the second transistor) is connected to wiring 21 in wiring layer L5, and the drain of transistor Q5 (corresponding to the third transistor) is connected to output wiring OUT in wiring layer L5. The drain of transistor Q2 (corresponding to the second transistor) is connected to wiring 21 in wiring layer L5.

[0040] Furthermore, for example, focusing on transistor Q5 (corresponding to the first transistor), in a planar view, output wiring OUT (corresponding to the first wiring) overlaps the drain region of transistor Q5 in a C-shape and has a recess OUTb extending from the C-shaped opening toward the source region S of transistor Q5, and wiring 22 (corresponding to the second wiring) has a protrusion 22a protruding into the recess OUTb of output wiring OUT and overlapping with the source region S of transistor Q5. The source of transistor Q3 (corresponding to the second transistor) is connected to the output wiring OUT of wiring layer L5, and the source of transistor Q4 (corresponding to the third transistor) is connected to wiring 22 of wiring layer L5. The drain of transistor Q6 (corresponding to the third transistor) is connected to wiring 22 of wiring layer L5.

[0041] This configuration can improve electrical conductivity and thermal conductivity. Specifically, the difference in heat dissipation resistance is related to the contact area. In this regard, as shown in FIG. 2, the source and drain are in contact with each other over the entire surface, while the source and wiring are connected through multiple vias. Because the ease of heat transfer (thermal conductivity) is proportional to the contact area, the thermal conductivity is in the following relationship: "drain (large contact area)" > "source (small contact area)." Therefore, by using the configuration of the present disclosure, the contact area of ​​the drain, which transfers heat easily, can be increased compared to the comparative example shown in FIG. 6, thereby improving thermal conductivity. Furthermore, because the contact area of ​​the drain is increased, electrical resistance can be reduced and electrical conductivity can be improved.

[0042] (Variation) In the above embodiment, the X2-direction end of the wiring 21 extends to the X2-direction end of the transistor Q3, but this is not limiting. For example, as shown in FIG. 5, the X2-direction end of the wiring 21 may extend beyond the X2-direction end of the transistor Q3. Even in this case, the wiring 21 overlaps the drain region of the transistor Q3 in a C-shape in plan view and has a recess extending from the opening of the C-shape toward the source region of the transistor Q3. The output wiring OUT protrudes into the recess and has a protrusion that overlaps the source region of the transistor Q3, thereby achieving the same effects as the above embodiment. The same applies to the relationship between the output wiring OUT and the transistor Q5.

[0043] The technology of the present disclosure can also be applied to inverter devices with circuit configurations other than that shown in Fig. 1. For example, in the above embodiment, the transistors Q2 and Q4 may be replaced with diodes (not shown).

[0044] In this case, the diode (first diode) replacing transistor Q2 has its cathode connected to the wiring 21 of the wiring layer L5 and its anode connected to the ground wiring GND of the wiring layer L2. Similarly, the diode (second diode) replacing transistor Q4 has its cathode connected to the ground wiring GND of the wiring layer L2 and its anode connected to the wiring 22 of the wiring layer L2. Even in this configuration, the configurations of transistors Q3 and Q5 and their connections to the wiring are similar to those of the above-described embodiment, and similar effects to those of the above-described embodiment can be obtained.

[0045] In the above embodiment, the transistor Q includes a lead frame Qb that is U-shaped in cross-sectional side view as shown in Fig. 2, but this is not limiting. For example, as shown in Fig. 7, the lead frame Qb may have a rectangular shape in cross-sectional side view that is longer on both sides in the X direction than the semiconductor chip Qa. In this case, the width in the Y direction may be wider than both sides in the Y direction, as in the above embodiment, or may be the same width as the semiconductor chip Qa.

[0046] In the configuration of FIG. 7, for example, the drain (lead frame Qb) of the drain-source surface of transistor Q3 is connected to wiring 21 of wiring layer L5 through a via V. Similarly, the drain (lead frame Qb) of the drain-source surface of transistor Q5 is connected to output wiring OUT of wiring layer L5 through a via V. The rest of the configuration is the same as in FIG. 2. The configuration of FIG. 7 also provides the same effects as the above-described embodiments.

[0047] Second Embodiment FIG. 8 is a plan view of the inverter device according to this embodiment, illustrating the wiring of the wiring layer L2 as the wiring layer. That is, the diagram illustrates a state in which the wiring layer L1 is omitted. In this embodiment, the circuit diagram of the inverter device 1 is the same as that of FIG. 1. Note that in this embodiment, the same reference numerals are used for components corresponding to those in the first embodiment. The following description will focus on differences from the first embodiment. Note that it is not intended to limit the various design parameters / process parameters, etc., of elements, etc., that are given the same reference numerals in the first and second embodiments to the same elements. In other words, the technical scope of the present disclosure includes configurations in which the various parameters of elements, etc., that are given the same reference numerals in the first and second embodiments are different from each other in the first and second embodiments.

[0048] The configuration of the wiring board is the same as that of the first embodiment, and a detailed description thereof will be omitted here.

[0049] -Transistor- FIG. 9 is a plan view of one phase of the inverter device 1, viewed from above the wiring layer L2, and FIG. 10 is a bottom view of the wiring layer L5. In FIGS. 9 and 10, the positions of the transistors Q1 to Q6 are indicated by dashed lines. The X and Y directions are defined as directions that are orthogonal to the up-down direction and perpendicular to each other. In the X directions, the left direction in FIG. 9 is referred to as the X1 direction, and the right direction in FIG. 9 is referred to as the X2 direction. In the Y directions, the top direction in FIG. 9 is referred to as the Y1 direction, and the bottom direction in FIG. 9 is referred to as the Y2 direction.

[0050] The transistors Q1 to Q6 will be described below. The structure and features of the individual transistors Q (Q1 to Q6) are the same as those in the first embodiment, and detailed description thereof will be omitted here.

[0051] 9 to 12, the transistors Q1 to Q6 for three phases are arranged on an intermediate layer between the wiring layer L2 and the wiring layer L5. That is, the transistors Q1 to Q6 for three phases are arranged side by side in the XY directions on the intermediate layer in a plan view. The configuration of the transistors Q1 to Q6 is common to the U-phase, V-phase, and W-phase, and the following explanation will be given for one phase.

[0052] The transistor Q1 is disposed with its drain surface facing the wiring layer L2 and its source-drain surface facing the wiring layer L5. That is, the transistor Q1 is disposed with its drain surface facing upward. The drain of the transistor Q1 is connected to the first power supply wiring 11 of the wiring layer L2, and the source is connected to the wiring 21 of the wiring layer L5.

[0053] The transistor Q6 is disposed in the Y2 direction of the transistor Q1, with its source-drain surface facing the wiring layer L2 and its drain surface facing the wiring layer L5. That is, the transistor Q6 is disposed so that its source-drain surface faces upward. The source of the transistor Q6 is connected to the second power supply wiring 12 of the wiring layer L2, and the drain of the drain surface is connected to the wiring 22 of the wiring layer L5.

[0054] Transistor Q2 is arranged in the X2 direction of transistor Q1, with its source-drain surface facing wiring layer L2 and its drain surface facing wiring layer L5. That is, it is arranged so that its source-drain surface faces upward. Transistor Q2 has its source connected to the ground wiring GND of wiring layer L2 and its drain connected to wiring 21 of wiring layer L5.

[0055] Transistor Q4 is arranged in the Y2 direction of transistor Q2 and the X2 direction of transistor Q6, with its drain surface facing the wiring layer L2 and its source-drain surface facing the wiring layer L5. That is, it is arranged so that the drain surface faces upward. Transistor Q4 has its source connected to wiring 22 of wiring layer L5 and its drain connected to the ground wiring GND of wiring layer L2.

[0056] The transistor Q3 is disposed in the X2 direction of the transistor Q2, with its drain surface facing the wiring layer L2 and its source-drain surface facing the wiring layer L5. That is, the transistor Q3 is disposed so that its drain surface faces upward. The source of the transistor Q3 is connected to the output wiring OUT of the wiring layer L5, and the drain on the X1 direction side of the source-drain surface is connected to the wiring 21 of the wiring layer L5.

[0057] Transistor Q5 is arranged in the Y2 direction of transistor Q3 and the X2 direction of transistor Q4, with its drain surface facing the wiring layer L2 and its source-drain surface facing the wiring layer L5. That is, it is arranged so that its drain surface faces upward. Transistor Q5 has its source connected to wiring 22 of wiring layer L5, its drain on the X2 direction side of the source-drain surface connected to output wiring OUT of wiring layer L5, and its drain surface connected to output wiring OUT of wiring layer L2.

[0058] -capacity- The first capacitor C1 is provided between a first power supply wiring 11 to which a positive power supply voltage P(+) is supplied from a battery (not shown) or the like, and a ground wiring GND connected to the ground. The second capacitor C2 is provided between the ground wiring GND and a second power supply wiring 12 to which a negative power supply voltage N(-) is supplied from a battery (not shown) or the like.

[0059] Specifically, the first capacitor C1 and the second capacitor C2 are mounted on the surface of the wiring layer L1. In the wiring layer L1, a ground wiring GND is provided between a first power supply wiring 11 provided at a position overlapping the transistor Q1 and a second power supply wiring 12 provided at a position overlapping the transistor Q6 in a plan view. The first capacitor C1 is arranged such that a terminal C11 overlaps the first power supply wiring 11 and a terminal C12 overlaps the ground wiring GND in a plan view. In the wiring layer L1, the terminal C11 and the first power supply wiring 11 are connected, and the terminal C12 and the ground wiring GND are connected. In the second capacitor C2, a terminal C21 overlaps the second power supply wiring 12 and a terminal C22 overlaps the ground wiring GND in a plan view. In the wiring layer L1, the terminal C21 and the second power supply wiring 12 are connected, and the terminal C22 and the ground wiring GND are connected.

[0060] 11 and 12, in the present embodiment, in the wiring layer L1, the first power supply wiring 11 extends in the X2 direction from a position overlapping with the transistor Q1 to a position overlapping with the transistor Q2, and the second power supply wiring 12 extends in the X2 direction to a position overlapping with the transistor Q4. In addition, in the wiring layer L1, the ground wiring GND extends in the X2 direction to between the first power supply wiring 11 provided at a position overlapping with the transistor Q2 and the second power supply wiring 12 provided at a position overlapping with the transistor Q4. A part of the first capacitor C1 is arranged so that the terminal C11 overlaps with the first power supply wiring 11 at a position overlapping with the transistor Q2 in a plan view, and the terminal C12 overlaps with the ground wiring GND provided in the X2 direction of the transistor Q2, and they are connected to each other. Similarly, a portion of the second capacitor C2 is arranged and connected such that, in a plan view, terminal C21 overlaps with the second power supply wiring 12 at a position overlapping with the transistor Q4, and terminal C22 overlaps with the ground wiring GND provided in the X1 direction of the transistor Q4. Note that if sufficient installation space is secured for the first capacitor C1 and the second capacitor C2, the first capacitor C1 does not need to be arranged at a position overlapping with the transistor Q2, and similarly, the second capacitor C2 does not need to be arranged at a position overlapping with the transistor Q4.

[0061] -wiring- As described above, the first power supply wiring 11 is connected to the terminal C11 (see FIG. 8) of the first capacitor C1 in the wiring layer L1. The first power supply wiring 11 in the wiring layer L2 is also connected to the drain of the transistor Q1. That is, the first power supply wiring 11 is a wiring formed in the wiring layers L1 and L2. The first power supply wiring 11 in the wiring layer L2 is further connected to the first power supply wiring 11 in the wiring layer L5 through a via or the like (not shown). The first power supply wiring 11 in the wiring layer L5 is then connected to the drain of the transistor Q1 through the source-drain surface of the transistor Q1. Specifically, the first power supply wiring 11 is connected to the drain of the transistor Q1 in a C-shaped region where the first power supply wiring 11 and the drain region D of the transistor Q1 overlap when viewed from below in FIG. 10. In other words, the first power supply wiring 11 overlaps the drain region D of the source-drain surface of the transistor Q1 in a C-shape when viewed from below, and has a recess 11a that recesses in a rectangular shape in the X1 direction from the opening of the C-shape toward the source region S of the transistor Q1.

[0062] The wiring 21 is formed in the wiring layer L5 and extends, for example, from the source region S of the transistor Q1 to the drain region D of the transistor Q3. The wiring 21 connects the source of the transistor Q1, the drain of the transistor Q2, and the drain of the transistor Q3 to one another. As shown in FIG. 10 , the wiring 21 has a protruding portion 21c that protrudes in the X1 direction toward the recessed portion 11a of the first power supply wiring 11 in a plan view and overlaps with the source region S of the transistor Q1. The wiring 21 is connected to the source of the transistor Q1 at the position where the protruding portion 21c and the source region S of the transistor Q1 overlap. The wiring 21 also has a recessed portion 21d that overlaps in a C-shape with the drain region D of the source-drain surface of the transistor Q3 in a plan view and is recessed in a rectangular shape in the X1 direction from the opening of the C-shape toward the source region S of the transistor Q1.

[0063] The output wiring OUT is a wiring formed in the wiring layer L5, and connects the source of the transistor Q3 and the drain of the transistor Q5 to each other. Specifically, the output wiring OUT includes, in a plan view, a protruding portion OUTc that protrudes in the X1 direction toward the recessed portion 21d of the wiring 21 and overlaps with the source region S of the transistor Q3, and a rectangular wiring OUTd that is formed integrally with the protruding portion OUTc and extends in the Y direction. Furthermore, the output wiring OUT has a recessed portion OUTe that extends in the X1 direction from the wiring OUTd in a plan view, overlaps with the drain region D of the source-drain surface of the transistor Q5 in a C-shape, and is recessed in a rectangular shape in the X2 direction from the opening of the C-shape toward the source region S of the transistor Q5.

[0064] The wiring 22 is formed in the wiring layer L5 and extends, for example, from the source region S of the transistor Q5 to a position beyond the end of the transistor Q6 in the X1 direction. The wiring 22 connects the source of the transistor Q5, the source of the transistor Q4, and the drain of the transistor Q6 to one another. In a plan view, the wiring 22 protrudes in the X2 direction toward the recess OUTe of the output wiring OUT and has a protrusion 22b that overlaps with the source region S of the transistor Q5. The wiring 22 is connected to the source of the transistor Q5 at the position where the protrusion 22b and the source region S of the transistor Q5 overlap.

[0065] In the wiring layer L1, the ground wiring GND is connected to the terminal C12 of the first capacitor C1 (see FIG. 8) and the terminal C22 of the second capacitor C2 (see FIG. 8). As described above, the ground wiring GND of the wiring layer L2 is connected to the source of the transistor Q2 and the drain of the transistor Q4. Furthermore, as shown in FIG. 8, the ground wirings GND of the three-phase inverter circuits 3 are connected to each other by a common ground wiring GND (corresponding to a common ground wiring) extending in the Y direction across the three phases. While FIG. 8 illustrates the wiring layer L2, a common ground wiring GND extending in the Y direction across the three phases may also be provided in the wiring layer L1. For example, the common ground wiring is provided so as to overlap the transistors Q3 and Q5 and extend in the Y direction. That is, the ground wirings GND of the wiring layer L1 in FIGS. 11 and 12 are connected to each other and extend across the three-phase inverter circuits 3.

[0066] The second power supply wiring 12 is connected to the terminal C21 (see FIG. 8) of the second capacitor C2 in the wiring layer L1. As described above, the second power supply wiring 12 in the wiring layer L2 is connected to the source of the transistor Q6. That is, the second power supply wiring 12 is a wiring formed in the wiring layers L1 and L2.

[0067] -Effects of the second embodiment- As described above, in this embodiment, as in the first embodiment, the inverter device 1 includes a wiring board 2 having a first wiring layer and a second wiring layer, and a plurality of transistors Q arranged side by side on an intermediate layer between the first wiring layer and the second wiring layer of the wiring board 2. Each of the plurality of transistors Q has a source region S on one surface and a drain region D surrounding the source region S. In the above embodiment, the wiring layer L5 corresponds to the first wiring layer, the wiring layer L2 corresponds to the second wiring layer, and the source-drain surface corresponds to one surface.

[0068] Furthermore, the plurality of transistors Q include a first transistor whose source-drain surface is disposed opposite the wiring layer L5, whose drain is connected to a first wiring in the wiring layer L5, and whose source is connected to a second wiring in the wiring layer L5. The first wiring overlaps the drain region of the first transistor in a C-shape in plan view and has a recess extending from the C-shaped opening toward the source region, and the second wiring has a protrusion that protrudes into the recess of the first wiring in plan view and overlaps the source region of the first transistor.

[0069] By adopting such a configuration, it is possible to improve the electrical conductivity and heat conductivity, as in the first embodiment. Furthermore, as in the first embodiment, the contact area of ​​the drain increases, so that the electrical resistance can be reduced and the electrical conductivity can be improved.

[0070] (Variation) As in the modified example of the first embodiment, in the configuration of this embodiment, for example, the configuration of FIGS. 11 and 12, the shape of the lead frame Qb may be a rectangle longer on both sides in the X direction than the semiconductor chip Qa in a side cross-sectional view, as shown in FIG. 7. Even in this case, as in the modified example of the first embodiment (case of FIG. 7), for example, the drain (lead frame Qb) of the drain-source surface of transistor Q3 is connected to the wiring 21 of the wiring layer L5 through a via V. Similarly, the drain (lead frame Qb) of the drain-source surface of transistor Q5 is connected to the output wiring OUT of the wiring layer L5 through a via V. Even when the lead frame Qb is changed, the same effects as those of the second embodiment described above can be obtained. [Industrial Applicability]

[0071] The technology disclosed herein is extremely useful because it can improve the heat dissipation performance of an inverter device. [Explanation of symbols]

[0072] 1. Inverter device 21 Wiring (1st wiring) 22 Wiring (2nd wiring) OUT Output wiring (1st wiring, 2nd wiring) L2 wiring layer (2nd wiring layer) L5 wiring layer (1st wiring layer) Q transistor Q1 transistor (second transistor) Q3 transistor (first transistor) Q5 Transistor (1st transistor, 3rd transistor)

Claims

1. a wiring substrate having a first wiring layer and a second wiring layer; a plurality of transistors each having a source region on one surface and a drain region surrounding the source region, the transistors being arranged side by side in an intermediate layer between the first wiring layer and the second wiring layer; The plurality of transistors include: a first transistor, the one surface of which is disposed opposite the first wiring layer, the drain of which is connected to a first wiring of the first wiring layer, and the source of which is connected to a second wiring of the first wiring layer; the first wiring overlaps the drain region of the first transistor in a C-shape in plan view and has a recess extending from an opening of the C-shape toward the source region; the second wiring has a protrusion that protrudes into the recess in a plan view and overlaps with the source region of the first transistor.

2. 2. The inverter device according to claim 1, The plurality of transistors include: a second transistor, the one surface of which is disposed opposite the first wiring layer and the source of which is connected to the first wiring of the first wiring layer; a third transistor, the one surface of which is disposed opposite the first wiring layer and the drain of which is connected to the second wiring of the first wiring layer.

3. 2. The inverter device according to claim 1, The plurality of transistors include: a second transistor having a drain formed on the other surface thereof, the other surface thereof being disposed opposite the first wiring layer, and the drain on the other surface being connected to the first wiring of the first wiring layer; a third transistor, the one surface of which is disposed opposite the first wiring layer and the drain of which is connected to the second wiring of the first wiring layer.

4. 2. The inverter device according to claim 1, The plurality of transistors include: a second transistor, the one surface of which is disposed opposite the first wiring layer and the source of which is connected to the first wiring of the first wiring layer; a third transistor, the one surface of which is disposed opposite the first wiring layer and the source of which is connected to the second wiring of the first wiring layer.

5. 2. The inverter device according to claim 1, The plurality of transistors include: a second transistor, the one surface of which is disposed opposite the first wiring layer and the source of which is connected to the first wiring of the first wiring layer; a third transistor having a drain formed on the other surface thereof, the other surface thereof being arranged opposite the first wiring layer, and the drain on the other surface being connected to the second wiring of the first wiring layer.

6. 2. The inverter device according to claim 1, the plurality of transistors include a second transistor having a drain formed on the other surface thereof, the other surface thereof facing the first wiring layer and arranged alongside the first transistor, and the drain on the other surface thereof connected to the second wiring of the first wiring layer; The inverter device has a power supply wiring connected to the first wiring.

7. 2. The inverter device according to claim 1, the plurality of transistors include a second transistor, the one surface of which is disposed opposite the first wiring layer and the drain of which is connected to the second wiring of the first wiring layer; The inverter device has a power supply wiring connected to the first wiring.

8. a substrate having a first wiring layer and a second wiring layer; a plurality of transistors each having a source region on one side of which a source is formed, a drain region surrounding the source region and having a drain formed therein, and a drain region on the other side of which a drain is formed, the plurality of transistors being arranged side by side in an intermediate layer between the first wiring layer and the second wiring layer; The plurality of transistors include: a first transistor, the one surface of which is disposed opposite the first wiring layer and the source of which is connected to a first wiring formed in the first wiring layer; a second transistor, the other surface of which is disposed opposite the first wiring layer and the drain of which is connected to the first wiring; a third transistor, the one surface of which is disposed opposite the first wiring layer, the source of which is connected to an output wiring formed in the first wiring layer, and the drain of the one surface of which is connected to the first wiring; a fourth transistor, the one surface of which is disposed opposite the first wiring layer, the source of which is connected to a second wiring formed in the first wiring layer, and the drain of the one surface of which is connected to the output wiring; a fifth transistor, the one surface of which is disposed opposite the first wiring layer and the source of which is connected to the second wiring; a sixth transistor, the other surface of which is disposed opposite the first wiring layer and the drain of which is connected to the second wiring; the first wiring overlaps the drain region of the third transistor in a C-shape in plan view and has a first recess extending from an opening of the C-shape toward the source region; the output wiring has a first convex portion that protrudes into the first concave portion in a plan view and overlaps with the source region of the third transistor, and a second concave portion that overlaps with the drain region of the fifth transistor in a C-shape and extends from an opening of the C-shape toward the source region; the second wiring has a second convex portion that protrudes into the second concave portion and overlaps with the source region of the fifth transistor in a plan view.

9. 9. The inverter device according to claim 8, the drain of the first transistor is connected to a power supply line; the power supply wiring overlaps the drain region of the first transistor in a C-shape in plan view and has a third recess extending from an opening of the C-shape toward the source region; the first wiring has a third protrusion that protrudes into the third recess and overlaps with the source region of the first transistor in a plan view.

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