Semiconductor device, inspection method and semiconductor chip

Abstract

To enable simple inspection of an electrical connection state between semiconductor chips in a semiconductor device having a multichip configuration.SOLUTION: A semiconductor device includes first and second semiconductor chips connected to each other. The first semiconductor chip includes: first and second alignment marks made of conductors electrically separated from each other; and first and second terminals electrically connected to the first and second alignment marks. The second semiconductor chip includes: a guard ring including an annular conductor provided along an outer edge of the second semiconductor chip; and third and fourth alignment marks each made of a conductor electrically connected to the guard ring. The first semiconductor chip and the second semiconductor chip are connected such that the first alignment mark overlaps the third alignment mark, and the second alignment mark overlaps the fourth alignment mark.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The disclosed technology relates to a semiconductor device, an inspection method, and a semiconductor chip. [Background technology]

[0002] The following techniques are known as techniques related to mounting semiconductor chips using alignment marks. For example, Patent Document 1 describes a circuit board on which a semiconductor chip having electrode pads on one main surface is flip-chip mounted. This circuit board includes an insulating substrate, a circuit pattern formed on one main surface of the insulating substrate, bonding metal bumps formed on the circuit pattern to bond the electrode pads to the circuit pattern, and alignment marks formed on one main surface of the insulating substrate and used for alignment when flip-chip mounting the semiconductor chip on the circuit board.

[0003] The following techniques are known as techniques for inspecting electrical connections between semiconductor chips: For example, Patent Document 2 describes an inspection circuit that inspects electrical connections between chip-on-chip (COC) semiconductor chips, in which one or more semiconductor chips are mounted by bonding them onto a base semiconductor chip. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-111148 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-20550 Summary of the Invention [Problem to be solved by the invention]

[0005] In a semiconductor device having a multi-chip configuration including multiple semiconductor chips, electrical connections between the semiconductor chips are inspected. One possible inspection method is to operate the internal circuit of one of the semiconductor chips, but this method requires a relatively long inspection time.

[0006] The disclosed technology aims to enable simple testing of the electrical connection state between semiconductor chips in a semiconductor device having a multi-chip configuration including a plurality of semiconductor chips. [Means for solving the problem]

[0007] The semiconductor device according to the disclosed technology includes a first semiconductor chip and a second semiconductor chip connected to the first semiconductor chip. The first semiconductor chip includes a first alignment mark made of a conductor, a second alignment mark made of a conductor electrically isolated from the first alignment mark, a first terminal electrically connected to the first alignment mark, and a second terminal electrically connected to the second alignment mark. The second semiconductor chip includes a guard ring including a ring-shaped conductor provided along the outer edge of the second semiconductor chip, a third alignment mark made of a conductor electrically connected to the guard ring, and a fourth alignment mark made of a conductor electrically connected to the guard ring. The first semiconductor chip and the second semiconductor chip are connected so that the first alignment mark and the third alignment mark overlap and the second alignment mark and the fourth alignment mark overlap.

[0008] An inspection method according to the disclosed technique is a method for inspecting the semiconductor device described above, and includes measuring an electrical characteristic that indicates an electrical connection state between the first terminal and the second terminal.

[0009] The semiconductor chip related to the disclosed technology includes a first alignment mark made of a conductor, a second alignment mark made of a conductor electrically isolated from the first alignment mark, a first terminal electrically connected to the first alignment mark, and a second terminal electrically connected to the second alignment mark.

[0010] Another semiconductor chip related to the disclosed technology includes a guard ring including a ring-shaped conductor arranged along the outer edge of the semiconductor chip, a third alignment mark consisting of a conductor electrically connected to the guard ring, and a fourth alignment mark consisting of a conductor electrically connected to the guard ring. [Effects of the Invention]

[0011] According to the present invention, in a semiconductor device having a multi-chip configuration including a plurality of semiconductor chips, it is possible to easily inspect the state of electrical connection between the semiconductor chips. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a perspective view illustrating an example of a configuration of a semiconductor device according to an embodiment of the disclosed technique; [Figure 2] 1 is a plan view of a first semiconductor chip according to an embodiment of the disclosed technique, viewed from the bonding surface side with respect to a second semiconductor chip. [Figure 3] 10 is a plan view of a second semiconductor chip according to an embodiment of the disclosed technique, viewed from the bonding surface side with respect to the first semiconductor chip. FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line 4-4 in FIG. [Figure 5] 1 is a planar perspective view of a semiconductor device in which a first semiconductor chip and a second semiconductor chip are bonded together according to an embodiment of the disclosed technique. [Figure 6] 1A and 1B are diagrams schematically illustrating conductive paths formed by bonding a first semiconductor chip and a second semiconductor chip together according to an embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals.

[0014] FIG. 1 is a perspective view showing an example of the configuration of a semiconductor device 1 according to an embodiment of the disclosed technology. The semiconductor device 1 has a multi-chip configuration including a first semiconductor chip 10 and a second semiconductor chip 20. The first semiconductor chip 10 is, for example, a custom chip and has a functional unit for realizing a specific function according to the application. The second semiconductor chip 20 is, for example, a general-purpose core chip and has general-purpose functional units such as a CPU and memory. The applications and functions of the first semiconductor chip 10 and the second semiconductor chip 20 are not particularly limited.

[0015] The first semiconductor chip 10 and the second semiconductor chip 20 each have a plurality of connection terminals arranged in a grid pattern on the surface of the semiconductor substrate. Figure 1 shows a plurality of connection terminals 11 provided on the first semiconductor chip 10. The first semiconductor chip 10 and the second semiconductor chip 20 are electrically and mechanically connected to each other by bonding the connection terminals together. The connection terminals may be made of, for example, Cu, and the bonding between the connection terminals may be Cu-Cu bonding.

[0016] The area of ​​the first semiconductor chip 10 is larger than the area of ​​the second semiconductor chip 20, and the second semiconductor chip 20 is stacked on the first semiconductor chip 10. After the second semiconductor chip 20 and the first semiconductor chip 10 are connected, the second semiconductor chip 20 can be accessed only via the first semiconductor chip 10.

[0017] 2 is a plan view of the first semiconductor chip 10 as viewed from the bonding surface side with the second semiconductor chip 20. The first semiconductor chip 10 has a plurality of connection terminals 11, alignment marks 12A and 12B, and measurement terminals 13A and 13B.

[0018] The plurality of connection terminals 11 are terminals used for connection to the second semiconductor chip 20. The plurality of connection terminals 11 are provided in the center of the first semiconductor chip 10. Each of the plurality of connection terminals 11 is made of a conductor such as Cu.

[0019] The alignment marks 12A and 12B are marks used to align the first semiconductor chip 10 and the second semiconductor chip 20. The alignment marks 12A and 12B are provided outside the multiple connection terminals 11. The positions of the alignment marks 12A and 12B correspond to the positions of alignment marks 22A and 22B (see FIG. 3) of the second semiconductor chip 20, which will be described later. The alignment marks 12A and 12B are made of the same material as the connection terminals 11, for example, a conductor such as Cu. The alignment marks 12A and 12B are electrically isolated from each other.

[0020] In order to improve the recognition accuracy of image recognition, alignment marks 12A and 12B preferably have a characteristic shape different from that of connection terminal 11. FIG. 2 illustrates alignment marks 12A and 12B having a cross-shaped pattern. However, the disclosed technology is not limited to this embodiment, and the patterns of alignment marks 12A and 12B can be determined arbitrarily. Alignment mark 12A is an example of a "first alignment mark" in the disclosed technology, and alignment mark 12B is an example of a "second alignment mark" in the disclosed technology.

[0021] The measurement terminals 13A and 13B are electrode pads used to test the electrical connection between the first semiconductor chip 10 and the second semiconductor chip 20. The measurement terminal 13A is electrically connected to the alignment mark 12A via the wiring 14A, and the measurement terminal 13B is electrically connected to the alignment mark 12B via the wiring 14B. The measurement terminals 13A and 13B are made of a conductor such as Al. The measurement terminals 13A and 13B are disposed, for example, near the outer edge of the first semiconductor chip 10. Note that the first semiconductor chip 10 may have multiple terminals other than the measurement terminals 13A and 13B provided along its outer edge as shown in FIG. 1 . The measurement terminal 13A is an example of a “first terminal” in the disclosed technology, and the measurement terminal 13B is an example of a “second terminal” in the disclosed technology.

[0022] 3 is a plan view of second semiconductor chip 20 viewed from the bonding surface side with first semiconductor chip 10. Second semiconductor chip 20 has a plurality of connection terminals 21, alignment marks 22A and 22B, and a guard ring 23.

[0023] The plurality of connection terminals 21 are terminals used for connection with the first semiconductor chip 10, and correspond to the plurality of connection terminals 21 provided on the first semiconductor chip 10. The plurality of connection terminals 21 are provided in the center of the second semiconductor chip 20. Each of the plurality of connection terminals 21 is made of a conductor such as Cu.

[0024] The alignment marks 22A and 22B are marks used to align the first semiconductor chip 10 and the second semiconductor chip 20. The alignment marks 22A and 22B are provided outside the multiple connection terminals 21. The alignment marks 22A and 22B are preferably arranged near two corners of the second semiconductor chip 20 that are diagonally opposite each other. The positions of the alignment marks 22A and 22B correspond to the positions of the alignment marks 12A and 12B (see FIG. 2) provided on the first semiconductor chip 10. The alignment marks 22A and 22B are made of the same material as the connection terminals 21, for example, a conductor such as Cu.

[0025] Alignment mark 22A is electrically connected to guard ring 23 via wiring 24A, and alignment mark 22B is electrically connected to guard ring 23 via wiring 24B. Alignment marks 22A and 22B are preferably provided near guard ring 23. For example, the distance between alignment marks 22A and 22B and guard ring 23 is preferably 10% or less of the length of one side of rectangular second semiconductor chip 20. This makes it possible to reduce the area in which wiring 24A and 24B are arranged.

[0026] In order to improve the recognition accuracy by image recognition, it is preferable that alignment marks 22A and 22B have a characteristic shape different from that of connection terminal 21. FIG. 3 shows alignment marks 22A and 22B having a cross pattern. However, the disclosed technology is not limited to this embodiment, and the patterns of alignment marks 22A and 22B can be determined arbitrarily. Alignment mark 22A is an example of a "third alignment mark" in the disclosed technology, and alignment mark 22B is an example of a "fourth alignment mark" in the disclosed technology.

[0027] The guard ring 23 is configured to include a ring-shaped conductor provided along the outer edge of the second semiconductor chip 20. The region inside the guard ring 23 is a device region where devices that realize the original functions of the second semiconductor chip 20 are formed. For example, circuits composed of elements such as transistors, resistors, capacitors, and wiring are formed in the device region. The second semiconductor chip 20 is singulated by cutting the wafer along scribe lines. By surrounding the outer periphery of the device region with the guard ring 23, it is possible to reduce the risk of chipping that may occur when singulating the second semiconductor chip 20 and reach the device region. As described above, the alignment marks 22A and 22B are each electrically connected to the guard ring 23. Because the guard ring 23 is configured to include a ring-shaped conductor, the alignment marks 22A and 22B are electrically connected to each other via the guard ring 23.

[0028] 4 is a cross-sectional view taken along line 4-4 in FIG. 3. The second semiconductor chip 20 has a semiconductor substrate 25, such as a silicon substrate, and an insulator layer 26 provided on the semiconductor substrate 25. The guard ring 23 has multiple conductive films 27 provided inside the insulator layer 26. The conductive films 27 of each layer are connected to the conductive films 27 of adjacent layers through vias 28. The alignment mark 22A and the wiring 24A are provided on the surface of the insulator layer 26. The alignment mark 22A is connected to the topmost conductive film 27 of the conductive films 27 that make up the guard ring 23, which is provided on the surface of the insulator layer 26, through the wiring 24A. The same applies to the alignment mark 22B and the wiring 24B.

[0029] 5 is a plan perspective view of the semiconductor device 1 in which the first semiconductor chip 10 and the second semiconductor chip 20 are bonded together. The first semiconductor chip 10 and the second semiconductor chip 20 are connected so that the alignment marks 12A and 22A overlap and the alignment marks 12B and 22B overlap. This aligns the first semiconductor chip 10 and the second semiconductor chip 20, and the multiple connection terminals 11 and the multiple connection terminals 21 are bonded together.

[0030] Alignment mark 12A provided on first semiconductor chip 10 and alignment mark 22A provided on second semiconductor chip 20 are bonded to each other, for example, by Cu-Cu bonding. Similarly, alignment mark 12B provided on first semiconductor chip 10 and alignment mark 22B provided on second semiconductor chip 20 are bonded to each other, for example, by Cu-Cu bonding. When first semiconductor chip 10 and second semiconductor chip 20 are bonded to each other, measurement terminals 13A and 13B are not covered by second semiconductor chip 20 and are exposed.

[0031] 6 is a diagram schematically illustrating a conductive path formed by bonding the first semiconductor chip 10 and the second semiconductor chip 20. When the electrical connection between the alignment mark 12A and the alignment mark 22A and the electrical connection between the alignment mark 12B and the alignment mark 22B are properly formed, the measurement terminal 13A is electrically connected to the measurement terminal 13B via the wiring 14A, the alignment mark 12A, the alignment mark 22A, the wiring 24A, the guard ring 23, the wiring 24B, the alignment mark 22B, the alignment mark 12B, and the wiring 14B. Therefore, by checking the electrical connection between the measurement terminal 13A and the measurement terminal 13B, the electrical connection between the alignment mark 12A and the alignment mark 22A and the electrical connection between the alignment marks 12B and 22B can be grasped.

[0032] In the first semiconductor chip 10, the surfaces of the alignment marks 12A and 12B and the connection terminals 11 are planarized by CMP (Chemical Mechanical Polishing), and the surface height is uniform. Similarly, in the second semiconductor chip 20, the surfaces of the alignment marks 22A and 22B and the connection terminals 21 are planarized by CMP, and the surface height is uniform. The electrical connection between the connection terminals 11 provided on the first semiconductor chip 10 and the connection terminals 21 provided on the second semiconductor chip 20 is formed by Cu-Cu bonding, the same as the electrical connection between the alignment marks. Therefore, when the electrical connection between the alignment marks 12A and 22A and the electrical connection between the alignment marks 12B and 22B are properly formed, the electrical connection between the connection terminals 11 and 21 can also be considered to be properly formed. Therefore, by checking the electrical connection state between measurement terminal 13A and measurement terminal 13B, it is possible to easily inspect the electrical connection state between connection terminal 11 and connection terminal 21 (i.e., the electrical connection state between first semiconductor chip 10 and second semiconductor chip 20).

[0033] A method for inspecting the electrical connection between a first semiconductor chip 10 and a second semiconductor chip 20 according to an embodiment of the disclosed technique includes measuring an electrical characteristic indicating the electrical connection between a measurement terminal 13A and a measurement terminal 13B. For example, the voltage at measurement terminal 13B may be measured when a predetermined voltage (e.g., 1 V) is applied to measurement terminal 13A. In this case, if the measured voltage at measurement terminal 13B is substantially equal to the level of the voltage applied to measurement terminal 13A, it can be determined that the electrical connection between the first semiconductor chip 10 and the second semiconductor chip 20 via connection terminals 11 and 21 is good. On the other hand, if the measured voltage at measurement terminal 13B is different from the level of the voltage applied to measurement terminal 13A, it can be determined that the electrical connection between the first semiconductor chip 10 and the second semiconductor chip 20 via connection terminals 11 and 21 is poor.

[0034] The electrical characteristic indicating the electrical connection state between the measurement terminals 13A and 13B may be the electrical resistance between the measurement terminals 13A and 13B. In this case, if the electrical resistance between the measurement terminals 13A and 13B is less than a predetermined value, it can be determined that the state of the electrical connection between the first semiconductor chip 10 and the second semiconductor chip 20 via the connection terminals 11 and 21 is good. On the other hand, if the electrical resistance between the measurement terminals 13A and 13B is equal to or greater than a predetermined value, it can be determined that the state of the electrical connection between the first semiconductor chip 10 and the second semiconductor chip 20 via the connection terminals 11 and 21 is poor. The measurement of the electrical characteristic indicating the electrical connection state between the measurement terminals 13A and 13B can be performed, for example, by contacting probes (not shown) with the measurement terminals 13A and 13B, respectively.

[0035] As described above, the semiconductor device 1 according to the embodiment of the disclosed technology enables simple inspection of the electrical connection between the first semiconductor chip 10 and the second semiconductor chip 20. Consider a case where the alignment marks 22A and 22B in the second semiconductor chip 20 are electrically connected by wiring provided on the second semiconductor chip 20. Because the alignment marks 22A and 22B are located at positions distant from each other, the length of the wiring for electrically connecting them is relatively long. Therefore, when the alignment marks 22A and 22B are electrically connected by wiring provided on the second semiconductor chip 20, a relatively large area for arranging the wiring must be secured on the second semiconductor chip 20. If it is difficult to secure a relatively large area for arranging the wiring, the size of the second semiconductor chip 20 must be increased. On the other hand, the semiconductor device 1 according to the embodiment of the disclosed technology electrically connects the alignment marks 22A and 22B by the guard ring 23, eliminating the need to secure a relatively large area for arranging the wiring on the second semiconductor chip 20.

[0036] The following additional notes are provided regarding the above-described embodiments. (Appendix 1) A semiconductor device including a first semiconductor chip and a second semiconductor chip connected to the first semiconductor chip, The first semiconductor chip comprises: a first alignment mark made of a conductor; a second alignment mark made of a conductor electrically isolated from the first alignment mark; a first terminal electrically connected to the first alignment mark; a second terminal electrically connected to the second alignment mark; Including, The second semiconductor chip comprises: a guard ring including a ring-shaped conductor provided along an outer edge of the second semiconductor chip; a third alignment mark made of a conductor electrically connected to the guard ring; a fourth alignment mark made of a conductor electrically connected to the guard ring; Including, The first semiconductor chip and the second semiconductor chip are connected so that the first alignment mark and the third alignment mark overlap, and the second alignment mark and the fourth alignment mark overlap. Semiconductor device.

[0037] (Appendix 2) The third alignment mark and the fourth alignment mark are provided near the guard ring. 2. The semiconductor device according to claim 1.

[0038] (Appendix 3) The first semiconductor chip is larger than the second semiconductor chip, and the first terminal and the second terminal are exposed when the first semiconductor chip and the second semiconductor chip are bonded together. 10. The semiconductor device according to claim 1 or 2.

[0039] (Appendix 4) the first semiconductor chip and the second semiconductor chip each have a connection terminal for connecting to each other; The first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark each have a shape different from that of the connection terminal. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0040] (Appendix 5) A method for inspecting a semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 4, measuring an electrical characteristic indicative of an electrical connection between the first terminal and the second terminal. Testing method.

[0041] (Appendix 6) a first alignment mark made of a conductor; a second alignment mark made of a conductor electrically isolated from the first alignment mark; a first terminal electrically connected to the first alignment mark; a second terminal electrically connected to the second alignment mark; 1. A semiconductor chip comprising:

[0042] (Appendix 7) a guard ring including a ring-shaped conductor provided along the outer edge of the semiconductor chip; a third alignment mark made of a conductor electrically connected to the guard ring; a fourth alignment mark made of a conductor electrically connected to the guard ring; 1. A semiconductor chip comprising: [Explanation of symbols]

[0043] 1. Semiconductor device 10 First Semiconductor Chip 11 Connection terminal 12A, 12B alignment marks 13A, 13B measurement terminal 20 The second semiconductor chip 21 Connection terminal 22A, 22B alignment marks 23 Guard Ring

Claims

1. A semiconductor device including a first semiconductor chip and a second semiconductor chip connected to the first semiconductor chip, The first semiconductor chip includes: a first alignment mark made of a conductor; a second alignment mark made of a conductor electrically isolated from the first alignment mark; a first terminal electrically connected to the first alignment mark; a second terminal electrically connected to the second alignment mark; Including, The second semiconductor chip includes: a guard ring including a ring-shaped conductor provided along an outer edge of the second semiconductor chip; a third alignment mark made of a conductor electrically connected to the guard ring; a fourth alignment mark made of a conductor electrically connected to the guard ring; Including, The first semiconductor chip and the second semiconductor chip are connected so that the first alignment mark and the third alignment mark overlap, and the second alignment mark and the fourth alignment mark overlap. Semiconductor device.

2. The third alignment mark and the fourth alignment mark are provided near the guard ring. The semiconductor device according to claim 1 .

3. The first semiconductor chip is larger than the second semiconductor chip, and the first terminals and the second terminals are exposed when the first semiconductor chip and the second semiconductor chip are bonded together. The semiconductor device according to claim 1 .

4. the first semiconductor chip and the second semiconductor chip each have a connection terminal for connecting to each other; The first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark each have a shape different from that of the connection terminal. The semiconductor device according to claim 1 .

5. 5. A method for inspecting a semiconductor device according to claim 1, comprising: measuring an electrical characteristic indicative of an electrical connection between the first terminal and the second terminal. Testing method.

6. a first alignment mark made of a conductor; a second alignment mark made of a conductor electrically isolated from the first alignment mark; a first terminal electrically connected to the first alignment mark; a second terminal electrically connected to the second alignment mark; 1. A semiconductor chip comprising:

7. a guard ring including a ring-shaped conductor provided along the outer edge of the semiconductor chip; a third alignment mark made of a conductor electrically connected to the guard ring; a fourth alignment mark made of a conductor electrically connected to the guard ring; 1. A semiconductor chip comprising:

Images